1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
4 //
5 // Copyright (C) 2021 Renesas Electronics Corp.
6 // Copyright (C) 2019 Chris Brandt.
7 //
8
9 #include <linux/clk.h>
10 #include <linux/dmaengine.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18
19 /* REGISTER OFFSET */
20 #define SSICR 0x000
21 #define SSISR 0x004
22 #define SSIFCR 0x010
23 #define SSIFSR 0x014
24 #define SSIFTDR 0x018
25 #define SSIFRDR 0x01c
26 #define SSIOFR 0x020
27 #define SSISCR 0x024
28
29 /* SSI REGISTER BITS */
30 #define SSICR_DWL(x) (((x) & 0x7) << 19)
31 #define SSICR_SWL(x) (((x) & 0x7) << 16)
32
33 #define SSICR_CKS BIT(30)
34 #define SSICR_TUIEN BIT(29)
35 #define SSICR_TOIEN BIT(28)
36 #define SSICR_RUIEN BIT(27)
37 #define SSICR_ROIEN BIT(26)
38 #define SSICR_MST BIT(14)
39 #define SSICR_BCKP BIT(13)
40 #define SSICR_LRCKP BIT(12)
41 #define SSICR_PDTA BIT(9)
42 #define SSICR_CKDV(x) (((x) & 0xf) << 4)
43 #define SSICR_TEN BIT(1)
44 #define SSICR_REN BIT(0)
45
46 #define SSISR_TUIRQ BIT(29)
47 #define SSISR_TOIRQ BIT(28)
48 #define SSISR_RUIRQ BIT(27)
49 #define SSISR_ROIRQ BIT(26)
50 #define SSISR_IIRQ BIT(25)
51
52 #define SSIFCR_AUCKE BIT(31)
53 #define SSIFCR_SSIRST BIT(16)
54 #define SSIFCR_TIE BIT(3)
55 #define SSIFCR_RIE BIT(2)
56 #define SSIFCR_TFRST BIT(1)
57 #define SSIFCR_RFRST BIT(0)
58 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST)
59
60 #define SSIFSR_TDC_MASK 0x3f
61 #define SSIFSR_TDC_SHIFT 24
62 #define SSIFSR_RDC_MASK 0x3f
63 #define SSIFSR_RDC_SHIFT 8
64
65 #define SSIFSR_TDE BIT(16)
66 #define SSIFSR_RDF BIT(0)
67
68 #define SSIOFR_LRCONT BIT(8)
69
70 #define SSISCR_TDES(x) (((x) & 0x1f) << 8)
71 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
72
73 /* Pre allocated buffers sizes */
74 #define PREALLOC_BUFFER (SZ_32K)
75 #define PREALLOC_BUFFER_MAX (SZ_32K)
76
77 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */
78 #define SSI_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
79 SNDRV_PCM_FMTBIT_S32_LE)
80 #define SSI_CHAN_MIN 2
81 #define SSI_CHAN_MAX 2
82 #define SSI_FIFO_DEPTH 32
83
84 struct rz_ssi_priv;
85
86 struct rz_ssi_stream {
87 struct rz_ssi_priv *priv;
88 struct snd_pcm_substream *substream;
89 int fifo_sample_size; /* sample capacity of SSI FIFO */
90 int dma_buffer_pos; /* The address for the next DMA descriptor */
91 int completed_dma_buf_pos; /* The address of the last completed DMA descriptor. */
92 int period_counter; /* for keeping track of periods transferred */
93 int buffer_pos; /* current frame position in the buffer */
94 int running; /* 0=stopped, 1=running */
95
96 int uerr_num;
97 int oerr_num;
98
99 struct dma_chan *dma_ch;
100
101 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
102 };
103
104 struct rz_ssi_priv {
105 void __iomem *base;
106 struct reset_control *rstc;
107 struct device *dev;
108 struct clk *sfr_clk;
109 struct clk *clk;
110
111 phys_addr_t phys;
112 int irq_int;
113 int irq_tx;
114 int irq_rx;
115 int irq_rt;
116
117 spinlock_t lock;
118
119 /*
120 * The SSI supports full-duplex transmission and reception.
121 * However, if an error occurs, channel reset (both transmission
122 * and reception reset) is required.
123 * So it is better to use as half-duplex (playing and recording
124 * should be done on separate channels).
125 */
126 struct rz_ssi_stream playback;
127 struct rz_ssi_stream capture;
128
129 /* clock */
130 unsigned long audio_mck;
131 unsigned long audio_clk_1;
132 unsigned long audio_clk_2;
133
134 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
135 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
136 bool dma_rt;
137
138 struct {
139 bool tx_active;
140 bool rx_active;
141 bool one_stream_triggered;
142 } dup;
143
144 /* Full duplex communication support */
145 struct {
146 unsigned int rate;
147 unsigned int channels;
148 unsigned int sample_width;
149 unsigned int sample_bits;
150 } hw_params_cache;
151 };
152
153 static void rz_ssi_dma_complete(void *data);
154
rz_ssi_reg_writel(struct rz_ssi_priv * priv,uint reg,u32 data)155 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
156 {
157 writel(data, (priv->base + reg));
158 }
159
rz_ssi_reg_readl(struct rz_ssi_priv * priv,uint reg)160 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
161 {
162 return readl(priv->base + reg);
163 }
164
rz_ssi_reg_mask_setl(struct rz_ssi_priv * priv,uint reg,u32 bclr,u32 bset)165 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
166 u32 bclr, u32 bset)
167 {
168 u32 val;
169
170 val = readl(priv->base + reg);
171 val = (val & ~bclr) | bset;
172 writel(val, (priv->base + reg));
173 }
174
rz_ssi_stream_is_play(struct snd_pcm_substream * substream)175 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream)
176 {
177 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
178 }
179
180 static inline struct rz_ssi_stream *
rz_ssi_stream_get(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)181 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
182 {
183 return (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? &ssi->playback : &ssi->capture;
184 }
185
rz_ssi_is_dma_enabled(struct rz_ssi_priv * ssi)186 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
187 {
188 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
189 }
190
rz_ssi_set_substream(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)191 static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
192 struct snd_pcm_substream *substream)
193 {
194 struct rz_ssi_priv *ssi = strm->priv;
195
196 guard(spinlock_irqsave)(&ssi->lock);
197
198 strm->substream = substream;
199 }
200
rz_ssi_stream_is_valid(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)201 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
202 struct rz_ssi_stream *strm)
203 {
204 guard(spinlock_irqsave)(&ssi->lock);
205
206 return strm->substream && strm->substream->runtime;
207 }
208
rz_ssi_is_stream_running(struct rz_ssi_stream * strm)209 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm)
210 {
211 return strm->substream && strm->running;
212 }
213
rz_ssi_stream_init(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)214 static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
215 struct snd_pcm_substream *substream)
216 {
217 rz_ssi_set_substream(strm, substream);
218 strm->dma_buffer_pos = 0;
219 strm->completed_dma_buf_pos = 0;
220 strm->period_counter = 0;
221 strm->buffer_pos = 0;
222
223 strm->oerr_num = 0;
224 strm->uerr_num = 0;
225 strm->running = 0;
226
227 /* fifo init */
228 strm->fifo_sample_size = SSI_FIFO_DEPTH;
229 }
230
rz_ssi_stream_quit(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)231 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
232 struct rz_ssi_stream *strm)
233 {
234 struct device *dev = ssi->dev;
235
236 rz_ssi_set_substream(strm, NULL);
237
238 if (strm->oerr_num > 0)
239 dev_info(dev, "overrun = %d\n", strm->oerr_num);
240
241 if (strm->uerr_num > 0)
242 dev_info(dev, "underrun = %d\n", strm->uerr_num);
243 }
244
rz_ssi_clk_setup(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels)245 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
246 unsigned int channels)
247 {
248 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 };
249 unsigned int channel_bits = 32; /* System Word Length */
250 unsigned long bclk_rate = rate * channels * channel_bits;
251 unsigned int div;
252 unsigned int i;
253 u32 ssicr = 0;
254 u32 clk_ckdv;
255
256 /* Clear AUCKE so we can set MST */
257 rz_ssi_reg_writel(ssi, SSIFCR, 0);
258
259 /* Continue to output LRCK pin even when idle */
260 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
261 if (ssi->audio_clk_1 && ssi->audio_clk_2) {
262 if (ssi->audio_clk_1 % bclk_rate)
263 ssi->audio_mck = ssi->audio_clk_2;
264 else
265 ssi->audio_mck = ssi->audio_clk_1;
266 }
267
268 /* Clock setting */
269 ssicr |= SSICR_MST;
270 if (ssi->audio_mck == ssi->audio_clk_1)
271 ssicr |= SSICR_CKS;
272 if (ssi->bckp_rise)
273 ssicr |= SSICR_BCKP;
274 if (ssi->lrckp_fsync_fall)
275 ssicr |= SSICR_LRCKP;
276
277 /* Determine the clock divider */
278 clk_ckdv = 0;
279 div = ssi->audio_mck / bclk_rate;
280 /* try to find an match */
281 for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
282 if (ckdv[i] == div) {
283 clk_ckdv = i;
284 break;
285 }
286 }
287
288 if (i == ARRAY_SIZE(ckdv)) {
289 dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
290 return -EINVAL;
291 }
292
293 /*
294 * DWL: Data Word Length = {16, 24, 32} bits
295 * SWL: System Word Length = 32 bits
296 */
297 ssicr |= SSICR_CKDV(clk_ckdv);
298 switch (ssi->hw_params_cache.sample_width) {
299 case 16:
300 ssicr |= SSICR_DWL(1);
301 break;
302 case 24:
303 ssicr |= SSICR_DWL(5) | SSICR_PDTA;
304 break;
305 case 32:
306 ssicr |= SSICR_DWL(6);
307 break;
308 default:
309 dev_err(ssi->dev, "Not support %u data width",
310 ssi->hw_params_cache.sample_width);
311 return -EINVAL;
312 }
313
314 ssicr |= SSICR_SWL(3);
315 rz_ssi_reg_writel(ssi, SSICR, ssicr);
316 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST);
317
318 return 0;
319 }
320
rz_ssi_set_idle(struct rz_ssi_priv * ssi)321 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi)
322 {
323 u32 tmp;
324 int ret;
325
326 /* Disable irqs */
327 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
328 SSICR_RUIEN | SSICR_ROIEN, 0);
329 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
330
331 /* Clear all error flags */
332 rz_ssi_reg_mask_setl(ssi, SSISR,
333 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
334 SSISR_RUIRQ), 0);
335
336 /* Wait for idle */
337 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100);
338 if (ret)
339 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n");
340
341 /* Hold FIFOs in reset */
342 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST);
343 }
344
rz_ssi_start(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)345 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
346 {
347 bool is_play = rz_ssi_stream_is_play(strm->substream);
348 bool is_full_duplex;
349 u32 ssicr, ssifcr;
350
351 is_full_duplex = ssi->dup.tx_active && ssi->dup.rx_active;
352 ssicr = rz_ssi_reg_readl(ssi, SSICR);
353 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR);
354 if (!is_full_duplex) {
355 ssifcr &= ~0xF;
356 } else if (ssi->dup.one_stream_triggered) {
357 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
358 rz_ssi_set_idle(ssi);
359 ssifcr &= ~SSIFCR_FIFO_RST;
360 }
361
362 /* FIFO interrupt thresholds */
363 if (rz_ssi_is_dma_enabled(ssi))
364 rz_ssi_reg_writel(ssi, SSISCR, 0);
365 else
366 rz_ssi_reg_writel(ssi, SSISCR,
367 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
368 SSISCR_RDFS(0));
369
370 /* enable IRQ */
371 if (is_play) {
372 ssicr |= SSICR_TUIEN | SSICR_TOIEN;
373 ssifcr |= SSIFCR_TIE;
374 if (!is_full_duplex)
375 ssifcr |= SSIFCR_RFRST;
376 } else {
377 ssicr |= SSICR_RUIEN | SSICR_ROIEN;
378 ssifcr |= SSIFCR_RIE;
379 if (!is_full_duplex)
380 ssifcr |= SSIFCR_TFRST;
381 }
382
383 rz_ssi_reg_writel(ssi, SSICR, ssicr);
384 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
385
386 /* Clear all error flags */
387 rz_ssi_reg_mask_setl(ssi, SSISR,
388 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
389 SSISR_RUIRQ), 0);
390
391 strm->running = 1;
392 if (!is_full_duplex) {
393 ssicr |= is_play ? SSICR_TEN : SSICR_REN;
394 rz_ssi_reg_writel(ssi, SSICR, ssicr);
395 } else if (ssi->dup.one_stream_triggered) {
396 ssicr |= SSICR_TEN | SSICR_REN;
397 rz_ssi_reg_writel(ssi, SSICR, ssicr);
398 ssi->dup.one_stream_triggered = false;
399 } else {
400 ssi->dup.one_stream_triggered = true;
401 }
402
403 return 0;
404 }
405
rz_ssi_swreset(struct rz_ssi_priv * ssi)406 static int rz_ssi_swreset(struct rz_ssi_priv *ssi)
407 {
408 u32 tmp;
409
410 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
411 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
412 return readl_poll_timeout_atomic(ssi->base + SSIFCR, tmp, !(tmp & SSIFCR_SSIRST), 1, 5);
413 }
414
rz_ssi_stop(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)415 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
416 {
417 strm->running = 0;
418
419 if (rz_ssi_is_stream_running(&ssi->playback) ||
420 rz_ssi_is_stream_running(&ssi->capture))
421 return 0;
422
423 /* Disable TX/RX */
424 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
425
426 /* Cancel all remaining DMA transactions */
427 if (rz_ssi_is_dma_enabled(ssi)) {
428 if (ssi->playback.dma_ch)
429 dmaengine_terminate_async(ssi->playback.dma_ch);
430 if (ssi->capture.dma_ch)
431 dmaengine_terminate_async(ssi->capture.dma_ch);
432 }
433
434 rz_ssi_set_idle(ssi);
435
436 return 0;
437 }
438
rz_ssi_pointer_update(struct rz_ssi_stream * strm,int frames)439 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
440 {
441 struct snd_pcm_substream *substream = strm->substream;
442 struct snd_pcm_runtime *runtime;
443 int current_period;
444
445 if (!strm->running || !substream || !substream->runtime)
446 return;
447
448 runtime = substream->runtime;
449 strm->buffer_pos += frames;
450 WARN_ON(strm->buffer_pos > runtime->buffer_size);
451
452 /* ring buffer */
453 if (strm->buffer_pos == runtime->buffer_size)
454 strm->buffer_pos = 0;
455
456 current_period = strm->buffer_pos / runtime->period_size;
457 if (strm->period_counter != current_period) {
458 snd_pcm_period_elapsed(strm->substream);
459 strm->period_counter = current_period;
460 }
461
462 strm->completed_dma_buf_pos += runtime->period_size;
463 if (strm->completed_dma_buf_pos >= runtime->buffer_size)
464 strm->completed_dma_buf_pos = 0;
465 }
466
rz_ssi_pio_recv(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)467 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
468 {
469 struct snd_pcm_substream *substream = strm->substream;
470 struct snd_pcm_runtime *runtime;
471 int fifo_samples;
472 int frames_left;
473 int samples;
474 int i;
475
476 if (!rz_ssi_stream_is_valid(ssi, strm))
477 return -EINVAL;
478
479 runtime = substream->runtime;
480
481 do {
482 /* frames left in this period */
483 frames_left = runtime->period_size -
484 (strm->buffer_pos % runtime->period_size);
485 if (!frames_left)
486 frames_left = runtime->period_size;
487
488 /* Samples in RX FIFO */
489 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
490 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
491
492 /* Only read full frames at a time */
493 samples = 0;
494 while (frames_left && (fifo_samples >= runtime->channels)) {
495 samples += runtime->channels;
496 fifo_samples -= runtime->channels;
497 frames_left--;
498 }
499
500 /* not enough samples yet */
501 if (!samples)
502 break;
503
504 /* calculate new buffer index */
505 if (ssi->hw_params_cache.sample_width == 16) {
506 u16 *buf;
507
508 buf = (u16 *)runtime->dma_area;
509 buf += strm->buffer_pos * runtime->channels;
510
511 for (i = 0; i < samples; i++)
512 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
513 } else {
514 u32 *buf;
515
516 buf = (u32 *)runtime->dma_area;
517 buf += strm->buffer_pos * runtime->channels;
518
519 for (i = 0; i < samples; i++)
520 *buf++ = rz_ssi_reg_readl(ssi, SSIFRDR);
521 }
522
523 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
524 rz_ssi_pointer_update(strm, samples / runtime->channels);
525 } while (!frames_left && fifo_samples >= runtime->channels);
526
527 return 0;
528 }
529
rz_ssi_pio_send(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)530 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
531 {
532 struct snd_pcm_substream *substream = strm->substream;
533 struct snd_pcm_runtime *runtime = substream->runtime;
534 int sample_space;
535 int samples = 0;
536 int frames_left;
537 int i;
538 u32 ssifsr;
539
540 if (!rz_ssi_stream_is_valid(ssi, strm))
541 return -EINVAL;
542
543 /* frames left in this period */
544 frames_left = runtime->period_size - (strm->buffer_pos %
545 runtime->period_size);
546 if (frames_left == 0)
547 frames_left = runtime->period_size;
548
549 sample_space = strm->fifo_sample_size;
550 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
551 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
552 if (sample_space < 0)
553 return -EINVAL;
554
555 /* Only add full frames at a time */
556 while (frames_left && (sample_space >= runtime->channels)) {
557 samples += runtime->channels;
558 sample_space -= runtime->channels;
559 frames_left--;
560 }
561
562 /* no space to send anything right now */
563 if (samples == 0)
564 return 0;
565
566 /* calculate new buffer index */
567 if (ssi->hw_params_cache.sample_width == 16) {
568 u16 *buf;
569
570 buf = (u16 *)(runtime->dma_area);
571 buf += strm->buffer_pos * runtime->channels;
572
573 for (i = 0; i < samples; i++)
574 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
575 } else {
576 u32 *buf;
577
578 buf = (u32 *)(runtime->dma_area);
579 buf += strm->buffer_pos * runtime->channels;
580
581 for (i = 0; i < samples; i++)
582 rz_ssi_reg_writel(ssi, SSIFTDR, *buf++);
583 }
584
585 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
586 rz_ssi_pointer_update(strm, samples / runtime->channels);
587
588 return 0;
589 }
590
rz_ssi_interrupt(int irq,void * data)591 static irqreturn_t rz_ssi_interrupt(int irq, void *data)
592 {
593 struct rz_ssi_stream *strm_playback = NULL;
594 struct rz_ssi_stream *strm_capture = NULL;
595 struct rz_ssi_priv *ssi = data;
596 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
597
598 if (ssi->playback.substream)
599 strm_playback = &ssi->playback;
600 if (ssi->capture.substream)
601 strm_capture = &ssi->capture;
602
603 if (!strm_playback && !strm_capture)
604 return IRQ_HANDLED; /* Left over TX/RX interrupt */
605
606 if (irq == ssi->irq_int) { /* error or idle */
607 bool is_stopped = !!(ssisr & (SSISR_RUIRQ | SSISR_ROIRQ |
608 SSISR_TUIRQ | SSISR_TOIRQ));
609 int i, count;
610
611 if (rz_ssi_is_dma_enabled(ssi))
612 count = 4;
613 else
614 count = 1;
615
616 if (ssi->capture.substream && is_stopped) {
617 if (ssisr & SSISR_RUIRQ)
618 strm_capture->uerr_num++;
619 if (ssisr & SSISR_ROIRQ)
620 strm_capture->oerr_num++;
621
622 rz_ssi_stop(ssi, strm_capture);
623 }
624
625 if (ssi->playback.substream && is_stopped) {
626 if (ssisr & SSISR_TUIRQ)
627 strm_playback->uerr_num++;
628 if (ssisr & SSISR_TOIRQ)
629 strm_playback->oerr_num++;
630
631 rz_ssi_stop(ssi, strm_playback);
632 }
633
634 /* Clear all flags */
635 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ |
636 SSISR_ROIRQ | SSISR_RUIRQ, 0);
637
638 /* Add/remove more data */
639 if (ssi->capture.substream && is_stopped) {
640 for (i = 0; i < count; i++)
641 strm_capture->transfer(ssi, strm_capture);
642 }
643
644 if (ssi->playback.substream && is_stopped) {
645 for (i = 0; i < count; i++)
646 strm_playback->transfer(ssi, strm_playback);
647 }
648
649 /* Resume */
650 if (ssi->playback.substream && is_stopped)
651 rz_ssi_start(ssi, &ssi->playback);
652 if (ssi->capture.substream && is_stopped)
653 rz_ssi_start(ssi, &ssi->capture);
654 }
655
656 if (!rz_ssi_is_stream_running(&ssi->playback) &&
657 !rz_ssi_is_stream_running(&ssi->capture))
658 return IRQ_HANDLED;
659
660 /* tx data empty */
661 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback))
662 strm_playback->transfer(ssi, &ssi->playback);
663
664 /* rx data full */
665 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) {
666 strm_capture->transfer(ssi, &ssi->capture);
667 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
668 }
669
670 if (irq == ssi->irq_rt) {
671 if (ssi->playback.substream) {
672 strm_playback->transfer(ssi, &ssi->playback);
673 } else {
674 strm_capture->transfer(ssi, &ssi->capture);
675 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
676 }
677 }
678
679 return IRQ_HANDLED;
680 }
681
rz_ssi_dma_slave_config(struct rz_ssi_priv * ssi,struct dma_chan * dma_ch,bool is_play)682 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
683 struct dma_chan *dma_ch, bool is_play)
684 {
685 struct dma_slave_config cfg;
686
687 memset(&cfg, 0, sizeof(cfg));
688
689 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
690 cfg.dst_addr = ssi->phys + SSIFTDR;
691 cfg.src_addr = ssi->phys + SSIFRDR;
692 if (ssi->hw_params_cache.sample_width == 16) {
693 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
694 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
695 } else {
696 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
697 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
698 }
699
700 return dmaengine_slave_config(dma_ch, &cfg);
701 }
702
rz_ssi_dma_transfer(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)703 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
704 struct rz_ssi_stream *strm)
705 {
706 struct snd_pcm_substream *substream = strm->substream;
707 struct dma_async_tx_descriptor *desc;
708 struct snd_pcm_runtime *runtime;
709 enum dma_transfer_direction dir;
710 u32 dma_paddr, dma_size;
711 int amount;
712
713 if (!rz_ssi_stream_is_valid(ssi, strm))
714 return -EINVAL;
715
716 runtime = substream->runtime;
717 if (runtime->state == SNDRV_PCM_STATE_DRAINING)
718 /*
719 * Stream is ending, so do not queue up any more DMA
720 * transfers otherwise we play partial sound clips
721 * because we can't shut off the DMA quick enough.
722 */
723 return 0;
724
725 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
726
727 /* Always transfer 1 period */
728 amount = runtime->period_size;
729
730 /* DMA physical address and size */
731 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
732 strm->dma_buffer_pos);
733 dma_size = frames_to_bytes(runtime, amount);
734 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
735 dir,
736 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
737 if (!desc) {
738 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
739 return -ENOMEM;
740 }
741
742 desc->callback = rz_ssi_dma_complete;
743 desc->callback_param = strm;
744
745 if (dmaengine_submit(desc) < 0) {
746 dev_err(ssi->dev, "dmaengine_submit() fail\n");
747 return -EIO;
748 }
749
750 /* Update DMA pointer */
751 strm->dma_buffer_pos += amount;
752 if (strm->dma_buffer_pos >= runtime->buffer_size)
753 strm->dma_buffer_pos = 0;
754
755 /* Start DMA */
756 dma_async_issue_pending(strm->dma_ch);
757
758 return 0;
759 }
760
rz_ssi_dma_complete(void * data)761 static void rz_ssi_dma_complete(void *data)
762 {
763 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
764
765 if (!strm->running || !strm->substream || !strm->substream->runtime)
766 return;
767
768 /* Note that next DMA transaction has probably already started */
769 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
770
771 /* Queue up another DMA transaction */
772 rz_ssi_dma_transfer(strm->priv, strm);
773 }
774
rz_ssi_release_dma_channels(struct rz_ssi_priv * ssi)775 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
776 {
777 if (ssi->playback.dma_ch) {
778 dma_release_channel(ssi->playback.dma_ch);
779 ssi->playback.dma_ch = NULL;
780 if (ssi->dma_rt)
781 ssi->dma_rt = false;
782 }
783
784 if (ssi->capture.dma_ch) {
785 dma_release_channel(ssi->capture.dma_ch);
786 ssi->capture.dma_ch = NULL;
787 }
788 }
789
rz_ssi_dma_request(struct rz_ssi_priv * ssi,struct device * dev)790 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
791 {
792 ssi->playback.dma_ch = dma_request_chan(dev, "tx");
793 if (IS_ERR(ssi->playback.dma_ch))
794 ssi->playback.dma_ch = NULL;
795
796 ssi->capture.dma_ch = dma_request_chan(dev, "rx");
797 if (IS_ERR(ssi->capture.dma_ch))
798 ssi->capture.dma_ch = NULL;
799
800 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
801 ssi->playback.dma_ch = dma_request_chan(dev, "rt");
802 if (IS_ERR(ssi->playback.dma_ch)) {
803 ssi->playback.dma_ch = NULL;
804 goto no_dma;
805 }
806
807 ssi->dma_rt = true;
808 }
809
810 if (!rz_ssi_is_dma_enabled(ssi))
811 goto no_dma;
812
813 return 0;
814
815 no_dma:
816 rz_ssi_release_dma_channels(ssi);
817
818 return -ENODEV;
819 }
820
rz_ssi_trigger_resume(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)821 static int rz_ssi_trigger_resume(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
822 {
823 struct snd_pcm_substream *substream = strm->substream;
824 struct snd_pcm_runtime *runtime = substream->runtime;
825 int ret;
826
827 strm->dma_buffer_pos = strm->completed_dma_buf_pos + runtime->period_size;
828
829 if (rz_ssi_is_stream_running(&ssi->playback) ||
830 rz_ssi_is_stream_running(&ssi->capture))
831 return 0;
832
833 ret = rz_ssi_swreset(ssi);
834 if (ret)
835 return ret;
836
837 return rz_ssi_clk_setup(ssi, ssi->hw_params_cache.rate,
838 ssi->hw_params_cache.channels);
839 }
840
rz_ssi_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)841 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
842 struct snd_soc_dai *dai)
843 {
844 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
845 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
846 int ret = 0, i, num_transfer = 1;
847
848 switch (cmd) {
849 case SNDRV_PCM_TRIGGER_RESUME:
850 ret = rz_ssi_trigger_resume(ssi, strm);
851 if (ret)
852 return ret;
853
854 fallthrough;
855
856 case SNDRV_PCM_TRIGGER_START:
857 if (cmd == SNDRV_PCM_TRIGGER_START)
858 rz_ssi_stream_init(strm, substream);
859
860 if (rz_ssi_is_dma_enabled(ssi)) {
861 bool is_playback = rz_ssi_stream_is_play(substream);
862
863 if (ssi->dma_rt)
864 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
865 is_playback);
866 else
867 ret = rz_ssi_dma_slave_config(ssi, strm->dma_ch,
868 is_playback);
869
870 /* Fallback to pio */
871 if (ret < 0) {
872 ssi->playback.transfer = rz_ssi_pio_send;
873 ssi->capture.transfer = rz_ssi_pio_recv;
874 rz_ssi_release_dma_channels(ssi);
875 } else {
876 /* For DMA, queue up multiple DMA descriptors */
877 num_transfer = 4;
878 }
879 }
880
881 for (i = 0; i < num_transfer; i++) {
882 ret = strm->transfer(ssi, strm);
883 if (ret)
884 return ret;
885 }
886
887 ret = rz_ssi_start(ssi, strm);
888 break;
889
890 case SNDRV_PCM_TRIGGER_SUSPEND:
891 rz_ssi_stop(ssi, strm);
892 break;
893
894 case SNDRV_PCM_TRIGGER_STOP:
895 rz_ssi_stop(ssi, strm);
896 rz_ssi_stream_quit(ssi, strm);
897 break;
898 }
899
900 return ret;
901 }
902
rz_ssi_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)903 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
904 {
905 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
906
907 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
908 case SND_SOC_DAIFMT_BP_FP:
909 break;
910 default:
911 dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
912 return -EINVAL;
913 }
914
915 /*
916 * set clock polarity
917 *
918 * "normal" BCLK = Signal is available at rising edge of BCLK
919 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
920 */
921 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
922 case SND_SOC_DAIFMT_NB_NF:
923 ssi->bckp_rise = false;
924 ssi->lrckp_fsync_fall = false;
925 break;
926 case SND_SOC_DAIFMT_NB_IF:
927 ssi->bckp_rise = false;
928 ssi->lrckp_fsync_fall = true;
929 break;
930 case SND_SOC_DAIFMT_IB_NF:
931 ssi->bckp_rise = true;
932 ssi->lrckp_fsync_fall = false;
933 break;
934 case SND_SOC_DAIFMT_IB_IF:
935 ssi->bckp_rise = true;
936 ssi->lrckp_fsync_fall = true;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 /* only i2s support */
943 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
944 case SND_SOC_DAIFMT_I2S:
945 break;
946 default:
947 dev_err(ssi->dev, "Only I2S mode is supported.\n");
948 return -EINVAL;
949 }
950
951 return 0;
952 }
953
rz_ssi_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)954 static int rz_ssi_startup(struct snd_pcm_substream *substream,
955 struct snd_soc_dai *dai)
956 {
957 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
958
959 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
960 ssi->dup.tx_active = true;
961 else
962 ssi->dup.rx_active = true;
963
964 return 0;
965 }
966
rz_ssi_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)967 static void rz_ssi_shutdown(struct snd_pcm_substream *substream,
968 struct snd_soc_dai *dai)
969 {
970 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
971
972 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
973 ssi->dup.tx_active = false;
974 else
975 ssi->dup.rx_active = false;
976 }
977
rz_ssi_is_valid_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)978 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
979 unsigned int channels,
980 unsigned int sample_width,
981 unsigned int sample_bits)
982 {
983 if (ssi->hw_params_cache.rate != rate ||
984 ssi->hw_params_cache.channels != channels ||
985 ssi->hw_params_cache.sample_width != sample_width ||
986 ssi->hw_params_cache.sample_bits != sample_bits)
987 return false;
988
989 return true;
990 }
991
rz_ssi_cache_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)992 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
993 unsigned int channels,
994 unsigned int sample_width,
995 unsigned int sample_bits)
996 {
997 ssi->hw_params_cache.rate = rate;
998 ssi->hw_params_cache.channels = channels;
999 ssi->hw_params_cache.sample_width = sample_width;
1000 ssi->hw_params_cache.sample_bits = sample_bits;
1001 }
1002
rz_ssi_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1003 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
1004 struct snd_pcm_hw_params *params,
1005 struct snd_soc_dai *dai)
1006 {
1007 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
1008 unsigned int sample_bits = hw_param_interval(params,
1009 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1010 unsigned int sample_width = params_width(params);
1011 unsigned int channels = params_channels(params);
1012 unsigned int rate = params_rate(params);
1013 int ret;
1014
1015 if (!(sample_bits == 16 || sample_bits == 24 || sample_bits == 32)) {
1016 dev_err(ssi->dev, "Unsupported sample width: %d\n",
1017 sample_bits);
1018 return -EINVAL;
1019 }
1020
1021 if (channels != 2) {
1022 dev_err(ssi->dev, "Number of channels not matched: %d\n",
1023 channels);
1024 return -EINVAL;
1025 }
1026
1027 if (rz_ssi_is_stream_running(&ssi->playback) ||
1028 rz_ssi_is_stream_running(&ssi->capture)) {
1029 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, sample_width, sample_bits))
1030 return 0;
1031
1032 dev_err(ssi->dev, "Full duplex needs same HW params\n");
1033 return -EINVAL;
1034 }
1035
1036 rz_ssi_cache_hw_params(ssi, rate, channels, sample_width, sample_bits);
1037
1038 ret = rz_ssi_swreset(ssi);
1039 if (ret)
1040 return ret;
1041
1042 return rz_ssi_clk_setup(ssi, rate, channels);
1043 }
1044
1045 static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
1046 .startup = rz_ssi_startup,
1047 .shutdown = rz_ssi_shutdown,
1048 .trigger = rz_ssi_dai_trigger,
1049 .set_fmt = rz_ssi_dai_set_fmt,
1050 .hw_params = rz_ssi_dai_hw_params,
1051 };
1052
1053 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
1054 .info = SNDRV_PCM_INFO_INTERLEAVED |
1055 SNDRV_PCM_INFO_MMAP |
1056 SNDRV_PCM_INFO_MMAP_VALID |
1057 SNDRV_PCM_INFO_RESUME,
1058 .buffer_bytes_max = PREALLOC_BUFFER,
1059 .period_bytes_min = 32,
1060 .period_bytes_max = 8192,
1061 .channels_min = SSI_CHAN_MIN,
1062 .channels_max = SSI_CHAN_MAX,
1063 .periods_min = 1,
1064 .periods_max = 32,
1065 .fifo_size = 32 * 2,
1066 };
1067
rz_ssi_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)1068 static int rz_ssi_pcm_open(struct snd_soc_component *component,
1069 struct snd_pcm_substream *substream)
1070 {
1071 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
1072
1073 return snd_pcm_hw_constraint_integer(substream->runtime,
1074 SNDRV_PCM_HW_PARAM_PERIODS);
1075 }
1076
rz_ssi_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)1077 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
1078 struct snd_pcm_substream *substream)
1079 {
1080 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1081 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1082 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
1083 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
1084
1085 return strm->buffer_pos;
1086 }
1087
rz_ssi_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)1088 static int rz_ssi_pcm_new(struct snd_soc_component *component,
1089 struct snd_soc_pcm_runtime *rtd)
1090 {
1091 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
1092 rtd->card->snd_card->dev,
1093 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1094 return 0;
1095 }
1096
1097 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
1098 {
1099 .name = "rz-ssi-dai",
1100 .playback = {
1101 .rates = SSI_RATES,
1102 .formats = SSI_FMTS,
1103 .channels_min = SSI_CHAN_MIN,
1104 .channels_max = SSI_CHAN_MAX,
1105 },
1106 .capture = {
1107 .rates = SSI_RATES,
1108 .formats = SSI_FMTS,
1109 .channels_min = SSI_CHAN_MIN,
1110 .channels_max = SSI_CHAN_MAX,
1111 },
1112 .ops = &rz_ssi_dai_ops,
1113 },
1114 };
1115
1116 static const struct snd_soc_component_driver rz_ssi_soc_component = {
1117 .name = "rz-ssi",
1118 .open = rz_ssi_pcm_open,
1119 .pointer = rz_ssi_pcm_pointer,
1120 .pcm_construct = rz_ssi_pcm_new,
1121 .legacy_dai_naming = 1,
1122 };
1123
rz_ssi_probe(struct platform_device * pdev)1124 static int rz_ssi_probe(struct platform_device *pdev)
1125 {
1126 struct device *dev = &pdev->dev;
1127 struct rz_ssi_priv *ssi;
1128 struct clk *audio_clk;
1129 struct resource *res;
1130 int ret;
1131
1132 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1133 if (!ssi)
1134 return -ENOMEM;
1135
1136 ssi->dev = dev;
1137 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1138 if (IS_ERR(ssi->base))
1139 return PTR_ERR(ssi->base);
1140
1141 ssi->phys = res->start;
1142 ssi->clk = devm_clk_get(dev, "ssi");
1143 if (IS_ERR(ssi->clk))
1144 return PTR_ERR(ssi->clk);
1145
1146 ssi->sfr_clk = devm_clk_get(dev, "ssi_sfr");
1147 if (IS_ERR(ssi->sfr_clk))
1148 return PTR_ERR(ssi->sfr_clk);
1149
1150 audio_clk = devm_clk_get(dev, "audio_clk1");
1151 if (IS_ERR(audio_clk))
1152 return dev_err_probe(dev, PTR_ERR(audio_clk), "no audio clk1");
1153
1154 ssi->audio_clk_1 = clk_get_rate(audio_clk);
1155 audio_clk = devm_clk_get(dev, "audio_clk2");
1156 if (IS_ERR(audio_clk))
1157 return dev_err_probe(dev, PTR_ERR(audio_clk), "no audio clk2");
1158
1159 ssi->audio_clk_2 = clk_get_rate(audio_clk);
1160 if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
1161 return dev_err_probe(dev, -EINVAL, "no audio clk1 or audio clk2");
1162
1163 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
1164
1165 /* Detect DMA support */
1166 ret = rz_ssi_dma_request(ssi, dev);
1167 if (ret < 0) {
1168 dev_warn(dev, "DMA not available, using PIO\n");
1169 ssi->playback.transfer = rz_ssi_pio_send;
1170 ssi->capture.transfer = rz_ssi_pio_recv;
1171 } else {
1172 dev_info(dev, "DMA enabled");
1173 ssi->playback.transfer = rz_ssi_dma_transfer;
1174 ssi->capture.transfer = rz_ssi_dma_transfer;
1175 }
1176
1177 ssi->playback.priv = ssi;
1178 ssi->capture.priv = ssi;
1179
1180 spin_lock_init(&ssi->lock);
1181 dev_set_drvdata(dev, ssi);
1182
1183 /* Error Interrupt */
1184 ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
1185 if (ssi->irq_int < 0) {
1186 ret = ssi->irq_int;
1187 goto err_release_dma_chs;
1188 }
1189
1190 ret = devm_request_irq(dev, ssi->irq_int, rz_ssi_interrupt,
1191 0, dev_name(dev), ssi);
1192 if (ret < 0) {
1193 dev_err_probe(dev, ret, "irq request error (int_req)\n");
1194 goto err_release_dma_chs;
1195 }
1196
1197 if (!rz_ssi_is_dma_enabled(ssi)) {
1198 /* Tx and Rx interrupts (pio only) */
1199 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
1200 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
1201 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
1202 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
1203 if (ssi->irq_rt < 0)
1204 return ssi->irq_rt;
1205
1206 ret = devm_request_irq(dev, ssi->irq_rt,
1207 rz_ssi_interrupt, 0,
1208 dev_name(dev), ssi);
1209 if (ret < 0)
1210 return dev_err_probe(dev, ret,
1211 "irq request error (dma_rt)\n");
1212 } else {
1213 if (ssi->irq_tx < 0)
1214 return ssi->irq_tx;
1215
1216 if (ssi->irq_rx < 0)
1217 return ssi->irq_rx;
1218
1219 ret = devm_request_irq(dev, ssi->irq_tx,
1220 rz_ssi_interrupt, 0,
1221 dev_name(dev), ssi);
1222 if (ret < 0)
1223 return dev_err_probe(dev, ret,
1224 "irq request error (dma_tx)\n");
1225
1226 ret = devm_request_irq(dev, ssi->irq_rx,
1227 rz_ssi_interrupt, 0,
1228 dev_name(dev), ssi);
1229 if (ret < 0)
1230 return dev_err_probe(dev, ret,
1231 "irq request error (dma_rx)\n");
1232 }
1233 }
1234
1235 ssi->rstc = devm_reset_control_get_exclusive(dev, NULL);
1236 if (IS_ERR(ssi->rstc)) {
1237 ret = PTR_ERR(ssi->rstc);
1238 goto err_release_dma_chs;
1239 }
1240
1241 /* Default 0 for power saving. Can be overridden via sysfs. */
1242 pm_runtime_set_autosuspend_delay(dev, 0);
1243 pm_runtime_use_autosuspend(dev);
1244 ret = devm_pm_runtime_enable(dev);
1245 if (ret < 0) {
1246 dev_err(dev, "Failed to enable runtime PM!\n");
1247 goto err_release_dma_chs;
1248 }
1249
1250 ret = devm_snd_soc_register_component(dev, &rz_ssi_soc_component,
1251 rz_ssi_soc_dai,
1252 ARRAY_SIZE(rz_ssi_soc_dai));
1253 if (ret < 0) {
1254 dev_err(dev, "failed to register snd component\n");
1255 goto err_release_dma_chs;
1256 }
1257
1258 return 0;
1259
1260 err_release_dma_chs:
1261 rz_ssi_release_dma_channels(ssi);
1262
1263 return ret;
1264 }
1265
rz_ssi_remove(struct platform_device * pdev)1266 static void rz_ssi_remove(struct platform_device *pdev)
1267 {
1268 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
1269
1270 rz_ssi_release_dma_channels(ssi);
1271
1272 reset_control_assert(ssi->rstc);
1273 }
1274
1275 static const struct of_device_id rz_ssi_of_match[] = {
1276 { .compatible = "renesas,rz-ssi", },
1277 { /* Sentinel */ }
1278 };
1279 MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
1280
rz_ssi_runtime_suspend(struct device * dev)1281 static int rz_ssi_runtime_suspend(struct device *dev)
1282 {
1283 struct rz_ssi_priv *ssi = dev_get_drvdata(dev);
1284
1285 return reset_control_assert(ssi->rstc);
1286 }
1287
rz_ssi_runtime_resume(struct device * dev)1288 static int rz_ssi_runtime_resume(struct device *dev)
1289 {
1290 struct rz_ssi_priv *ssi = dev_get_drvdata(dev);
1291
1292 return reset_control_deassert(ssi->rstc);
1293 }
1294
1295 static const struct dev_pm_ops rz_ssi_pm_ops = {
1296 RUNTIME_PM_OPS(rz_ssi_runtime_suspend, rz_ssi_runtime_resume, NULL)
1297 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1298 };
1299
1300 static struct platform_driver rz_ssi_driver = {
1301 .driver = {
1302 .name = "rz-ssi-pcm-audio",
1303 .of_match_table = rz_ssi_of_match,
1304 .pm = pm_ptr(&rz_ssi_pm_ops),
1305 },
1306 .probe = rz_ssi_probe,
1307 .remove = rz_ssi_remove,
1308 };
1309
1310 module_platform_driver(rz_ssi_driver);
1311
1312 MODULE_LICENSE("GPL v2");
1313 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
1314 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1315