1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * KUnit tests for amdgpu_dm_plane.c
4 *
5 * Copyright 2026 Advanced Micro Devices, Inc.
6 */
7
8 #include <kunit/test.h>
9 #include <drm/drm_atomic.h>
10 #include <drm/drm_blend.h>
11 #include "link_enc_cfg.h"
12 #include "amdgpu_dm_plane.h"
13 #include "amdgpu_rlc.h"
14 #include "gc/gc_11_0_0_offset.h"
15 #include "gc/gc_11_0_0_sh_mask.h"
16 #include <drm/amdgpu_drm.h>
17 #include <drm/drm_plane.h>
18
19 struct dm_test_dcc_cap_ctx {
20 bool callback_ret;
21 bool capable;
22 bool output_independent_64b_blks;
23 bool called;
24 struct dc_dcc_surface_param captured_input;
25 };
26
27 static struct dm_test_dcc_cap_ctx *dm_test_dcc_ctx;
28
29 struct dm_test_gfx11_reg_ctx {
30 u32 gb_addr_config;
31 u32 gc_reg_offsets[1];
32 u32 expected_reg;
33 u32 captured_reg;
34 u32 captured_acc_flags;
35 u32 captured_hwip;
36 u32 captured_xcc_id;
37 bool called;
38 };
39
40 static struct dm_test_gfx11_reg_ctx *dm_test_gfx11_reg_ctx;
41
dm_test_gfx11_rreg32(struct amdgpu_device * adev,u32 reg,u32 acc_flags,u32 hwip,u32 xcc_id)42 static u32 dm_test_gfx11_rreg32(struct amdgpu_device *adev,
43 u32 reg, u32 acc_flags, u32 hwip,
44 u32 xcc_id)
45 {
46 if (!dm_test_gfx11_reg_ctx)
47 return 0;
48
49 dm_test_gfx11_reg_ctx->called = true;
50 dm_test_gfx11_reg_ctx->captured_reg = reg;
51 dm_test_gfx11_reg_ctx->captured_acc_flags = acc_flags;
52 dm_test_gfx11_reg_ctx->captured_hwip = hwip;
53 dm_test_gfx11_reg_ctx->captured_xcc_id = xcc_id;
54
55 return dm_test_gfx11_reg_ctx->gb_addr_config;
56 }
57
58 static const struct amdgpu_rlc_reg_funcs dm_test_gfx11_reg_funcs = {
59 .rreg32 = dm_test_gfx11_rreg32,
60 };
61
dm_test_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)62 static bool dm_test_get_dcc_compression_cap(const struct dc *dc,
63 const struct dc_dcc_surface_param *input,
64 struct dc_surface_dcc_cap *output)
65 {
66 if (!dm_test_dcc_ctx)
67 return false;
68
69 dm_test_dcc_ctx->called = true;
70 dm_test_dcc_ctx->captured_input = *input;
71 output->capable = dm_test_dcc_ctx->capable;
72 output->grph.rgb.independent_64b_blks = dm_test_dcc_ctx->output_independent_64b_blks;
73
74 return dm_test_dcc_ctx->callback_ret;
75 }
76
dm_test_init_validate_dcc_inputs(struct amdgpu_device ** adev,struct dc ** dc,struct dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address,struct plane_size * plane_size,struct kunit * test)77 static void dm_test_init_validate_dcc_inputs(struct amdgpu_device **adev,
78 struct dc **dc,
79 struct dc_tiling_info *tiling_info,
80 struct dc_plane_dcc_param *dcc,
81 struct dc_plane_address *address,
82 struct plane_size *plane_size,
83 struct kunit *test)
84 {
85 *adev = kunit_kzalloc(test, sizeof(**adev), GFP_KERNEL);
86 *dc = kunit_kzalloc(test, sizeof(**dc), GFP_KERNEL);
87 KUNIT_ASSERT_NOT_NULL(test, *adev);
88 KUNIT_ASSERT_NOT_NULL(test, *dc);
89
90 (*adev)->dm.dc = *dc;
91 (*adev)->family = AMDGPU_FAMILY_NV;
92
93 tiling_info->gfx9.swizzle = 9;
94 dcc->enable = 1;
95 dcc->independent_64b_blks = 1;
96 plane_size->surface_size.width = 1920;
97 plane_size->surface_size.height = 1080;
98
99 (void)address;
100 }
101
102
103 /**
104 * dm_test_plane_is_video_format_known_video() - Verify known video formats.
105 * @test: KUnit test context.
106 *
107 * Verify if NV12, NV21, and P010 are treated as video formats.
108 */
dm_test_plane_is_video_format_known_video(struct kunit * test)109 static void dm_test_plane_is_video_format_known_video(struct kunit *test)
110 {
111 KUNIT_EXPECT_TRUE(test, amdgpu_dm_plane_is_video_format(DRM_FORMAT_NV12));
112 KUNIT_EXPECT_TRUE(test, amdgpu_dm_plane_is_video_format(DRM_FORMAT_NV21));
113 KUNIT_EXPECT_TRUE(test, amdgpu_dm_plane_is_video_format(DRM_FORMAT_P010));
114 }
115
116 /**
117 * dm_test_fill_blending_defaults() - Verify default blending output values.
118 * @test: KUnit test context.
119 *
120 * Verify if default blending output values are used for opaque alpha and no
121 * per-pixel blending.
122 */
dm_test_fill_blending_defaults(struct kunit * test)123 static void dm_test_fill_blending_defaults(struct kunit *test)
124 {
125 struct drm_plane_state state = { 0 };
126 bool per_pixel_alpha;
127 bool pre_multiplied_alpha;
128 bool global_alpha;
129 int global_alpha_value;
130
131 state.pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
132 state.alpha = 0xffff;
133
134 amdgpu_dm_plane_fill_blending_from_plane_state(&state,
135 &per_pixel_alpha,
136 &pre_multiplied_alpha,
137 &global_alpha,
138 &global_alpha_value);
139
140 KUNIT_EXPECT_FALSE(test, per_pixel_alpha);
141 KUNIT_EXPECT_TRUE(test, pre_multiplied_alpha);
142 KUNIT_EXPECT_FALSE(test, global_alpha);
143 KUNIT_EXPECT_EQ(test, global_alpha_value, 0xff);
144 }
145
146 /**
147 * dm_test_fill_blending_premulti_alpha_format() - Verify premultiplied alpha path.
148 * @test: KUnit test context.
149 *
150 * Verify if premultiplied mode enables per-pixel alpha for ARGB8888.
151 */
dm_test_fill_blending_premulti_alpha_format(struct kunit * test)152 static void dm_test_fill_blending_premulti_alpha_format(struct kunit *test)
153 {
154 struct drm_plane_state state = { 0 };
155 struct drm_framebuffer fb = { 0 };
156 bool per_pixel_alpha;
157 bool pre_multiplied_alpha;
158 bool global_alpha;
159 int global_alpha_value;
160
161 fb.format = drm_format_info(DRM_FORMAT_ARGB8888);
162 KUNIT_ASSERT_NOT_NULL(test, fb.format);
163
164 state.fb = &fb;
165 state.pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
166 state.alpha = 0xffff;
167
168 amdgpu_dm_plane_fill_blending_from_plane_state(&state,
169 &per_pixel_alpha,
170 &pre_multiplied_alpha,
171 &global_alpha,
172 &global_alpha_value);
173
174 KUNIT_EXPECT_TRUE(test, per_pixel_alpha);
175 KUNIT_EXPECT_TRUE(test, pre_multiplied_alpha);
176 KUNIT_EXPECT_FALSE(test, global_alpha);
177 KUNIT_EXPECT_EQ(test, global_alpha_value, 0xff);
178 }
179
180 /**
181 * dm_test_fill_blending_coverage_alpha_format() - Verify coverage mode behavior.
182 * @test: KUnit test context.
183 *
184 * Verify if coverage mode sets per-pixel alpha and disables
185 * pre_multiplied_alpha for ARGB8888.
186 */
dm_test_fill_blending_coverage_alpha_format(struct kunit * test)187 static void dm_test_fill_blending_coverage_alpha_format(struct kunit *test)
188 {
189 struct drm_plane_state state = { 0 };
190 struct drm_framebuffer fb = { 0 };
191 bool per_pixel_alpha;
192 bool pre_multiplied_alpha;
193 bool global_alpha;
194 int global_alpha_value;
195
196 fb.format = drm_format_info(DRM_FORMAT_ARGB8888);
197 KUNIT_ASSERT_NOT_NULL(test, fb.format);
198
199 state.fb = &fb;
200 state.pixel_blend_mode = DRM_MODE_BLEND_COVERAGE;
201 state.alpha = 0xffff;
202
203 amdgpu_dm_plane_fill_blending_from_plane_state(&state,
204 &per_pixel_alpha,
205 &pre_multiplied_alpha,
206 &global_alpha,
207 &global_alpha_value);
208
209 KUNIT_EXPECT_TRUE(test, per_pixel_alpha);
210 KUNIT_EXPECT_FALSE(test, pre_multiplied_alpha);
211 KUNIT_EXPECT_FALSE(test, global_alpha);
212 KUNIT_EXPECT_EQ(test, global_alpha_value, 0xff);
213 }
214
215 /**
216 * dm_test_fill_blending_global_alpha() - Verify global alpha conversion to 8 bits.
217 * @test: KUnit test context.
218 *
219 * Verify if global alpha is enabled and converted from 16-bit to 8-bit.
220 */
dm_test_fill_blending_global_alpha(struct kunit * test)221 static void dm_test_fill_blending_global_alpha(struct kunit *test)
222 {
223 struct amdgpu_device *adev;
224 struct drm_plane *plane;
225 struct drm_plane_state *state;
226 bool per_pixel_alpha;
227 bool pre_multiplied_alpha;
228 bool global_alpha;
229 int global_alpha_value;
230
231 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
232 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
233 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
234 KUNIT_ASSERT_NOT_NULL(test, adev);
235 KUNIT_ASSERT_NOT_NULL(test, plane);
236 KUNIT_ASSERT_NOT_NULL(test, state);
237
238 plane->dev = &adev->ddev;
239 state->plane = plane;
240 state->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
241 state->alpha = 0x8000;
242
243 amdgpu_dm_plane_fill_blending_from_plane_state(state,
244 &per_pixel_alpha,
245 &pre_multiplied_alpha,
246 &global_alpha,
247 &global_alpha_value);
248
249 KUNIT_EXPECT_FALSE(test, per_pixel_alpha);
250 KUNIT_EXPECT_TRUE(test, pre_multiplied_alpha);
251 KUNIT_EXPECT_TRUE(test, global_alpha);
252 KUNIT_EXPECT_EQ(test, global_alpha_value, 0x80);
253 }
254
255 /**
256 * dm_test_modifier_has_dcc() - Verify helper detects AMD DCC modifiers.
257 * @test: KUnit test context.
258 *
259 * Verify if DCC detection works for linear and AMD DCC modifiers.
260 */
dm_test_modifier_has_dcc(struct kunit * test)261 static void dm_test_modifier_has_dcc(struct kunit *test)
262 {
263 uint64_t dcc_mod = AMD_FMT_MOD | AMD_FMT_MOD_SET(DCC, 1);
264
265 KUNIT_EXPECT_FALSE(test, amdgpu_dm_plane_modifier_has_dcc(DRM_FORMAT_MOD_LINEAR));
266 KUNIT_EXPECT_TRUE(test, amdgpu_dm_plane_modifier_has_dcc(dcc_mod));
267 }
268
269 /**
270 * dm_test_modifier_gfx9_swizzle_mode() - Verify swizzle helper for linear and AMD modifiers.
271 * @test: KUnit test context.
272 *
273 * Verify if swizzle mode decoding works for linear and AMD tiled modifiers.
274 */
dm_test_modifier_gfx9_swizzle_mode(struct kunit * test)275 static void dm_test_modifier_gfx9_swizzle_mode(struct kunit *test)
276 {
277 uint64_t mod = AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X);
278
279 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_modifier_gfx9_swizzle_mode(DRM_FORMAT_MOD_LINEAR), 0U);
280 KUNIT_EXPECT_EQ(test,
281 amdgpu_dm_plane_modifier_gfx9_swizzle_mode(mod),
282 (unsigned int)AMD_FMT_MOD_TILE_GFX9_64K_S_X);
283 }
284
285 /**
286 * dm_test_get_plane_formats() - Verify plane format counts for key plane types.
287 * @test: KUnit test context.
288 *
289 * Verify if returned format counts match primary, overlay, and cursor planes.
290 */
dm_test_get_plane_formats(struct kunit * test)291 static void dm_test_get_plane_formats(struct kunit *test)
292 {
293 struct drm_plane *plane;
294 struct dc_plane_cap *cap;
295 uint32_t formats[32] = {0};
296
297 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
298 cap = kunit_kzalloc(test, sizeof(*cap), GFP_KERNEL);
299 KUNIT_ASSERT_NOT_NULL(test, plane);
300 KUNIT_ASSERT_NOT_NULL(test, cap);
301
302 plane->type = DRM_PLANE_TYPE_PRIMARY;
303 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_plane_formats(plane, NULL, formats, 32), 14);
304
305 cap->pixel_format_support.nv12 = true;
306 cap->pixel_format_support.p010 = true;
307 cap->pixel_format_support.fp16 = true;
308 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_plane_formats(plane, cap, formats, 32), 20);
309
310 plane->type = DRM_PLANE_TYPE_OVERLAY;
311 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_plane_formats(plane, NULL, formats, 32), 9);
312
313 plane->type = DRM_PLANE_TYPE_CURSOR;
314 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_get_plane_formats(plane, NULL, formats, 32), 1);
315 }
316
317 /**
318 * dm_test_get_plane_modifiers() - Verify early-return and cursor modifier list.
319 * @test: KUnit test context.
320 *
321 * Verify if modifier list handling works for unsupported families and cursor planes.
322 */
dm_test_get_plane_modifiers(struct kunit * test)323 static void dm_test_get_plane_modifiers(struct kunit *test)
324 {
325 struct amdgpu_device *adev;
326 uint64_t *mods = NULL;
327
328 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
329 KUNIT_ASSERT_NOT_NULL(test, adev);
330
331 adev->family = AMDGPU_FAMILY_NV;
332 KUNIT_ASSERT_EQ(test,
333 amdgpu_dm_plane_get_plane_modifiers(adev, DRM_PLANE_TYPE_CURSOR, &mods),
334 0);
335 KUNIT_ASSERT_NOT_NULL(test, mods);
336 KUNIT_EXPECT_EQ(test, mods[0], DRM_FORMAT_MOD_LINEAR);
337 KUNIT_EXPECT_EQ(test, mods[1], DRM_FORMAT_MOD_INVALID);
338 kfree(mods);
339 }
340
341 /**
342 * dm_test_fill_dc_scaling_info() - Verify basic error and success paths.
343 * @test: KUnit test context.
344 *
345 * Verify if scaling info rejects invalid sizes and accepts valid sizes.
346 */
dm_test_fill_dc_scaling_info(struct kunit * test)347 static void dm_test_fill_dc_scaling_info(struct kunit *test)
348 {
349 struct amdgpu_device *adev;
350 struct drm_plane_state state = {0};
351 struct dc_scaling_info info = {0};
352
353 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
354 KUNIT_ASSERT_NOT_NULL(test, adev);
355
356 state.src_w = 0;
357 state.src_h = 100 << 16;
358 state.crtc_w = 100;
359 state.crtc_h = 100;
360 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_fill_dc_scaling_info(adev, &state, &info), -EINVAL);
361
362 state.src_w = 100 << 16;
363 state.src_h = 100 << 16;
364 state.crtc_w = 100;
365 state.crtc_h = 100;
366 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_fill_dc_scaling_info(adev, &state, &info), 0);
367 }
368
369 /**
370 * dm_test_get_min_max_dc_plane_scaling() - Verify format-specific cap selection and 1->1000 conversion.
371 * @test: KUnit test context.
372 *
373 * Verify if min/max scaling values are correct for NV12 and XRGB8888 formats.
374 */
dm_test_get_min_max_dc_plane_scaling(struct kunit * test)375 static void dm_test_get_min_max_dc_plane_scaling(struct kunit *test)
376 {
377 struct amdgpu_device *adev;
378 struct dc *dc;
379 struct drm_framebuffer *fb;
380 int min_downscale = 0;
381 int max_upscale = 0;
382
383 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
384 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
385 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
386 KUNIT_ASSERT_NOT_NULL(test, adev);
387 KUNIT_ASSERT_NOT_NULL(test, dc);
388 KUNIT_ASSERT_NOT_NULL(test, fb);
389
390 adev->dm.dc = dc;
391 dc->caps.planes[0].max_upscale_factor.nv12 = 1;
392 dc->caps.planes[0].max_downscale_factor.nv12 = 1;
393 dc->caps.planes[0].max_upscale_factor.argb8888 = 1600;
394 dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
395
396 fb->format = drm_format_info(DRM_FORMAT_NV12);
397 KUNIT_ASSERT_NOT_NULL(test, fb->format);
398 amdgpu_dm_plane_get_min_max_dc_plane_scaling(&adev->ddev, fb, &min_downscale, &max_upscale);
399 KUNIT_EXPECT_EQ(test, min_downscale, 1000);
400 KUNIT_EXPECT_EQ(test, max_upscale, 1000);
401
402 fb->format = drm_format_info(DRM_FORMAT_XRGB8888);
403 KUNIT_ASSERT_NOT_NULL(test, fb->format);
404 amdgpu_dm_plane_get_min_max_dc_plane_scaling(&adev->ddev, fb, &min_downscale, &max_upscale);
405 KUNIT_EXPECT_EQ(test, min_downscale, 250);
406 KUNIT_EXPECT_EQ(test, max_upscale, 1600);
407 }
408
409 /**
410 * dm_test_get_cursor_position() - Verify cursor clipping and off-screen handling.
411 * @test: KUnit test context.
412 *
413 * Verify if cursor clipping, hotspot adjustment, and off-screen disable behavior work.
414 */
dm_test_get_cursor_position(struct kunit * test)415 static void dm_test_get_cursor_position(struct kunit *test)
416 {
417 struct amdgpu_device *adev;
418 struct amdgpu_crtc *amdgpu_crtc;
419 struct drm_plane *plane;
420 struct drm_plane_state *state;
421 struct drm_framebuffer *fb;
422 struct dc_cursor_position position = {0};
423
424 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
425 amdgpu_crtc = kunit_kzalloc(test, sizeof(*amdgpu_crtc), GFP_KERNEL);
426 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
427 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
428 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
429 KUNIT_ASSERT_NOT_NULL(test, adev);
430 KUNIT_ASSERT_NOT_NULL(test, amdgpu_crtc);
431 KUNIT_ASSERT_NOT_NULL(test, plane);
432 KUNIT_ASSERT_NOT_NULL(test, state);
433 KUNIT_ASSERT_NOT_NULL(test, fb);
434
435 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 0);
436 amdgpu_crtc->max_cursor_width = 64;
437 amdgpu_crtc->max_cursor_height = 64;
438
439 plane->dev = &adev->ddev;
440 plane->state = state;
441 state->fb = fb;
442 state->crtc_x = -5;
443 state->crtc_y = -7;
444 state->crtc_w = 32;
445 state->crtc_h = 32;
446
447 KUNIT_ASSERT_EQ(test,
448 amdgpu_dm_plane_get_cursor_position(plane, &amdgpu_crtc->base, &position),
449 0);
450 KUNIT_EXPECT_TRUE(test, position.enable);
451 KUNIT_EXPECT_EQ(test, position.x, 0);
452 KUNIT_EXPECT_EQ(test, position.y, 0);
453 KUNIT_EXPECT_EQ(test, position.x_hotspot, 5);
454 KUNIT_EXPECT_EQ(test, position.y_hotspot, 7);
455 KUNIT_EXPECT_TRUE(test, position.translate_by_source);
456
457 memset(&position, 0, sizeof(position));
458 state->crtc_x = -64;
459 state->crtc_y = 0;
460 KUNIT_ASSERT_EQ(test,
461 amdgpu_dm_plane_get_cursor_position(plane, &amdgpu_crtc->base, &position),
462 0);
463 KUNIT_EXPECT_FALSE(test, position.enable);
464 }
465
466 /**
467 * dm_test_format_mod_supported() - Verify key format/modifier acceptance and rejection paths.
468 * @test: KUnit test context.
469 *
470 * Verify if format-modifier support checks match accepted and rejected cases.
471 */
dm_test_format_mod_supported(struct kunit * test)472 static void dm_test_format_mod_supported(struct kunit *test)
473 {
474 struct amdgpu_device *adev;
475 struct drm_plane *plane;
476 uint64_t listed_mod;
477
478 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
479 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
480 KUNIT_ASSERT_NOT_NULL(test, adev);
481 KUNIT_ASSERT_NOT_NULL(test, plane);
482
483 adev->family = AMDGPU_FAMILY_NV;
484 plane->dev = &adev->ddev;
485
486 KUNIT_EXPECT_TRUE(test,
487 amdgpu_dm_plane_format_mod_supported(plane, DRM_FORMAT_XRGB8888,
488 DRM_FORMAT_MOD_LINEAR));
489 KUNIT_EXPECT_TRUE(test,
490 amdgpu_dm_plane_format_mod_supported(plane, DRM_FORMAT_XRGB8888,
491 DRM_FORMAT_MOD_INVALID));
492
493 KUNIT_EXPECT_FALSE(test,
494 amdgpu_dm_plane_format_mod_supported(plane, DRM_FORMAT_XRGB8888,
495 DRM_FORMAT_MOD_VENDOR_AMD));
496
497 listed_mod = AMD_FMT_MOD |
498 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
499 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
500 AMD_FMT_MOD_SET(DCC, 1);
501 plane->modifiers = &listed_mod;
502 plane->modifier_count = 1;
503
504 KUNIT_EXPECT_FALSE(test,
505 amdgpu_dm_plane_format_mod_supported(plane, DRM_FORMAT_NV12, listed_mod));
506 }
507
508 /**
509 * dm_test_fill_gfx12_plane_attributes_from_modifiers() - Verify GFX12 DCC mapping path.
510 * @test: KUnit test context.
511 *
512 * Verify if GFX12 modifier parsing enables DCC and sets expected DCC block mode.
513 */
dm_test_fill_gfx12_plane_attributes_from_modifiers(struct kunit * test)514 static void dm_test_fill_gfx12_plane_attributes_from_modifiers(struct kunit *test)
515 {
516 struct amdgpu_device *adev;
517 struct dc *dc;
518 struct amdgpu_framebuffer *afb;
519 struct plane_size plane_size = {0};
520 struct dc_tiling_info tiling_info = {0};
521 struct dc_plane_dcc_param dcc = {0};
522 struct dc_plane_address address = {0};
523 struct dm_test_dcc_cap_ctx ctx = {
524 .callback_ret = true,
525 .capable = true,
526 .output_independent_64b_blks = false,
527 };
528
529 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
530 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
531 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
532 KUNIT_ASSERT_NOT_NULL(test, adev);
533 KUNIT_ASSERT_NOT_NULL(test, dc);
534 KUNIT_ASSERT_NOT_NULL(test, afb);
535
536 adev->family = AMDGPU_FAMILY_GC_12_0_0;
537 adev->dm.dc = dc;
538 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
539 adev->gfx.config.gb_addr_config_fields.num_banks = 4;
540 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256;
541 adev->gfx.config.gb_addr_config_fields.num_se = 1;
542 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2;
543 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1;
544 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
545 dm_test_dcc_ctx = &ctx;
546
547 afb->base.modifier = AMD_FMT_MOD |
548 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) |
549 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
550 AMD_FMT_MOD_SET(DCC, 1) |
551 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 1);
552 plane_size.surface_size.width = 1920;
553 plane_size.surface_size.height = 1080;
554
555 KUNIT_EXPECT_EQ(test,
556 amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers(
557 adev, afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
558 ROTATION_ANGLE_0, &plane_size, &tiling_info, &dcc, &address),
559 0);
560 KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxAddr3);
561 KUNIT_EXPECT_TRUE(test, dcc.enable);
562 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_128b);
563
564 dm_test_dcc_ctx = NULL;
565 }
566
567 /**
568 * dm_test_fill_gfx9_plane_attributes_from_modifiers() - Verify basic GFX9 linear modifier path.
569 * @test: KUnit test context.
570 *
571 * Verify if GFX9 linear modifier handling keeps DCC disabled.
572 */
dm_test_fill_gfx9_plane_attributes_from_modifiers(struct kunit * test)573 static void dm_test_fill_gfx9_plane_attributes_from_modifiers(struct kunit *test)
574 {
575 struct amdgpu_device *adev;
576 struct amdgpu_framebuffer *afb;
577 struct plane_size plane_size = {0};
578 struct dc_tiling_info tiling_info = {0};
579 struct dc_plane_dcc_param dcc = {0};
580 struct dc_plane_address address = {0};
581
582 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
583 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
584 KUNIT_ASSERT_NOT_NULL(test, adev);
585 KUNIT_ASSERT_NOT_NULL(test, afb);
586
587 adev->family = AMDGPU_FAMILY_NV;
588 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
589 adev->gfx.config.gb_addr_config_fields.num_banks = 4;
590 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256;
591 adev->gfx.config.gb_addr_config_fields.num_se = 1;
592 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2;
593 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1;
594 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
595 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
596
597 afb->base.modifier = DRM_FORMAT_MOD_LINEAR;
598
599 KUNIT_EXPECT_EQ(test,
600 amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers(
601 adev, afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
602 ROTATION_ANGLE_0, &plane_size, &tiling_info, &dcc, &address),
603 0);
604 KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxVersion9);
605 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.swizzle, 0U);
606 KUNIT_EXPECT_FALSE(test, dcc.enable);
607 }
608
609 /**
610 * dm_test_helper_check_state_viewport_reject() - Verify viewport outside screen rejects state.
611 * @test: KUnit test context.
612 *
613 * Verify if plane state is rejected when the viewport is outside display bounds.
614 */
dm_test_helper_check_state_viewport_reject(struct kunit * test)615 static void dm_test_helper_check_state_viewport_reject(struct kunit *test)
616 {
617 struct drm_plane *plane;
618 struct drm_plane_state *state;
619 struct drm_crtc *crtc;
620 struct drm_crtc_state *new_crtc_state;
621 struct drm_framebuffer *fb;
622
623 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
624 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
625 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
626 new_crtc_state = kunit_kzalloc(test, sizeof(*new_crtc_state), GFP_KERNEL);
627 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
628 KUNIT_ASSERT_NOT_NULL(test, plane);
629 KUNIT_ASSERT_NOT_NULL(test, state);
630 KUNIT_ASSERT_NOT_NULL(test, crtc);
631 KUNIT_ASSERT_NOT_NULL(test, new_crtc_state);
632 KUNIT_ASSERT_NOT_NULL(test, fb);
633
634 plane->type = DRM_PLANE_TYPE_OVERLAY;
635 state->plane = plane;
636 state->fb = fb;
637 state->crtc = crtc;
638 state->crtc_x = 200;
639 state->crtc_y = 0;
640 state->crtc_w = 100;
641 state->crtc_h = 100;
642 new_crtc_state->mode.crtc_hdisplay = 100;
643 new_crtc_state->mode.crtc_vdisplay = 100;
644
645 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_helper_check_state(state, new_crtc_state), -EINVAL);
646 }
647
648 /**
649 * dm_test_validate_dcc_disabled_returns_success() - Verify disabled DCC is accepted.
650 * @test: KUnit test context.
651 *
652 * Verify if DCC validation succeeds when DCC is disabled.
653 */
dm_test_validate_dcc_disabled_returns_success(struct kunit * test)654 static void dm_test_validate_dcc_disabled_returns_success(struct kunit *test)
655 {
656 struct amdgpu_device *adev;
657 struct dc *dc;
658 struct dc_tiling_info tiling_info = {0};
659 struct dc_plane_dcc_param dcc = {0};
660 struct dc_plane_address address = {0};
661 struct plane_size plane_size = {0};
662
663 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
664 &plane_size, test);
665 dcc.enable = 0;
666
667 KUNIT_EXPECT_EQ(test,
668 amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
669 ROTATION_ANGLE_0, &tiling_info, &dcc,
670 &address, &plane_size),
671 0);
672 }
673
674 /**
675 * dm_test_validate_dcc_video_non_gfx12_fails() - Verify video format restriction on pre-GFX12.
676 * @test: KUnit test context.
677 *
678 * Verify if video format DCC validation fails on non-GFX12 devices.
679 */
dm_test_validate_dcc_video_non_gfx12_fails(struct kunit * test)680 static void dm_test_validate_dcc_video_non_gfx12_fails(struct kunit *test)
681 {
682 struct amdgpu_device *adev;
683 struct dc *dc;
684 struct dc_tiling_info tiling_info = {0};
685 struct dc_plane_dcc_param dcc = {0};
686 struct dc_plane_address address = {0};
687 struct plane_size plane_size = {0};
688
689 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
690 &plane_size, test);
691 adev->family = AMDGPU_FAMILY_NV;
692
693 KUNIT_EXPECT_EQ(test,
694 amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr,
695 ROTATION_ANGLE_0, &tiling_info, &dcc,
696 &address, &plane_size),
697 -EINVAL);
698 }
699
700 /**
701 * dm_test_validate_dcc_missing_cap_func_fails() - Verify missing capability callback fails.
702 * @test: KUnit test context.
703 *
704 * Verify if validation fails when DCC capability callback is not provided.
705 */
dm_test_validate_dcc_missing_cap_func_fails(struct kunit * test)706 static void dm_test_validate_dcc_missing_cap_func_fails(struct kunit *test)
707 {
708 struct amdgpu_device *adev;
709 struct dc *dc;
710 struct dc_tiling_info tiling_info = {0};
711 struct dc_plane_dcc_param dcc = {0};
712 struct dc_plane_address address = {0};
713 struct plane_size plane_size = {0};
714
715 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
716 &plane_size, test);
717 dc->cap_funcs.get_dcc_compression_cap = NULL;
718
719 KUNIT_EXPECT_EQ(test,
720 amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
721 ROTATION_ANGLE_0, &tiling_info, &dcc,
722 &address, &plane_size),
723 -EINVAL);
724 }
725
726 /**
727 * dm_test_validate_dcc_cap_callback_fails() - Verify callback failure path.
728 * @test: KUnit test context.
729 *
730 * Verify if validation fails when the DCC capability callback returns false.
731 */
dm_test_validate_dcc_cap_callback_fails(struct kunit * test)732 static void dm_test_validate_dcc_cap_callback_fails(struct kunit *test)
733 {
734 struct amdgpu_device *adev;
735 struct dc *dc;
736 struct dc_tiling_info tiling_info = {0};
737 struct dc_plane_dcc_param dcc = {0};
738 struct dc_plane_address address = {0};
739 struct plane_size plane_size = {0};
740 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
741 enum dc_rotation_angle rotation = ROTATION_ANGLE_0;
742 struct dm_test_dcc_cap_ctx ctx = {
743 .callback_ret = false,
744 .capable = true,
745 };
746 int ret;
747
748 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
749 &plane_size, test);
750 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
751 dm_test_dcc_ctx = &ctx;
752
753 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, &tiling_info,
754 &dcc, &address, &plane_size);
755 KUNIT_EXPECT_EQ(test, ret, -EINVAL);
756 KUNIT_EXPECT_TRUE(test, ctx.called);
757
758 dm_test_dcc_ctx = NULL;
759 }
760
761 /**
762 * dm_test_validate_dcc_not_capable_fails() - Verify not-capable callback output.
763 * @test: KUnit test context.
764 *
765 * Verify if validation fails when the DCC capability callback reports that the
766 * surface is not DCC capable.
767 */
dm_test_validate_dcc_not_capable_fails(struct kunit * test)768 static void dm_test_validate_dcc_not_capable_fails(struct kunit *test)
769 {
770 struct amdgpu_device *adev;
771 struct dc *dc;
772 struct dc_tiling_info tiling_info = {0};
773 struct dc_plane_dcc_param dcc = {0};
774 struct dc_plane_address address = {0};
775 struct plane_size plane_size = {0};
776 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
777 enum dc_rotation_angle rotation = ROTATION_ANGLE_0;
778 struct dm_test_dcc_cap_ctx ctx = {
779 .callback_ret = true,
780 .capable = false,
781 };
782 int ret;
783
784 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
785 &plane_size, test);
786 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
787 dm_test_dcc_ctx = &ctx;
788
789 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, &tiling_info,
790 &dcc, &address, &plane_size);
791 KUNIT_EXPECT_EQ(test, ret, -EINVAL);
792 KUNIT_EXPECT_TRUE(test, ctx.called);
793
794 dm_test_dcc_ctx = NULL;
795 }
796
797 /**
798 * dm_test_validate_dcc_success_and_scan_mapping() - Verify success path and rotation-to-scan mapping.
799 * @test: KUnit test context.
800 *
801 * Verify if DCC validation succeeds and rotation-to-scan mapping is correct.
802 */
dm_test_validate_dcc_success_and_scan_mapping(struct kunit * test)803 static void dm_test_validate_dcc_success_and_scan_mapping(struct kunit *test)
804 {
805 struct amdgpu_device *adev;
806 struct dc *dc;
807 struct dc_tiling_info tiling_info = {0};
808 struct dc_plane_dcc_param dcc = {0};
809 struct dc_plane_address address = {0};
810 struct plane_size plane_size = {0};
811 struct dm_test_dcc_cap_ctx ctx = {
812 .callback_ret = true,
813 .capable = true,
814 .output_independent_64b_blks = true,
815 };
816
817 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
818 &plane_size, test);
819 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
820 dm_test_dcc_ctx = &ctx;
821
822 KUNIT_EXPECT_EQ(test,
823 amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
824 ROTATION_ANGLE_90, &tiling_info, &dcc,
825 &address, &plane_size),
826 0);
827 KUNIT_EXPECT_TRUE(test, ctx.called);
828 KUNIT_EXPECT_EQ(test, (int)ctx.captured_input.scan, (int)SCAN_DIRECTION_VERTICAL);
829 KUNIT_EXPECT_EQ(test, (int)ctx.captured_input.format,
830 (int)SURFACE_PIXEL_FORMAT_GRPH_ARGB8888);
831
832 dm_test_dcc_ctx = NULL;
833 }
834
835 /**
836 * dm_test_validate_dcc_independent_64b_mismatch_fails() - Verify 64B compatibility check.
837 * @test: KUnit test context.
838 *
839 * Verify if validation fails when independent_64b_blks values do not match.
840 */
dm_test_validate_dcc_independent_64b_mismatch_fails(struct kunit * test)841 static void dm_test_validate_dcc_independent_64b_mismatch_fails(struct kunit *test)
842 {
843 struct amdgpu_device *adev;
844 struct dc *dc;
845 struct dc_tiling_info tiling_info = {0};
846 struct dc_plane_dcc_param dcc = {0};
847 struct dc_plane_address address = {0};
848 struct plane_size plane_size = {0};
849 struct dm_test_dcc_cap_ctx ctx = {
850 .callback_ret = true,
851 .capable = true,
852 .output_independent_64b_blks = true,
853 };
854
855 dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
856 &plane_size, test);
857 dcc.independent_64b_blks = 0;
858 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
859 dm_test_dcc_ctx = &ctx;
860
861 KUNIT_EXPECT_EQ(test,
862 amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
863 ROTATION_ANGLE_0, &tiling_info, &dcc,
864 &address, &plane_size),
865 -EINVAL);
866
867 dm_test_dcc_ctx = NULL;
868 }
869
870 /**
871 * dm_test_add_modifier_appends_value() - Verify one modifier append.
872 * @test: KUnit test context.
873 *
874 * Verify if a modifier is appended and size is updated.
875 */
dm_test_add_modifier_appends_value(struct kunit * test)876 static void dm_test_add_modifier_appends_value(struct kunit *test)
877 {
878 uint64_t size = 0;
879 uint64_t cap = 2;
880 uint64_t *mods = kmalloc_array(cap, sizeof(*mods), GFP_KERNEL);
881
882 KUNIT_ASSERT_NOT_NULL(test, mods);
883
884 amdgpu_dm_plane_add_modifier(&mods, &size, &cap, 0x1234ULL);
885
886 KUNIT_ASSERT_NOT_NULL(test, mods);
887 KUNIT_EXPECT_EQ(test, size, 1ULL);
888 KUNIT_EXPECT_EQ(test, cap, 2ULL);
889 KUNIT_EXPECT_EQ(test, mods[0], 0x1234ULL);
890
891 kfree(mods);
892 }
893
894 /**
895 * dm_test_add_modifier_grows_capacity() - Verify add triggers growth and preserves old data.
896 * @test: KUnit test context.
897 *
898 * Verify if modifier array growth keeps old data and appends new data.
899 */
dm_test_add_modifier_grows_capacity(struct kunit * test)900 static void dm_test_add_modifier_grows_capacity(struct kunit *test)
901 {
902 uint64_t size = 1;
903 uint64_t cap = 1;
904 uint64_t *mods = kmalloc_array(cap, sizeof(*mods), GFP_KERNEL);
905
906 KUNIT_ASSERT_NOT_NULL(test, mods);
907 mods[0] = 0xAAULL;
908
909 amdgpu_dm_plane_add_modifier(&mods, &size, &cap, 0xBBULL);
910
911 KUNIT_ASSERT_NOT_NULL(test, mods);
912 KUNIT_EXPECT_EQ(test, cap, 2ULL);
913 KUNIT_EXPECT_EQ(test, size, 2ULL);
914 KUNIT_EXPECT_EQ(test, mods[0], 0xAAULL);
915 KUNIT_EXPECT_EQ(test, mods[1], 0xBBULL);
916
917 kfree(mods);
918 }
919
920 /**
921 * dm_test_add_modifier_noop_when_mods_null() - Verify helper is a no-op on NULL mods list.
922 * @test: KUnit test context.
923 *
924 * Verify if add_modifier does nothing when the modifier list is NULL.
925 */
dm_test_add_modifier_noop_when_mods_null(struct kunit * test)926 static void dm_test_add_modifier_noop_when_mods_null(struct kunit *test)
927 {
928 uint64_t size = 3;
929 uint64_t cap = 7;
930 uint64_t *mods = NULL;
931
932 amdgpu_dm_plane_add_modifier(&mods, &size, &cap, 0x55ULL);
933
934 KUNIT_EXPECT_PTR_EQ(test, mods, NULL);
935 KUNIT_EXPECT_EQ(test, size, 3ULL);
936 KUNIT_EXPECT_EQ(test, cap, 7ULL);
937 }
938
939 /**
940 * dm_test_fill_gfx9_tiling_info_from_device_pre_10_3() - Verify GFX9 field copy before 10.3.
941 * @test: KUnit test context.
942 *
943 * Verify if pre-10.3 device fields are copied and existing num_pkrs is kept.
944 */
dm_test_fill_gfx9_tiling_info_from_device_pre_10_3(struct kunit * test)945 static void dm_test_fill_gfx9_tiling_info_from_device_pre_10_3(struct kunit *test)
946 {
947 struct amdgpu_device *adev;
948 struct dc_tiling_info tiling_info = {0};
949
950 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
951 KUNIT_ASSERT_NOT_NULL(test, adev);
952
953 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
954 adev->gfx.config.gb_addr_config_fields.num_banks = 8;
955 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256;
956 adev->gfx.config.gb_addr_config_fields.num_se = 2;
957 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1;
958 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
959 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3;
960 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 2, 9);
961
962 tiling_info.gfx9.num_pkrs = 0x5a;
963
964 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, &tiling_info);
965
966 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 4U);
967 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_banks, 8U);
968 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.pipe_interleave, 256U);
969 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_shader_engines, 2U);
970 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.max_compressed_frags, 1U);
971 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_rb_per_se, 2U);
972 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.shaderEnable, 1U);
973 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pkrs, 0x5aU);
974 }
975
976 /**
977 * dm_test_fill_gfx9_tiling_info_from_device_10_3_plus() - Verify num_pkrs update on 10.3+.
978 * @test: KUnit test context.
979 *
980 * Verify if 10.3+ device fields are copied and num_pkrs is updated.
981 */
dm_test_fill_gfx9_tiling_info_from_device_10_3_plus(struct kunit * test)982 static void dm_test_fill_gfx9_tiling_info_from_device_10_3_plus(struct kunit *test)
983 {
984 struct amdgpu_device *adev;
985 struct dc_tiling_info tiling_info = {0};
986
987 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
988 KUNIT_ASSERT_NOT_NULL(test, adev);
989
990 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
991 adev->gfx.config.gb_addr_config_fields.num_banks = 4;
992 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 128;
993 adev->gfx.config.gb_addr_config_fields.num_se = 1;
994 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2;
995 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1;
996 adev->gfx.config.gb_addr_config_fields.num_pkrs = 6;
997 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
998
999 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, &tiling_info);
1000
1001 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 2U);
1002 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_banks, 4U);
1003 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.pipe_interleave, 128U);
1004 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_shader_engines, 1U);
1005 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.max_compressed_frags, 2U);
1006 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_rb_per_se, 1U);
1007 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.shaderEnable, 1U);
1008 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pkrs, 6U);
1009 }
1010
1011 /**
1012 * dm_test_fill_gfx9_tiling_info_from_modifier_linear() - Verify non-AMD modifier keeps device values.
1013 * @test: KUnit test context.
1014 *
1015 * Verify if linear modifier path keeps values from device configuration.
1016 */
dm_test_fill_gfx9_tiling_info_from_modifier_linear(struct kunit * test)1017 static void dm_test_fill_gfx9_tiling_info_from_modifier_linear(struct kunit *test)
1018 {
1019 struct amdgpu_device *adev;
1020 struct dc_tiling_info tiling_info = {0};
1021
1022 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1023 KUNIT_ASSERT_NOT_NULL(test, adev);
1024
1025 adev->family = AMDGPU_FAMILY_NV;
1026 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1027 adev->gfx.config.gb_addr_config_fields.num_banks = 8;
1028 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256;
1029 adev->gfx.config.gb_addr_config_fields.num_se = 2;
1030 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1;
1031 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
1032 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3;
1033 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1034
1035 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, &tiling_info,
1036 DRM_FORMAT_MOD_LINEAR);
1037
1038 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 4U);
1039 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_banks, 8U);
1040 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.pipe_interleave, 256U);
1041 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_shader_engines, 2U);
1042 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.max_compressed_frags, 1U);
1043 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_rb_per_se, 2U);
1044 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.shaderEnable, 1U);
1045 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pkrs, 3U);
1046 }
1047
1048 /**
1049 * dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv() - Verify AMD modifier updates banks on pre-NV.
1050 * @test: KUnit test context.
1051 *
1052 * Verify if AMD modifier updates pre-NV pipe, engine, and bank fields.
1053 */
dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv(struct kunit * test)1054 static void dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv(struct kunit *test)
1055 {
1056 struct amdgpu_device *adev;
1057 struct dc_tiling_info tiling_info = {0};
1058 uint64_t modifier;
1059
1060 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1061 KUNIT_ASSERT_NOT_NULL(test, adev);
1062
1063 adev->family = AMDGPU_FAMILY_RV;
1064 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1065 adev->gfx.config.gb_addr_config_fields.num_banks = 16;
1066 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 256;
1067 adev->gfx.config.gb_addr_config_fields.num_se = 2;
1068 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1;
1069 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
1070 adev->gfx.config.gb_addr_config_fields.num_pkrs = 7;
1071 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 2, 9);
1072
1073 tiling_info.gfx9.num_pkrs = 0x5a;
1074
1075 modifier = AMD_FMT_MOD |
1076 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1077 AMD_FMT_MOD_SET(PIPE_XOR_BITS, 7) |
1078 AMD_FMT_MOD_SET(BANK_XOR_BITS, 3) |
1079 AMD_FMT_MOD_SET(PACKERS, 2);
1080
1081 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, &tiling_info, modifier);
1082
1083 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 32U);
1084 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_shader_engines, 4U);
1085 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_banks, 8U);
1086 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pkrs, 0x5aU);
1087 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.shaderEnable, 1U);
1088 }
1089
1090 /**
1091 * dm_test_fill_gfx9_tiling_info_from_modifier_nv() - Verify AMD modifier updates packers on NV+.
1092 * @test: KUnit test context.
1093 *
1094 * Verify if AMD modifier updates NV+ pipe, engine, and packer fields.
1095 */
dm_test_fill_gfx9_tiling_info_from_modifier_nv(struct kunit * test)1096 static void dm_test_fill_gfx9_tiling_info_from_modifier_nv(struct kunit *test)
1097 {
1098 struct amdgpu_device *adev;
1099 struct dc_tiling_info tiling_info = {0};
1100 uint64_t modifier;
1101
1102 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1103 KUNIT_ASSERT_NOT_NULL(test, adev);
1104
1105 adev->family = AMDGPU_FAMILY_NV;
1106 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
1107 adev->gfx.config.gb_addr_config_fields.num_banks = 9;
1108 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 128;
1109 adev->gfx.config.gb_addr_config_fields.num_se = 1;
1110 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 2;
1111 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1;
1112 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
1113 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1114
1115 modifier = AMD_FMT_MOD |
1116 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1117 AMD_FMT_MOD_SET(PIPE_XOR_BITS, 6) |
1118 AMD_FMT_MOD_SET(BANK_XOR_BITS, 2) |
1119 AMD_FMT_MOD_SET(PACKERS, 3);
1120
1121 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, &tiling_info, modifier);
1122
1123 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 32U);
1124 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_shader_engines, 2U);
1125 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_banks, 9U);
1126 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pkrs, 8U);
1127 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.shaderEnable, 1U);
1128 }
1129
1130 /**
1131 * dm_test_get_format_info() - Verify modifier-based format info lookup.
1132 * @test: KUnit test context.
1133 *
1134 * Verify if non-AMD modifiers return NULL and AMD DCC modifiers resolve a
1135 * dedicated format info structure.
1136 */
dm_test_get_format_info(struct kunit * test)1137 static void dm_test_get_format_info(struct kunit *test)
1138 {
1139 u64 dcc_mod = AMD_FMT_MOD |
1140 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
1141 AMD_FMT_MOD_SET(DCC, 1);
1142 const struct drm_format_info *format_info;
1143
1144 KUNIT_EXPECT_PTR_EQ(test,
1145 (void *)amdgpu_dm_plane_get_format_info(DRM_FORMAT_XRGB8888,
1146 DRM_FORMAT_MOD_LINEAR),
1147 NULL);
1148 format_info = amdgpu_dm_plane_get_format_info(DRM_FORMAT_XRGB8888, dcc_mod);
1149 KUNIT_EXPECT_NOT_NULL(test, format_info);
1150 }
1151
1152 /**
1153 * dm_test_fill_blending_global_alpha_dcn42() - Verify DCN 4.2 alpha scaling.
1154 * @test: KUnit test context.
1155 *
1156 * Verify if DCN 4.2 scales the 16-bit DRM alpha down by 4 bits instead of 8.
1157 */
dm_test_fill_blending_global_alpha_dcn42(struct kunit * test)1158 static void dm_test_fill_blending_global_alpha_dcn42(struct kunit *test)
1159 {
1160 struct amdgpu_device *adev;
1161 struct drm_plane *plane;
1162 struct drm_plane_state *state;
1163 bool per_pixel_alpha;
1164 bool pre_multiplied_alpha;
1165 bool global_alpha;
1166 int global_alpha_value;
1167
1168 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1169 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
1170 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
1171 KUNIT_ASSERT_NOT_NULL(test, adev);
1172 KUNIT_ASSERT_NOT_NULL(test, plane);
1173 KUNIT_ASSERT_NOT_NULL(test, state);
1174
1175 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 2, 0);
1176 plane->dev = &adev->ddev;
1177 state->plane = plane;
1178 state->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
1179 state->alpha = 0x8000;
1180
1181 amdgpu_dm_plane_fill_blending_from_plane_state(state,
1182 &per_pixel_alpha,
1183 &pre_multiplied_alpha,
1184 &global_alpha,
1185 &global_alpha_value);
1186
1187 KUNIT_EXPECT_TRUE(test, global_alpha);
1188 KUNIT_EXPECT_EQ(test, global_alpha_value, 0x800);
1189 }
1190
dm_test_expect_mods_terminated(struct kunit * test,struct amdgpu_device * adev)1191 static void dm_test_expect_mods_terminated(struct kunit *test, struct amdgpu_device *adev)
1192 {
1193 u64 *mods = NULL;
1194 int ret;
1195 int i;
1196
1197 ret = amdgpu_dm_plane_get_plane_modifiers(adev, DRM_PLANE_TYPE_PRIMARY, &mods);
1198 KUNIT_ASSERT_EQ(test, ret, 0);
1199 KUNIT_ASSERT_NOT_NULL(test, mods);
1200
1201 for (i = 0; mods[i] != DRM_FORMAT_MOD_INVALID; i++)
1202 ;
1203
1204 KUNIT_EXPECT_GT(test, i, 0);
1205 KUNIT_EXPECT_EQ(test, mods[i - 1], DRM_FORMAT_MOD_LINEAR);
1206 kfree(mods);
1207 }
1208
dm_test_mods_contain(const u64 * mods,u64 expected)1209 static bool dm_test_mods_contain(const u64 *mods, u64 expected)
1210 {
1211 int i;
1212
1213 for (i = 0; mods[i] != DRM_FORMAT_MOD_INVALID; i++) {
1214 if (mods[i] == expected)
1215 return true;
1216 }
1217
1218 return false;
1219 }
1220
dm_test_get_primary_mods(struct kunit * test,struct amdgpu_device * adev)1221 static u64 *dm_test_get_primary_mods(struct kunit *test, struct amdgpu_device *adev)
1222 {
1223 u64 *mods = NULL;
1224 int ret;
1225
1226 ret = amdgpu_dm_plane_get_plane_modifiers(adev, DRM_PLANE_TYPE_PRIMARY, &mods);
1227 KUNIT_ASSERT_EQ(test, ret, 0);
1228 KUNIT_ASSERT_NOT_NULL(test, mods);
1229
1230 return mods;
1231 }
1232
dm_test_gfx9_attrs(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const struct plane_size * plane_size,struct dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)1233 static int dm_test_gfx9_attrs(struct amdgpu_device *adev,
1234 const struct amdgpu_framebuffer *afb,
1235 const struct plane_size *plane_size,
1236 struct dc_tiling_info *tiling_info,
1237 struct dc_plane_dcc_param *dcc,
1238 struct dc_plane_address *address)
1239 {
1240 return amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers(adev,
1241 afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, ROTATION_ANGLE_0,
1242 plane_size, tiling_info, dcc, address);
1243 }
1244
dm_test_gfx12_attrs(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const struct plane_size * plane_size,struct dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)1245 static int dm_test_gfx12_attrs(struct amdgpu_device *adev,
1246 const struct amdgpu_framebuffer *afb,
1247 const struct plane_size *plane_size,
1248 struct dc_tiling_info *tiling_info,
1249 struct dc_plane_dcc_param *dcc,
1250 struct dc_plane_address *address)
1251 {
1252 return amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers(adev,
1253 afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, ROTATION_ANGLE_0,
1254 plane_size, tiling_info, dcc, address);
1255 }
1256
dm_test_plane_attrs(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)1257 static int dm_test_plane_attrs(struct amdgpu_device *adev,
1258 const struct amdgpu_framebuffer *afb,
1259 enum surface_pixel_format format,
1260 struct dc_tiling_info *tiling_info,
1261 struct plane_size *plane_size,
1262 struct dc_plane_dcc_param *dcc,
1263 struct dc_plane_address *address)
1264 {
1265 return amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, format,
1266 ROTATION_ANGLE_0, tiling_info, plane_size, dcc, address,
1267 false);
1268 }
1269
dm_test_video_attrs(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)1270 static int dm_test_video_attrs(struct amdgpu_device *adev,
1271 const struct amdgpu_framebuffer *afb,
1272 struct dc_tiling_info *tiling_info,
1273 struct plane_size *plane_size,
1274 struct dc_plane_dcc_param *dcc,
1275 struct dc_plane_address *address)
1276 {
1277 return dm_test_plane_attrs(adev, afb, SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr,
1278 tiling_info, plane_size, dcc, address);
1279 }
1280
dm_test_graphics_attrs(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)1281 static int dm_test_graphics_attrs(struct amdgpu_device *adev,
1282 const struct amdgpu_framebuffer *afb,
1283 struct dc_tiling_info *tiling_info,
1284 struct plane_size *plane_size,
1285 struct dc_plane_dcc_param *dcc,
1286 struct dc_plane_address *address)
1287 {
1288 return dm_test_plane_attrs(adev, afb, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
1289 tiling_info, plane_size, dcc, address);
1290 }
1291
dm_test_setup_gfx9_dcc_device(struct amdgpu_device * adev,struct dc * dc,struct dm_test_dcc_cap_ctx * ctx,bool output_independent_64b_blks)1292 static void dm_test_setup_gfx9_dcc_device(struct amdgpu_device *adev,
1293 struct dc *dc,
1294 struct dm_test_dcc_cap_ctx *ctx,
1295 bool output_independent_64b_blks)
1296 {
1297 adev->family = AMDGPU_FAMILY_NV;
1298 adev->dm.dc = dc;
1299 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
1300 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
1301 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1302 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
1303 ctx->callback_ret = true;
1304 ctx->capable = true;
1305 ctx->output_independent_64b_blks = output_independent_64b_blks;
1306 dm_test_dcc_ctx = ctx;
1307 }
1308
dm_test_gfx9_dcc_modifier(u64 tile_version,bool independent_64b_blks,bool independent_128b_blks)1309 static u64 dm_test_gfx9_dcc_modifier(u64 tile_version, bool independent_64b_blks,
1310 bool independent_128b_blks)
1311 {
1312 return AMD_FMT_MOD |
1313 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1314 AMD_FMT_MOD_SET(TILE_VERSION, tile_version) |
1315 AMD_FMT_MOD_SET(DCC, 1) |
1316 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, independent_64b_blks) |
1317 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b_blks);
1318 }
1319
dm_test_setup_gfx11_device(struct amdgpu_device * adev,struct dm_test_gfx11_reg_ctx * ctx,u32 num_pkrs_log2,u32 num_pipes_log2)1320 static void dm_test_setup_gfx11_device(struct amdgpu_device *adev,
1321 struct dm_test_gfx11_reg_ctx *ctx,
1322 u32 num_pkrs_log2, u32 num_pipes_log2)
1323 {
1324 ctx->gb_addr_config =
1325 REG_SET_FIELD(0, GB_ADDR_CONFIG, NUM_PKRS, num_pkrs_log2) |
1326 REG_SET_FIELD(0, GB_ADDR_CONFIG, NUM_PIPES, num_pipes_log2);
1327 ctx->gc_reg_offsets[regGB_ADDR_CONFIG_BASE_IDX] = 0;
1328 ctx->expected_reg = ctx->gc_reg_offsets[regGB_ADDR_CONFIG_BASE_IDX] +
1329 regGB_ADDR_CONFIG;
1330 dm_test_gfx11_reg_ctx = ctx;
1331
1332 adev->family = AMDGPU_FAMILY_GC_11_0_0;
1333 adev->reg_offset[GC_HWIP][0] = ctx->gc_reg_offsets;
1334 adev->gfx.rlc.reg_funcs = &dm_test_gfx11_reg_funcs;
1335 }
1336
dm_test_gfx11_dcc_best_modifier(u32 pipe_xor_bits,u32 pkrs,u32 tile)1337 static u64 dm_test_gfx11_dcc_best_modifier(u32 pipe_xor_bits, u32 pkrs, u32 tile)
1338 {
1339 return AMD_FMT_MOD |
1340 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
1341 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
1342 AMD_FMT_MOD_SET(TILE, tile) |
1343 AMD_FMT_MOD_SET(PACKERS, pkrs) |
1344 AMD_FMT_MOD_SET(DCC, 1) |
1345 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
1346 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
1347 }
1348
dm_test_gfx11_dcc_4k_modifier(u32 pipe_xor_bits,u32 pkrs,u32 tile)1349 static u64 dm_test_gfx11_dcc_4k_modifier(u32 pipe_xor_bits, u32 pkrs, u32 tile)
1350 {
1351 return AMD_FMT_MOD |
1352 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
1353 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
1354 AMD_FMT_MOD_SET(TILE, tile) |
1355 AMD_FMT_MOD_SET(PACKERS, pkrs) |
1356 AMD_FMT_MOD_SET(DCC, 1) |
1357 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
1358 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
1359 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
1360 }
1361
1362 /**
1363 * dm_test_get_plane_formats_overlay_universal_cap() - Verify universal overlay.
1364 * @test: KUnit test context.
1365 *
1366 * Verify if an overlay plane with a DCN universal plane cap reports the RGB
1367 * format list instead of the overlay-only list.
1368 */
dm_test_get_plane_formats_overlay_universal_cap(struct kunit * test)1369 static void dm_test_get_plane_formats_overlay_universal_cap(struct kunit *test)
1370 {
1371 struct drm_plane *plane;
1372 struct dc_plane_cap *cap;
1373 u32 formats[32] = {0};
1374
1375 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
1376 cap = kunit_kzalloc(test, sizeof(*cap), GFP_KERNEL);
1377 KUNIT_ASSERT_NOT_NULL(test, plane);
1378 KUNIT_ASSERT_NOT_NULL(test, cap);
1379
1380 plane->type = DRM_PLANE_TYPE_OVERLAY;
1381 cap->type = DC_PLANE_TYPE_DCN_UNIVERSAL;
1382
1383 KUNIT_EXPECT_EQ(test,
1384 amdgpu_dm_plane_get_plane_formats(plane, cap, formats, 32),
1385 14);
1386 }
1387
1388 /**
1389 * dm_test_get_plane_modifiers_gfx9() - Verify GFX9 modifier list generation.
1390 * @test: KUnit test context.
1391 *
1392 * Verify if the GFX9 family produces a non-empty modifier list terminated by
1393 * LINEAR and INVALID entries.
1394 */
dm_test_get_plane_modifiers_gfx9(struct kunit * test)1395 static void dm_test_get_plane_modifiers_gfx9(struct kunit *test)
1396 {
1397 struct amdgpu_device *adev;
1398
1399 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1400 KUNIT_ASSERT_NOT_NULL(test, adev);
1401
1402 adev->family = AMDGPU_FAMILY_AI;
1403 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1404 adev->gfx.config.gb_addr_config_fields.num_banks = 8;
1405 adev->gfx.config.gb_addr_config_fields.num_se = 2;
1406 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
1407
1408 dm_test_expect_mods_terminated(test, adev);
1409 }
1410
1411 /**
1412 * dm_test_get_plane_modifiers_rv() - Verify RV modifier list generation.
1413 * @test: KUnit test context.
1414 *
1415 * Verify if pre-Raven2 RV devices add RV-specific S-swizzle modifiers and
1416 * non-constant-encode DCC modifiers.
1417 */
dm_test_get_plane_modifiers_rv(struct kunit * test)1418 static void dm_test_get_plane_modifiers_rv(struct kunit *test)
1419 {
1420 struct amdgpu_device *adev;
1421 u64 *mods;
1422 u64 dcc_mod;
1423 u64 s_x_mod;
1424 u64 s_mod;
1425 int pipes = 2;
1426 int pipe_xor_bits = 3;
1427 int bank_xor_bits = 2;
1428
1429 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1430 KUNIT_ASSERT_NOT_NULL(test, adev);
1431
1432 adev->family = AMDGPU_FAMILY_RV;
1433 adev->asic_type = CHIP_RAVEN;
1434 adev->external_rev_id = 0x80;
1435 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1436 adev->gfx.config.gb_addr_config_fields.num_banks = 4;
1437 adev->gfx.config.gb_addr_config_fields.num_se = 2;
1438 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
1439
1440 mods = dm_test_get_primary_mods(test, adev);
1441 dcc_mod = AMD_FMT_MOD |
1442 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1443 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
1444 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
1445 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
1446 AMD_FMT_MOD_SET(DCC, 1) |
1447 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
1448 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
1449 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0);
1450 s_x_mod = AMD_FMT_MOD |
1451 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1452 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
1453 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
1454 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits);
1455 s_mod = AMD_FMT_MOD |
1456 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
1457 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9);
1458
1459 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, dcc_mod));
1460 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, dcc_mod |
1461 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
1462 AMD_FMT_MOD_SET(RB, 2) |
1463 AMD_FMT_MOD_SET(PIPE, pipes)));
1464 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, s_x_mod));
1465 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, s_mod));
1466
1467 kfree(mods);
1468 }
1469
1470 /**
1471 * dm_test_get_plane_modifiers_rv_constant_encode() - Verify Raven2+ modifiers.
1472 * @test: KUnit test context.
1473 *
1474 * Verify if Raven2 and later RV devices add the constant-encode modifier
1475 * variants.
1476 */
dm_test_get_plane_modifiers_rv_constant_encode(struct kunit * test)1477 static void dm_test_get_plane_modifiers_rv_constant_encode(struct kunit *test)
1478 {
1479 struct amdgpu_device *adev;
1480 u64 *mods;
1481 u64 dcc_mod;
1482 int pipes = 2;
1483 int pipe_xor_bits = 3;
1484 int bank_xor_bits = 2;
1485
1486 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1487 KUNIT_ASSERT_NOT_NULL(test, adev);
1488
1489 adev->family = AMDGPU_FAMILY_RV;
1490 adev->asic_type = CHIP_RAVEN;
1491 adev->external_rev_id = 0x81;
1492 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1493 adev->gfx.config.gb_addr_config_fields.num_banks = 4;
1494 adev->gfx.config.gb_addr_config_fields.num_se = 2;
1495 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 2;
1496
1497 mods = dm_test_get_primary_mods(test, adev);
1498 dcc_mod = AMD_FMT_MOD |
1499 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1500 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
1501 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
1502 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
1503 AMD_FMT_MOD_SET(DCC, 1) |
1504 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
1505 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
1506 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1);
1507
1508 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, dcc_mod));
1509 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, dcc_mod |
1510 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
1511 AMD_FMT_MOD_SET(RB, 2) |
1512 AMD_FMT_MOD_SET(PIPE, pipes)));
1513
1514 kfree(mods);
1515 }
1516
1517 /**
1518 * dm_test_get_plane_modifiers_gfx10_1() - Verify GFX10.1 modifier list generation.
1519 * @test: KUnit test context.
1520 *
1521 * Verify if a pre-10.3 NV family device dispatches to the GFX10.1 modifier
1522 * builder and produces a terminated list.
1523 */
dm_test_get_plane_modifiers_gfx10_1(struct kunit * test)1524 static void dm_test_get_plane_modifiers_gfx10_1(struct kunit *test)
1525 {
1526 struct amdgpu_device *adev;
1527
1528 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1529 KUNIT_ASSERT_NOT_NULL(test, adev);
1530
1531 adev->family = AMDGPU_FAMILY_NV;
1532 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1533 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 0);
1534
1535 dm_test_expect_mods_terminated(test, adev);
1536 }
1537
1538 /**
1539 * dm_test_get_plane_modifiers_gfx10_3() - Verify GFX10.3 modifier list generation.
1540 * @test: KUnit test context.
1541 *
1542 * Verify if a 10.3+ NV family device dispatches to the GFX10.3 modifier
1543 * builder and produces a terminated list.
1544 */
dm_test_get_plane_modifiers_gfx10_3(struct kunit * test)1545 static void dm_test_get_plane_modifiers_gfx10_3(struct kunit *test)
1546 {
1547 struct amdgpu_device *adev;
1548
1549 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1550 KUNIT_ASSERT_NOT_NULL(test, adev);
1551
1552 adev->family = AMDGPU_FAMILY_NV;
1553 adev->gfx.config.gb_addr_config_fields.num_pipes = 4;
1554 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
1555 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1556
1557 dm_test_expect_mods_terminated(test, adev);
1558 }
1559
1560 /**
1561 * dm_test_get_plane_modifiers_gfx11_64k_first() - Verify GFX11 small-pipe order.
1562 * @test: KUnit test context.
1563 *
1564 * Verify if GFX11 modifier generation reads GB_ADDR_CONFIG through the RLC
1565 * register callback and prefers 64K_R_X when the pipe count is 16 or lower.
1566 */
dm_test_get_plane_modifiers_gfx11_64k_first(struct kunit * test)1567 static void dm_test_get_plane_modifiers_gfx11_64k_first(struct kunit *test)
1568 {
1569 struct dm_test_gfx11_reg_ctx ctx = {0};
1570 struct amdgpu_device *adev;
1571 u64 *mods;
1572 u32 pipe_xor_bits = 4;
1573 u32 pkrs = 1;
1574 u32 tile = AMD_FMT_MOD_TILE_GFX9_64K_R_X;
1575 u64 dcc_best;
1576 u64 dcc_4k;
1577 u64 d_mod;
1578
1579 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1580 KUNIT_ASSERT_NOT_NULL(test, adev);
1581 dm_test_setup_gfx11_device(adev, &ctx, pkrs, pipe_xor_bits);
1582
1583 mods = dm_test_get_primary_mods(test, adev);
1584 dcc_best = dm_test_gfx11_dcc_best_modifier(pipe_xor_bits, pkrs, tile);
1585 dcc_4k = dm_test_gfx11_dcc_4k_modifier(pipe_xor_bits, pkrs, tile);
1586 d_mod = AMD_FMT_MOD |
1587 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
1588 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D);
1589
1590 KUNIT_EXPECT_TRUE(test, ctx.called);
1591 KUNIT_EXPECT_EQ(test, ctx.captured_reg, ctx.expected_reg);
1592 KUNIT_EXPECT_EQ(test, ctx.captured_acc_flags, 0U);
1593 KUNIT_EXPECT_EQ(test, ctx.captured_hwip, (u32)GC_HWIP);
1594 KUNIT_EXPECT_EQ(test, ctx.captured_xcc_id, 0U);
1595 KUNIT_EXPECT_EQ(test, mods[0], dcc_best);
1596 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, dcc_4k));
1597 KUNIT_EXPECT_TRUE(test,
1598 dm_test_mods_contain(mods,
1599 dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)));
1600 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, d_mod));
1601
1602 dm_test_gfx11_reg_ctx = NULL;
1603 kfree(mods);
1604 }
1605
1606 /**
1607 * dm_test_get_plane_modifiers_gfx11_256k_first() - Verify GFX11 large-pipe order.
1608 * @test: KUnit test context.
1609 *
1610 * Verify if GFX11 modifier generation prefers 256K_R_X when more than 16 pipes
1611 * are reported by GB_ADDR_CONFIG.
1612 */
dm_test_get_plane_modifiers_gfx11_256k_first(struct kunit * test)1613 static void dm_test_get_plane_modifiers_gfx11_256k_first(struct kunit *test)
1614 {
1615 struct dm_test_gfx11_reg_ctx ctx = {0};
1616 struct amdgpu_device *adev;
1617 u64 *mods;
1618 u32 pipe_xor_bits = 5;
1619 u32 pkrs = 2;
1620 u32 tile = AMD_FMT_MOD_TILE_GFX11_256K_R_X;
1621 u32 fallback_tile = AMD_FMT_MOD_TILE_GFX9_64K_R_X;
1622 u64 dcc_best;
1623 u64 fallback_dcc_best = dm_test_gfx11_dcc_best_modifier(pipe_xor_bits, pkrs,
1624 fallback_tile);
1625
1626 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1627 KUNIT_ASSERT_NOT_NULL(test, adev);
1628 dm_test_setup_gfx11_device(adev, &ctx, pkrs, pipe_xor_bits);
1629
1630 mods = dm_test_get_primary_mods(test, adev);
1631 dcc_best = dm_test_gfx11_dcc_best_modifier(pipe_xor_bits, pkrs, tile);
1632
1633 KUNIT_EXPECT_TRUE(test, ctx.called);
1634 KUNIT_EXPECT_EQ(test, ctx.captured_reg, ctx.expected_reg);
1635 KUNIT_EXPECT_EQ(test, mods[0], dcc_best);
1636 KUNIT_EXPECT_TRUE(test, dm_test_mods_contain(mods, fallback_dcc_best));
1637
1638 dm_test_gfx11_reg_ctx = NULL;
1639 kfree(mods);
1640 }
1641
1642 /**
1643 * dm_test_get_plane_modifiers_gfx12() - Verify GFX12 modifier list generation.
1644 * @test: KUnit test context.
1645 *
1646 * Verify if the GFX12 family dispatches to the GFX12 modifier builder and
1647 * produces a terminated list.
1648 */
dm_test_get_plane_modifiers_gfx12(struct kunit * test)1649 static void dm_test_get_plane_modifiers_gfx12(struct kunit *test)
1650 {
1651 struct amdgpu_device *adev;
1652
1653 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1654 KUNIT_ASSERT_NOT_NULL(test, adev);
1655
1656 adev->family = AMDGPU_FAMILY_GC_12_0_0;
1657
1658 dm_test_expect_mods_terminated(test, adev);
1659 }
1660
1661 /**
1662 * dm_test_fill_gfx9_plane_attributes_dcc() - Verify GFX9 DCC modifier path.
1663 * @test: KUnit test context.
1664 *
1665 * Verify if a GFX10-RBPLUS DCC modifier enables DCC and selects the 64B
1666 * independent block mode.
1667 */
dm_test_fill_gfx9_plane_attributes_dcc(struct kunit * test)1668 static void dm_test_fill_gfx9_plane_attributes_dcc(struct kunit *test)
1669 {
1670 struct amdgpu_device *adev;
1671 struct dc *dc;
1672 struct amdgpu_framebuffer *afb;
1673 struct plane_size plane_size = {0};
1674 struct dc_tiling_info tiling_info = {0};
1675 struct dc_plane_dcc_param dcc = {0};
1676 struct dc_plane_address address = {0};
1677 struct dm_test_dcc_cap_ctx ctx = {
1678 .callback_ret = true,
1679 .capable = true,
1680 .output_independent_64b_blks = true,
1681 };
1682 int ret;
1683
1684 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1685 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1686 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1687 KUNIT_ASSERT_NOT_NULL(test, adev);
1688 KUNIT_ASSERT_NOT_NULL(test, dc);
1689 KUNIT_ASSERT_NOT_NULL(test, afb);
1690
1691 adev->family = AMDGPU_FAMILY_NV;
1692 adev->dm.dc = dc;
1693 adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
1694 adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
1695 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1696 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
1697 dm_test_dcc_ctx = &ctx;
1698
1699 afb->base.pitches[1] = 256;
1700 afb->base.modifier = AMD_FMT_MOD |
1701 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
1702 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
1703 AMD_FMT_MOD_SET(DCC, 1) |
1704 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1);
1705 plane_size.surface_size.width = 1920;
1706 plane_size.surface_size.height = 1080;
1707
1708 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1709 &address);
1710 KUNIT_EXPECT_EQ(test, ret, 0);
1711 KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxVersion9);
1712 KUNIT_EXPECT_TRUE(test, dcc.enable);
1713 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_64b);
1714 KUNIT_EXPECT_EQ(test, dcc.meta_pitch, 256U);
1715
1716 dm_test_dcc_ctx = NULL;
1717 }
1718
1719 /**
1720 * dm_test_fill_gfx9_plane_attributes_validate_fails() - Verify GFX9 error path.
1721 * @test: KUnit test context.
1722 *
1723 * Verify if GFX9 modifier parsing returns validation errors from the shared DCC
1724 * validation helper.
1725 */
dm_test_fill_gfx9_plane_attributes_validate_fails(struct kunit * test)1726 static void dm_test_fill_gfx9_plane_attributes_validate_fails(struct kunit *test)
1727 {
1728 struct amdgpu_device *adev;
1729 struct dc *dc;
1730 struct amdgpu_framebuffer *afb;
1731 struct plane_size plane_size = {0};
1732 struct dc_tiling_info tiling_info = {0};
1733 struct dc_plane_dcc_param dcc = {0};
1734 struct dc_plane_address address = {0};
1735 u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
1736 int ret;
1737
1738 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1739 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1740 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1741 KUNIT_ASSERT_NOT_NULL(test, adev);
1742 KUNIT_ASSERT_NOT_NULL(test, dc);
1743 KUNIT_ASSERT_NOT_NULL(test, afb);
1744
1745 adev->family = AMDGPU_FAMILY_NV;
1746 adev->dm.dc = dc;
1747 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
1748 afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, true, false);
1749 plane_size.surface_size.width = 1920;
1750 plane_size.surface_size.height = 1080;
1751
1752 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1753 &address);
1754 KUNIT_EXPECT_EQ(test, ret, -EINVAL);
1755 }
1756
1757 /**
1758 * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl() - Verify block mode.
1759 * @test: KUnit test context.
1760 *
1761 * Verify if a GFX10-RBPLUS modifier with both 64B and 128B independent block
1762 * bits selects the 64B-no-128BCL block mode.
1763 */
dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl(struct kunit * test)1764 static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl(struct kunit *test)
1765 {
1766 struct amdgpu_device *adev;
1767 struct dc *dc;
1768 struct amdgpu_framebuffer *afb;
1769 struct plane_size plane_size = {0};
1770 struct dc_tiling_info tiling_info = {0};
1771 struct dc_plane_dcc_param dcc = {0};
1772 struct dc_plane_address address = {0};
1773 struct dm_test_dcc_cap_ctx ctx = {0};
1774 u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
1775 int ret;
1776
1777 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1778 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1779 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1780 KUNIT_ASSERT_NOT_NULL(test, adev);
1781 KUNIT_ASSERT_NOT_NULL(test, dc);
1782 KUNIT_ASSERT_NOT_NULL(test, afb);
1783
1784 dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, true);
1785 afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, true, true);
1786 plane_size.surface_size.width = 1920;
1787 plane_size.surface_size.height = 1080;
1788
1789 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1790 &address);
1791 KUNIT_EXPECT_EQ(test, ret, 0);
1792 KUNIT_EXPECT_TRUE(test, dcc.enable);
1793 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk,
1794 (int)hubp_ind_block_64b_no_128bcl);
1795
1796 dm_test_dcc_ctx = NULL;
1797 }
1798
1799 /**
1800 * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b() - Verify 128B block mode.
1801 * @test: KUnit test context.
1802 *
1803 * Verify if a GFX10-RBPLUS modifier with only the 128B independent block bit
1804 * selects the 128B block mode.
1805 */
dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b(struct kunit * test)1806 static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b(struct kunit *test)
1807 {
1808 struct amdgpu_device *adev;
1809 struct dc *dc;
1810 struct amdgpu_framebuffer *afb;
1811 struct plane_size plane_size = {0};
1812 struct dc_tiling_info tiling_info = {0};
1813 struct dc_plane_dcc_param dcc = {0};
1814 struct dc_plane_address address = {0};
1815 struct dm_test_dcc_cap_ctx ctx = {0};
1816 u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
1817 int ret;
1818
1819 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1820 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1821 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1822 KUNIT_ASSERT_NOT_NULL(test, adev);
1823 KUNIT_ASSERT_NOT_NULL(test, dc);
1824 KUNIT_ASSERT_NOT_NULL(test, afb);
1825
1826 dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false);
1827 afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, false, true);
1828 plane_size.surface_size.width = 1920;
1829 plane_size.surface_size.height = 1080;
1830
1831 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1832 &address);
1833 KUNIT_EXPECT_EQ(test, ret, 0);
1834 KUNIT_EXPECT_TRUE(test, dcc.enable);
1835 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_128b);
1836
1837 dm_test_dcc_ctx = NULL;
1838 }
1839
1840 /**
1841 * dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained() - Verify block mode.
1842 * @test: KUnit test context.
1843 *
1844 * Verify if a GFX10-RBPLUS modifier without independent block bits selects the
1845 * unconstrained block mode.
1846 */
dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained(struct kunit * test)1847 static void dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained(struct kunit *test)
1848 {
1849 struct amdgpu_device *adev;
1850 struct dc *dc;
1851 struct amdgpu_framebuffer *afb;
1852 struct plane_size plane_size = {0};
1853 struct dc_tiling_info tiling_info = {0};
1854 struct dc_plane_dcc_param dcc = {0};
1855 struct dc_plane_address address = {0};
1856 struct dm_test_dcc_cap_ctx ctx = {0};
1857 u64 tile_version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
1858 int ret;
1859
1860 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1861 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1862 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1863 KUNIT_ASSERT_NOT_NULL(test, adev);
1864 KUNIT_ASSERT_NOT_NULL(test, dc);
1865 KUNIT_ASSERT_NOT_NULL(test, afb);
1866
1867 dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false);
1868 afb->base.modifier = dm_test_gfx9_dcc_modifier(tile_version, false, false);
1869 plane_size.surface_size.width = 1920;
1870 plane_size.surface_size.height = 1080;
1871
1872 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1873 &address);
1874 KUNIT_EXPECT_EQ(test, ret, 0);
1875 KUNIT_EXPECT_TRUE(test, dcc.enable);
1876 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk,
1877 (int)hubp_ind_block_unconstrained);
1878
1879 dm_test_dcc_ctx = NULL;
1880 }
1881
1882 /**
1883 * dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b() - Verify legacy 64B mode.
1884 * @test: KUnit test context.
1885 *
1886 * Verify if a pre-RBPLUS GFX9 modifier with the 64B independent block bit
1887 * selects the 64B block mode.
1888 */
dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b(struct kunit * test)1889 static void dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b(struct kunit *test)
1890 {
1891 struct amdgpu_device *adev;
1892 struct dc *dc;
1893 struct amdgpu_framebuffer *afb;
1894 struct plane_size plane_size = {0};
1895 struct dc_tiling_info tiling_info = {0};
1896 struct dc_plane_dcc_param dcc = {0};
1897 struct dc_plane_address address = {0};
1898 struct dm_test_dcc_cap_ctx ctx = {0};
1899 int ret;
1900
1901 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1902 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1903 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1904 KUNIT_ASSERT_NOT_NULL(test, adev);
1905 KUNIT_ASSERT_NOT_NULL(test, dc);
1906 KUNIT_ASSERT_NOT_NULL(test, afb);
1907
1908 dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, true);
1909 afb->base.modifier = dm_test_gfx9_dcc_modifier(AMD_FMT_MOD_TILE_VER_GFX9,
1910 true, false);
1911 plane_size.surface_size.width = 1920;
1912 plane_size.surface_size.height = 1080;
1913
1914 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1915 &address);
1916 KUNIT_EXPECT_EQ(test, ret, 0);
1917 KUNIT_EXPECT_TRUE(test, dcc.enable);
1918 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_64b);
1919
1920 dm_test_dcc_ctx = NULL;
1921 }
1922
1923 /**
1924 * dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained() - Verify legacy mode.
1925 * @test: KUnit test context.
1926 *
1927 * Verify if a pre-RBPLUS GFX9 modifier without the 64B independent block bit
1928 * selects the unconstrained block mode.
1929 */
dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained(struct kunit * test)1930 static void dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained(struct kunit *test)
1931 {
1932 struct amdgpu_device *adev;
1933 struct dc *dc;
1934 struct amdgpu_framebuffer *afb;
1935 struct plane_size plane_size = {0};
1936 struct dc_tiling_info tiling_info = {0};
1937 struct dc_plane_dcc_param dcc = {0};
1938 struct dc_plane_address address = {0};
1939 struct dm_test_dcc_cap_ctx ctx = {0};
1940 int ret;
1941
1942 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1943 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1944 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1945 KUNIT_ASSERT_NOT_NULL(test, adev);
1946 KUNIT_ASSERT_NOT_NULL(test, dc);
1947 KUNIT_ASSERT_NOT_NULL(test, afb);
1948
1949 dm_test_setup_gfx9_dcc_device(adev, dc, &ctx, false);
1950 afb->base.modifier = dm_test_gfx9_dcc_modifier(AMD_FMT_MOD_TILE_VER_GFX9,
1951 false, false);
1952 plane_size.surface_size.width = 1920;
1953 plane_size.surface_size.height = 1080;
1954
1955 ret = dm_test_gfx9_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
1956 &address);
1957 KUNIT_EXPECT_EQ(test, ret, 0);
1958 KUNIT_EXPECT_TRUE(test, dcc.enable);
1959 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk,
1960 (int)hubp_ind_block_unconstrained);
1961
1962 dm_test_dcc_ctx = NULL;
1963 }
1964
1965 /**
1966 * dm_test_fill_gfx12_plane_attributes_block0() - Verify GFX12 64B max-compressed-block path.
1967 * @test: KUnit test context.
1968 *
1969 * Verify if a zero max-compressed-block modifier selects the 64B independent
1970 * block mode on GFX12.
1971 */
dm_test_fill_gfx12_plane_attributes_block0(struct kunit * test)1972 static void dm_test_fill_gfx12_plane_attributes_block0(struct kunit *test)
1973 {
1974 struct amdgpu_device *adev;
1975 struct dc *dc;
1976 struct amdgpu_framebuffer *afb;
1977 struct plane_size plane_size = {0};
1978 struct dc_tiling_info tiling_info = {0};
1979 struct dc_plane_dcc_param dcc = {0};
1980 struct dc_plane_address address = {0};
1981 struct dm_test_dcc_cap_ctx ctx = {
1982 .callback_ret = true,
1983 .capable = true,
1984 .output_independent_64b_blks = false,
1985 };
1986 int ret;
1987
1988 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
1989 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
1990 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
1991 KUNIT_ASSERT_NOT_NULL(test, adev);
1992 KUNIT_ASSERT_NOT_NULL(test, dc);
1993 KUNIT_ASSERT_NOT_NULL(test, afb);
1994
1995 adev->family = AMDGPU_FAMILY_GC_12_0_0;
1996 adev->dm.dc = dc;
1997 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
1998 dm_test_dcc_ctx = &ctx;
1999
2000 afb->base.modifier = AMD_FMT_MOD |
2001 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) |
2002 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
2003 AMD_FMT_MOD_SET(DCC, 1) |
2004 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);
2005 plane_size.surface_size.width = 1920;
2006 plane_size.surface_size.height = 1080;
2007
2008 ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
2009 &address);
2010 KUNIT_EXPECT_EQ(test, ret, 0);
2011 KUNIT_EXPECT_TRUE(test, dcc.enable);
2012 KUNIT_EXPECT_TRUE(test, dcc.independent_64b_blks);
2013 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk, (int)hubp_ind_block_64b);
2014
2015 dm_test_dcc_ctx = NULL;
2016 }
2017
2018 /**
2019 * dm_test_fill_gfx12_plane_attributes_block_unconstrained() - Verify block path.
2020 * @test: KUnit test context.
2021 *
2022 * Verify if a max-compressed-block value above one selects the unconstrained
2023 * independent block mode on GFX12.
2024 */
dm_test_fill_gfx12_plane_attributes_block_unconstrained(struct kunit * test)2025 static void dm_test_fill_gfx12_plane_attributes_block_unconstrained(struct kunit *test)
2026 {
2027 struct amdgpu_device *adev;
2028 struct dc *dc;
2029 struct amdgpu_framebuffer *afb;
2030 struct plane_size plane_size = {0};
2031 struct dc_tiling_info tiling_info = {0};
2032 struct dc_plane_dcc_param dcc = {0};
2033 struct dc_plane_address address = {0};
2034 struct dm_test_dcc_cap_ctx ctx = {
2035 .callback_ret = true,
2036 .capable = true,
2037 .output_independent_64b_blks = false,
2038 };
2039 int ret;
2040
2041 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2042 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2043 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
2044 KUNIT_ASSERT_NOT_NULL(test, adev);
2045 KUNIT_ASSERT_NOT_NULL(test, dc);
2046 KUNIT_ASSERT_NOT_NULL(test, afb);
2047
2048 adev->family = AMDGPU_FAMILY_GC_12_0_0;
2049 adev->dm.dc = dc;
2050 dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
2051 dm_test_dcc_ctx = &ctx;
2052
2053 afb->base.modifier = AMD_FMT_MOD |
2054 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) |
2055 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
2056 AMD_FMT_MOD_SET(DCC, 1) |
2057 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 2);
2058 plane_size.surface_size.width = 1920;
2059 plane_size.surface_size.height = 1080;
2060
2061 ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
2062 &address);
2063 KUNIT_EXPECT_EQ(test, ret, 0);
2064 KUNIT_EXPECT_TRUE(test, dcc.enable);
2065 KUNIT_EXPECT_FALSE(test, dcc.independent_64b_blks);
2066 KUNIT_EXPECT_EQ(test, (int)dcc.dcc_ind_blk,
2067 (int)hubp_ind_block_unconstrained);
2068
2069 dm_test_dcc_ctx = NULL;
2070 }
2071
2072 /**
2073 * dm_test_fill_gfx12_plane_attributes_validate_fails() - Verify GFX12 error path.
2074 * @test: KUnit test context.
2075 *
2076 * Verify if GFX12 modifier parsing returns validation errors from the shared
2077 * DCC validation helper.
2078 */
dm_test_fill_gfx12_plane_attributes_validate_fails(struct kunit * test)2079 static void dm_test_fill_gfx12_plane_attributes_validate_fails(struct kunit *test)
2080 {
2081 struct amdgpu_device *adev;
2082 struct dc *dc;
2083 struct amdgpu_framebuffer *afb;
2084 struct plane_size plane_size = {0};
2085 struct dc_tiling_info tiling_info = {0};
2086 struct dc_plane_dcc_param dcc = {0};
2087 struct dc_plane_address address = {0};
2088 int ret;
2089
2090 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2091 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2092 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
2093 KUNIT_ASSERT_NOT_NULL(test, adev);
2094 KUNIT_ASSERT_NOT_NULL(test, dc);
2095 KUNIT_ASSERT_NOT_NULL(test, afb);
2096
2097 adev->family = AMDGPU_FAMILY_GC_12_0_0;
2098 adev->dm.dc = dc;
2099 afb->base.modifier = AMD_FMT_MOD |
2100 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D) |
2101 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
2102 AMD_FMT_MOD_SET(DCC, 1) |
2103 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 1);
2104 plane_size.surface_size.width = 1920;
2105 plane_size.surface_size.height = 1080;
2106
2107 ret = dm_test_gfx12_attrs(adev, afb, &plane_size, &tiling_info, &dcc,
2108 &address);
2109 KUNIT_EXPECT_EQ(test, ret, -EINVAL);
2110 }
2111
2112 /**
2113 * dm_test_fill_plane_buffer_attributes_video() - Verify NV12 attributes.
2114 * @test: KUnit test context.
2115 *
2116 * Verify if a video pixel format fills chroma plane size and the progressive
2117 * video address type on a GFX9 family device.
2118 */
dm_test_fill_plane_buffer_attributes_video(struct kunit * test)2119 static void dm_test_fill_plane_buffer_attributes_video(struct kunit *test)
2120 {
2121 struct amdgpu_device *adev;
2122 struct amdgpu_framebuffer *afb;
2123 struct dc_tiling_info tiling_info;
2124 struct plane_size plane_size;
2125 struct dc_plane_dcc_param dcc;
2126 struct dc_plane_address address;
2127 int ret;
2128
2129 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2130 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
2131 tiling_info = (struct dc_tiling_info){0};
2132 plane_size = (struct plane_size){0};
2133 dcc = (struct dc_plane_dcc_param){0};
2134 address = (struct dc_plane_address){0};
2135 KUNIT_ASSERT_NOT_NULL(test, adev);
2136 KUNIT_ASSERT_NOT_NULL(test, afb);
2137
2138 adev->family = AMDGPU_FAMILY_NV;
2139 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
2140 afb->address = 0x80000000ULL;
2141 afb->base.width = 1920;
2142 afb->base.height = 1080;
2143 afb->base.offsets[0] = 0;
2144 afb->base.offsets[1] = 0x200000;
2145 afb->base.pitches[0] = 1920;
2146 afb->base.pitches[1] = 1920;
2147 afb->base.format = drm_format_info(DRM_FORMAT_NV12);
2148 afb->base.modifier = DRM_FORMAT_MOD_LINEAR;
2149 KUNIT_ASSERT_NOT_NULL(test, afb->base.format);
2150
2151 ret = dm_test_video_attrs(adev, afb, &tiling_info, &plane_size, &dcc,
2152 &address);
2153
2154 KUNIT_EXPECT_EQ(test, ret, 0);
2155 KUNIT_EXPECT_EQ(test, plane_size.surface_size.width, 1920);
2156 KUNIT_EXPECT_EQ(test, plane_size.chroma_size.width, 960U);
2157 KUNIT_EXPECT_EQ(test, plane_size.chroma_size.height, 540U);
2158 KUNIT_EXPECT_EQ(test, address.type,
2159 (int)PLN_ADDR_TYPE_VIDEO_PROGRESSIVE);
2160 KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxVersion9);
2161 }
2162
2163 /**
2164 * dm_test_fill_plane_buffer_attributes_gfx12() - Verify GFX12 dispatch path.
2165 * @test: KUnit test context.
2166 *
2167 * Verify if a GFX12 family device fills graphics attributes via the GFX12
2168 * modifier path and reports the GFX addr3 version.
2169 */
dm_test_fill_plane_buffer_attributes_gfx12(struct kunit * test)2170 static void dm_test_fill_plane_buffer_attributes_gfx12(struct kunit *test)
2171 {
2172 struct amdgpu_device *adev;
2173 struct dc *dc;
2174 struct amdgpu_framebuffer *afb;
2175 struct dc_tiling_info tiling_info;
2176 struct plane_size plane_size;
2177 struct dc_plane_dcc_param dcc;
2178 struct dc_plane_address address;
2179 int ret;
2180
2181 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2182 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2183 afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
2184 tiling_info = (struct dc_tiling_info){0};
2185 plane_size = (struct plane_size){0};
2186 dcc = (struct dc_plane_dcc_param){0};
2187 address = (struct dc_plane_address){0};
2188 KUNIT_ASSERT_NOT_NULL(test, adev);
2189 KUNIT_ASSERT_NOT_NULL(test, dc);
2190 KUNIT_ASSERT_NOT_NULL(test, afb);
2191
2192 adev->family = AMDGPU_FAMILY_GC_12_0_0;
2193 adev->dm.dc = dc;
2194 afb->address = 0x80000000ULL;
2195 afb->base.width = 1920;
2196 afb->base.height = 1080;
2197 afb->base.pitches[0] = 7680;
2198 afb->base.format = drm_format_info(DRM_FORMAT_XRGB8888);
2199 afb->base.modifier = DRM_FORMAT_MOD_LINEAR;
2200 KUNIT_ASSERT_NOT_NULL(test, afb->base.format);
2201
2202 ret = dm_test_graphics_attrs(adev, afb, &tiling_info, &plane_size, &dcc,
2203 &address);
2204
2205 KUNIT_EXPECT_EQ(test, ret, 0);
2206 KUNIT_EXPECT_EQ(test, address.type, (int)PLN_ADDR_TYPE_GRAPHICS);
2207 KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxAddr3);
2208 }
2209
2210 /**
2211 * dm_test_get_min_max_dc_plane_scaling_fp16() - Verify fp16 cap selection.
2212 * @test: KUnit test context.
2213 *
2214 * Verify if 64bpp fp16 formats use the fp16 scaling caps.
2215 */
dm_test_get_min_max_dc_plane_scaling_fp16(struct kunit * test)2216 static void dm_test_get_min_max_dc_plane_scaling_fp16(struct kunit *test)
2217 {
2218 struct amdgpu_device *adev;
2219 struct dc *dc;
2220 struct drm_framebuffer *fb;
2221 int min_downscale = 0;
2222 int max_upscale = 0;
2223
2224 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2225 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2226 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2227 KUNIT_ASSERT_NOT_NULL(test, adev);
2228 KUNIT_ASSERT_NOT_NULL(test, dc);
2229 KUNIT_ASSERT_NOT_NULL(test, fb);
2230
2231 adev->dm.dc = dc;
2232 dc->caps.planes[0].max_upscale_factor.fp16 = 2000;
2233 dc->caps.planes[0].max_downscale_factor.fp16 = 500;
2234
2235 fb->format = drm_format_info(DRM_FORMAT_ARGB16161616F);
2236 KUNIT_ASSERT_NOT_NULL(test, fb->format);
2237 amdgpu_dm_plane_get_min_max_dc_plane_scaling(&adev->ddev, fb,
2238 &min_downscale, &max_upscale);
2239 KUNIT_EXPECT_EQ(test, min_downscale, 500);
2240 KUNIT_EXPECT_EQ(test, max_upscale, 2000);
2241 }
2242
2243 /**
2244 * dm_test_helper_check_state_small_viewport_width() - Verify width rejection.
2245 * @test: KUnit test context.
2246 *
2247 * Verify if a viewport width below the minimum pipe-split width is rejected.
2248 */
dm_test_helper_check_state_small_viewport_width(struct kunit * test)2249 static void dm_test_helper_check_state_small_viewport_width(struct kunit *test)
2250 {
2251 struct drm_plane *plane;
2252 struct drm_plane_state *state;
2253 struct drm_crtc *crtc;
2254 struct drm_crtc_state *new_crtc_state;
2255 struct drm_framebuffer *fb;
2256
2257 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2258 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2259 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2260 new_crtc_state = kunit_kzalloc(test, sizeof(*new_crtc_state), GFP_KERNEL);
2261 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2262 KUNIT_ASSERT_NOT_NULL(test, plane);
2263 KUNIT_ASSERT_NOT_NULL(test, state);
2264 KUNIT_ASSERT_NOT_NULL(test, crtc);
2265 KUNIT_ASSERT_NOT_NULL(test, new_crtc_state);
2266 KUNIT_ASSERT_NOT_NULL(test, fb);
2267
2268 plane->type = DRM_PLANE_TYPE_OVERLAY;
2269 state->plane = plane;
2270 state->fb = fb;
2271 state->crtc = crtc;
2272 state->crtc_x = 0;
2273 state->crtc_y = 0;
2274 state->crtc_w = 10;
2275 state->crtc_h = 100;
2276 new_crtc_state->mode.crtc_hdisplay = 1920;
2277 new_crtc_state->mode.crtc_vdisplay = 1080;
2278
2279 KUNIT_EXPECT_EQ(test,
2280 amdgpu_dm_plane_helper_check_state(state, new_crtc_state),
2281 -EINVAL);
2282 }
2283
2284 /**
2285 * dm_test_helper_check_state_small_viewport_height() - Verify height rejection.
2286 * @test: KUnit test context.
2287 *
2288 * Verify if a negative-offset viewport with a too-small height is rejected.
2289 */
dm_test_helper_check_state_small_viewport_height(struct kunit * test)2290 static void dm_test_helper_check_state_small_viewport_height(struct kunit *test)
2291 {
2292 struct drm_plane *plane;
2293 struct drm_plane_state *state;
2294 struct drm_crtc *crtc;
2295 struct drm_crtc_state *new_crtc_state;
2296 struct drm_framebuffer *fb;
2297
2298 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2299 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2300 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2301 new_crtc_state = kunit_kzalloc(test, sizeof(*new_crtc_state), GFP_KERNEL);
2302 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2303 KUNIT_ASSERT_NOT_NULL(test, plane);
2304 KUNIT_ASSERT_NOT_NULL(test, state);
2305 KUNIT_ASSERT_NOT_NULL(test, crtc);
2306 KUNIT_ASSERT_NOT_NULL(test, new_crtc_state);
2307 KUNIT_ASSERT_NOT_NULL(test, fb);
2308
2309 plane->type = DRM_PLANE_TYPE_OVERLAY;
2310 state->plane = plane;
2311 state->fb = fb;
2312 state->crtc = crtc;
2313 state->crtc_x = -2;
2314 state->crtc_y = -95;
2315 state->crtc_w = 100;
2316 state->crtc_h = 100;
2317 new_crtc_state->mode.crtc_hdisplay = 1920;
2318 new_crtc_state->mode.crtc_vdisplay = 1080;
2319
2320 KUNIT_EXPECT_EQ(test,
2321 amdgpu_dm_plane_helper_check_state(state, new_crtc_state),
2322 -EINVAL);
2323 }
2324
2325 /**
2326 * dm_test_helper_check_state_bottom_clipped_height() - Verify bottom clipping.
2327 * @test: KUnit test context.
2328 *
2329 * Verify if a viewport clipped by the bottom edge to below the minimum height
2330 * is rejected.
2331 */
dm_test_helper_check_state_bottom_clipped_height(struct kunit * test)2332 static void dm_test_helper_check_state_bottom_clipped_height(struct kunit *test)
2333 {
2334 struct drm_plane *plane;
2335 struct drm_plane_state *state;
2336 struct drm_crtc *crtc;
2337 struct drm_crtc_state *new_crtc_state;
2338 struct drm_framebuffer *fb;
2339
2340 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2341 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2342 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2343 new_crtc_state = kunit_kzalloc(test, sizeof(*new_crtc_state), GFP_KERNEL);
2344 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2345 KUNIT_ASSERT_NOT_NULL(test, plane);
2346 KUNIT_ASSERT_NOT_NULL(test, state);
2347 KUNIT_ASSERT_NOT_NULL(test, crtc);
2348 KUNIT_ASSERT_NOT_NULL(test, new_crtc_state);
2349 KUNIT_ASSERT_NOT_NULL(test, fb);
2350
2351 plane->type = DRM_PLANE_TYPE_OVERLAY;
2352 state->plane = plane;
2353 state->fb = fb;
2354 state->crtc = crtc;
2355 state->crtc_x = 0;
2356 state->crtc_y = 95;
2357 state->crtc_w = 100;
2358 state->crtc_h = 100;
2359 new_crtc_state->mode.crtc_hdisplay = 1920;
2360 new_crtc_state->mode.crtc_vdisplay = 100;
2361
2362 KUNIT_EXPECT_EQ(test,
2363 amdgpu_dm_plane_helper_check_state(state, new_crtc_state),
2364 -EINVAL);
2365 }
2366
2367 /**
2368 * dm_test_helper_check_state_scaling_caps() - Verify DC scaling caps are applied.
2369 * @test: KUnit test context.
2370 *
2371 * Verify if helper_check_state converts DC plane scaling caps to DRM scale
2372 * limits and rejects scaling outside those limits.
2373 */
dm_test_helper_check_state_scaling_caps(struct kunit * test)2374 static void dm_test_helper_check_state_scaling_caps(struct kunit *test)
2375 {
2376 struct amdgpu_device *adev;
2377 struct dc *dc;
2378 struct drm_plane *plane;
2379 struct drm_plane_state *state;
2380 struct drm_crtc *crtc;
2381 struct drm_crtc_state *new_crtc_state;
2382 struct drm_framebuffer *fb;
2383
2384 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2385 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2386 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2387 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2388 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2389 new_crtc_state = kunit_kzalloc(test, sizeof(*new_crtc_state), GFP_KERNEL);
2390 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2391 KUNIT_ASSERT_NOT_NULL(test, adev);
2392 KUNIT_ASSERT_NOT_NULL(test, dc);
2393 KUNIT_ASSERT_NOT_NULL(test, plane);
2394 KUNIT_ASSERT_NOT_NULL(test, state);
2395 KUNIT_ASSERT_NOT_NULL(test, crtc);
2396 KUNIT_ASSERT_NOT_NULL(test, new_crtc_state);
2397 KUNIT_ASSERT_NOT_NULL(test, fb);
2398
2399 adev->dm.dc = dc;
2400 dc->caps.planes[0].max_upscale_factor.argb8888 = 1;
2401 dc->caps.planes[0].max_downscale_factor.argb8888 = 1;
2402
2403 plane->type = DRM_PLANE_TYPE_OVERLAY;
2404 plane->dev = &adev->ddev;
2405 crtc->dev = &adev->ddev;
2406 fb->width = 100;
2407 fb->height = 100;
2408 fb->format = drm_format_info(DRM_FORMAT_XRGB8888);
2409 KUNIT_ASSERT_NOT_NULL(test, fb->format);
2410
2411 state->plane = plane;
2412 state->fb = fb;
2413 state->crtc = crtc;
2414 state->src_w = 100 << 16;
2415 state->src_h = 100 << 16;
2416 state->crtc_w = 200;
2417 state->crtc_h = 200;
2418 new_crtc_state->crtc = crtc;
2419 new_crtc_state->mode.crtc_hdisplay = 1920;
2420 new_crtc_state->mode.crtc_vdisplay = 1080;
2421
2422 KUNIT_EXPECT_EQ(test,
2423 amdgpu_dm_plane_helper_check_state(state, new_crtc_state),
2424 -ERANGE);
2425 }
2426
2427 /**
2428 * dm_test_fill_dc_scaling_info_nv12_dcn1x() - Verify NV12 DCN1x rejection.
2429 * @test: KUnit test context.
2430 *
2431 * Verify if a non-zero NV12 source origin is rejected on DCN 1.0 to avoid the
2432 * known DCN1x hang.
2433 */
dm_test_fill_dc_scaling_info_nv12_dcn1x(struct kunit * test)2434 static void dm_test_fill_dc_scaling_info_nv12_dcn1x(struct kunit *test)
2435 {
2436 struct amdgpu_device *adev;
2437 struct drm_plane_state state = {0};
2438 struct drm_framebuffer fb = {0};
2439 struct dc_scaling_info info = {0};
2440
2441 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2442 KUNIT_ASSERT_NOT_NULL(test, adev);
2443
2444 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2445 fb.format = drm_format_info(DRM_FORMAT_NV12);
2446 KUNIT_ASSERT_NOT_NULL(test, fb.format);
2447
2448 state.fb = &fb;
2449 state.src_x = 10 << 16;
2450 state.src_y = 0;
2451 state.src_w = 100 << 16;
2452 state.src_h = 100 << 16;
2453 state.crtc_w = 100;
2454 state.crtc_h = 100;
2455
2456 KUNIT_EXPECT_EQ(test,
2457 amdgpu_dm_plane_fill_dc_scaling_info(adev, &state, &info),
2458 -EINVAL);
2459
2460 state.src_x = 0;
2461 state.src_y = 10 << 16;
2462 memset(&info, 0, sizeof(info));
2463
2464 KUNIT_EXPECT_EQ(test,
2465 amdgpu_dm_plane_fill_dc_scaling_info(adev, &state, &info),
2466 -EINVAL);
2467 }
2468
2469 /**
2470 * dm_test_fill_dc_scaling_info_plane_caps() - Verify scaling caps path.
2471 * @test: KUnit test context.
2472 *
2473 * Verify if scaling info uses plane caps when the state references a plane,
2474 * device, and framebuffer.
2475 */
dm_test_fill_dc_scaling_info_plane_caps(struct kunit * test)2476 static void dm_test_fill_dc_scaling_info_plane_caps(struct kunit *test)
2477 {
2478 struct amdgpu_device *adev;
2479 struct dc *dc;
2480 struct drm_plane *plane;
2481 struct drm_plane_state *state;
2482 struct drm_framebuffer *fb;
2483 struct dc_scaling_info info = {0};
2484
2485 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2486 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2487 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2488 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2489 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2490 KUNIT_ASSERT_NOT_NULL(test, adev);
2491 KUNIT_ASSERT_NOT_NULL(test, dc);
2492 KUNIT_ASSERT_NOT_NULL(test, plane);
2493 KUNIT_ASSERT_NOT_NULL(test, state);
2494 KUNIT_ASSERT_NOT_NULL(test, fb);
2495
2496 adev->dm.dc = dc;
2497 dc->caps.planes[0].max_upscale_factor.argb8888 = 16000;
2498 dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
2499
2500 plane->dev = &adev->ddev;
2501 fb->format = drm_format_info(DRM_FORMAT_XRGB8888);
2502 KUNIT_ASSERT_NOT_NULL(test, fb->format);
2503
2504 state->plane = plane;
2505 state->fb = fb;
2506 state->src_w = 100 << 16;
2507 state->src_h = 100 << 16;
2508 state->crtc_w = 100;
2509 state->crtc_h = 100;
2510
2511 KUNIT_EXPECT_EQ(test,
2512 amdgpu_dm_plane_fill_dc_scaling_info(adev, state, &info),
2513 0);
2514 }
2515
2516 /**
2517 * dm_test_get_cursor_position_bad_size() - Verify oversized cursor rejection.
2518 * @test: KUnit test context.
2519 *
2520 * Verify if a cursor larger than the CRTC maximum is rejected.
2521 */
dm_test_get_cursor_position_bad_size(struct kunit * test)2522 static void dm_test_get_cursor_position_bad_size(struct kunit *test)
2523 {
2524 struct amdgpu_device *adev;
2525 struct amdgpu_crtc *amdgpu_crtc;
2526 struct drm_plane *plane;
2527 struct drm_plane_state *state;
2528 struct drm_framebuffer *fb;
2529 struct dc_cursor_position position = {0};
2530
2531 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2532 amdgpu_crtc = kunit_kzalloc(test, sizeof(*amdgpu_crtc), GFP_KERNEL);
2533 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2534 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2535 fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
2536 KUNIT_ASSERT_NOT_NULL(test, adev);
2537 KUNIT_ASSERT_NOT_NULL(test, amdgpu_crtc);
2538 KUNIT_ASSERT_NOT_NULL(test, plane);
2539 KUNIT_ASSERT_NOT_NULL(test, state);
2540 KUNIT_ASSERT_NOT_NULL(test, fb);
2541
2542 amdgpu_crtc->max_cursor_width = 64;
2543 amdgpu_crtc->max_cursor_height = 64;
2544 plane->dev = &adev->ddev;
2545 plane->state = state;
2546 state->fb = fb;
2547 state->crtc_w = 128;
2548 state->crtc_h = 32;
2549
2550 KUNIT_EXPECT_EQ(test,
2551 amdgpu_dm_plane_get_cursor_position(plane, &amdgpu_crtc->base, &position),
2552 -EINVAL);
2553 }
2554
2555 /**
2556 * dm_test_format_mod_supported_d_swizzle_reject() - Verify D swizzle rejection.
2557 * @test: KUnit test context.
2558 *
2559 * Verify if a D micro-swizzle modifier is rejected for formats narrower than
2560 * 8 bytes per pixel.
2561 */
dm_test_format_mod_supported_d_swizzle_reject(struct kunit * test)2562 static void dm_test_format_mod_supported_d_swizzle_reject(struct kunit *test)
2563 {
2564 struct amdgpu_device *adev;
2565 struct drm_plane *plane;
2566 u64 listed_mod;
2567
2568 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2569 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2570 KUNIT_ASSERT_NOT_NULL(test, adev);
2571 KUNIT_ASSERT_NOT_NULL(test, plane);
2572
2573 adev->family = AMDGPU_FAMILY_RV;
2574 plane->dev = &adev->ddev;
2575
2576 listed_mod = AMD_FMT_MOD |
2577 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
2578 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9);
2579 plane->modifiers = &listed_mod;
2580 plane->modifier_count = 1;
2581
2582 KUNIT_EXPECT_FALSE(test,
2583 amdgpu_dm_plane_format_mod_supported(plane, DRM_FORMAT_XRGB8888,
2584 listed_mod));
2585 }
2586
2587 /**
2588 * dm_test_atomic_async_check_rejects() - Verify async check rejections.
2589 * @test: KUnit test context.
2590 *
2591 * Verify if async flip on non-overlay planes and async cursor update on
2592 * non-cursor planes are rejected.
2593 */
dm_test_atomic_async_check_rejects(struct kunit * test)2594 static void dm_test_atomic_async_check_rejects(struct kunit *test)
2595 {
2596 struct drm_plane *plane;
2597
2598 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2599 KUNIT_ASSERT_NOT_NULL(test, plane);
2600
2601 plane->type = DRM_PLANE_TYPE_PRIMARY;
2602 KUNIT_EXPECT_EQ(test,
2603 amdgpu_dm_plane_atomic_async_check(plane, NULL, true),
2604 -EINVAL);
2605 KUNIT_EXPECT_EQ(test,
2606 amdgpu_dm_plane_atomic_async_check(plane, NULL, false),
2607 -EINVAL);
2608 }
2609
2610 /**
2611 * dm_test_atomic_async_check_overlay_cursor() - Verify overlay cursor rejection.
2612 * @test: KUnit test context.
2613 *
2614 * Verify if async cursor updates are rejected while the CRTC is using an
2615 * overlay cursor mode.
2616 */
dm_test_atomic_async_check_overlay_cursor(struct kunit * test)2617 static void dm_test_atomic_async_check_overlay_cursor(struct kunit *test)
2618 {
2619 struct drm_atomic_commit *state;
2620 struct __drm_planes_state *planes;
2621 struct __drm_crtcs_state *crtcs;
2622 struct drm_plane *plane;
2623 struct drm_plane_state *plane_state;
2624 struct drm_crtc *crtc;
2625 struct dm_crtc_state *dm_crtc_state;
2626
2627 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2628 planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
2629 crtcs = kunit_kzalloc(test, sizeof(*crtcs), GFP_KERNEL);
2630 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2631 plane_state = kunit_kzalloc(test, sizeof(*plane_state), GFP_KERNEL);
2632 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2633 dm_crtc_state = kunit_kzalloc(test, sizeof(*dm_crtc_state), GFP_KERNEL);
2634 KUNIT_ASSERT_NOT_NULL(test, state);
2635 KUNIT_ASSERT_NOT_NULL(test, planes);
2636 KUNIT_ASSERT_NOT_NULL(test, crtcs);
2637 KUNIT_ASSERT_NOT_NULL(test, plane);
2638 KUNIT_ASSERT_NOT_NULL(test, plane_state);
2639 KUNIT_ASSERT_NOT_NULL(test, crtc);
2640 KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
2641
2642 plane->type = DRM_PLANE_TYPE_CURSOR;
2643 plane->index = 0;
2644 crtc->index = 0;
2645 plane_state->crtc = crtc;
2646 dm_crtc_state->cursor_mode = DM_CURSOR_OVERLAY_MODE;
2647 state->planes = planes;
2648 state->crtcs = crtcs;
2649 state->planes[0].new_state = plane_state;
2650 state->crtcs[0].new_state = &dm_crtc_state->base;
2651
2652 KUNIT_EXPECT_EQ(test,
2653 amdgpu_dm_plane_atomic_async_check(plane, state, false),
2654 -EINVAL);
2655
2656 dm_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE;
2657 KUNIT_EXPECT_EQ(test,
2658 amdgpu_dm_plane_atomic_async_check(plane, state, false),
2659 0);
2660 }
2661
dm_test_init_atomic_check_state(struct kunit * test,struct drm_atomic_commit ** state,struct drm_plane ** plane,struct dm_plane_state ** dm_plane_state,struct drm_crtc_state ** new_crtc_state,struct drm_framebuffer ** fb)2662 static struct amdgpu_device *dm_test_init_atomic_check_state(struct kunit *test,
2663 struct drm_atomic_commit **state,
2664 struct drm_plane **plane,
2665 struct dm_plane_state **dm_plane_state,
2666 struct drm_crtc_state **new_crtc_state,
2667 struct drm_framebuffer **fb)
2668 {
2669 struct amdgpu_device *adev;
2670 struct dc *dc;
2671 struct __drm_planes_state *planes;
2672 struct __drm_crtcs_state *crtcs;
2673 struct dc_plane_state *dc_plane_state;
2674 struct drm_crtc *crtc;
2675
2676 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2677 dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
2678 *state = kunit_kzalloc(test, sizeof(**state), GFP_KERNEL);
2679 planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
2680 crtcs = kunit_kzalloc(test, sizeof(*crtcs), GFP_KERNEL);
2681 *plane = kunit_kzalloc(test, sizeof(**plane), GFP_KERNEL);
2682 *dm_plane_state = kunit_kzalloc(test, sizeof(**dm_plane_state), GFP_KERNEL);
2683 dc_plane_state = kunit_kzalloc(test, sizeof(*dc_plane_state), GFP_KERNEL);
2684 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2685 *new_crtc_state = kunit_kzalloc(test, sizeof(**new_crtc_state), GFP_KERNEL);
2686 *fb = kunit_kzalloc(test, sizeof(**fb), GFP_KERNEL);
2687 KUNIT_ASSERT_NOT_NULL(test, adev);
2688 KUNIT_ASSERT_NOT_NULL(test, dc);
2689 KUNIT_ASSERT_NOT_NULL(test, *state);
2690 KUNIT_ASSERT_NOT_NULL(test, planes);
2691 KUNIT_ASSERT_NOT_NULL(test, crtcs);
2692 KUNIT_ASSERT_NOT_NULL(test, *plane);
2693 KUNIT_ASSERT_NOT_NULL(test, *dm_plane_state);
2694 KUNIT_ASSERT_NOT_NULL(test, dc_plane_state);
2695 KUNIT_ASSERT_NOT_NULL(test, crtc);
2696 KUNIT_ASSERT_NOT_NULL(test, *new_crtc_state);
2697 KUNIT_ASSERT_NOT_NULL(test, *fb);
2698
2699 adev->dm.dc = dc;
2700 dc->caps.planes[0].max_upscale_factor.argb8888 = 1000;
2701 dc->caps.planes[0].max_downscale_factor.argb8888 = 1000;
2702 dc->caps.planes[0].max_upscale_factor.nv12 = 1000;
2703 dc->caps.planes[0].max_downscale_factor.nv12 = 1000;
2704
2705 (*plane)->dev = &adev->ddev;
2706 (*plane)->index = 0;
2707 (*plane)->type = DRM_PLANE_TYPE_OVERLAY;
2708 (*plane)->name = "kunit-plane";
2709 crtc->dev = &adev->ddev;
2710 crtc->index = 0;
2711 (*fb)->width = 100;
2712 (*fb)->height = 100;
2713 (*fb)->format = drm_format_info(DRM_FORMAT_XRGB8888);
2714 KUNIT_ASSERT_NOT_NULL(test, (*fb)->format);
2715
2716 (*dm_plane_state)->base.plane = *plane;
2717 (*dm_plane_state)->base.state = *state;
2718 (*dm_plane_state)->base.crtc = crtc;
2719 (*dm_plane_state)->base.fb = *fb;
2720 (*dm_plane_state)->base.src_w = 100 << 16;
2721 (*dm_plane_state)->base.src_h = 100 << 16;
2722 (*dm_plane_state)->base.crtc_w = 100;
2723 (*dm_plane_state)->base.crtc_h = 100;
2724 (*dm_plane_state)->dc_state = dc_plane_state;
2725
2726 (*new_crtc_state)->crtc = crtc;
2727 (*new_crtc_state)->enable = true;
2728 (*new_crtc_state)->mode.crtc_hdisplay = 1920;
2729 (*new_crtc_state)->mode.crtc_vdisplay = 1080;
2730
2731 (*state)->planes = planes;
2732 (*state)->crtcs = crtcs;
2733 (*state)->planes[0].new_state = &(*dm_plane_state)->base;
2734 (*state)->crtcs[0].new_state = *new_crtc_state;
2735
2736 return adev;
2737 }
2738
2739 /**
2740 * dm_test_atomic_check_no_dc_state() - Verify missing DC plane state succeeds.
2741 * @test: KUnit test context.
2742 *
2743 * Verify if atomic_check exits before deeper validation when the DM plane state
2744 * has no DC plane state attached.
2745 */
dm_test_atomic_check_no_dc_state(struct kunit * test)2746 static void dm_test_atomic_check_no_dc_state(struct kunit *test)
2747 {
2748 struct amdgpu_device *adev;
2749 struct drm_atomic_commit *state;
2750 struct __drm_planes_state *planes;
2751 struct drm_plane *plane;
2752 struct dm_plane_state *dm_plane_state;
2753
2754 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2755 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2756 planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
2757 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2758 dm_plane_state = kunit_kzalloc(test, sizeof(*dm_plane_state), GFP_KERNEL);
2759 KUNIT_ASSERT_NOT_NULL(test, adev);
2760 KUNIT_ASSERT_NOT_NULL(test, state);
2761 KUNIT_ASSERT_NOT_NULL(test, planes);
2762 KUNIT_ASSERT_NOT_NULL(test, plane);
2763 KUNIT_ASSERT_NOT_NULL(test, dm_plane_state);
2764
2765 plane->dev = &adev->ddev;
2766 plane->index = 0;
2767 dm_plane_state->base.plane = plane;
2768 state->planes = planes;
2769 state->planes[0].new_state = &dm_plane_state->base;
2770
2771 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_atomic_check(plane, state), 0);
2772 }
2773
2774 /**
2775 * dm_test_atomic_check_missing_crtc_state() - Verify missing CRTC state fails.
2776 * @test: KUnit test context.
2777 *
2778 * Verify if atomic_check rejects a plane with DC state when the atomic CRTC
2779 * state is absent.
2780 */
dm_test_atomic_check_missing_crtc_state(struct kunit * test)2781 static void dm_test_atomic_check_missing_crtc_state(struct kunit *test)
2782 {
2783 struct amdgpu_device *adev;
2784 struct drm_atomic_commit *state;
2785 struct __drm_planes_state *planes;
2786 struct __drm_crtcs_state *crtcs;
2787 struct drm_plane *plane;
2788 struct dm_plane_state *dm_plane_state;
2789 struct dc_plane_state *dc_plane_state;
2790 struct drm_crtc *crtc;
2791
2792 adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
2793 state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
2794 planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
2795 crtcs = kunit_kzalloc(test, sizeof(*crtcs), GFP_KERNEL);
2796 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2797 dm_plane_state = kunit_kzalloc(test, sizeof(*dm_plane_state), GFP_KERNEL);
2798 dc_plane_state = kunit_kzalloc(test, sizeof(*dc_plane_state), GFP_KERNEL);
2799 crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
2800 KUNIT_ASSERT_NOT_NULL(test, adev);
2801 KUNIT_ASSERT_NOT_NULL(test, state);
2802 KUNIT_ASSERT_NOT_NULL(test, planes);
2803 KUNIT_ASSERT_NOT_NULL(test, crtcs);
2804 KUNIT_ASSERT_NOT_NULL(test, plane);
2805 KUNIT_ASSERT_NOT_NULL(test, dm_plane_state);
2806 KUNIT_ASSERT_NOT_NULL(test, dc_plane_state);
2807 KUNIT_ASSERT_NOT_NULL(test, crtc);
2808
2809 plane->dev = &adev->ddev;
2810 plane->index = 0;
2811 crtc->index = 0;
2812 dm_plane_state->base.plane = plane;
2813 dm_plane_state->base.crtc = crtc;
2814 dm_plane_state->dc_state = dc_plane_state;
2815 state->planes = planes;
2816 state->crtcs = crtcs;
2817 state->planes[0].new_state = &dm_plane_state->base;
2818
2819 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_atomic_check(plane, state), -EINVAL);
2820 }
2821
2822 /**
2823 * dm_test_atomic_check_helper_failure() - Verify helper-check failures return.
2824 * @test: KUnit test context.
2825 *
2826 * Verify if atomic_check returns before DC validation when the DRM helper state
2827 * validation rejects the plane.
2828 */
dm_test_atomic_check_helper_failure(struct kunit * test)2829 static void dm_test_atomic_check_helper_failure(struct kunit *test)
2830 {
2831 struct drm_atomic_commit *state;
2832 struct drm_plane *plane;
2833 struct dm_plane_state *dm_plane_state;
2834 struct drm_crtc_state *new_crtc_state;
2835 struct drm_framebuffer *fb;
2836
2837 dm_test_init_atomic_check_state(test, &state, &plane, &dm_plane_state,
2838 &new_crtc_state, &fb);
2839 dm_plane_state->base.crtc_w = 10;
2840
2841 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_atomic_check(plane, state), -EINVAL);
2842 }
2843
2844 /**
2845 * dm_test_atomic_check_color_pipeline_conflict() - Verify color conflict rejection.
2846 * @test: KUnit test context.
2847 *
2848 * Verify if atomic_check rejects use of both plane COLOR_PIPELINE and CRTC
2849 * DEGAMMA_LUT before DC validation.
2850 */
dm_test_atomic_check_color_pipeline_conflict(struct kunit * test)2851 static void dm_test_atomic_check_color_pipeline_conflict(struct kunit *test)
2852 {
2853 struct drm_atomic_commit *state;
2854 struct drm_plane *plane;
2855 struct dm_plane_state *dm_plane_state;
2856 struct drm_crtc_state *new_crtc_state;
2857 struct drm_framebuffer *fb;
2858 void *color_pipeline;
2859 void *degamma_lut;
2860
2861 dm_test_init_atomic_check_state(test, &state, &plane, &dm_plane_state,
2862 &new_crtc_state, &fb);
2863 color_pipeline = kunit_kzalloc(test, 1, GFP_KERNEL);
2864 degamma_lut = kunit_kzalloc(test, 1, GFP_KERNEL);
2865 KUNIT_ASSERT_NOT_NULL(test, color_pipeline);
2866 KUNIT_ASSERT_NOT_NULL(test, degamma_lut);
2867
2868 dm_plane_state->base.color_pipeline = color_pipeline;
2869 new_crtc_state->degamma_lut = degamma_lut;
2870
2871 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_atomic_check(plane, state), -EINVAL);
2872 }
2873
2874 /**
2875 * dm_test_atomic_check_scaling_failure() - Verify scaling-info failures return.
2876 * @test: KUnit test context.
2877 *
2878 * Verify if atomic_check returns the scaling-info error before DC validation.
2879 */
dm_test_atomic_check_scaling_failure(struct kunit * test)2880 static void dm_test_atomic_check_scaling_failure(struct kunit *test)
2881 {
2882 struct amdgpu_device *adev;
2883 struct drm_atomic_commit *state;
2884 struct drm_plane *plane;
2885 struct dm_plane_state *dm_plane_state;
2886 struct drm_crtc_state *new_crtc_state;
2887 struct drm_framebuffer *fb;
2888
2889 adev = dm_test_init_atomic_check_state(test, &state, &plane, &dm_plane_state,
2890 &new_crtc_state, &fb);
2891 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2892 fb->width = 200;
2893 fb->format = drm_format_info(DRM_FORMAT_NV12);
2894 KUNIT_ASSERT_NOT_NULL(test, fb->format);
2895 dm_plane_state->base.src_x = 1 << 16;
2896
2897 KUNIT_EXPECT_EQ(test, amdgpu_dm_plane_atomic_check(plane, state), -EINVAL);
2898 }
2899
2900 /**
2901 * dm_test_panic_flush_no_dc_state() - Verify panic flush exits without DC state.
2902 * @test: KUnit test context.
2903 *
2904 * Verify if panic_flush returns without dereferencing DC state when the current
2905 * plane state has no DC plane state attached.
2906 */
dm_test_panic_flush_no_dc_state(struct kunit * test)2907 static void dm_test_panic_flush_no_dc_state(struct kunit *test)
2908 {
2909 struct drm_plane *plane;
2910 struct dm_plane_state *dm_plane_state;
2911
2912 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2913 dm_plane_state = kunit_kzalloc(test, sizeof(*dm_plane_state), GFP_KERNEL);
2914 KUNIT_ASSERT_NOT_NULL(test, plane);
2915 KUNIT_ASSERT_NOT_NULL(test, dm_plane_state);
2916
2917 plane->state = &dm_plane_state->base;
2918
2919 amdgpu_dm_plane_panic_flush(plane);
2920 }
2921
2922 static const struct drm_plane_funcs dm_test_plane_reset_funcs = {
2923 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
2924 };
2925
2926 /**
2927 * dm_test_plane_reset_initializes_state() - Verify reset installs default state.
2928 * @test: KUnit test context.
2929 *
2930 * Verify amdgpu_dm_plane_drm_plane_reset() destroys the existing plane state,
2931 * allocates a fresh dm_plane_state, and initializes the AMD-specific transfer
2932 * function and HDR multiplier defaults.
2933 */
dm_test_plane_reset_initializes_state(struct kunit * test)2934 static void dm_test_plane_reset_initializes_state(struct kunit *test)
2935 {
2936 struct dm_plane_state *old_state;
2937 struct dm_plane_state *new_state;
2938 struct drm_plane *plane;
2939
2940 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2941 KUNIT_ASSERT_NOT_NULL(test, plane);
2942
2943 /*
2944 * Provide an existing state plus a funcs table so reset exercises the
2945 * destroy-existing-state path. The destroy hook frees this state, so it
2946 * must be a plain (non-KUnit-managed) allocation.
2947 */
2948 old_state = kzalloc_obj(*old_state);
2949 KUNIT_ASSERT_NOT_NULL(test, old_state);
2950 plane->funcs = &dm_test_plane_reset_funcs;
2951 plane->state = &old_state->base;
2952
2953 amdgpu_dm_plane_drm_plane_reset(plane);
2954
2955 KUNIT_ASSERT_NOT_NULL(test, plane->state);
2956 new_state = to_dm_plane_state(plane->state);
2957 KUNIT_EXPECT_EQ(test, new_state->degamma_tf, AMDGPU_TRANSFER_FUNCTION_DEFAULT);
2958 KUNIT_EXPECT_EQ(test, new_state->hdr_mult, AMDGPU_HDR_MULT_DEFAULT);
2959 KUNIT_EXPECT_EQ(test, new_state->shaper_tf, AMDGPU_TRANSFER_FUNCTION_DEFAULT);
2960 KUNIT_EXPECT_EQ(test, new_state->blend_tf, AMDGPU_TRANSFER_FUNCTION_DEFAULT);
2961
2962 kfree(new_state);
2963 }
2964
2965 /**
2966 * dm_test_plane_duplicate_state_copies_fields() - Verify state duplication.
2967 * @test: KUnit test context.
2968 *
2969 * Verify amdgpu_dm_plane_drm_plane_duplicate_state() allocates a new state and
2970 * copies the transfer-function and HDR-multiplier fields from the current
2971 * plane state when no DC state or color blob is attached.
2972 */
dm_test_plane_duplicate_state_copies_fields(struct kunit * test)2973 static void dm_test_plane_duplicate_state_copies_fields(struct kunit *test)
2974 {
2975 struct dm_plane_state *old_state;
2976 struct drm_plane_state *dup_base;
2977 struct dm_plane_state *dup_state;
2978 struct drm_plane *plane;
2979
2980 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
2981 old_state = kunit_kzalloc(test, sizeof(*old_state), GFP_KERNEL);
2982 KUNIT_ASSERT_NOT_NULL(test, plane);
2983 KUNIT_ASSERT_NOT_NULL(test, old_state);
2984
2985 old_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_PQ_EOTF;
2986 old_state->hdr_mult = 0x123456789ULL;
2987 old_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_IDENTITY;
2988 old_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
2989 plane->state = &old_state->base;
2990
2991 dup_base = amdgpu_dm_plane_drm_plane_duplicate_state(plane);
2992 KUNIT_ASSERT_NOT_NULL(test, dup_base);
2993
2994 dup_state = to_dm_plane_state(dup_base);
2995 KUNIT_EXPECT_EQ(test, dup_state->degamma_tf, AMDGPU_TRANSFER_FUNCTION_PQ_EOTF);
2996 KUNIT_EXPECT_EQ(test, dup_state->hdr_mult, 0x123456789ULL);
2997 KUNIT_EXPECT_EQ(test, dup_state->shaper_tf, AMDGPU_TRANSFER_FUNCTION_IDENTITY);
2998 KUNIT_EXPECT_EQ(test, dup_state->blend_tf, AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF);
2999 KUNIT_EXPECT_NULL(test, dup_state->dc_state);
3000
3001 kfree(dup_state);
3002 }
3003
3004 /**
3005 * dm_test_plane_destroy_state_minimal() - Verify destroy of a minimal state.
3006 * @test: KUnit test context.
3007 *
3008 * Verify amdgpu_dm_plane_drm_plane_destroy_state() tears down a plane state
3009 * that has no color blobs or DC plane state attached without dereferencing
3010 * NULL resources.
3011 */
dm_test_plane_destroy_state_minimal(struct kunit * test)3012 static void dm_test_plane_destroy_state_minimal(struct kunit *test)
3013 {
3014 struct dm_plane_state *dm_plane_state;
3015 struct drm_plane *plane;
3016
3017 plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
3018 KUNIT_ASSERT_NOT_NULL(test, plane);
3019
3020 /* destroy_state frees the state itself, so use a plain allocation. */
3021 dm_plane_state = kzalloc_obj(*dm_plane_state);
3022 KUNIT_ASSERT_NOT_NULL(test, dm_plane_state);
3023
3024 amdgpu_dm_plane_drm_plane_destroy_state(plane, &dm_plane_state->base);
3025 }
3026
3027 static struct kunit_case amdgpu_dm_plane_test_cases[] = {
3028 /* amdgpu_dm_plane_is_video_format() */
3029 KUNIT_CASE(dm_test_plane_is_video_format_known_video),
3030 /* amdgpu_dm_plane_get_format_info() */
3031 KUNIT_CASE(dm_test_get_format_info),
3032 /* amdgpu_dm_plane_fill_blending_from_plane_state() */
3033 KUNIT_CASE(dm_test_fill_blending_defaults),
3034 KUNIT_CASE(dm_test_fill_blending_premulti_alpha_format),
3035 KUNIT_CASE(dm_test_fill_blending_coverage_alpha_format),
3036 KUNIT_CASE(dm_test_fill_blending_global_alpha),
3037 KUNIT_CASE(dm_test_fill_blending_global_alpha_dcn42),
3038 /* amdgpu_dm_plane_modifier_* helpers() */
3039 KUNIT_CASE(dm_test_modifier_has_dcc),
3040 KUNIT_CASE(dm_test_modifier_gfx9_swizzle_mode),
3041 /* amdgpu_dm_plane_get_plane_formats() */
3042 KUNIT_CASE(dm_test_get_plane_formats),
3043 KUNIT_CASE(dm_test_get_plane_formats_overlay_universal_cap),
3044 /* amdgpu_dm_plane_get_plane_modifiers() */
3045 KUNIT_CASE(dm_test_get_plane_modifiers),
3046 KUNIT_CASE(dm_test_get_plane_modifiers_gfx9),
3047 KUNIT_CASE(dm_test_get_plane_modifiers_rv),
3048 KUNIT_CASE(dm_test_get_plane_modifiers_rv_constant_encode),
3049 KUNIT_CASE(dm_test_get_plane_modifiers_gfx10_1),
3050 KUNIT_CASE(dm_test_get_plane_modifiers_gfx10_3),
3051 KUNIT_CASE(dm_test_get_plane_modifiers_gfx11_64k_first),
3052 KUNIT_CASE(dm_test_get_plane_modifiers_gfx11_256k_first),
3053 KUNIT_CASE(dm_test_get_plane_modifiers_gfx12),
3054 /* amdgpu_dm_plane_fill_dc_scaling_info() */
3055 KUNIT_CASE(dm_test_fill_dc_scaling_info),
3056 KUNIT_CASE(dm_test_fill_dc_scaling_info_nv12_dcn1x),
3057 KUNIT_CASE(dm_test_fill_dc_scaling_info_plane_caps),
3058 /* amdgpu_dm_plane_get_min_max_dc_plane_scaling() */
3059 KUNIT_CASE(dm_test_get_min_max_dc_plane_scaling),
3060 KUNIT_CASE(dm_test_get_min_max_dc_plane_scaling_fp16),
3061 /* amdgpu_dm_plane_fill_plane_buffer_attributes() */
3062 KUNIT_CASE(dm_test_fill_plane_buffer_attributes_video),
3063 KUNIT_CASE(dm_test_fill_plane_buffer_attributes_gfx12),
3064 /* amdgpu_dm_plane_get_cursor_position() */
3065 KUNIT_CASE(dm_test_get_cursor_position),
3066 KUNIT_CASE(dm_test_get_cursor_position_bad_size),
3067 /* amdgpu_dm_plane_format_mod_supported() */
3068 KUNIT_CASE(dm_test_format_mod_supported),
3069 KUNIT_CASE(dm_test_format_mod_supported_d_swizzle_reject),
3070 /* amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers() */
3071 KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_from_modifiers),
3072 KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_block0),
3073 KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_block_unconstrained),
3074 KUNIT_CASE(dm_test_fill_gfx12_plane_attributes_validate_fails),
3075 /* amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers() */
3076 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_from_modifiers),
3077 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc),
3078 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_validate_fails),
3079 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_64b_no_128bcl),
3080 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_128b),
3081 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_rbplus_unconstrained),
3082 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_gfx9_64b),
3083 KUNIT_CASE(dm_test_fill_gfx9_plane_attributes_dcc_gfx9_unconstrained),
3084 /* amdgpu_dm_plane_helper_check_state() */
3085 KUNIT_CASE(dm_test_helper_check_state_viewport_reject),
3086 KUNIT_CASE(dm_test_helper_check_state_small_viewport_width),
3087 KUNIT_CASE(dm_test_helper_check_state_small_viewport_height),
3088 KUNIT_CASE(dm_test_helper_check_state_bottom_clipped_height),
3089 KUNIT_CASE(dm_test_helper_check_state_scaling_caps),
3090 /* amdgpu_dm_plane_atomic_async_check() */
3091 KUNIT_CASE(dm_test_atomic_async_check_rejects),
3092 KUNIT_CASE(dm_test_atomic_async_check_overlay_cursor),
3093 /* amdgpu_dm_plane_atomic_check() */
3094 KUNIT_CASE(dm_test_atomic_check_no_dc_state),
3095 KUNIT_CASE(dm_test_atomic_check_missing_crtc_state),
3096 KUNIT_CASE(dm_test_atomic_check_helper_failure),
3097 KUNIT_CASE(dm_test_atomic_check_color_pipeline_conflict),
3098 KUNIT_CASE(dm_test_atomic_check_scaling_failure),
3099 /* amdgpu_dm_plane_panic_flush() */
3100 KUNIT_CASE(dm_test_panic_flush_no_dc_state),
3101 /* amdgpu_dm_plane_drm_plane_reset() */
3102 KUNIT_CASE(dm_test_plane_reset_initializes_state),
3103 /* amdgpu_dm_plane_drm_plane_duplicate_state() */
3104 KUNIT_CASE(dm_test_plane_duplicate_state_copies_fields),
3105 /* amdgpu_dm_plane_drm_plane_destroy_state() */
3106 KUNIT_CASE(dm_test_plane_destroy_state_minimal),
3107 /* amdgpu_dm_plane_add_modifier() */
3108 KUNIT_CASE(dm_test_add_modifier_appends_value),
3109 KUNIT_CASE(dm_test_add_modifier_grows_capacity),
3110 KUNIT_CASE(dm_test_add_modifier_noop_when_mods_null),
3111 /* amdgpu_dm_plane_fill_gfx9_tiling_info_from_device() */
3112 KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_pre_10_3),
3113 KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_10_3_plus),
3114 /* amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier() */
3115 KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_modifier_linear),
3116 KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv),
3117 KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_modifier_nv),
3118 /* amdgpu_dm_plane_validate_dcc() */
3119 KUNIT_CASE(dm_test_validate_dcc_disabled_returns_success),
3120 KUNIT_CASE(dm_test_validate_dcc_video_non_gfx12_fails),
3121 KUNIT_CASE(dm_test_validate_dcc_missing_cap_func_fails),
3122 KUNIT_CASE(dm_test_validate_dcc_cap_callback_fails),
3123 KUNIT_CASE(dm_test_validate_dcc_not_capable_fails),
3124 KUNIT_CASE(dm_test_validate_dcc_success_and_scan_mapping),
3125 KUNIT_CASE(dm_test_validate_dcc_independent_64b_mismatch_fails),
3126 {}
3127 };
3128
3129 static struct kunit_suite amdgpu_dm_plane_test_suite = {
3130 .name = "amdgpu_dm_plane",
3131 .test_cases = amdgpu_dm_plane_test_cases,
3132 };
3133
3134 kunit_test_suite(amdgpu_dm_plane_test_suite);
3135
3136 MODULE_DESCRIPTION("KUnit tests for amdgpu_dm_plane");
3137 MODULE_LICENSE("Dual MIT/GPL");
3138