1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 #include "phy-qcom-qmp-pcs-pcie-v4.h" 32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 33 #include "phy-qcom-qmp-pcs-pcie-v5.h" 34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 35 #include "phy-qcom-qmp-pcs-pcie-v6.h" 36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h" 38 #include "phy-qcom-qmp-pcs-v6_30.h" 39 #include "phy-qcom-qmp-pcie-qhp.h" 40 #include "phy-qcom-qmp-qserdes-com-v8.h" 41 #include "phy-qcom-qmp-pcs-pcie-v8.h" 42 #include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h" 43 #include "phy-qcom-qmp-pcs-pcie-v10.h" 44 #include "phy-qcom-qmp-pcs-pcie-v10_60.h" 45 46 #define PHY_INIT_COMPLETE_TIMEOUT 10000 47 48 /* set of registers with offsets different per-PHY */ 49 enum qphy_reg_layout { 50 /* PCS registers */ 51 QPHY_SW_RESET, 52 QPHY_START_CTRL, 53 QPHY_PCS_STATUS, 54 QPHY_PCS_POWER_DOWN_CONTROL, 55 /* Keep last to ensure regs_layout arrays are properly initialized */ 56 QPHY_LAYOUT_SIZE 57 }; 58 59 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 60 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 61 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 62 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 64 }; 65 66 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 67 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 68 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 69 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 70 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 71 }; 72 73 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 74 [QPHY_SW_RESET] = 0x00, 75 [QPHY_START_CTRL] = 0x08, 76 [QPHY_PCS_STATUS] = 0x2ac, 77 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 78 }; 79 80 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 82 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 83 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 85 }; 86 87 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 88 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 89 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 90 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 91 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 92 }; 93 94 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 95 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 96 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 97 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 98 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 99 }; 100 101 static const unsigned int pciephy_v7_regs_layout[QPHY_LAYOUT_SIZE] = { 102 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET, 103 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL, 104 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1, 105 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL, 106 }; 107 108 static const unsigned int pciephy_v8_regs_layout[QPHY_LAYOUT_SIZE] = { 109 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 110 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 111 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 112 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 113 }; 114 115 static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_START_CTRL] = QPHY_V8_50_PCS_START_CONTROL, 117 [QPHY_PCS_STATUS] = QPHY_V8_50_PCS_STATUS1, 118 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_50_PCS_POWER_DOWN_CONTROL, 119 }; 120 121 static const unsigned int pciephy_v10_regs_layout[QPHY_LAYOUT_SIZE] = { 122 [QPHY_SW_RESET] = QPHY_V10_PCS_SW_RESET, 123 [QPHY_START_CTRL] = QPHY_V10_PCS_START_CONTROL, 124 [QPHY_PCS_STATUS] = QPHY_V10_PCS_PCS_STATUS1, 125 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_PCS_POWER_DOWN_CONTROL, 126 }; 127 128 static const unsigned int pciephy_v10_60_regs_layout[QPHY_LAYOUT_SIZE] = { 129 [QPHY_SW_RESET] = QPHY_V10_60_PCS_SW_RESET, 130 [QPHY_START_CTRL] = QPHY_V10_60_PCS_START_CONTROL, 131 [QPHY_PCS_STATUS] = QPHY_V10_60_PCS_PCS_STATUS1, 132 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_60_PCS_POWER_DOWN_CONTROL, 133 }; 134 135 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 168 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 169 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 170 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 171 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 172 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 173 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 178 }; 179 180 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 181 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 182 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 183 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 184 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 185 }; 186 187 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 189 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 190 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 191 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 192 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 193 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 194 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 195 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 196 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 197 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 198 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 199 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 200 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 201 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 202 }; 203 204 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 215 }; 216 217 static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_serdes_tbl[] = { 218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xb4), 232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x03), 233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 242 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 243 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 244 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x24), 245 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 246 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 247 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 249 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 250 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 251 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 252 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 253 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 254 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 255 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 256 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 257 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 258 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 259 }; 260 261 static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_pcs_tbl[] = { 262 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 263 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e), 264 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 265 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 266 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 267 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 268 }; 269 270 static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_misc_pcs_tbl[] = { 271 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 272 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 273 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 274 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 275 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 276 }; 277 278 static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_tx_tbl[] = { 279 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x17), 280 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 281 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 282 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 283 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 284 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 285 }; 286 287 static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_rx_tbl[] = { 288 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 289 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 290 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 291 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0xf0), 292 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 293 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 294 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 295 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), 296 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x04), 297 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 298 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x0d), 299 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 300 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 301 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 302 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 303 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 304 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x0c), 305 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 306 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 307 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 308 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 309 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 310 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 311 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 312 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 313 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 314 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 315 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 316 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 317 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 318 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 319 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 320 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 321 }; 322 323 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 324 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 325 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 326 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 327 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 328 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 329 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 330 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 331 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 332 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 333 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 334 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 335 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 336 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 337 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 338 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 339 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 340 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 341 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 342 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 343 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 344 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 345 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 346 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 347 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 348 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 349 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 350 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 351 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 352 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 353 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 354 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 355 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 356 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 357 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 358 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 359 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 360 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 361 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 362 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 363 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 364 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 365 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 366 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 367 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 368 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 369 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 370 }; 371 372 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 373 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 374 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 375 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 376 }; 377 378 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 379 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 382 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 383 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 384 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 385 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 386 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 387 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 388 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 389 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 390 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 391 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 392 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 393 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 394 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 395 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 396 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 402 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 403 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 404 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 409 }; 410 411 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 412 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 413 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 414 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 415 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 416 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 417 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 418 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 419 }; 420 421 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 422 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 423 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 424 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 425 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 426 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 427 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 428 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 429 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 430 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 431 }; 432 433 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 434 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 435 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), 436 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf), 437 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1), 438 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0), 439 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), 440 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), 441 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6), 442 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf), 443 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0), 444 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1), 445 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20), 446 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa), 447 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), 448 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa), 449 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xa), 450 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 451 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3), 452 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 453 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 454 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0), 455 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xD), 456 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xD04), 457 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x33), 458 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2), 459 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), 460 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0xb), 461 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 462 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 463 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 464 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 465 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 466 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1), 467 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 468 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1), 469 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2), 470 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0), 471 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), 472 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), 473 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), 474 }; 475 476 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 477 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 478 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x6), 479 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET, 0x2), 480 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), 481 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x36), 482 QMP_PHY_INIT_CFG(QSERDES_V2_TX_SLEW_CNTL, 0x0a), 483 }; 484 485 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 486 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x1c), 487 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 488 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 489 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 490 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 491 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 492 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x4), 493 }; 494 495 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 496 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 497 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 498 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 499 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 500 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 501 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 502 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 503 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 504 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 505 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 506 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 507 }; 508 509 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 510 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 511 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 512 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 513 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 514 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 515 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 516 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 517 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 518 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 519 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 520 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 521 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 522 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 523 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 524 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 525 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 526 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 527 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 528 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 529 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 530 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 531 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 532 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 533 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 534 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 535 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 536 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 537 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 538 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 539 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 540 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 541 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 542 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 543 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 544 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 545 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 546 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 547 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 548 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 549 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 550 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 551 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 552 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 553 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 554 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 555 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 556 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 557 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 558 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 559 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 560 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 561 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 562 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 563 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 564 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 565 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 566 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 567 }; 568 569 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 570 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 571 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 572 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 573 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 574 }; 575 576 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 607 }; 608 609 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 612 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 613 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 614 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 618 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 619 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 620 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 621 }; 622 623 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 624 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 625 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 626 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 627 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 628 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 629 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 630 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 631 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 632 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 633 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 637 }; 638 639 static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_serdes_tbl[] = { 640 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x02), 641 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 642 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 643 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 644 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xff), 645 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x04), 646 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xff), 647 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x09), 648 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 649 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x23), 650 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x23), 651 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x10), 652 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x10), 653 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x01), 654 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x01), 655 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 656 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 658 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 659 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x19), 660 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x14), 661 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xfe), 662 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x03), 663 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xfe), 664 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x03), 665 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 666 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 667 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 668 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 669 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 670 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 671 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 672 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 673 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 674 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x07), 675 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x10), 676 }; 677 678 static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_rx_tbl[] = { 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x03), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 708 }; 709 710 static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_misc_tbl[] = { 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x04), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1, 0x02), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4, 0xff), 720 }; 721 722 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { 723 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 724 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 725 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 726 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 727 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 728 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 729 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 730 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 731 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 732 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 733 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 734 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 735 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 736 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 737 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 738 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 739 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 740 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 741 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 742 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 743 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 744 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 745 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 746 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 747 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 748 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 749 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 751 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 752 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 753 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 754 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 755 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 756 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 757 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 758 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 759 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 760 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 761 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 762 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 763 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 764 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 765 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 766 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 767 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 768 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 769 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 770 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 771 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 772 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 773 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 774 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 775 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 776 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 777 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 778 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 779 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 780 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 781 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 782 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 783 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 784 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 785 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 786 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 787 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 788 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 789 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 790 }; 791 792 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { 793 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 794 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 795 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 796 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 797 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 798 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 799 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 800 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 801 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 802 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 803 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 804 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 805 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 806 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 807 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 808 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 809 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 810 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 811 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 812 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 813 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 814 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 815 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 816 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 817 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 818 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 819 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 820 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 821 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 822 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 823 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 824 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 825 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 826 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 827 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 828 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 829 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 830 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 831 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 832 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 833 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 834 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 835 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 836 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 837 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 838 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 839 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 840 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 841 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 842 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 843 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 844 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 845 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 846 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 847 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 848 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 849 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 850 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 851 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 852 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 853 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 854 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 855 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 856 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 857 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 858 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 859 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 860 }; 861 862 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), 882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), 888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 893 }; 894 895 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { 896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 902 }; 903 904 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { 905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), 912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), 913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), 914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 916 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 920 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 921 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), 922 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 923 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 924 }; 925 926 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { 927 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 928 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 929 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 930 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 931 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 932 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 933 }; 934 935 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { 936 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 937 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 938 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 939 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 940 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 941 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 942 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), 943 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), 944 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), 945 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), 946 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), 947 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 948 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), 949 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 950 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), 951 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 952 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), 953 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), 954 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), 955 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 956 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 957 }; 958 959 static const struct qmp_phy_init_tbl ipq9650_pcie_serdes_tbl[] = { 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x14), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x06), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_RESETSM_CNTRL, 0x20), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER1, 0xff), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER2, 0x3f), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x68), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xaa), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x14), 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xd4), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE0, 0x02), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0b), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x53), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x29), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xaa), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x00), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x7d), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x05), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0x0a), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x04), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x08), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xa2), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x13), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb5), 1019 }; 1020 1021 static const struct qmp_phy_init_tbl ipq9650_pcie_tx_tbl[] = { 1022 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xb5), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x00), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl ipq9650_pcie_rx_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x11), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_LSB, 0x00), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_MSB, 0x00), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x00), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x00), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1, 0x00), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2, 0x00), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_POST_THRESH, 0x00), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH, 0x00), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x3f), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x67), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3a), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1076 }; 1077 1078 static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_tbl[] = { 1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x25), 1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 1081 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x03), 1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x00), 1085 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1086 }; 1087 1088 static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_misc_tbl[] = { 1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1090 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1091 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1095 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1096 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x1c), 1097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), 1098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST, 0x34), 1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1100 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST, 0x40), 1101 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1102 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1103 }; 1104 1105 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = { 1106 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1107 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), 1108 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf), 1109 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1), 1110 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0), 1111 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), 1112 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), 1113 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6), 1114 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf), 1115 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0), 1116 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1), 1117 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20), 1118 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa), 1119 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), 1120 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x9), 1121 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x4), 1122 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 1123 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3), 1124 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 1125 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 1126 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0), 1127 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xd), 1128 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x04), 1129 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x35), 1130 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2), 1131 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), 1132 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x4), 1133 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 1134 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x30), 1135 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 1136 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1137 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 1138 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa), 1139 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1), 1140 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 1141 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1), 1142 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2), 1143 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0), 1144 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), 1145 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), 1146 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), 1147 }; 1148 1149 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = { 1150 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x1c), 1151 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1152 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 1153 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 1154 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 1155 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 1156 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x4), 1157 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN_HALF, 0x4), 1158 }; 1159 1160 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = { 1161 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 1162 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x6), 1163 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET, 0x2), 1164 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), 1165 }; 1166 1167 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = { 1168 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 1169 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 1170 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 1171 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 1172 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 1173 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 1174 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 1175 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 1176 QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7), 1177 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 1178 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 1179 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 1180 }; 1181 1182 static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = { 1183 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1232 }; 1233 1234 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 1235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 1237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 1238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 1239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 1241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 1242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 1243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 1244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 1245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 1246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 1247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 1248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 1249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 1250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 1251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 1252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 1253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 1254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 1255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 1256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 1257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 1258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 1259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 1260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 1261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 1262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 1263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 1264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 1265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 1266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 1267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 1270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 1271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 1272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 1273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 1274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 1275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 1276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 1277 }; 1278 1279 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 1280 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 1281 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1282 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1283 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 1284 }; 1285 1286 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 1287 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1288 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 1289 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1290 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1291 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 1292 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 1293 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 1294 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 1295 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 1296 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 1297 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 1298 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 1299 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1300 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 1301 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 1302 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 1303 }; 1304 1305 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 1307 1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 1312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1313 1314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 1315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 1316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 1317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 1318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 1319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 1320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 1321 1322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 1323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 1324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1325 1326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 1327 }; 1328 1329 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 1330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 1331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 1332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 1333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 1334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1335 }; 1336 1337 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 1338 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 1339 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 1340 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 1341 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 1342 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 1343 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 1344 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1345 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1346 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 1347 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 1348 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 1349 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 1350 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 1351 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 1352 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 1353 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 1354 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 1355 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 1356 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 1357 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 1358 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 1359 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 1360 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 1361 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 1362 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 1363 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 1364 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 1365 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 1366 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 1367 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 1368 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1369 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 1370 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 1371 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 1372 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 1373 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 1374 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 1375 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 1376 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 1377 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 1378 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 1379 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 1380 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 1381 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 1382 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 1383 }; 1384 1385 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 1386 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 1387 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 1388 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 1389 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 1390 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 1391 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 1392 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 1393 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 1394 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 1395 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 1396 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 1397 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 1398 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 1399 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 1400 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 1401 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 1402 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 1403 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 1404 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 1405 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 1406 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 1407 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 1408 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 1409 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 1410 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 1411 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 1412 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 1413 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 1414 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 1415 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 1416 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 1417 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 1418 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 1419 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 1420 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 1421 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 1422 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 1423 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 1424 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 1425 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 1426 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 1427 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 1428 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 1429 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 1430 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 1431 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 1432 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 1433 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 1434 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 1435 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 1436 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 1437 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 1438 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 1439 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 1440 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 1441 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 1442 }; 1443 1444 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 1445 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 1446 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 1447 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 1448 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 1449 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 1450 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 1451 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 1452 }; 1453 1454 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 1455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1497 }; 1498 1499 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 1500 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1501 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 1502 }; 1503 1504 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 1505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 1509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 1510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 1511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 1512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 1518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 1522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 1527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 1530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 1532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 1533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 1537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 1539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1541 }; 1542 1543 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 1544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1546 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1547 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1548 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 1549 }; 1550 1551 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 1552 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1553 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1554 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1555 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1556 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1557 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1558 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1559 }; 1560 1561 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 1562 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 1563 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1564 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1565 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1566 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1567 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1568 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1569 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1570 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1571 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1572 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1573 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1574 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1575 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1576 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1577 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1578 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1579 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1580 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1581 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1582 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1583 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1584 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1585 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1586 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1587 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1588 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1589 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1590 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1591 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1592 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1593 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1594 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1595 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1596 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1597 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1598 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 1599 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1600 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 1601 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1602 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1603 }; 1604 1605 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1607 }; 1608 1609 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 1610 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1611 }; 1612 1613 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 1614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1615 }; 1616 1617 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 1618 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1619 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1620 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1621 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1622 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1623 }; 1624 1625 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 1626 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1627 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1628 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1629 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1630 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1631 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1632 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1633 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1634 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1635 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1636 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1637 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1638 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1639 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1640 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1641 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1642 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1643 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1644 }; 1645 1646 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 1647 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1648 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1649 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1650 }; 1651 1652 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1653 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1654 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1655 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1656 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1657 }; 1658 1659 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 1660 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1661 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1666 }; 1667 1668 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 1669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1686 }; 1687 1688 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 1689 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1690 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 1691 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1692 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 1693 }; 1694 1695 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1696 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1697 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1698 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1699 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1700 }; 1701 1702 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 1703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1748 }; 1749 1750 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = { 1751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1752 }; 1753 1754 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1755 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1756 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1757 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1758 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1759 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), 1760 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1761 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1762 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1763 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), 1764 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1765 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1766 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1767 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1768 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1769 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1770 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1771 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1772 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1773 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1774 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1775 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1776 }; 1777 1778 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { 1779 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1780 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1781 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1782 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1783 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1784 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1785 }; 1786 1787 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 1788 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1789 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1790 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1791 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1792 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1793 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1794 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1795 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1796 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), 1797 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), 1798 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1799 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), 1800 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), 1801 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1802 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1803 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1804 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1805 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1806 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), 1807 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), 1808 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1809 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1810 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1811 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1812 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1813 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1814 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1815 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1816 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), 1817 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), 1818 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1819 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1820 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), 1821 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1822 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1823 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1824 }; 1825 1826 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 1827 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1828 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 1829 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1830 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1831 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1832 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1833 }; 1834 1835 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1836 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1837 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1838 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1839 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1840 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1841 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1842 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1843 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 1844 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 1845 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1846 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1847 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), 1848 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1849 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1850 }; 1851 1852 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = { 1853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1857 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1858 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08), 1859 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04), 1860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d), 1861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1884 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1885 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1886 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1887 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1888 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1889 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1890 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1891 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1892 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1893 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1894 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1895 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1896 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1897 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1898 }; 1899 1900 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = { 1901 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1902 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1903 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1904 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1905 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1906 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1907 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1908 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1909 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1910 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1911 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1912 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1913 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1914 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1915 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1916 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1917 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1918 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1919 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1920 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1921 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1922 }; 1923 1924 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = { 1925 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1926 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05), 1927 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1928 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1929 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1930 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1931 }; 1932 1933 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = { 1934 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1935 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1936 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1937 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1938 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1939 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1940 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1941 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1942 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1943 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c), 1944 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1945 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1946 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1947 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1948 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1949 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1950 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1951 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4), 1952 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23), 1953 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1954 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1955 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38), 1956 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1957 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1958 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c), 1959 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4), 1960 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1961 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1962 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69), 1963 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1964 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1965 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1966 }; 1967 1968 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = { 1969 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)), 1970 }; 1971 1972 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = { 1973 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00), 1974 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e), 1975 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99), 1976 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00), 1977 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00), 1978 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22), 1979 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04), 1980 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02), 1981 }; 1982 1983 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = { 1984 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1985 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00), 1986 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16), 1987 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02), 1988 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e), 1989 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03), 1990 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28), 1991 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18), 1992 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1993 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1994 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27), 1995 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27), 1996 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0), 1997 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d), 1998 }; 1999 2000 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 2001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 2002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 2003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 2004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 2005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 2006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 2007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 2008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 2009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 2010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 2011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 2012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 2013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 2014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 2015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 2016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 2017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 2018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 2019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 2020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 2021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 2022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 2023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 2024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 2025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 2026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 2027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 2028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 2029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 2030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 2031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 2032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 2033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 2034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 2035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 2036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 2037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 2042 }; 2043 2044 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 2045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 2046 }; 2047 2048 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 2049 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 2050 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 2051 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 2052 }; 2053 2054 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 2055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 2056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 2057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 2058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 2059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 2060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 2061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 2062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 2063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 2064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 2065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 2066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 2067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 2068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 2069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 2070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 2071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 2072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 2073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 2074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 2075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 2076 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 2077 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 2078 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 2079 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 2080 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 2081 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 2082 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 2083 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 2084 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 2085 }; 2086 2087 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 2088 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 2089 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 2090 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 2091 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 2092 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 2093 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 2094 }; 2095 2096 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 2097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 2098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 2099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 2100 }; 2101 2102 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 2103 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 2104 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 2105 }; 2106 2107 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 2108 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2109 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 2110 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 2111 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 2112 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 2113 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 2114 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2115 }; 2116 2117 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2118 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 2119 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 2120 }; 2121 2122 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 2123 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 2124 }; 2125 2126 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 2127 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 2128 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 2129 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 2130 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2131 }; 2132 2133 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 2134 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 2135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 2136 }; 2137 2138 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2139 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 2140 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2141 }; 2142 2143 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 2144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 2145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 2146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 2147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 2148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 2149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 2150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 2152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 2153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 2154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 2155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 2156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 2157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 2158 }; 2159 2160 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 2161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 2162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 2163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 2164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 2165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 2166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 2169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 2170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 2171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 2172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 2173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 2174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 2175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 2176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 2177 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 2178 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 2179 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 2180 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 2181 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 2182 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 2183 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 2184 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 2185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 2186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 2187 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 2188 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 2189 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 2190 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 2191 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 2192 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 2193 }; 2194 2195 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 2196 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 2197 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 2198 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 2199 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 2200 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 2201 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 2202 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 2203 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 2204 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 2205 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 2206 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 2207 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 2208 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 2209 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 2210 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 2211 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 2212 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2213 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2214 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2215 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2216 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 2217 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 2218 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 2219 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 2220 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 2221 }; 2222 2223 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 2224 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 2225 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 2226 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 2227 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 2228 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 2229 }; 2230 2231 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 2232 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 2233 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 2234 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 2235 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 2236 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 2237 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 2238 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 2239 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 2240 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 2241 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 2242 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 2243 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 2244 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 2245 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 2246 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 2247 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 2248 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 2249 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 2250 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 2251 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 2252 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 2253 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 2254 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 2255 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2256 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 2257 }; 2258 2259 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 2260 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 2261 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 2262 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 2263 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 2264 }; 2265 2266 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 2267 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 2268 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 2269 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 2270 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 2271 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2272 }; 2273 2274 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 2275 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2276 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2277 }; 2278 2279 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = { 2280 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2281 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2282 }; 2283 2284 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 2285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 2318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2319 }; 2320 2321 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 2322 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2323 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2324 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 2325 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 2326 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 2327 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 2328 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2329 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 2330 }; 2331 2332 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 2333 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2334 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 2335 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 2336 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 2337 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 2338 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2339 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2340 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 2341 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 2342 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 2343 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 2344 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 2345 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 2346 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 2347 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 2348 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 2349 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 2350 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 2351 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 2352 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 2353 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 2354 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 2355 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 2356 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 2357 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2358 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2359 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 2360 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2361 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2362 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2363 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 2377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 2382 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2383 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2384 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 2385 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2386 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2387 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 2388 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 2389 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2390 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2391 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2392 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2393 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2394 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 2395 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2396 }; 2397 2398 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 2399 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2400 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 2401 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 2402 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2403 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2404 }; 2405 2406 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 2407 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2408 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2409 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2410 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 2411 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2412 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2413 }; 2414 2415 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = { 2416 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2417 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2418 }; 2419 2420 static const struct qmp_phy_init_tbl shikra_pcie_serdes_tbl[] = { 2421 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 2422 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), 2423 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf), 2424 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1), 2425 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0), 2426 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), 2427 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), 2428 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6), 2429 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf), 2430 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0), 2431 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1), 2432 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20), 2433 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa), 2434 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), 2435 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x9), 2436 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xa), 2437 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 2438 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3), 2439 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 2440 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 2441 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0), 2442 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xd), 2443 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x04), 2444 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x35), 2445 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2), 2446 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), 2447 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x4), 2448 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 2449 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x30), 2450 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 2451 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 2452 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 2453 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa), 2454 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1), 2455 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 2456 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1), 2457 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2), 2458 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0), 2459 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), 2460 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), 2461 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), 2462 }; 2463 2464 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 2465 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2466 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2467 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 2468 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2469 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 2470 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 2471 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 2472 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 2473 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2474 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 2475 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2476 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2477 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2478 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2479 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2480 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2481 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 2482 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 2483 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 2484 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 2485 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2486 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2487 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 2488 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2489 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2490 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2491 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2492 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2493 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2494 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 2495 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 2496 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 2497 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 2498 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 2499 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2500 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2501 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2502 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2503 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2504 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2505 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2506 }; 2507 2508 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 2509 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 2510 }; 2511 2512 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 2513 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2514 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2515 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2516 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 2517 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 2518 }; 2519 2520 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 2521 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 2522 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 2523 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 2524 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 2525 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 2526 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 2527 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 2528 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 2529 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 2530 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 2531 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 2532 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 2533 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2534 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 2535 }; 2536 2537 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2538 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2539 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2540 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 2541 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2542 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2543 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 2544 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 2545 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 2546 }; 2547 2548 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 2549 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 2550 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 2551 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 2552 }; 2553 2554 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2555 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2556 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 2557 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 2558 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2559 }; 2560 2561 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 2562 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2563 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2564 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2565 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2566 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2567 }; 2568 2569 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2570 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2571 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2572 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2573 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2574 }; 2575 2576 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 2577 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 2578 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 2579 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 2580 }; 2581 2582 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 2583 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 2584 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 2585 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 2586 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2587 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2588 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2589 }; 2590 2591 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 2592 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 2593 }; 2594 2595 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 2596 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2597 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2598 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2599 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2600 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2601 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2602 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2603 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2604 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2605 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2607 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2608 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2609 }; 2610 2611 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 2612 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2613 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2615 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2616 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2617 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2618 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2629 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2630 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2631 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2633 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2634 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2635 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2636 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2637 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2638 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2639 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 2640 }; 2641 2642 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 2643 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2644 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2645 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 2646 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2647 }; 2648 2649 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 2650 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2651 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2652 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 2653 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 2654 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 2655 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 2656 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2657 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2658 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 2659 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2660 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2661 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 2662 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2663 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 2664 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 2665 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 2666 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2667 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2668 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2669 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2670 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2671 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2672 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2673 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2674 2675 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2676 2677 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2678 2679 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2680 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2681 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2682 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2683 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2684 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2685 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2686 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2687 2688 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2689 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2690 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2691 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2692 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2693 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2694 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2695 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2696 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2697 }; 2698 2699 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 2700 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2701 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2702 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2703 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 2704 }; 2705 2706 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2707 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2708 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2709 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2710 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2711 }; 2712 2713 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 2714 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2715 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2716 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 2717 }; 2718 2719 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 2720 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2721 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2722 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2723 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2724 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2725 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2726 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2727 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2728 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2729 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2730 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2731 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2732 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2733 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2734 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2735 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2736 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2737 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2738 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2739 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2740 }; 2741 2742 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 2743 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2744 }; 2745 2746 static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_serdes_tbl[] = { 2747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 2749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 2750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), 2751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 2752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 2765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0a), 2767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 2768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), 2769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), 2770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 2771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 2774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 2775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2785 }; 2786 2787 static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_rx_tbl[] = { 2788 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2789 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 2790 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 2791 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 2792 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 2793 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 2794 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 2795 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 2796 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 2797 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 2798 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 2799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 2800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 2801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 2802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 2803 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 2804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), 2805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 2806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 2807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 2808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 2809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 2810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 2811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 2813 }; 2814 2815 static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2816 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2817 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2818 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2819 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2820 }; 2821 2822 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 2823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 2829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 2848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 2852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 2853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 2854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2857 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2858 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2859 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2861 }; 2862 2863 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 2864 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 2865 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 2866 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 2867 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 2868 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 2869 }; 2870 2871 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 2872 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2873 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 2874 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 2875 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 2876 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 2877 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 2878 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 2879 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 2880 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 2881 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 2882 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 2883 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 2884 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 2885 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 2886 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 2887 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 2888 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), 2889 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 2890 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 2891 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 2892 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 2893 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 2894 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 2895 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2896 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 2897 }; 2898 2899 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 2900 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 2901 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 2902 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 2903 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 2904 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 2905 }; 2906 2907 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2908 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 2909 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 2910 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2911 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2912 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2913 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2914 }; 2915 2916 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 2917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 2918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 2919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 2920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 2930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 2933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 2943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2945 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2946 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2947 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 2948 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 2949 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2950 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2951 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 2952 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2953 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 2954 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 2955 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2956 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2957 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2958 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 2959 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 2960 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 2961 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 2962 }; 2963 2964 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 2965 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 2966 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 2967 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 2968 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 2969 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 2970 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 2971 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 2972 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 2973 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 2974 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 2975 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 2976 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2977 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2978 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2979 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2980 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2981 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2982 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2983 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2984 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2985 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 2986 }; 2987 2988 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 2989 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2990 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 2991 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 2992 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 2993 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 2994 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 2995 }; 2996 2997 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 2998 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 2999 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 3000 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 3001 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 3002 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 3003 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 3004 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 3005 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 3006 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 3007 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 3008 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 3009 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 3010 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 3011 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 3012 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 3013 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 3014 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 3015 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 3016 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 3017 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 3018 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 3019 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 3020 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 3021 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 3022 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 3023 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 3024 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 3025 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 3026 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 3027 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 3028 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 3029 }; 3030 3031 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 3032 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3033 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 3034 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 3035 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 3036 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 3037 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 3038 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 3039 }; 3040 3041 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 3042 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 3043 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 3044 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 3045 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 3046 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 3047 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 3048 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 3049 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 3050 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 3051 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 3052 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 3053 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 3054 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 3055 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 3056 }; 3057 3058 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 3059 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 3060 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 3061 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 3062 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 3063 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 3064 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 3065 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 3066 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 3067 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 3068 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 3069 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 3070 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 3071 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 3072 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 3073 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 3074 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 3075 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 3076 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 3077 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 3078 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 3079 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 3080 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 3081 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 3082 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 3083 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 3084 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 3085 }; 3086 3087 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_serdes_tbl[] = { 3088 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x1), 3089 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62), 3090 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02), 3091 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 3092 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01), 3093 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0x93), 3094 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01), 3095 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_ENABLE1, 0x90), 3096 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYS_CLK_CTRL, 0x82), 3097 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_IVCO, 0x07), 3098 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02), 3099 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02), 3100 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16), 3101 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16), 3102 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36), 3103 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36), 3104 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x08), 3105 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a), 3106 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_EN, 0x42), 3107 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x04), 3108 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x0d), 3109 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x0a), 3110 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x1a), 3111 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41), 3112 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x34), 3113 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0xab), 3114 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0xaa), 3115 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01), 3116 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55), 3117 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x55), 3118 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01), 3119 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x14), 3120 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_SELECT, 0x34), 3121 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01), 3122 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04), 3123 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16), 3124 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC_3, 0x0F), 3125 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0xA0), 3126 }; 3127 3128 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_rx_tbl[] = { 3129 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 3130 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x11), 3131 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xBF), 3132 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xBF), 3133 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xB7), 3134 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEA), 3135 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3F), 3136 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x09), 3137 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x49), 3138 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1B), 3139 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x9C), 3140 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xD1), 3141 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH, 0x09), 3142 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH2, 0x49), 3143 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x1B), 3144 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH4, 0x9C), 3145 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_LOW, 0xD1), 3146 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1, 0x3E), 3147 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2, 0x1E), 3148 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_POST_THRESH, 0xD2), 3149 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x09), 3150 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x05), 3151 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08), 3152 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08), 3153 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x09), 3154 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_ENABLES, 0x1C), 3155 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x60), 3156 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07), 3157 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08), 3158 }; 3159 3160 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_tx_tbl[] = { 3161 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0x35), 3162 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x10), 3163 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x31), 3164 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x7F), 3165 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x02), 3166 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x08), 3167 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x14), 3168 }; 3169 3170 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_tbl[] = { 3171 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x05), 3172 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0x77), 3173 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RATE_SLEW_CNTRL1, 0x0B), 3174 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG2, 0x0F), 3175 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x8C), 3176 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3177 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G3S2_PRE_GAIN, 0x2E), 3178 }; 3179 3180 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 3181 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1E), 3182 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 3183 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D), 3184 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 3185 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1), 3186 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 3187 }; 3188 3189 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 3190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 3191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 3192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 3193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 3194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 3195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 3196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 3197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 3198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 3199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 3200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 3201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 3202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 3203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 3204 }; 3205 3206 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { 3207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 3208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 3209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 3210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 3211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 3212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 3213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 3214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 3215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 3216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 3217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 3218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 3219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 3220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 3221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 3222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 3223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 3224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 3225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 3226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 3227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 3228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 3229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 3230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 3231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 3232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 3233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 3234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 3235 }; 3236 3237 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { 3238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07), 3239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 3240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 3241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 3242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4), 3243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 3244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 3245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 3246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 3247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 3248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 3249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4), 3250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 3251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 3252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 3253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 3254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3), 3255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 3256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed), 3257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5), 3258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d), 3259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6), 3260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e), 3261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 3262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 3263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 3264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 3265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 3266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 3267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 3268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 3269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 3270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 3271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 3272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 3273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 3274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 3275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 3276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 3277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 3278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 3279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03), 3280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08), 3281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 3282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 3283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 3284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01), 3285 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 3286 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 3287 }; 3288 3289 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { 3290 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 3291 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 3292 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 3293 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 3294 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), 3295 }; 3296 3297 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { 3298 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27), 3299 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27), 3300 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 3301 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 3302 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 3303 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 3304 }; 3305 3306 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { 3307 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 3308 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 3309 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 3310 }; 3311 3312 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = { 3313 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 3314 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 3315 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 3316 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 3317 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff), 3318 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89), 3319 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00), 3320 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50), 3321 }; 3322 3323 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 3324 QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00), 3325 }; 3326 3327 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { 3328 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 3329 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 3330 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 3331 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 3332 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 3333 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 3334 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 3335 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 3336 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 3337 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 3338 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 3339 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 3340 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 3341 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 3342 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 3343 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 3344 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 3345 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 3346 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 3347 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 3348 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 3349 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 3350 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2), 3351 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 3352 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 3353 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 3354 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 3355 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 3356 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), 3357 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2), 3358 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), 3359 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 3360 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 3361 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 3362 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3), 3363 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), 3364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4), 3365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6), 3366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 3367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6), 3368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e), 3369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 3370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 3371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 3372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 3373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 3374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 3375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 3376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06), 3377 }; 3378 3379 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { 3380 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 3381 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 3382 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 3383 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 3384 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 3385 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 3386 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 3387 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 3388 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 3389 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 3390 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 3391 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 3392 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 3393 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 3394 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 3395 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 3396 }; 3397 3398 3399 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { 3400 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 3401 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 3402 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 3403 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 3404 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 3405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 3406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 3407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 3408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 3409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 3410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 3411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 3412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 3413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 3414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 3415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 3416 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 3417 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 3418 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 3419 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 3420 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 3421 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 3422 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 3423 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 3424 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 3425 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 3426 }; 3427 3428 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { 3429 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 3430 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 3431 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 3432 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 3433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 3434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 3435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 3436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 3437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 3438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 3439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 3440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 3441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 3442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 3443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 3444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 3445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 3446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 3447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 3448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 3449 }; 3450 3451 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { 3452 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), 3453 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), 3454 }; 3455 3456 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 3457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 3458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 3459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 3460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), 3461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 3462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 3463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 3464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 3465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 3466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 3467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 3468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 3469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 3470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 3471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 3472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 3473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 3474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 3475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 3476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 3477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 3478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), 3479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), 3480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 3481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 3482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 3483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 3484 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 3485 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 3486 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 3487 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 3488 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 3489 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 3490 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 3491 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 3492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 3493 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 3494 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 3495 }; 3496 3497 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = { 3498 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01), 3499 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01), 3500 }; 3501 3502 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = { 3503 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2), 3504 }; 3505 3506 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 3507 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3508 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e), 3509 }; 3510 3511 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = { 3512 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00), 3513 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06), 3514 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07), 3515 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 3516 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28), 3517 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28), 3518 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d), 3519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d), 3520 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00), 3521 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00), 3522 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 3523 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 3524 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 3525 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff), 3526 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09), 3527 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19), 3528 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14), 3529 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 3530 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03), 3531 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 3532 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03), 3533 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 3534 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 3535 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 3536 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 3537 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 3538 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 3539 }; 3540 3541 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = { 3542 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3543 }; 3544 3545 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = { 3546 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 3547 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14), 3548 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 3549 }; 3550 3551 static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_serdes_tbl[] = { 3552 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0x93), 3553 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 3554 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06), 3555 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 3556 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 3557 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 3558 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x0a), 3559 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x1a), 3560 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x34), 3561 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 3562 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x55), 3563 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 3564 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 3565 3566 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 3567 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 3568 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06), 3569 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 3570 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 3571 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE0, 0x0a), 3572 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x04), 3573 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x0d), 3574 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 3575 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0xab), 3576 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0xaa), 3577 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 3578 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 3579 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 3580 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 3581 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 3582 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 3583 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CLK_ENABLE1, 0x90), 3584 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYS_CLK_CTRL, 0x82), 3585 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x0f), 3586 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x08), 3587 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x46), 3588 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x04), 3589 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x14), 3590 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CLK_SELECT, 0x34), 3591 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0xa0), 3592 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 3593 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_MISC_1, 0x88), 3594 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_MODE, 0x04), 3595 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_DC_LEVEL_CTRL, 0x0f), 3596 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_SPARE_FOR_ECO, 0x02), 3597 }; 3598 3599 static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_tx_tbl[] = { 3600 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_RES_CODE_LANE_OFFSET_TX, 0x1b), 3601 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_RES_CODE_LANE_OFFSET_RX, 0x14), 3602 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_LANE_MODE_1, 0x00), 3603 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_LANE_MODE_2, 0x40), 3604 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_LANE_MODE_3, 0x00), 3605 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_TRAN_DRVR_EMP_EN, 0x04), 3606 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_TX_BAND0, 0x05), 3607 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_TX_BAND1, 0x00), 3608 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_SEL_10B_8B, 0x07), 3609 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_SEL_20B_10B, 0x1f), 3610 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_PARRATE_REC_DETECT_IDLE_EN, 0x90), 3611 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_TX_ADAPT_POST_THRESH1, 0x02), 3612 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_TX_ADAPT_POST_THRESH2, 0x0d), 3613 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_EQ_RCF_CTRL_RATE3, 0x53), 3614 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_EQ_RCF_CTRL_RATE4, 0x54), 3615 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_TX_PHPRE_CTRL, 0x20), 3616 }; 3617 3618 static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_rx_tbl[] = { 3619 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_FO_GAIN_RATE4, 0x0b), 3620 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_SO_GAIN_RATE3, 0x04), 3621 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_SO_GAIN_RATE4, 0x05), 3622 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_PI_CONTROLS, 0x15), 3623 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_VGA_CAL_CNTRL1, 0x00), 3624 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_VGA_CAL_MAN_VAL, 0x89), 3625 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_EQU_ADAPTOR_CNTRL4, 0x2d), 3626 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_SIGDET_ENABLES, 0x1c), 3627 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_SIGDET_LVL, 0x04), 3628 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RXCLK_DIV2_CTRL, 0x01), 3629 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_BAND_CTRL0, 0x05), 3630 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_TERM_BW_CTRL0, 0x00), 3631 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_TERM_BW_CTRL1, 0x00), 3632 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_SVS_MODE_CTRL, 0x00), 3633 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_PI_CTRL1, 0x40), 3634 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_PI_CTRL2, 0x42), 3635 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_SB2_THRESH2_RATE3, 0x18), 3636 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_SB2_GAIN1_RATE3, 0x12), 3637 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_UCDR_SB2_GAIN2_RATE3, 0x18), 3638 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B0, 0xc2), 3639 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B1, 0xc2), 3640 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B2, 0x18), 3641 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B4, 0x0f), 3642 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B7, 0x62), 3643 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B0, 0xe4), 3644 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B1, 0x63), 3645 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B2, 0xd8), 3646 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B3, 0x99), 3647 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B4, 0x67), 3648 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B0, 0xa4), 3649 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B1, 0xa4), 3650 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B2, 0x28), 3651 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B3, 0x9f), 3652 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B4, 0x48), 3653 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B5, 0x24), 3654 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x01), 3655 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_Q_PI_INTRINSIC_BIAS_RATE4, 0x00), 3656 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_EOM_MAX_ERR_LIMIT_LSB, 0xff), 3657 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_EOM_MAX_ERR_LIMIT_MSB, 0xff), 3658 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_AUXDATA_BIN_RATE23, 0x30), 3659 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_AUXDATA_BIN_RATE4, 0x03), 3660 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_VTHRESH_CAL_MAN_VAL_RATE3, 0x1f), 3661 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_VTHRESH_CAL_MAN_VAL_RATE4, 0x1f), 3662 QMP_PHY_INIT_CFG(QSERDES_V8_PCIE_RX_GM_CAL, 0x0d), 3663 }; 3664 3665 static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_pcs_tbl[] = { 3666 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3667 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN, 0x2e), 3668 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_RX_SIGDET_LVL, 0xcc), 3669 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL, 0x40), 3670 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1, 0x04), 3671 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2, 0x02), 3672 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_EQ_CONFIG4, 0x00), 3673 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_EQ_CONFIG5, 0x22), 3674 }; 3675 3676 static const struct qmp_phy_init_tbl kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 3677 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_TX_RX_CONFIG, 0xc0), 3678 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2, 0x1d), 3679 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 3680 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS, 0x00), 3681 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_EQ_CONFIG1, 0x16), 3682 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME, 0x27), 3683 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME, 0x27), 3684 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5, 0x02), 3685 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G4_PRE_GAIN, 0x2e), 3686 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1, 0x03), 3687 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3, 0x28), 3688 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5, 0x0f), 3689 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 3690 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 3691 QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6, 0x1f), 3692 }; 3693 3694 static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_serdes_tbl[] = { 3695 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01), 3696 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62), 3697 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02), 3698 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 3699 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01), 3700 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0x93), 3701 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01), 3702 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_ENABLE1, 0x90), 3703 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYS_CLK_CTRL, 0x82), 3704 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_IVCO, 0x07), 3705 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02), 3706 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02), 3707 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16), 3708 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16), 3709 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36), 3710 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36), 3711 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x08), 3712 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a), 3713 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_EN, 0x42), 3714 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x04), 3715 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x0d), 3716 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x0a), 3717 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x1a), 3718 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41), 3719 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x34), 3720 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0xab), 3721 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0xaa), 3722 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01), 3723 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55), 3724 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x55), 3725 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01), 3726 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x14), 3727 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_SELECT, 0x34), 3728 QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01), 3729 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04), 3730 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16), 3731 QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC_3, 0x0f), 3732 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0xa0), 3733 }; 3734 3735 static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_rx_tbl[] = { 3736 QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 3737 QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x11), 3738 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf), 3739 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xbf), 3740 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xb7), 3741 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xec), 3742 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f), 3743 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09), 3744 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x49), 3745 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0x1b), 3746 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0x9c), 3747 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0xd1), 3748 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH, 0x09), 3749 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH2, 0x49), 3750 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH3, 0x1b), 3751 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH4, 0x9c), 3752 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_LOW, 0xd1), 3753 QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 3754 QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 3755 QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_POST_THRESH, 0xd2), 3756 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x09), 3757 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x05), 3758 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08), 3759 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08), 3760 QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x09), 3761 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x1c), 3762 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x60), 3763 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07), 3764 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08), 3765 }; 3766 3767 static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_tx_tbl[] = { 3768 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0x25), 3769 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x10), 3770 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31), 3771 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x7d), 3772 QMP_PHY_INIT_CFG(QSERDES_V10_TX_PI_QEC_CTRL, 0x02), 3773 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 3774 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x14), 3775 }; 3776 3777 static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_tbl[] = { 3778 QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x05), 3779 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x77), 3780 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RATE_SLEW_CNTRL1, 0x0b), 3781 QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG2, 0x0f), 3782 QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x8c), 3783 QMP_PHY_INIT_CFG(QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3784 QMP_PHY_INIT_CFG(QPHY_V10_PCS_G3S2_PRE_GAIN, 0x2e), 3785 }; 3786 3787 static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 3788 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_EQ_CONFIG1, 0x1e), 3789 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_RXEQEVAL_TIME, 0x27), 3790 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2, 0x1d), 3791 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4, 0x07), 3792 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6, 0x1f), 3793 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 3794 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS, 0x00), 3795 }; 3796 3797 static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_serdes_tbl[] = { 3798 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1, 0x93), 3799 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1, 0x01), 3800 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE1, 0x06), 3801 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE1, 0x16), 3802 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE1, 0x36), 3803 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE1, 0x04), 3804 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE1, 0x0a), 3805 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE1, 0x1a), 3806 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE1, 0x34), 3807 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1, 0x55), 3808 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1, 0x55), 3809 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1, 0x01), 3810 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_SEL_1, 0x01), 3811 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 3812 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0, 0x01), 3813 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE0, 0x06), 3814 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE0, 0x16), 3815 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE0, 0x36), 3816 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE0, 0x0a), 3817 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE0, 0x04), 3818 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE0, 0x0d), 3819 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE0, 0x41), 3820 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0, 0xab), 3821 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0, 0xaa), 3822 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0, 0x01), 3823 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 3824 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BG_TIMER, 0x0a), 3825 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER1, 0x62), 3826 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER2, 0x02), 3827 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 3828 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_ENABLE1, 0x90), 3829 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYS_CLK_CTRL, 0x82), 3830 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_IVCO, 0x0f), 3831 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYSCLK_EN_SEL, 0x08), 3832 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_EN, 0x46), 3833 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_CFG, 0x04), 3834 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_TUNE_MAP, 0x14), 3835 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_SELECT, 0x34), 3836 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORE_CLK_EN, 0xa0), 3837 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_CONFIG_1, 0x16), 3838 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MISC1, 0x88), 3839 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MODE, 0x14), 3840 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL, 0x0f), 3841 QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO, 0x02), 3842 }; 3843 3844 static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_tx_tbl[] = { 3845 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX, 0x1a), 3846 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX, 0x12), 3847 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1, 0x00), 3848 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2, 0x00), 3849 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM, 0x66), 3850 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND0, 0x05), 3851 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND1, 0x00), 3852 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_10B_8B, 0x07), 3853 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_20B_10B, 0x1f), 3854 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3, 0x22), 3855 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4, 0x22), 3856 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_PHPRE_CTRL, 0x20), 3857 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1, 0x14), 3858 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x14), 3859 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3, 0x14), 3860 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x14), 3861 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1, 0x04), 3862 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2, 0x04), 3863 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3, 0x04), 3864 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x04), 3865 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL1, 0x40), 3866 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL2, 0x02), 3867 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL3, 0x00), 3868 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL4, 0x00), 3869 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SVS_MODE_CTRL, 0x00), 3870 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL, 0x01), 3871 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_BAND_CTRL0, 0x05), 3872 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0, 0x00), 3873 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1, 0x00), 3874 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1, 0x0a), 3875 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2, 0x0a), 3876 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3, 0x06), 3877 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4, 0x06), 3878 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1, 0x04), 3879 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2, 0x06), 3880 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3, 0x04), 3881 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4, 0x04), 3882 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS, 0x07), 3883 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3, 0x03), 3884 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4, 0x03), 3885 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB, 0xff), 3886 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB, 0xff), 3887 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1, 0x04), 3888 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL, 0x8e), 3889 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_GM_CAL, 0x00), 3890 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6, 0xca), 3891 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_ENABLES, 0x1c), 3892 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CNTRL, 0x6f), 3893 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_LVL, 0x84), 3894 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL, 0x06), 3895 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32, 0x11), 3896 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45, 0x10), 3897 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0, 0xc2), 3898 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1, 0xc2), 3899 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2, 0xd8), 3900 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3, 0x05), 3901 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4, 0x98), 3902 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5, 0x36), 3903 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6, 0x14), 3904 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7, 0x06), 3905 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8, 0xc0), 3906 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9, 0x07), 3907 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10, 0x00), 3908 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0, 0x0a), 3909 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1, 0x0a), 3910 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2, 0xd8), 3911 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3, 0x1a), 3912 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4, 0x98), 3913 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5, 0x36), 3914 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6, 0x14), 3915 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7, 0x06), 3916 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8, 0xc0), 3917 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9, 0x07), 3918 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10, 0x00), 3919 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0, 0x13), 3920 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1, 0xd3), 3921 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2, 0xc0), 3922 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3, 0x13), 3923 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4, 0x13), 3924 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5, 0x36), 3925 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6, 0x4c), 3926 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7, 0x06), 3927 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8, 0xc0), 3928 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9, 0x07), 3929 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10, 0x00), 3930 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0, 0x24), 3931 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1, 0x24), 3932 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2, 0xc0), 3933 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3, 0x0b), 3934 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4, 0x1a), 3935 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5, 0x24), 3936 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6, 0x2c), 3937 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7, 0x86), 3938 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8, 0x83), 3939 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9, 0x1f), 3940 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10, 0x00), 3941 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_1, 0x0c), 3942 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_2, 0xc0), 3943 QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_3, 0x00), 3944 }; 3945 3946 static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_tbl[] = { 3947 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3948 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G3S2_PRE_GAIN, 0x2e), 3949 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_RX_SIGDET_LVL, 0xcc), 3950 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_ELECIDLE_DLY_SEL, 0x40), 3951 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1, 0x04), 3952 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2, 0x02), 3953 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG4, 0x00), 3954 QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG5, 0x22), 3955 }; 3956 3957 static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_misc_tbl[] = { 3958 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2, 0x1d), 3959 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG, 0xc0), 3960 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 3961 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS, 0x00), 3962 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_EQ_CONFIG1, 0x16), 3963 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME, 0x27), 3964 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME, 0x27), 3965 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5, 0x02), 3966 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN, 0x2e), 3967 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1, 0x03), 3968 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3, 0x28), 3969 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5, 0x0f), 3970 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 3971 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 3972 QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6, 0x1f), 3973 }; 3974 3975 struct qmp_pcie_offsets { 3976 u16 serdes; 3977 u16 pcs; 3978 u16 pcs_misc; 3979 u16 pcs_lane1; 3980 u16 tx; 3981 u16 rx; 3982 u16 tx2; 3983 u16 rx2; 3984 u16 txz; 3985 u16 rxz; 3986 u16 txrxz; 3987 u16 ln_shrd; 3988 }; 3989 3990 struct qmp_phy_cfg_tbls { 3991 const struct qmp_phy_init_tbl *serdes; 3992 int serdes_num; 3993 const struct qmp_phy_init_tbl *tx; 3994 int tx_num; 3995 const struct qmp_phy_init_tbl *rx; 3996 int rx_num; 3997 const struct qmp_phy_init_tbl *txz; 3998 int txz_num; 3999 const struct qmp_phy_init_tbl *rxz; 4000 int rxz_num; 4001 const struct qmp_phy_init_tbl *pcs; 4002 int pcs_num; 4003 const struct qmp_phy_init_tbl *pcs_misc; 4004 int pcs_misc_num; 4005 const struct qmp_phy_init_tbl *pcs_lane1; 4006 int pcs_lane1_num; 4007 const struct qmp_phy_init_tbl *ln_shrd; 4008 int ln_shrd_num; 4009 }; 4010 4011 /* struct qmp_phy_cfg - per-PHY initialization config */ 4012 struct qmp_phy_cfg { 4013 int lanes; 4014 4015 const struct qmp_pcie_offsets *offsets; 4016 4017 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 4018 const struct qmp_phy_cfg_tbls tbls; 4019 /* 4020 * Additional init sequences for PHY blocks, providing additional 4021 * register programming. They are used for providing separate sequences 4022 * for the Root Complex and End Point use cases. 4023 * 4024 * If EP mode is not supported, both tables can be left unset. 4025 */ 4026 const struct qmp_phy_cfg_tbls *tbls_rc; 4027 const struct qmp_phy_cfg_tbls *tbls_ep; 4028 4029 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 4030 int serdes_4ln_num; 4031 4032 /* resets to be requested */ 4033 const char * const *reset_list; 4034 int num_resets; 4035 /* regulators to be requested */ 4036 const char * const *vreg_list; 4037 int num_vregs; 4038 4039 /* array of registers with different offsets */ 4040 const unsigned int *regs; 4041 4042 unsigned int pwrdn_ctrl; 4043 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 4044 unsigned int phy_status; 4045 4046 bool skip_start_delay; 4047 4048 /* QMP PHY pipe clock interface rate */ 4049 unsigned long pipe_clock_rate; 4050 4051 /* QMP PHY AUX clock interface rate */ 4052 unsigned long aux_clock_rate; 4053 }; 4054 4055 struct qmp_pcie { 4056 struct device *dev; 4057 4058 const struct qmp_phy_cfg *cfg; 4059 bool tcsr_4ln_config; 4060 bool skip_init; 4061 4062 void __iomem *serdes; 4063 void __iomem *pcs; 4064 void __iomem *pcs_misc; 4065 void __iomem *pcs_lane1; 4066 void __iomem *tx; 4067 void __iomem *rx; 4068 void __iomem *tx2; 4069 void __iomem *rx2; 4070 void __iomem *txz; 4071 void __iomem *rxz; 4072 void __iomem *ln_shrd; 4073 4074 void __iomem *port_b; 4075 4076 struct clk_bulk_data *clks; 4077 struct clk_bulk_data pipe_clks[2]; 4078 int num_pipe_clks; 4079 4080 struct reset_control_bulk_data *resets; 4081 struct reset_control *nocsr_reset; 4082 struct regulator_bulk_data *vregs; 4083 4084 struct phy *phy; 4085 int mode; 4086 4087 struct clk_fixed_rate pipe_clk_fixed; 4088 struct clk_fixed_rate aux_clk_fixed; 4089 }; 4090 4091 /* list of clocks required by phy */ 4092 static const char * const qmp_pciephy_clk_l[] = { 4093 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", 4094 }; 4095 4096 /* list of regulators */ 4097 static const char * const qmp_phy_vreg_l[] = { 4098 "vdda-phy", "vdda-pll", 4099 }; 4100 4101 static const char * const ipq9650_qmp_phy_vreg_l[] = { 4102 "refgen", 4103 }; 4104 4105 static const char * const sm8550_qmp_phy_vreg_l[] = { 4106 "vdda-phy", "vdda-pll", "vdda-qref", 4107 }; 4108 4109 /* list of resets */ 4110 static const char * const ipq8074_pciephy_reset_l[] = { 4111 "phy", "common", 4112 }; 4113 4114 static const char * const sdm845_pciephy_reset_l[] = { 4115 "phy", 4116 }; 4117 4118 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { 4119 .serdes = 0, 4120 .pcs = 0x1800, 4121 .tx = 0x0800, 4122 /* no .rx for QHP */ 4123 }; 4124 4125 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { 4126 .serdes = 0, 4127 .pcs = 0x0800, 4128 .tx = 0x0200, 4129 .rx = 0x0400, 4130 }; 4131 4132 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { 4133 .serdes = 0, 4134 .pcs = 0x0800, 4135 .pcs_misc = 0x0600, 4136 .tx = 0x0200, 4137 .rx = 0x0400, 4138 }; 4139 4140 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { 4141 .serdes = 0, 4142 .pcs = 0x0800, 4143 .pcs_misc = 0x0c00, 4144 .tx = 0x0200, 4145 .rx = 0x0400, 4146 }; 4147 4148 static const struct qmp_pcie_offsets qmp_pcie_offsets_9650_v4x1 = { 4149 .serdes = 0, 4150 .pcs = 0x0600, 4151 .pcs_misc = 0x0a00, 4152 .tx = 0x0200, 4153 .rx = 0x0400, 4154 }; 4155 4156 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { 4157 .serdes = 0, 4158 .pcs = 0x0a00, 4159 .pcs_misc = 0x0e00, 4160 .tx = 0x0200, 4161 .rx = 0x0400, 4162 .tx2 = 0x0600, 4163 .rx2 = 0x0800, 4164 }; 4165 4166 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { 4167 .serdes = 0x1000, 4168 .pcs = 0x1200, 4169 .pcs_misc = 0x1600, 4170 .pcs_lane1 = 0x1e00, 4171 .tx = 0x0000, 4172 .rx = 0x0200, 4173 .tx2 = 0x0800, 4174 .rx2 = 0x0a00, 4175 }; 4176 4177 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 4178 .serdes = 0, 4179 .pcs = 0x0200, 4180 .pcs_misc = 0x0600, 4181 .tx = 0x0e00, 4182 .rx = 0x1000, 4183 .pcs_lane1 = 0x1400, 4184 .tx2 = 0x1600, 4185 .rx2 = 0x1800, 4186 }; 4187 4188 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { 4189 .serdes = 0, 4190 .pcs = 0x1000, 4191 .pcs_misc = 0x1400, 4192 .tx = 0x0200, 4193 .rx = 0x0400, 4194 .tx2 = 0x0600, 4195 .rx2 = 0x0800, 4196 }; 4197 4198 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { 4199 .serdes = 0x1000, 4200 .pcs = 0x1200, 4201 .pcs_misc = 0x1400, 4202 .pcs_lane1 = 0x1e00, 4203 .tx = 0x0000, 4204 .rx = 0x0200, 4205 .tx2 = 0x0800, 4206 .rx2 = 0x0a00, 4207 .ln_shrd = 0x0e00, 4208 }; 4209 4210 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 4211 .serdes = 0x2000, 4212 .pcs = 0x2200, 4213 .pcs_misc = 0x2400, 4214 .tx = 0x0, 4215 .rx = 0x0200, 4216 .tx2 = 0x3800, 4217 .rx2 = 0x3a00, 4218 }; 4219 4220 static const struct qmp_pcie_offsets qmp_pcie_offsets_v7 = { 4221 .serdes = 0x0, 4222 .pcs = 0x400, 4223 .pcs_misc = 0x800, 4224 .tx = 0x1000, 4225 .rx = 0x1200, 4226 .tx2 = 0x1800, 4227 .rx2 = 0x1a00, 4228 }; 4229 4230 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 4231 .serdes = 0x1000, 4232 .pcs = 0x1200, 4233 .pcs_misc = 0x1400, 4234 .tx = 0x0000, 4235 .rx = 0x0200, 4236 .tx2 = 0x0800, 4237 .rx2 = 0x0a00, 4238 .ln_shrd = 0x0e00, 4239 }; 4240 4241 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = { 4242 .serdes = 0x8800, 4243 .pcs = 0x9000, 4244 .pcs_misc = 0x9800, 4245 .tx = 0x0000, 4246 .rx = 0x0200, 4247 .txz = 0xe000, 4248 .rxz = 0xe200, 4249 .ln_shrd = 0x8000, 4250 }; 4251 4252 static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_0 = { 4253 .serdes = 0x1000, 4254 .pcs = 0x1400, 4255 .pcs_misc = 0x1800, 4256 .tx = 0x0000, 4257 .rx = 0x0200, 4258 .tx2 = 0x0800, 4259 .rx2 = 0x0a00, 4260 }; 4261 4262 static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = { 4263 .serdes = 0x8000, 4264 .pcs = 0x9000, 4265 .txrxz = 0xd000, 4266 }; 4267 4268 static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_0 = { 4269 .serdes = 0x0000, 4270 .pcs = 0x0400, 4271 .pcs_misc = 0x0800, 4272 .tx = 0x1000, 4273 .rx = 0x1200, 4274 .tx2 = 0x1800, 4275 .rx2 = 0x1a00, 4276 }; 4277 4278 static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_60 = { 4279 .tx = 0x0000, 4280 /* no .rx; tx and rx share the same register block */ 4281 .serdes = 0x1000, 4282 .pcs = 0x1400, 4283 .pcs_misc = 0x1800, 4284 }; 4285 4286 static const struct qmp_phy_cfg eliza_qmp_gen3x1_pciephy_cfg = { 4287 .lanes = 1, 4288 4289 .offsets = &qmp_pcie_offsets_v5, 4290 4291 .tbls = { 4292 .serdes = eliza_qmp_gen3x1_pcie_serdes_tbl, 4293 .serdes_num = ARRAY_SIZE(eliza_qmp_gen3x1_pcie_serdes_tbl), 4294 .tx = eliza_qmp_gen3x1_pcie_tx_tbl, 4295 .tx_num = ARRAY_SIZE(eliza_qmp_gen3x1_pcie_tx_tbl), 4296 .rx = eliza_qmp_gen3x1_pcie_rx_tbl, 4297 .rx_num = ARRAY_SIZE(eliza_qmp_gen3x1_pcie_rx_tbl), 4298 .pcs = eliza_qmp_gen3x1_pcie_pcs_tbl, 4299 .pcs_num = ARRAY_SIZE(eliza_qmp_gen3x1_pcie_pcs_tbl), 4300 .pcs_misc = eliza_qmp_gen3x1_pcie_misc_pcs_tbl, 4301 .pcs_misc_num = ARRAY_SIZE(eliza_qmp_gen3x1_pcie_misc_pcs_tbl), 4302 }, 4303 .reset_list = sdm845_pciephy_reset_l, 4304 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4305 .vreg_list = qmp_phy_vreg_l, 4306 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4307 .regs = pciephy_v6_regs_layout, 4308 4309 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4310 .phy_status = PHYSTATUS, 4311 }; 4312 4313 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 4314 .lanes = 1, 4315 4316 .offsets = &qmp_pcie_offsets_v2, 4317 4318 .tbls = { 4319 .serdes = ipq8074_pcie_serdes_tbl, 4320 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 4321 .tx = ipq8074_pcie_tx_tbl, 4322 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 4323 .rx = ipq8074_pcie_rx_tbl, 4324 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 4325 .pcs = ipq8074_pcie_pcs_tbl, 4326 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 4327 }, 4328 .reset_list = ipq8074_pciephy_reset_l, 4329 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4330 .vreg_list = NULL, 4331 .num_vregs = 0, 4332 .regs = pciephy_v2_regs_layout, 4333 4334 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4335 .phy_status = PHYSTATUS, 4336 }; 4337 4338 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 4339 .lanes = 1, 4340 4341 .offsets = &qmp_pcie_offsets_v4x1, 4342 4343 .tbls = { 4344 .serdes = ipq8074_pcie_gen3_serdes_tbl, 4345 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 4346 .tx = ipq8074_pcie_gen3_tx_tbl, 4347 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 4348 .rx = ipq8074_pcie_gen3_rx_tbl, 4349 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 4350 .pcs = ipq8074_pcie_gen3_pcs_tbl, 4351 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 4352 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 4353 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 4354 }, 4355 .reset_list = ipq8074_pciephy_reset_l, 4356 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4357 .vreg_list = NULL, 4358 .num_vregs = 0, 4359 .regs = pciephy_v4_regs_layout, 4360 4361 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4362 .phy_status = PHYSTATUS, 4363 4364 .pipe_clock_rate = 250000000, 4365 }; 4366 4367 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 4368 .lanes = 1, 4369 4370 .offsets = &qmp_pcie_offsets_v4x1, 4371 4372 .tbls = { 4373 .serdes = ipq6018_pcie_serdes_tbl, 4374 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 4375 .tx = ipq6018_pcie_tx_tbl, 4376 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 4377 .rx = ipq6018_pcie_rx_tbl, 4378 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 4379 .pcs = ipq6018_pcie_pcs_tbl, 4380 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 4381 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 4382 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 4383 }, 4384 .reset_list = ipq8074_pciephy_reset_l, 4385 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4386 .vreg_list = NULL, 4387 .num_vregs = 0, 4388 .regs = pciephy_v4_regs_layout, 4389 4390 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4391 .phy_status = PHYSTATUS, 4392 }; 4393 4394 static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg = { 4395 .lanes = 1, 4396 4397 .offsets = &qmp_pcie_offsets_v4x1, 4398 4399 .tbls = { 4400 .serdes = ipq9574_gen3x1_pcie_serdes_tbl, 4401 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), 4402 .tx = ipq8074_pcie_gen3_tx_tbl, 4403 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 4404 .rx = ipq9574_pcie_rx_tbl, 4405 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 4406 .pcs = ipq9574_gen3x1_pcie_pcs_tbl, 4407 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), 4408 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, 4409 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), 4410 }, 4411 4412 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4413 .serdes = ipq5210_gen3x1_pcie_ep_serdes_tbl, 4414 .serdes_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl), 4415 .tx = ipq6018_pcie_tx_tbl, 4416 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 4417 .rx = ipq5210_gen3x1_pcie_ep_rx_tbl, 4418 .rx_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl), 4419 .pcs = ipq6018_pcie_pcs_tbl, 4420 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 4421 .pcs_misc = ipq5210_gen3x1_pcie_ep_pcs_misc_tbl, 4422 .pcs_misc_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl), 4423 }, 4424 4425 .reset_list = ipq8074_pciephy_reset_l, 4426 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4427 .vreg_list = NULL, 4428 .num_vregs = 0, 4429 .regs = pciephy_v4_regs_layout, 4430 4431 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4432 .phy_status = PHYSTATUS, 4433 4434 .pipe_clock_rate = 250000000, 4435 }; 4436 4437 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { 4438 .lanes = 1, 4439 4440 .offsets = &qmp_pcie_offsets_v4x1, 4441 4442 .tbls = { 4443 .serdes = ipq9574_gen3x1_pcie_serdes_tbl, 4444 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), 4445 .tx = ipq8074_pcie_gen3_tx_tbl, 4446 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 4447 .rx = ipq9574_pcie_rx_tbl, 4448 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 4449 .pcs = ipq9574_gen3x1_pcie_pcs_tbl, 4450 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), 4451 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, 4452 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), 4453 }, 4454 .reset_list = ipq8074_pciephy_reset_l, 4455 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4456 .vreg_list = NULL, 4457 .num_vregs = 0, 4458 .regs = pciephy_v4_regs_layout, 4459 4460 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4461 .phy_status = PHYSTATUS, 4462 .pipe_clock_rate = 250000000, 4463 }; 4464 4465 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { 4466 .lanes = 2, 4467 4468 .offsets = &qmp_pcie_offsets_ipq9574, 4469 4470 .tbls = { 4471 .serdes = ipq9574_gen3x2_pcie_serdes_tbl, 4472 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), 4473 .tx = ipq8074_pcie_gen3_tx_tbl, 4474 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 4475 .rx = ipq9574_pcie_rx_tbl, 4476 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 4477 .pcs = ipq9574_gen3x2_pcie_pcs_tbl, 4478 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), 4479 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, 4480 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), 4481 }, 4482 .reset_list = ipq8074_pciephy_reset_l, 4483 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4484 .vreg_list = NULL, 4485 .num_vregs = 0, 4486 .regs = pciephy_v5_regs_layout, 4487 4488 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4489 .phy_status = PHYSTATUS, 4490 .pipe_clock_rate = 250000000, 4491 }; 4492 4493 static const struct qmp_phy_cfg ipq9650_gen3x1_pciephy_cfg = { 4494 .lanes = 1, 4495 4496 .offsets = &qmp_pcie_offsets_9650_v4x1, 4497 4498 .tbls = { 4499 .serdes = ipq9650_pcie_serdes_tbl, 4500 .serdes_num = ARRAY_SIZE(ipq9650_pcie_serdes_tbl), 4501 .tx = ipq9650_pcie_tx_tbl, 4502 .tx_num = ARRAY_SIZE(ipq9650_pcie_tx_tbl), 4503 .rx = ipq9650_pcie_rx_tbl, 4504 .rx_num = ARRAY_SIZE(ipq9650_pcie_rx_tbl), 4505 .pcs = ipq9650_pcie_pcs_tbl, 4506 .pcs_num = ARRAY_SIZE(ipq9650_pcie_pcs_tbl), 4507 .pcs_misc = ipq9650_pcie_pcs_misc_tbl, 4508 .pcs_misc_num = ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl), 4509 }, 4510 .reset_list = ipq8074_pciephy_reset_l, 4511 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4512 .vreg_list = ipq9650_qmp_phy_vreg_l, 4513 .num_vregs = ARRAY_SIZE(ipq9650_qmp_phy_vreg_l), 4514 .regs = pciephy_v4_regs_layout, 4515 4516 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4517 .phy_status = PHYSTATUS, 4518 .pipe_clock_rate = 250000000, 4519 }; 4520 4521 static const struct qmp_phy_cfg ipq9650_gen3x2_pciephy_cfg = { 4522 .lanes = 2, 4523 4524 .offsets = &qmp_pcie_offsets_v4x2, 4525 4526 .tbls = { 4527 .serdes = ipq9650_pcie_serdes_tbl, 4528 .serdes_num = ARRAY_SIZE(ipq9650_pcie_serdes_tbl), 4529 .tx = ipq9650_pcie_tx_tbl, 4530 .tx_num = ARRAY_SIZE(ipq9650_pcie_tx_tbl), 4531 .rx = ipq9650_pcie_rx_tbl, 4532 .rx_num = ARRAY_SIZE(ipq9650_pcie_rx_tbl), 4533 .pcs = ipq9650_pcie_pcs_tbl, 4534 .pcs_num = ARRAY_SIZE(ipq9650_pcie_pcs_tbl), 4535 .pcs_misc = ipq9650_pcie_pcs_misc_tbl, 4536 .pcs_misc_num = ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl), 4537 }, 4538 .reset_list = ipq8074_pciephy_reset_l, 4539 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4540 .vreg_list = ipq9650_qmp_phy_vreg_l, 4541 .num_vregs = ARRAY_SIZE(ipq9650_qmp_phy_vreg_l), 4542 .regs = pciephy_v4_regs_layout, 4543 4544 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4545 .phy_status = PHYSTATUS, 4546 .pipe_clock_rate = 250000000, 4547 }; 4548 4549 static const struct qmp_phy_cfg qcs615_pciephy_cfg = { 4550 .lanes = 1, 4551 4552 .offsets = &qmp_pcie_offsets_v2, 4553 4554 .tbls = { 4555 .serdes = qcs615_pcie_serdes_tbl, 4556 .serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl), 4557 .tx = qcs615_pcie_tx_tbl, 4558 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl), 4559 .rx = qcs615_pcie_rx_tbl, 4560 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl), 4561 .pcs = qcs615_pcie_pcs_tbl, 4562 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl), 4563 }, 4564 .reset_list = sdm845_pciephy_reset_l, 4565 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4566 .vreg_list = qmp_phy_vreg_l, 4567 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4568 .regs = pciephy_v2_regs_layout, 4569 4570 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4571 .phy_status = PHYSTATUS, 4572 }; 4573 4574 static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = { 4575 .lanes = 2, 4576 .offsets = &qmp_pcie_offsets_v5_20, 4577 4578 .tbls = { 4579 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 4580 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 4581 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 4582 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 4583 .rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl, 4584 .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl), 4585 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 4586 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 4587 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 4588 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 4589 }, 4590 4591 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4592 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 4593 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 4594 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 4595 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 4596 }, 4597 4598 .reset_list = sdm845_pciephy_reset_l, 4599 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4600 .vreg_list = qmp_phy_vreg_l, 4601 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4602 .regs = pciephy_v5_regs_layout, 4603 4604 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4605 .phy_status = PHYSTATUS_4_20, 4606 }; 4607 4608 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 4609 .lanes = 1, 4610 4611 .offsets = &qmp_pcie_offsets_v3, 4612 4613 .tbls = { 4614 .serdes = sdm845_qmp_pcie_serdes_tbl, 4615 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 4616 .tx = sdm845_qmp_pcie_tx_tbl, 4617 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 4618 .rx = sdm845_qmp_pcie_rx_tbl, 4619 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 4620 .pcs = sdm845_qmp_pcie_pcs_tbl, 4621 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 4622 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 4623 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 4624 }, 4625 .reset_list = sdm845_pciephy_reset_l, 4626 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4627 .vreg_list = qmp_phy_vreg_l, 4628 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4629 .regs = pciephy_v3_regs_layout, 4630 4631 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4632 .phy_status = PHYSTATUS, 4633 }; 4634 4635 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 4636 .lanes = 1, 4637 4638 .offsets = &qmp_pcie_offsets_qhp, 4639 4640 .tbls = { 4641 .serdes = sdm845_qhp_pcie_serdes_tbl, 4642 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 4643 .tx = sdm845_qhp_pcie_tx_tbl, 4644 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 4645 .pcs = sdm845_qhp_pcie_pcs_tbl, 4646 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 4647 }, 4648 .reset_list = sdm845_pciephy_reset_l, 4649 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4650 .vreg_list = qmp_phy_vreg_l, 4651 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4652 .regs = sdm845_qhp_pciephy_regs_layout, 4653 4654 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4655 .phy_status = PHYSTATUS, 4656 }; 4657 4658 static const struct qmp_phy_cfg shikra_pciephy_cfg = { 4659 .lanes = 1, 4660 4661 .offsets = &qmp_pcie_offsets_v2, 4662 4663 .tbls = { 4664 .serdes = shikra_pcie_serdes_tbl, 4665 .serdes_num = ARRAY_SIZE(shikra_pcie_serdes_tbl), 4666 .tx = qcs615_pcie_tx_tbl, 4667 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl), 4668 .rx = qcs615_pcie_rx_tbl, 4669 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl), 4670 .pcs = qcs615_pcie_pcs_tbl, 4671 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl), 4672 }, 4673 .reset_list = sdm845_pciephy_reset_l, 4674 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4675 .vreg_list = qmp_phy_vreg_l, 4676 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4677 .regs = pciephy_v2_regs_layout, 4678 4679 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4680 .phy_status = PHYSTATUS, 4681 }; 4682 4683 4684 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 4685 .lanes = 1, 4686 4687 .offsets = &qmp_pcie_offsets_v4x1, 4688 4689 .tbls = { 4690 .serdes = sm8250_qmp_pcie_serdes_tbl, 4691 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 4692 .tx = sm8250_qmp_pcie_tx_tbl, 4693 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 4694 .rx = sm8250_qmp_pcie_rx_tbl, 4695 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 4696 .pcs = sm8250_qmp_pcie_pcs_tbl, 4697 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 4698 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 4699 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 4700 }, 4701 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4702 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 4703 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 4704 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 4705 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 4706 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 4707 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 4708 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 4709 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 4710 }, 4711 .reset_list = sdm845_pciephy_reset_l, 4712 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4713 .vreg_list = qmp_phy_vreg_l, 4714 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4715 .regs = pciephy_v4_regs_layout, 4716 4717 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4718 .phy_status = PHYSTATUS, 4719 }; 4720 4721 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 4722 .lanes = 2, 4723 4724 .offsets = &qmp_pcie_offsets_v4x2, 4725 4726 .tbls = { 4727 .serdes = sm8250_qmp_pcie_serdes_tbl, 4728 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 4729 .tx = sm8250_qmp_pcie_tx_tbl, 4730 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 4731 .rx = sm8250_qmp_pcie_rx_tbl, 4732 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 4733 .pcs = sm8250_qmp_pcie_pcs_tbl, 4734 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 4735 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 4736 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 4737 }, 4738 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4739 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 4740 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 4741 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 4742 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 4743 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 4744 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 4745 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 4746 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 4747 }, 4748 .reset_list = sdm845_pciephy_reset_l, 4749 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4750 .vreg_list = qmp_phy_vreg_l, 4751 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4752 .regs = pciephy_v4_regs_layout, 4753 4754 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4755 .phy_status = PHYSTATUS, 4756 }; 4757 4758 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 4759 .lanes = 1, 4760 4761 .offsets = &qmp_pcie_offsets_v3, 4762 4763 .tbls = { 4764 .serdes = msm8998_pcie_serdes_tbl, 4765 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 4766 .tx = msm8998_pcie_tx_tbl, 4767 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 4768 .rx = msm8998_pcie_rx_tbl, 4769 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 4770 .pcs = msm8998_pcie_pcs_tbl, 4771 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 4772 }, 4773 .reset_list = ipq8074_pciephy_reset_l, 4774 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 4775 .vreg_list = qmp_phy_vreg_l, 4776 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4777 .regs = pciephy_v3_regs_layout, 4778 4779 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4780 .phy_status = PHYSTATUS, 4781 4782 .skip_start_delay = true, 4783 }; 4784 4785 static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = { 4786 .lanes = 2, 4787 4788 .offsets = &qmp_pcie_offsets_v5, 4789 4790 .tbls = { 4791 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 4792 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 4793 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 4794 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 4795 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 4796 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 4797 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, 4798 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), 4799 }, 4800 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4801 .serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl, 4802 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl), 4803 .tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl, 4804 .tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl), 4805 .pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl, 4806 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl), 4807 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 4808 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 4809 }, 4810 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4811 .serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl, 4812 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl), 4813 .pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl, 4814 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl), 4815 .pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl, 4816 .pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl), 4817 }, 4818 .reset_list = sdm845_pciephy_reset_l, 4819 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4820 .vreg_list = qmp_phy_vreg_l, 4821 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4822 .regs = pciephy_v5_regs_layout, 4823 4824 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4825 .phy_status = PHYSTATUS, 4826 }; 4827 4828 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 4829 .lanes = 2, 4830 4831 .offsets = &qmp_pcie_offsets_v4x2, 4832 4833 .tbls = { 4834 .serdes = sc8180x_qmp_pcie_serdes_tbl, 4835 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 4836 .tx = sc8180x_qmp_pcie_tx_tbl, 4837 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 4838 .rx = sc8180x_qmp_pcie_rx_tbl, 4839 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 4840 .pcs = sc8180x_qmp_pcie_pcs_tbl, 4841 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 4842 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 4843 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 4844 }, 4845 .reset_list = sdm845_pciephy_reset_l, 4846 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4847 .vreg_list = qmp_phy_vreg_l, 4848 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4849 .regs = pciephy_v4_regs_layout, 4850 4851 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4852 .phy_status = PHYSTATUS, 4853 }; 4854 4855 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 4856 .lanes = 1, 4857 4858 .offsets = &qmp_pcie_offsets_v5, 4859 4860 .tbls = { 4861 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 4862 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 4863 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 4864 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 4865 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 4866 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 4867 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 4868 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 4869 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 4870 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 4871 }, 4872 4873 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4874 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 4875 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 4876 }, 4877 4878 .reset_list = sdm845_pciephy_reset_l, 4879 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4880 .vreg_list = qmp_phy_vreg_l, 4881 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4882 .regs = pciephy_v5_regs_layout, 4883 4884 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4885 .phy_status = PHYSTATUS, 4886 }; 4887 4888 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 4889 .lanes = 2, 4890 4891 .offsets = &qmp_pcie_offsets_v5, 4892 4893 .tbls = { 4894 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 4895 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 4896 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 4897 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 4898 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 4899 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 4900 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 4901 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 4902 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 4903 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 4904 }, 4905 4906 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4907 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 4908 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 4909 }, 4910 4911 .reset_list = sdm845_pciephy_reset_l, 4912 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4913 .vreg_list = qmp_phy_vreg_l, 4914 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4915 .regs = pciephy_v5_regs_layout, 4916 4917 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4918 .phy_status = PHYSTATUS, 4919 }; 4920 4921 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 4922 .lanes = 4, 4923 4924 .offsets = &qmp_pcie_offsets_v5, 4925 4926 .tbls = { 4927 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 4928 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 4929 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 4930 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 4931 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 4932 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 4933 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 4934 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 4935 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 4936 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 4937 }, 4938 4939 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4940 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 4941 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 4942 }, 4943 4944 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 4945 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 4946 4947 .reset_list = sdm845_pciephy_reset_l, 4948 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4949 .vreg_list = qmp_phy_vreg_l, 4950 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4951 .regs = pciephy_v5_regs_layout, 4952 4953 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4954 .phy_status = PHYSTATUS, 4955 }; 4956 4957 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 4958 .lanes = 2, 4959 4960 .offsets = &qmp_pcie_offsets_v4_20, 4961 4962 .tbls = { 4963 .serdes = sdx55_qmp_pcie_serdes_tbl, 4964 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 4965 .tx = sdx55_qmp_pcie_tx_tbl, 4966 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 4967 .rx = sdx55_qmp_pcie_rx_tbl, 4968 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 4969 .pcs = sdx55_qmp_pcie_pcs_tbl, 4970 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 4971 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 4972 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 4973 }, 4974 4975 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4976 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 4977 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 4978 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 4979 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 4980 }, 4981 4982 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4983 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 4984 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 4985 .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl, 4986 .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl), 4987 }, 4988 4989 .reset_list = sdm845_pciephy_reset_l, 4990 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4991 .vreg_list = qmp_phy_vreg_l, 4992 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4993 .regs = pciephy_v4_regs_layout, 4994 4995 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4996 .phy_status = PHYSTATUS_4_20, 4997 }; 4998 4999 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 5000 .lanes = 1, 5001 5002 .offsets = &qmp_pcie_offsets_v5, 5003 5004 .tbls = { 5005 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 5006 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 5007 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 5008 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 5009 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 5010 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 5011 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 5012 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 5013 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 5014 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 5015 }, 5016 5017 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5018 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 5019 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 5020 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 5021 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 5022 }, 5023 5024 .reset_list = sdm845_pciephy_reset_l, 5025 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5026 .vreg_list = qmp_phy_vreg_l, 5027 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5028 .regs = pciephy_v5_regs_layout, 5029 5030 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5031 .phy_status = PHYSTATUS, 5032 }; 5033 5034 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 5035 .lanes = 2, 5036 5037 .offsets = &qmp_pcie_offsets_v5, 5038 5039 .tbls = { 5040 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 5041 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 5042 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 5043 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 5044 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 5045 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 5046 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 5047 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 5048 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 5049 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 5050 }, 5051 5052 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5053 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 5054 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 5055 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 5056 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 5057 }, 5058 5059 .reset_list = sdm845_pciephy_reset_l, 5060 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5061 .vreg_list = qmp_phy_vreg_l, 5062 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5063 .regs = pciephy_v5_regs_layout, 5064 5065 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5066 .phy_status = PHYSTATUS, 5067 }; 5068 5069 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 5070 .lanes = 2, 5071 5072 .offsets = &qmp_pcie_offsets_v6_20, 5073 5074 .tbls = { 5075 .serdes = sdx65_qmp_pcie_serdes_tbl, 5076 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 5077 .tx = sdx65_qmp_pcie_tx_tbl, 5078 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 5079 .rx = sdx65_qmp_pcie_rx_tbl, 5080 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 5081 .pcs = sdx65_qmp_pcie_pcs_tbl, 5082 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 5083 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 5084 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 5085 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 5086 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 5087 }, 5088 .reset_list = sdm845_pciephy_reset_l, 5089 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5090 .vreg_list = qmp_phy_vreg_l, 5091 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5092 .regs = pciephy_v6_regs_layout, 5093 5094 .pwrdn_ctrl = SW_PWRDN, 5095 .phy_status = PHYSTATUS_4_20, 5096 }; 5097 5098 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 5099 .lanes = 1, 5100 5101 .offsets = &qmp_pcie_offsets_v5, 5102 5103 .tbls = { 5104 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 5105 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 5106 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 5107 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 5108 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 5109 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 5110 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 5111 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 5112 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 5113 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 5114 }, 5115 5116 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5117 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 5118 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 5119 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 5120 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 5121 }, 5122 5123 .reset_list = sdm845_pciephy_reset_l, 5124 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5125 .vreg_list = qmp_phy_vreg_l, 5126 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5127 .regs = pciephy_v5_regs_layout, 5128 5129 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5130 .phy_status = PHYSTATUS, 5131 }; 5132 5133 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 5134 .lanes = 2, 5135 5136 .offsets = &qmp_pcie_offsets_v5_20, 5137 5138 .tbls = { 5139 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 5140 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 5141 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 5142 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 5143 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 5144 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 5145 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 5146 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 5147 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 5148 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 5149 }, 5150 5151 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5152 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 5153 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 5154 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 5155 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 5156 }, 5157 5158 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 5159 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 5160 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 5161 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 5162 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 5163 }, 5164 5165 .reset_list = sdm845_pciephy_reset_l, 5166 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5167 .vreg_list = qmp_phy_vreg_l, 5168 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5169 .regs = pciephy_v5_regs_layout, 5170 5171 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5172 .phy_status = PHYSTATUS_4_20, 5173 5174 /* 20MHz PHY AUX Clock */ 5175 .aux_clock_rate = 20000000, 5176 }; 5177 5178 static const struct qmp_phy_cfg sm8475_qmp_gen3x1_pciephy_cfg = { 5179 .lanes = 1, 5180 5181 .offsets = &qmp_pcie_offsets_v5, 5182 5183 .tbls = { 5184 .serdes = sm8475_qmp_gen3x1_pcie_serdes_tbl, 5185 .serdes_num = ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_serdes_tbl), 5186 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 5187 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 5188 .rx = sm8475_qmp_gen3x1_pcie_rx_tbl, 5189 .rx_num = ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_rx_tbl), 5190 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 5191 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 5192 .pcs_misc = sm8475_qmp_gen3x1_pcie_pcs_misc_tbl, 5193 .pcs_misc_num = ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_pcs_misc_tbl), 5194 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, 5195 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), 5196 }, 5197 .reset_list = sdm845_pciephy_reset_l, 5198 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5199 .vreg_list = qmp_phy_vreg_l, 5200 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5201 .regs = pciephy_v6_regs_layout, 5202 5203 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5204 .phy_status = PHYSTATUS, 5205 }; 5206 5207 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 5208 .lanes = 2, 5209 5210 .offsets = &qmp_pcie_offsets_v5, 5211 5212 .tbls = { 5213 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 5214 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 5215 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 5216 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 5217 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 5218 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 5219 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 5220 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 5221 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 5222 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 5223 }, 5224 .reset_list = sdm845_pciephy_reset_l, 5225 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5226 .vreg_list = qmp_phy_vreg_l, 5227 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5228 .regs = pciephy_v5_regs_layout, 5229 5230 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5231 .phy_status = PHYSTATUS, 5232 }; 5233 5234 static const struct qmp_phy_cfg sm8750_qmp_gen3x2_pciephy_cfg = { 5235 .lanes = 2, 5236 5237 .offsets = &qmp_pcie_offsets_v7, 5238 5239 .tbls = { 5240 .serdes = sm8750_qmp_gen3x2_pcie_serdes_tbl, 5241 .serdes_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_serdes_tbl), 5242 .tx = sm8750_qmp_gen3x2_pcie_tx_tbl, 5243 .tx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_tx_tbl), 5244 .rx = sm8750_qmp_gen3x2_pcie_rx_tbl, 5245 .rx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_rx_tbl), 5246 .pcs = sm8750_qmp_gen3x2_pcie_pcs_tbl, 5247 .pcs_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_tbl), 5248 .pcs_misc = sm8750_qmp_gen3x2_pcie_pcs_misc_tbl, 5249 .pcs_misc_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_misc_tbl), 5250 }, 5251 .reset_list = sdm845_pciephy_reset_l, 5252 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5253 .vreg_list = qmp_phy_vreg_l, 5254 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5255 .regs = pciephy_v7_regs_layout, 5256 5257 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5258 .phy_status = PHYSTATUS, 5259 }; 5260 5261 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 5262 .lanes = 2, 5263 5264 .offsets = &qmp_pcie_offsets_v6_20, 5265 5266 .tbls = { 5267 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 5268 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 5269 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 5270 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 5271 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 5272 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 5273 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 5274 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 5275 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 5276 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 5277 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 5278 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 5279 }, 5280 .reset_list = sdm845_pciephy_reset_l, 5281 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5282 .vreg_list = sm8550_qmp_phy_vreg_l, 5283 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 5284 .regs = pciephy_v6_regs_layout, 5285 5286 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5287 .phy_status = PHYSTATUS_4_20, 5288 5289 /* 20MHz PHY AUX Clock */ 5290 .aux_clock_rate = 20000000, 5291 }; 5292 5293 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 5294 .lanes = 2, 5295 5296 .offsets = &qmp_pcie_offsets_v6_20, 5297 5298 .tbls = { 5299 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 5300 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 5301 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 5302 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 5303 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 5304 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 5305 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 5306 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 5307 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 5308 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 5309 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 5310 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 5311 }, 5312 .reset_list = sdm845_pciephy_reset_l, 5313 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5314 .vreg_list = sm8550_qmp_phy_vreg_l, 5315 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 5316 .regs = pciephy_v6_regs_layout, 5317 5318 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5319 .phy_status = PHYSTATUS_4_20, 5320 5321 /* 20MHz PHY AUX Clock */ 5322 .aux_clock_rate = 20000000, 5323 }; 5324 5325 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 5326 .lanes = 2, 5327 .offsets = &qmp_pcie_offsets_v5_20, 5328 5329 .tbls = { 5330 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 5331 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 5332 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 5333 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 5334 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, 5335 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), 5336 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 5337 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 5338 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 5339 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 5340 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 5341 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 5342 .ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl, 5343 .ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl), 5344 5345 }, 5346 5347 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5348 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 5349 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 5350 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 5351 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 5352 }, 5353 5354 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 5355 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 5356 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 5357 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 5358 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 5359 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, 5360 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), 5361 }, 5362 5363 .reset_list = sdm845_pciephy_reset_l, 5364 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5365 .vreg_list = qmp_phy_vreg_l, 5366 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5367 .regs = pciephy_v5_regs_layout, 5368 5369 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5370 .phy_status = PHYSTATUS_4_20, 5371 }; 5372 5373 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { 5374 .lanes = 4, 5375 .offsets = &qmp_pcie_offsets_v5_30, 5376 5377 .tbls = { 5378 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, 5379 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), 5380 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 5381 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 5382 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, 5383 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), 5384 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 5385 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 5386 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 5387 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 5388 }, 5389 5390 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 5391 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, 5392 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), 5393 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 5394 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 5395 }, 5396 5397 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 5398 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 5399 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 5400 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 5401 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 5402 }, 5403 5404 .reset_list = sdm845_pciephy_reset_l, 5405 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5406 .vreg_list = qmp_phy_vreg_l, 5407 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5408 .regs = pciephy_v5_regs_layout, 5409 5410 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5411 .phy_status = PHYSTATUS_4_20, 5412 }; 5413 5414 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 5415 .lanes = 2, 5416 5417 .offsets = &qmp_pcie_offsets_v6_20, 5418 5419 .tbls = { 5420 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 5421 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 5422 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 5423 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 5424 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 5425 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 5426 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 5427 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 5428 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 5429 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 5430 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 5431 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 5432 }, 5433 5434 .reset_list = sdm845_pciephy_reset_l, 5435 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5436 .vreg_list = qmp_phy_vreg_l, 5437 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5438 .regs = pciephy_v6_regs_layout, 5439 5440 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5441 .phy_status = PHYSTATUS_4_20, 5442 }; 5443 5444 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { 5445 .lanes = 4, 5446 5447 .offsets = &qmp_pcie_offsets_v6_20, 5448 5449 .tbls = { 5450 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 5451 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 5452 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 5453 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 5454 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 5455 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 5456 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 5457 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 5458 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 5459 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 5460 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 5461 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 5462 }, 5463 5464 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl, 5465 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl), 5466 5467 .reset_list = sdm845_pciephy_reset_l, 5468 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5469 .vreg_list = qmp_phy_vreg_l, 5470 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5471 .regs = pciephy_v6_regs_layout, 5472 5473 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5474 .phy_status = PHYSTATUS_4_20, 5475 }; 5476 5477 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { 5478 .lanes = 8, 5479 5480 .offsets = &qmp_pcie_offsets_v6_30, 5481 .tbls = { 5482 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl, 5483 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl), 5484 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl, 5485 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl), 5486 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl, 5487 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl), 5488 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl, 5489 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl), 5490 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl, 5491 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl), 5492 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl, 5493 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl), 5494 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl, 5495 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl), 5496 }, 5497 5498 .reset_list = sdm845_pciephy_reset_l, 5499 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5500 .vreg_list = qmp_phy_vreg_l, 5501 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5502 .regs = pciephy_v6_regs_layout, 5503 5504 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5505 .phy_status = PHYSTATUS_4_20, 5506 }; 5507 5508 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { 5509 .lanes = 4, 5510 5511 .offsets = &qmp_pcie_offsets_v6_20, 5512 5513 .reset_list = sdm845_pciephy_reset_l, 5514 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5515 .vreg_list = qmp_phy_vreg_l, 5516 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5517 .regs = pciephy_v6_regs_layout, 5518 5519 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5520 .phy_status = PHYSTATUS_4_20, 5521 }; 5522 5523 static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy_cfg = { 5524 .lanes = 2, 5525 5526 .offsets = &qmp_pcie_offsets_v8_0, 5527 5528 .tbls = { 5529 .serdes = kaanapali_qmp_gen3x2_pcie_serdes_tbl, 5530 .serdes_num = ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_serdes_tbl), 5531 .tx = kaanapali_qmp_gen3x2_pcie_tx_tbl, 5532 .tx_num = ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_tx_tbl), 5533 .rx = kaanapali_qmp_gen3x2_pcie_rx_tbl, 5534 .rx_num = ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_rx_tbl), 5535 .pcs = kaanapali_qmp_gen3x2_pcie_pcs_tbl, 5536 .pcs_num = ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_pcs_tbl), 5537 .pcs_misc = kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl, 5538 .pcs_misc_num = ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl), 5539 }, 5540 5541 .reset_list = sdm845_pciephy_reset_l, 5542 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5543 .vreg_list = qmp_phy_vreg_l, 5544 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5545 .regs = pciephy_v8_regs_layout, 5546 5547 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5548 .phy_status = PHYSTATUS_4_20, 5549 }; 5550 5551 static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { 5552 .lanes = 4, 5553 5554 .offsets = &qmp_pcie_offsets_v8_50, 5555 5556 .reset_list = sdm845_pciephy_reset_l, 5557 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5558 .vreg_list = qmp_phy_vreg_l, 5559 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5560 5561 .regs = pciephy_v8_50_regs_layout, 5562 5563 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5564 .phy_status = PHYSTATUS_4_20, 5565 }; 5566 5567 static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { 5568 .lanes = 2, 5569 5570 .offsets = &qmp_pcie_offsets_v8_0, 5571 5572 .reset_list = sdm845_pciephy_reset_l, 5573 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5574 .vreg_list = qmp_phy_vreg_l, 5575 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5576 5577 .regs = pciephy_v8_regs_layout, 5578 5579 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5580 .phy_status = PHYSTATUS_4_20, 5581 }; 5582 5583 static const struct qmp_phy_cfg hawi_qmp_gen3x2_pciephy_cfg = { 5584 .lanes = 2, 5585 5586 .offsets = &qmp_pcie_offsets_v10_0, 5587 5588 .tbls = { 5589 .serdes = hawi_qmp_gen3x2_pcie_serdes_tbl, 5590 .serdes_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_serdes_tbl), 5591 .tx = hawi_qmp_gen3x2_pcie_tx_tbl, 5592 .tx_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_tx_tbl), 5593 .rx = hawi_qmp_gen3x2_pcie_rx_tbl, 5594 .rx_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_rx_tbl), 5595 .pcs = hawi_qmp_gen3x2_pcie_pcs_tbl, 5596 .pcs_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_tbl), 5597 .pcs_misc = hawi_qmp_gen3x2_pcie_pcs_misc_tbl, 5598 .pcs_misc_num = ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_misc_tbl), 5599 }, 5600 5601 .reset_list = sdm845_pciephy_reset_l, 5602 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5603 .vreg_list = qmp_phy_vreg_l, 5604 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5605 .regs = pciephy_v10_regs_layout, 5606 5607 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5608 .phy_status = PHYSTATUS, 5609 }; 5610 5611 static const struct qmp_phy_cfg hawi_qmp_gen4x1_pciephy_cfg = { 5612 .lanes = 1, 5613 5614 .offsets = &qmp_pcie_offsets_v10_60, 5615 5616 .tbls = { 5617 .serdes = hawi_qmp_gen4x1_pcie_serdes_tbl, 5618 .serdes_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_serdes_tbl), 5619 .tx = hawi_qmp_gen4x1_pcie_tx_tbl, 5620 .tx_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_tx_tbl), 5621 .pcs = hawi_qmp_gen4x1_pcie_pcs_tbl, 5622 .pcs_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_tbl), 5623 .pcs_misc = hawi_qmp_gen4x1_pcie_pcs_misc_tbl, 5624 .pcs_misc_num = ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_misc_tbl), 5625 }, 5626 5627 .reset_list = sdm845_pciephy_reset_l, 5628 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 5629 .vreg_list = qmp_phy_vreg_l, 5630 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 5631 .regs = pciephy_v10_60_regs_layout, 5632 5633 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 5634 .phy_status = PHYSTATUS_4_20, 5635 }; 5636 5637 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 5638 { 5639 const struct qmp_phy_cfg *cfg = qmp->cfg; 5640 const struct qmp_pcie_offsets *offs = cfg->offsets; 5641 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; 5642 5643 serdes = qmp->port_b + offs->serdes; 5644 tx3 = qmp->port_b + offs->tx; 5645 rx3 = qmp->port_b + offs->rx; 5646 tx4 = qmp->port_b + offs->tx2; 5647 rx4 = qmp->port_b + offs->rx2; 5648 pcs = qmp->port_b + offs->pcs; 5649 pcs_misc = qmp->port_b + offs->pcs_misc; 5650 ln_shrd = qmp->port_b + offs->ln_shrd; 5651 5652 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 5653 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 5654 5655 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); 5656 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); 5657 5658 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); 5659 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); 5660 5661 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 5662 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 5663 5664 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 5665 } 5666 5667 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 5668 { 5669 const struct qmp_phy_cfg *cfg = qmp->cfg; 5670 void __iomem *serdes = qmp->serdes; 5671 void __iomem *tx = qmp->tx; 5672 void __iomem *rx = qmp->rx; 5673 void __iomem *tx2 = qmp->tx2; 5674 void __iomem *rx2 = qmp->rx2; 5675 void __iomem *pcs = qmp->pcs; 5676 void __iomem *pcs_misc = qmp->pcs_misc; 5677 void __iomem *pcs_lane1 = qmp->pcs_lane1; 5678 void __iomem *ln_shrd = qmp->ln_shrd; 5679 5680 if (!tbls) 5681 return; 5682 5683 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 5684 5685 /* 5686 * Tx/Rx registers that require different settings than 5687 * txz/rxz must be programmed after txz/rxz. 5688 */ 5689 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); 5690 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); 5691 5692 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 5693 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 5694 5695 if (cfg->lanes >= 2) { 5696 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); 5697 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); 5698 } 5699 5700 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 5701 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 5702 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); 5703 5704 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 5705 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, 5706 cfg->serdes_4ln_num); 5707 qmp_pcie_init_port_b(qmp, tbls); 5708 } 5709 5710 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 5711 } 5712 5713 static int qmp_pcie_init(struct phy *phy) 5714 { 5715 struct qmp_pcie *qmp = phy_get_drvdata(phy); 5716 const struct qmp_phy_cfg *cfg = qmp->cfg; 5717 void __iomem *pcs = qmp->pcs; 5718 bool skip_reset; 5719 int ret; 5720 5721 /* 5722 * We can skip PHY initialization if all of the following conditions 5723 * are met: 5724 * 1. The PHY supports the nocsr_reset that preserves the PHY config. 5725 * 2. The PHY was started (and not powered down again) by the 5726 * bootloader, with all of the expected bits set correctly. 5727 * In this case, we can continue without having the init sequence 5728 * defined in the driver. 5729 */ 5730 qmp->skip_init = qmp->nocsr_reset && 5731 qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) && 5732 qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); 5733 5734 skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS], 5735 cfg->phy_status); 5736 5737 if (!qmp->skip_init && !cfg->tbls.serdes_num) { 5738 dev_err(qmp->dev, "Init sequence not available\n"); 5739 return -ENODATA; 5740 } 5741 5742 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 5743 if (ret) { 5744 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 5745 return ret; 5746 } 5747 5748 /* 5749 * Toggle BCR reset for PHY that doesn't support no_csr reset or has not 5750 * been initialized. 5751 */ 5752 if (!qmp->skip_init) { 5753 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 5754 if (ret) { 5755 dev_err(qmp->dev, "reset assert failed\n"); 5756 goto err_disable_regulators; 5757 } 5758 } 5759 5760 if (!skip_reset) { 5761 ret = reset_control_assert(qmp->nocsr_reset); 5762 if (ret) { 5763 dev_err(qmp->dev, "no-csr reset assert failed\n"); 5764 goto err_assert_reset; 5765 } 5766 5767 usleep_range(200, 300); 5768 } 5769 5770 if (!qmp->skip_init) { 5771 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 5772 if (ret) { 5773 dev_err(qmp->dev, "reset deassert failed\n"); 5774 goto err_assert_reset; 5775 } 5776 } 5777 5778 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 5779 if (ret) 5780 goto err_assert_reset; 5781 5782 return 0; 5783 5784 err_assert_reset: 5785 if (!qmp->skip_init) 5786 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 5787 err_disable_regulators: 5788 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 5789 5790 return ret; 5791 } 5792 5793 static int qmp_pcie_exit(struct phy *phy) 5794 { 5795 struct qmp_pcie *qmp = phy_get_drvdata(phy); 5796 const struct qmp_phy_cfg *cfg = qmp->cfg; 5797 5798 if (qmp->nocsr_reset) 5799 reset_control_assert(qmp->nocsr_reset); 5800 else 5801 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 5802 5803 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 5804 5805 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 5806 5807 return 0; 5808 } 5809 5810 static int qmp_pcie_power_on(struct phy *phy) 5811 { 5812 struct qmp_pcie *qmp = phy_get_drvdata(phy); 5813 const struct qmp_phy_cfg *cfg = qmp->cfg; 5814 const struct qmp_phy_cfg_tbls *mode_tbls; 5815 void __iomem *pcs = qmp->pcs; 5816 void __iomem *status; 5817 unsigned int mask, val; 5818 bool skip_reset; 5819 int ret; 5820 5821 skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS], 5822 cfg->phy_status); 5823 /* 5824 * Write CSR register for PHY that doesn't support no_csr reset or has not 5825 * been initialized. 5826 */ 5827 if (qmp->skip_init) 5828 goto skip_tbls_init; 5829 5830 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 5831 cfg->pwrdn_ctrl); 5832 5833 if (qmp->mode == PHY_MODE_PCIE_RC) 5834 mode_tbls = cfg->tbls_rc; 5835 else 5836 mode_tbls = cfg->tbls_ep; 5837 5838 qmp_pcie_init_registers(qmp, &cfg->tbls); 5839 qmp_pcie_init_registers(qmp, mode_tbls); 5840 5841 skip_tbls_init: 5842 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 5843 if (ret) 5844 return ret; 5845 5846 if (!skip_reset) { 5847 ret = reset_control_deassert(qmp->nocsr_reset); 5848 if (ret) { 5849 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 5850 goto err_disable_pipe_clk; 5851 } 5852 } 5853 5854 if (qmp->skip_init) 5855 goto skip_serdes_start; 5856 5857 /* Pull PHY out of reset state */ 5858 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 5859 5860 /* start SerDes and Phy-Coding-Sublayer */ 5861 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 5862 5863 if (!cfg->skip_start_delay) 5864 usleep_range(1000, 1200); 5865 5866 skip_serdes_start: 5867 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 5868 mask = cfg->phy_status; 5869 ret = readl_poll_timeout(status, val, !(val & mask), 200, 5870 PHY_INIT_COMPLETE_TIMEOUT); 5871 if (ret) { 5872 dev_err(qmp->dev, "phy initialization timed-out\n"); 5873 goto err_disable_pipe_clk; 5874 } 5875 5876 return 0; 5877 5878 err_disable_pipe_clk: 5879 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 5880 5881 return ret; 5882 } 5883 5884 static int qmp_pcie_power_off(struct phy *phy) 5885 { 5886 struct qmp_pcie *qmp = phy_get_drvdata(phy); 5887 const struct qmp_phy_cfg *cfg = qmp->cfg; 5888 5889 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 5890 5891 /* 5892 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In 5893 * this way, no matter whether the PHY settings were initially programmed by 5894 * bootloader or PHY driver itself, we can reuse them when PHY is powered on 5895 * next time. 5896 */ 5897 if (qmp->nocsr_reset) 5898 goto skip_phy_deinit; 5899 5900 /* PHY reset */ 5901 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 5902 5903 /* stop SerDes and Phy-Coding-Sublayer */ 5904 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 5905 SERDES_START | PCS_START); 5906 5907 /* Put PHY into POWER DOWN state: active low */ 5908 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 5909 cfg->pwrdn_ctrl); 5910 5911 skip_phy_deinit: 5912 return 0; 5913 } 5914 5915 static int qmp_pcie_enable(struct phy *phy) 5916 { 5917 int ret; 5918 5919 ret = qmp_pcie_init(phy); 5920 if (ret) 5921 return ret; 5922 5923 ret = qmp_pcie_power_on(phy); 5924 if (ret) 5925 qmp_pcie_exit(phy); 5926 5927 return ret; 5928 } 5929 5930 static int qmp_pcie_disable(struct phy *phy) 5931 { 5932 int ret; 5933 5934 ret = qmp_pcie_power_off(phy); 5935 if (ret) 5936 return ret; 5937 5938 return qmp_pcie_exit(phy); 5939 } 5940 5941 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 5942 { 5943 struct qmp_pcie *qmp = phy_get_drvdata(phy); 5944 5945 switch (submode) { 5946 case PHY_MODE_PCIE_RC: 5947 case PHY_MODE_PCIE_EP: 5948 qmp->mode = submode; 5949 break; 5950 default: 5951 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 5952 return -EINVAL; 5953 } 5954 5955 return 0; 5956 } 5957 5958 static const struct phy_ops qmp_pcie_phy_ops = { 5959 .power_on = qmp_pcie_enable, 5960 .power_off = qmp_pcie_disable, 5961 .set_mode = qmp_pcie_set_mode, 5962 .owner = THIS_MODULE, 5963 }; 5964 5965 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 5966 { 5967 const struct qmp_phy_cfg *cfg = qmp->cfg; 5968 struct device *dev = qmp->dev; 5969 int num = cfg->num_vregs; 5970 int i; 5971 5972 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 5973 if (!qmp->vregs) 5974 return -ENOMEM; 5975 5976 for (i = 0; i < num; i++) 5977 qmp->vregs[i].supply = cfg->vreg_list[i]; 5978 5979 return devm_regulator_bulk_get(dev, num, qmp->vregs); 5980 } 5981 5982 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 5983 { 5984 const struct qmp_phy_cfg *cfg = qmp->cfg; 5985 struct device *dev = qmp->dev; 5986 int i; 5987 int ret; 5988 5989 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 5990 sizeof(*qmp->resets), GFP_KERNEL); 5991 if (!qmp->resets) 5992 return -ENOMEM; 5993 5994 for (i = 0; i < cfg->num_resets; i++) 5995 qmp->resets[i].id = cfg->reset_list[i]; 5996 5997 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 5998 if (ret) 5999 return dev_err_probe(dev, ret, "failed to get resets\n"); 6000 6001 qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); 6002 if (IS_ERR(qmp->nocsr_reset)) 6003 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 6004 "failed to get no-csr reset\n"); 6005 6006 return 0; 6007 } 6008 6009 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 6010 { 6011 struct device *dev = qmp->dev; 6012 int num = ARRAY_SIZE(qmp_pciephy_clk_l); 6013 int i; 6014 6015 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 6016 if (!qmp->clks) 6017 return -ENOMEM; 6018 6019 for (i = 0; i < num; i++) 6020 qmp->clks[i].id = qmp_pciephy_clk_l[i]; 6021 6022 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 6023 } 6024 6025 static void phy_clk_release_provider(void *res) 6026 { 6027 of_clk_del_provider(res); 6028 } 6029 6030 /* 6031 * Register a fixed rate pipe clock. 6032 * 6033 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 6034 * controls it. The <s>_pipe_clk coming out of the GCC is requested 6035 * by the PHY driver for its operations. 6036 * We register the <s>_pipe_clksrc here. The gcc driver takes care 6037 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 6038 * Below picture shows this relationship. 6039 * 6040 * +---------------+ 6041 * | PHY block |<<---------------------------------------+ 6042 * | | | 6043 * | +-------+ | +-----+ | 6044 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 6045 * clk | +-------+ | +-----+ 6046 * +---------------+ 6047 */ 6048 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 6049 { 6050 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 6051 struct clk_init_data init = { }; 6052 int ret; 6053 6054 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); 6055 if (ret) { 6056 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 6057 return ret; 6058 } 6059 6060 init.ops = &clk_fixed_rate_ops; 6061 6062 /* 6063 * Controllers using QMP PHY-s use 125MHz pipe clock interface 6064 * unless other frequency is specified in the PHY config. 6065 */ 6066 if (qmp->cfg->pipe_clock_rate) 6067 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 6068 else 6069 fixed->fixed_rate = 125000000; 6070 6071 fixed->hw.init = &init; 6072 6073 return devm_clk_hw_register(qmp->dev, &fixed->hw); 6074 } 6075 6076 /* 6077 * Register a fixed rate PHY aux clock. 6078 * 6079 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate 6080 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested 6081 * by the PHY driver for its operations. 6082 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care 6083 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk. 6084 * Below picture shows this relationship. 6085 * 6086 * +---------------+ 6087 * | PHY block |<<---------------------------------------------+ 6088 * | | | 6089 * | +-------+ | +-----+ | 6090 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ 6091 * clk | +-------+ | +-----+ 6092 * +---------------+ 6093 */ 6094 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) 6095 { 6096 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 6097 struct clk_init_data init = { }; 6098 char name[64]; 6099 6100 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); 6101 6102 init.name = name; 6103 init.ops = &clk_fixed_rate_ops; 6104 6105 fixed->fixed_rate = qmp->cfg->aux_clock_rate; 6106 fixed->hw.init = &init; 6107 6108 return devm_clk_hw_register(qmp->dev, &fixed->hw); 6109 } 6110 6111 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) 6112 { 6113 struct qmp_pcie *qmp = data; 6114 6115 /* Support legacy bindings */ 6116 if (!clkspec->args_count) 6117 return &qmp->pipe_clk_fixed.hw; 6118 6119 switch (clkspec->args[0]) { 6120 case QMP_PCIE_PIPE_CLK: 6121 return &qmp->pipe_clk_fixed.hw; 6122 case QMP_PCIE_PHY_AUX_CLK: 6123 return &qmp->aux_clk_fixed.hw; 6124 } 6125 6126 return ERR_PTR(-EINVAL); 6127 } 6128 6129 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) 6130 { 6131 int ret; 6132 6133 ret = phy_pipe_clk_register(qmp, np); 6134 if (ret) 6135 return ret; 6136 6137 if (qmp->cfg->aux_clock_rate) { 6138 ret = phy_aux_clk_register(qmp, np); 6139 if (ret) 6140 return ret; 6141 6142 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp); 6143 if (ret) 6144 return ret; 6145 } else { 6146 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); 6147 if (ret) 6148 return ret; 6149 } 6150 6151 /* 6152 * Roll a devm action because the clock provider is the child node, but 6153 * the child node is not actually a device. 6154 */ 6155 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 6156 } 6157 6158 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 6159 { 6160 struct platform_device *pdev = to_platform_device(qmp->dev); 6161 const struct qmp_phy_cfg *cfg = qmp->cfg; 6162 struct device *dev = qmp->dev; 6163 struct clk *clk; 6164 6165 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 6166 if (IS_ERR(qmp->serdes)) 6167 return PTR_ERR(qmp->serdes); 6168 6169 /* 6170 * Get memory resources for the PHY: 6171 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 6172 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 6173 * For single lane PHYs: pcs_misc (optional) -> 3. 6174 */ 6175 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 6176 if (IS_ERR(qmp->tx)) 6177 return PTR_ERR(qmp->tx); 6178 6179 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 6180 qmp->rx = qmp->tx; 6181 else 6182 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 6183 if (IS_ERR(qmp->rx)) 6184 return PTR_ERR(qmp->rx); 6185 6186 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 6187 if (IS_ERR(qmp->pcs)) 6188 return PTR_ERR(qmp->pcs); 6189 6190 if (cfg->lanes >= 2) { 6191 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 6192 if (IS_ERR(qmp->tx2)) 6193 return PTR_ERR(qmp->tx2); 6194 6195 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 6196 if (IS_ERR(qmp->rx2)) 6197 return PTR_ERR(qmp->rx2); 6198 6199 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 6200 } else { 6201 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 6202 } 6203 6204 if (IS_ERR(qmp->pcs_misc) && 6205 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 6206 qmp->pcs_misc = qmp->pcs + 0x400; 6207 6208 if (IS_ERR(qmp->pcs_misc)) { 6209 if (cfg->tbls.pcs_misc || 6210 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 6211 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 6212 return PTR_ERR(qmp->pcs_misc); 6213 } 6214 } 6215 6216 /* 6217 * For all platforms where legacy bindings existed, PCS_LANE1 was 6218 * mapped as a part of the PCS_MISC region. 6219 */ 6220 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) 6221 qmp->pcs_lane1 = qmp->pcs_misc + 6222 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); 6223 6224 clk = devm_get_clk_from_child(dev, np, NULL); 6225 if (IS_ERR(clk)) { 6226 return dev_err_probe(dev, PTR_ERR(clk), 6227 "failed to get pipe clock\n"); 6228 } 6229 6230 qmp->num_pipe_clks = 1; 6231 qmp->pipe_clks[0].id = "pipe"; 6232 qmp->pipe_clks[0].clk = clk; 6233 6234 return 0; 6235 } 6236 6237 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 6238 { 6239 struct regmap *tcsr; 6240 unsigned int args[2]; 6241 int ret; 6242 6243 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 6244 "qcom,4ln-config-sel", 6245 ARRAY_SIZE(args), args); 6246 if (IS_ERR(tcsr)) { 6247 ret = PTR_ERR(tcsr); 6248 if (ret == -ENOENT) 6249 return 0; 6250 6251 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 6252 return ret; 6253 } 6254 6255 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 6256 if (ret < 0) { 6257 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 6258 return ret; 6259 } 6260 6261 qmp->tcsr_4ln_config = ret; 6262 6263 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 6264 6265 return 0; 6266 } 6267 6268 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 6269 { 6270 struct platform_device *pdev = to_platform_device(qmp->dev); 6271 const struct qmp_phy_cfg *cfg = qmp->cfg; 6272 const struct qmp_pcie_offsets *offs = cfg->offsets; 6273 struct device *dev = qmp->dev; 6274 void __iomem *base; 6275 int ret; 6276 6277 if (!offs) 6278 return -EINVAL; 6279 6280 ret = qmp_pcie_get_4ln_config(qmp); 6281 if (ret) 6282 return ret; 6283 6284 base = devm_platform_ioremap_resource(pdev, 0); 6285 if (IS_ERR(base)) 6286 return PTR_ERR(base); 6287 6288 qmp->serdes = base + offs->serdes; 6289 qmp->pcs = base + offs->pcs; 6290 qmp->pcs_misc = base + offs->pcs_misc; 6291 qmp->pcs_lane1 = base + offs->pcs_lane1; 6292 qmp->tx = base + offs->tx; 6293 qmp->rx = base + offs->rx; 6294 6295 if (cfg->lanes >= 2) { 6296 qmp->tx2 = base + offs->tx2; 6297 qmp->rx2 = base + offs->rx2; 6298 } 6299 6300 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 6301 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 6302 if (IS_ERR(qmp->port_b)) 6303 return PTR_ERR(qmp->port_b); 6304 } 6305 6306 qmp->txz = base + offs->txz; 6307 qmp->rxz = base + offs->rxz; 6308 6309 if (cfg->tbls.ln_shrd) 6310 qmp->ln_shrd = base + offs->ln_shrd; 6311 6312 qmp->num_pipe_clks = 2; 6313 qmp->pipe_clks[0].id = "pipe"; 6314 qmp->pipe_clks[1].id = "pipediv2"; 6315 6316 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 6317 if (ret) 6318 return ret; 6319 6320 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 6321 if (ret) 6322 return ret; 6323 6324 return 0; 6325 } 6326 6327 static int qmp_pcie_probe(struct platform_device *pdev) 6328 { 6329 struct device *dev = &pdev->dev; 6330 struct phy_provider *phy_provider; 6331 struct device_node *np; 6332 struct qmp_pcie *qmp; 6333 int ret; 6334 6335 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 6336 if (!qmp) 6337 return -ENOMEM; 6338 6339 qmp->dev = dev; 6340 6341 qmp->cfg = of_device_get_match_data(dev); 6342 if (!qmp->cfg) 6343 return -EINVAL; 6344 6345 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 6346 WARN_ON_ONCE(!qmp->cfg->phy_status); 6347 6348 ret = qmp_pcie_clk_init(qmp); 6349 if (ret) 6350 return ret; 6351 6352 ret = qmp_pcie_reset_init(qmp); 6353 if (ret) 6354 return ret; 6355 6356 ret = qmp_pcie_vreg_init(qmp); 6357 if (ret) 6358 return ret; 6359 6360 /* Check for legacy binding with child node. */ 6361 np = of_get_next_available_child(dev->of_node, NULL); 6362 if (np) { 6363 ret = qmp_pcie_parse_dt_legacy(qmp, np); 6364 } else { 6365 np = of_node_get(dev->of_node); 6366 ret = qmp_pcie_parse_dt(qmp); 6367 } 6368 if (ret) 6369 goto err_node_put; 6370 6371 ret = qmp_pcie_register_clocks(qmp, np); 6372 if (ret) 6373 goto err_node_put; 6374 6375 qmp->mode = PHY_MODE_PCIE_RC; 6376 6377 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 6378 if (IS_ERR(qmp->phy)) { 6379 ret = PTR_ERR(qmp->phy); 6380 dev_err(dev, "failed to create PHY: %d\n", ret); 6381 goto err_node_put; 6382 } 6383 6384 phy_set_drvdata(qmp->phy, qmp); 6385 6386 of_node_put(np); 6387 6388 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 6389 6390 return PTR_ERR_OR_ZERO(phy_provider); 6391 6392 err_node_put: 6393 of_node_put(np); 6394 return ret; 6395 } 6396 6397 static const struct of_device_id qmp_pcie_of_match_table[] = { 6398 { 6399 .compatible = "qcom,eliza-qmp-gen3x1-pcie-phy", 6400 .data = &eliza_qmp_gen3x1_pciephy_cfg, 6401 }, { 6402 .compatible = "qcom,eliza-qmp-gen3x2-pcie-phy", 6403 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 6404 }, { 6405 .compatible = "qcom,glymur-qmp-gen4x2-pcie-phy", 6406 .data = &glymur_qmp_gen4x2_pciephy_cfg, 6407 }, { 6408 .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", 6409 .data = &glymur_qmp_gen5x4_pciephy_cfg, 6410 }, { 6411 .compatible = "qcom,hawi-qmp-gen3x2-pcie-phy", 6412 .data = &hawi_qmp_gen3x2_pciephy_cfg, 6413 }, { 6414 .compatible = "qcom,hawi-qmp-gen4x1-pcie-phy", 6415 .data = &hawi_qmp_gen4x1_pciephy_cfg, 6416 }, { 6417 .compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy", 6418 .data = &ipq5210_gen3x1_pciephy_cfg, 6419 }, { 6420 .compatible = "qcom,ipq6018-qmp-pcie-phy", 6421 .data = &ipq6018_pciephy_cfg, 6422 }, { 6423 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 6424 .data = &ipq8074_pciephy_gen3_cfg, 6425 }, { 6426 .compatible = "qcom,ipq8074-qmp-pcie-phy", 6427 .data = &ipq8074_pciephy_cfg, 6428 }, { 6429 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", 6430 .data = &ipq9574_gen3x1_pciephy_cfg, 6431 }, { 6432 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", 6433 .data = &ipq9574_gen3x2_pciephy_cfg, 6434 }, { 6435 .compatible = "qcom,ipq9650-qmp-gen3x1-pcie-phy", 6436 .data = &ipq9650_gen3x1_pciephy_cfg, 6437 }, { 6438 .compatible = "qcom,ipq9650-qmp-gen3x2-pcie-phy", 6439 .data = &ipq9650_gen3x2_pciephy_cfg, 6440 }, { 6441 .compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy", 6442 .data = &qmp_v8_gen3x2_pciephy_cfg, 6443 }, { 6444 .compatible = "qcom,msm8998-qmp-pcie-phy", 6445 .data = &msm8998_pciephy_cfg, 6446 }, { 6447 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy", 6448 .data = &qcs615_pciephy_cfg, 6449 }, { 6450 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy", 6451 .data = &qcs8300_qmp_gen4x2_pciephy_cfg, 6452 }, { 6453 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", 6454 .data = &sa8775p_qmp_gen4x2_pciephy_cfg, 6455 }, { 6456 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", 6457 .data = &sa8775p_qmp_gen4x4_pciephy_cfg, 6458 }, { 6459 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy", 6460 .data = &sar2130p_qmp_gen3x2_pciephy_cfg, 6461 }, { 6462 .compatible = "qcom,sc8180x-qmp-pcie-phy", 6463 .data = &sc8180x_pciephy_cfg, 6464 }, { 6465 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 6466 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 6467 }, { 6468 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 6469 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 6470 }, { 6471 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 6472 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 6473 }, { 6474 .compatible = "qcom,sdm845-qhp-pcie-phy", 6475 .data = &sdm845_qhp_pciephy_cfg, 6476 }, { 6477 .compatible = "qcom,sdm845-qmp-pcie-phy", 6478 .data = &sdm845_qmp_pciephy_cfg, 6479 }, { 6480 .compatible = "qcom,sdx55-qmp-pcie-phy", 6481 .data = &sdx55_qmp_pciephy_cfg, 6482 }, { 6483 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 6484 .data = &sdx65_qmp_pciephy_cfg, 6485 }, { 6486 .compatible = "qcom,shikra-qmp-gen2x1-pcie-phy", 6487 .data = &shikra_pciephy_cfg, 6488 }, { 6489 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", 6490 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 6491 }, { 6492 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", 6493 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 6494 }, { 6495 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 6496 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 6497 }, { 6498 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 6499 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 6500 }, { 6501 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 6502 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 6503 }, { 6504 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 6505 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 6506 }, { 6507 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 6508 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 6509 }, { 6510 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 6511 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 6512 }, { 6513 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 6514 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 6515 }, { 6516 .compatible = "qcom,sm8475-qmp-gen3x1-pcie-phy", 6517 .data = &sm8475_qmp_gen3x1_pciephy_cfg, 6518 }, { 6519 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 6520 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 6521 }, { 6522 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 6523 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 6524 }, { 6525 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 6526 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 6527 }, { 6528 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 6529 .data = &sm8650_qmp_gen4x2_pciephy_cfg, 6530 }, { 6531 .compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy", 6532 .data = &sm8750_qmp_gen3x2_pciephy_cfg, 6533 }, { 6534 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", 6535 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 6536 }, { 6537 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", 6538 .data = &x1e80100_qmp_gen4x2_pciephy_cfg, 6539 }, { 6540 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", 6541 .data = &x1e80100_qmp_gen4x4_pciephy_cfg, 6542 }, { 6543 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy", 6544 .data = &x1e80100_qmp_gen4x8_pciephy_cfg, 6545 }, { 6546 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy", 6547 .data = &qmp_v6_gen4x4_pciephy_cfg, 6548 }, 6549 { }, 6550 }; 6551 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 6552 6553 static struct platform_driver qmp_pcie_driver = { 6554 .probe = qmp_pcie_probe, 6555 .driver = { 6556 .name = "qcom-qmp-pcie-phy", 6557 .of_match_table = qmp_pcie_of_match_table, 6558 }, 6559 }; 6560 6561 module_platform_driver(qmp_pcie_driver); 6562 6563 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 6564 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 6565 MODULE_LICENSE("GPL v2"); 6566