1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2024 NXP */ 3 4 #include <linux/clk.h> 5 #include <linux/module.h> 6 #include <linux/of_net.h> 7 #include <linux/of_platform.h> 8 #include <linux/unaligned.h> 9 10 #include "enetc_pf_common.h" 11 #include "enetc4_debugfs.h" 12 13 #define ENETC_SI_MAX_RING_NUM 8 14 15 #define ENETC_MAC_FILTER_TYPE_UC BIT(0) 16 #define ENETC_MAC_FILTER_TYPE_MC BIT(1) 17 #define ENETC_MAC_FILTER_TYPE_ALL (ENETC_MAC_FILTER_TYPE_UC | \ 18 ENETC_MAC_FILTER_TYPE_MC) 19 20 static void enetc4_get_port_caps(struct enetc_pf *pf) 21 { 22 struct enetc_hw *hw = &pf->si->hw; 23 u32 val; 24 25 val = enetc_port_rd(hw, ENETC4_ECAPR1); 26 pf->caps.num_vsi = (val & ECAPR1_NUM_VSI) >> 24; 27 pf->caps.num_msix = ((val & ECAPR1_NUM_MSIX) >> 12) + 1; 28 29 val = enetc_port_rd(hw, ENETC4_ECAPR2); 30 pf->caps.num_rx_bdr = (val & ECAPR2_NUM_RX_BDR) >> 16; 31 pf->caps.num_tx_bdr = val & ECAPR2_NUM_TX_BDR; 32 33 val = enetc_port_rd(hw, ENETC4_PMCAPR); 34 pf->caps.half_duplex = (val & PMCAPR_HD) ? 1 : 0; 35 36 val = enetc_port_rd(hw, ENETC4_PSIMAFCAPR); 37 pf->caps.mac_filter_num = val & PSIMAFCAPR_NUM_MAC_AFTE; 38 } 39 40 static void enetc4_get_psi_hw_features(struct enetc_si *si) 41 { 42 struct enetc_hw *hw = &si->hw; 43 u32 val; 44 45 val = enetc_port_rd(hw, ENETC4_PCAPR); 46 if (val & PCAPR_LINK_TYPE) 47 si->hw_features |= ENETC_SI_F_PPM; 48 } 49 50 static void enetc4_pf_set_si_primary_mac(struct enetc_hw *hw, int si, 51 const u8 *addr) 52 { 53 u16 lower = get_unaligned_le16(addr + 4); 54 u32 upper = get_unaligned_le32(addr); 55 56 if (si != 0) { 57 __raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si)); 58 __raw_writel(lower, hw->port + ENETC4_PSIPMAR1(si)); 59 } else { 60 __raw_writel(upper, hw->port + ENETC4_PMAR0); 61 __raw_writel(lower, hw->port + ENETC4_PMAR1); 62 } 63 } 64 65 static void enetc4_pf_get_si_primary_mac(struct enetc_hw *hw, int si, 66 u8 *addr) 67 { 68 u32 upper; 69 u16 lower; 70 71 upper = __raw_readl(hw->port + ENETC4_PSIPMAR0(si)); 72 lower = __raw_readl(hw->port + ENETC4_PSIPMAR1(si)); 73 74 put_unaligned_le32(upper, addr); 75 put_unaligned_le16(lower, addr + 4); 76 } 77 78 static void enetc4_pf_set_si_mac_promisc(struct enetc_hw *hw, int si, 79 bool uc_promisc, bool mc_promisc) 80 { 81 u32 val = enetc_port_rd(hw, ENETC4_PSIPMMR); 82 83 if (uc_promisc) 84 val |= PSIPMMR_SI_MAC_UP(si); 85 else 86 val &= ~PSIPMMR_SI_MAC_UP(si); 87 88 if (mc_promisc) 89 val |= PSIPMMR_SI_MAC_MP(si); 90 else 91 val &= ~PSIPMMR_SI_MAC_MP(si); 92 93 enetc_port_wr(hw, ENETC4_PSIPMMR, val); 94 } 95 96 static void enetc4_pf_set_si_uc_hash_filter(struct enetc_hw *hw, int si, 97 u64 hash) 98 { 99 enetc_port_wr(hw, ENETC4_PSIUMHFR0(si), lower_32_bits(hash)); 100 enetc_port_wr(hw, ENETC4_PSIUMHFR1(si), upper_32_bits(hash)); 101 } 102 103 static void enetc4_pf_set_si_mc_hash_filter(struct enetc_hw *hw, int si, 104 u64 hash) 105 { 106 enetc_port_wr(hw, ENETC4_PSIMMHFR0(si), lower_32_bits(hash)); 107 enetc_port_wr(hw, ENETC4_PSIMMHFR1(si), upper_32_bits(hash)); 108 } 109 110 static void enetc4_pf_set_loopback(struct net_device *ndev, bool en) 111 { 112 struct enetc_ndev_priv *priv = netdev_priv(ndev); 113 struct enetc_si *si = priv->si; 114 u32 val; 115 116 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 117 val = u32_replace_bits(val, en ? 1 : 0, PM_CMD_CFG_LOOP_EN); 118 /* Default to select MAC level loopback mode if loopback is enabled. */ 119 val = u32_replace_bits(val, en ? LPBCK_MODE_MAC_LEVEL : 0, 120 PM_CMD_CFG_LPBK_MODE); 121 122 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 123 } 124 125 static void enetc4_pf_clear_maft_entries(struct enetc_pf *pf) 126 { 127 int i; 128 129 for (i = 0; i < pf->num_mfe; i++) 130 ntmp_maft_delete_entry(&pf->si->ntmp_user, i); 131 132 pf->num_mfe = 0; 133 } 134 135 static int enetc4_pf_add_maft_entries(struct enetc_pf *pf, 136 struct enetc_mac_addr *mac, 137 int mac_cnt) 138 { 139 struct maft_entry_data maft = {}; 140 u16 si_bit = BIT(0); 141 int i, err; 142 143 maft.cfge.si_bitmap = cpu_to_le16(si_bit); 144 for (i = 0; i < mac_cnt; i++) { 145 ether_addr_copy(maft.keye.mac_addr, mac[i].addr); 146 err = ntmp_maft_add_entry(&pf->si->ntmp_user, i, &maft); 147 if (unlikely(err)) { 148 pf->num_mfe = i; 149 goto clear_maft_entries; 150 } 151 } 152 153 pf->num_mfe = mac_cnt; 154 155 return 0; 156 157 clear_maft_entries: 158 enetc4_pf_clear_maft_entries(pf); 159 160 return err; 161 } 162 163 static int enetc4_pf_set_uc_exact_filter(struct enetc_pf *pf) 164 { 165 int max_num_mfe = pf->caps.mac_filter_num; 166 struct enetc_mac_filter mac_filter = {}; 167 struct net_device *ndev = pf->si->ndev; 168 struct enetc_hw *hw = &pf->si->hw; 169 struct enetc_mac_addr *mac_tbl; 170 struct netdev_hw_addr *ha; 171 int i = 0, err; 172 int mac_cnt; 173 174 netif_addr_lock_bh(ndev); 175 176 mac_cnt = netdev_uc_count(ndev); 177 if (!mac_cnt) { 178 netif_addr_unlock_bh(ndev); 179 /* clear both MAC hash and exact filters */ 180 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 181 enetc4_pf_clear_maft_entries(pf); 182 183 return 0; 184 } 185 186 if (mac_cnt > max_num_mfe) { 187 err = -ENOSPC; 188 goto unlock_netif_addr; 189 } 190 191 mac_tbl = kzalloc_objs(*mac_tbl, mac_cnt, GFP_ATOMIC); 192 if (!mac_tbl) { 193 err = -ENOMEM; 194 goto unlock_netif_addr; 195 } 196 197 netdev_for_each_uc_addr(ha, ndev) { 198 enetc_add_mac_addr_ht_filter(&mac_filter, ha->addr); 199 ether_addr_copy(mac_tbl[i++].addr, ha->addr); 200 } 201 202 netif_addr_unlock_bh(ndev); 203 204 /* Set temporary unicast hash filters in case of Rx loss when 205 * updating MAC address filter table 206 */ 207 enetc4_pf_set_si_uc_hash_filter(hw, 0, *mac_filter.mac_hash_table); 208 enetc4_pf_clear_maft_entries(pf); 209 210 if (!enetc4_pf_add_maft_entries(pf, mac_tbl, i)) 211 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 212 213 kfree(mac_tbl); 214 215 return 0; 216 217 unlock_netif_addr: 218 netif_addr_unlock_bh(ndev); 219 220 return err; 221 } 222 223 static void enetc4_pf_set_mac_hash_filter(struct enetc_pf *pf, int type) 224 { 225 struct net_device *ndev = pf->si->ndev; 226 struct enetc_mac_filter *mac_filter; 227 struct enetc_hw *hw = &pf->si->hw; 228 struct netdev_hw_addr *ha; 229 230 netif_addr_lock_bh(ndev); 231 if (type & ENETC_MAC_FILTER_TYPE_UC) { 232 mac_filter = &pf->mac_filter[UC]; 233 enetc_reset_mac_addr_filter(mac_filter); 234 netdev_for_each_uc_addr(ha, ndev) 235 enetc_add_mac_addr_ht_filter(mac_filter, ha->addr); 236 237 enetc4_pf_set_si_uc_hash_filter(hw, 0, 238 *mac_filter->mac_hash_table); 239 } 240 241 if (type & ENETC_MAC_FILTER_TYPE_MC) { 242 mac_filter = &pf->mac_filter[MC]; 243 enetc_reset_mac_addr_filter(mac_filter); 244 netdev_for_each_mc_addr(ha, ndev) 245 enetc_add_mac_addr_ht_filter(mac_filter, ha->addr); 246 247 enetc4_pf_set_si_mc_hash_filter(hw, 0, 248 *mac_filter->mac_hash_table); 249 } 250 netif_addr_unlock_bh(ndev); 251 } 252 253 static void enetc4_pf_set_mac_filter(struct enetc_pf *pf, int type) 254 { 255 /* Currently, the MAC address filter table (MAFT) only has 4 entries, 256 * and multiple multicast addresses for filtering will be configured 257 * in the default network configuration, so MAFT is only suitable for 258 * unicast filtering. If the number of unicast addresses exceeds the 259 * table capacity, the MAC hash filter will be used. 260 */ 261 if (type & ENETC_MAC_FILTER_TYPE_UC && enetc4_pf_set_uc_exact_filter(pf)) { 262 /* Fall back to the MAC hash filter */ 263 enetc4_pf_set_mac_hash_filter(pf, ENETC_MAC_FILTER_TYPE_UC); 264 /* Clear the old MAC exact filter */ 265 enetc4_pf_clear_maft_entries(pf); 266 } 267 268 if (type & ENETC_MAC_FILTER_TYPE_MC) 269 enetc4_pf_set_mac_hash_filter(pf, ENETC_MAC_FILTER_TYPE_MC); 270 } 271 272 static const struct enetc_pf_ops enetc4_pf_ops = { 273 .set_si_primary_mac = enetc4_pf_set_si_primary_mac, 274 .get_si_primary_mac = enetc4_pf_get_si_primary_mac, 275 }; 276 277 static int enetc4_pf_struct_init(struct enetc_si *si) 278 { 279 struct enetc_pf *pf = enetc_si_priv(si); 280 281 pf->si = si; 282 pf->total_vfs = pci_sriov_get_totalvfs(si->pdev); 283 pf->ops = &enetc4_pf_ops; 284 285 enetc4_get_port_caps(pf); 286 enetc4_get_psi_hw_features(si); 287 288 return 0; 289 } 290 291 static u32 enetc4_psicfgr0_val_construct(bool is_vf, u32 num_tx_bdr, u32 num_rx_bdr) 292 { 293 u32 val; 294 295 val = ENETC_PSICFGR0_SET_TXBDR(num_tx_bdr); 296 val |= ENETC_PSICFGR0_SET_RXBDR(num_rx_bdr); 297 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 298 299 if (is_vf) 300 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 301 302 return val; 303 } 304 305 static void enetc4_default_rings_allocation(struct enetc_pf *pf) 306 { 307 struct enetc_hw *hw = &pf->si->hw; 308 u32 num_rx_bdr, num_tx_bdr, val; 309 u32 vf_tx_bdr, vf_rx_bdr; 310 int i, rx_rem, tx_rem; 311 312 if (pf->caps.num_rx_bdr < ENETC_SI_MAX_RING_NUM + pf->caps.num_vsi) 313 num_rx_bdr = pf->caps.num_rx_bdr - pf->caps.num_vsi; 314 else 315 num_rx_bdr = ENETC_SI_MAX_RING_NUM; 316 317 if (pf->caps.num_tx_bdr < ENETC_SI_MAX_RING_NUM + pf->caps.num_vsi) 318 num_tx_bdr = pf->caps.num_tx_bdr - pf->caps.num_vsi; 319 else 320 num_tx_bdr = ENETC_SI_MAX_RING_NUM; 321 322 val = enetc4_psicfgr0_val_construct(false, num_tx_bdr, num_rx_bdr); 323 enetc_port_wr(hw, ENETC4_PSICFGR0(0), val); 324 325 if (!pf->caps.num_vsi) 326 return; 327 328 num_rx_bdr = pf->caps.num_rx_bdr - num_rx_bdr; 329 rx_rem = num_rx_bdr % pf->caps.num_vsi; 330 num_rx_bdr = num_rx_bdr / pf->caps.num_vsi; 331 332 num_tx_bdr = pf->caps.num_tx_bdr - num_tx_bdr; 333 tx_rem = num_tx_bdr % pf->caps.num_vsi; 334 num_tx_bdr = num_tx_bdr / pf->caps.num_vsi; 335 336 for (i = 0; i < pf->caps.num_vsi; i++) { 337 vf_tx_bdr = (i < tx_rem) ? num_tx_bdr + 1 : num_tx_bdr; 338 vf_rx_bdr = (i < rx_rem) ? num_rx_bdr + 1 : num_rx_bdr; 339 val = enetc4_psicfgr0_val_construct(true, vf_tx_bdr, vf_rx_bdr); 340 enetc_port_wr(hw, ENETC4_PSICFGR0(i + 1), val); 341 } 342 } 343 344 static void enetc4_allocate_si_rings(struct enetc_pf *pf) 345 { 346 enetc4_default_rings_allocation(pf); 347 } 348 349 static void enetc4_pf_set_si_vlan_promisc(struct enetc_hw *hw, int si, bool en) 350 { 351 u32 val = enetc_port_rd(hw, ENETC4_PSIPVMR); 352 353 if (en) 354 val |= BIT(si); 355 else 356 val &= ~BIT(si); 357 358 enetc_port_wr(hw, ENETC4_PSIPVMR, val); 359 } 360 361 static void enetc4_set_default_si_vlan_promisc(struct enetc_pf *pf) 362 { 363 struct enetc_hw *hw = &pf->si->hw; 364 int num_si = pf->caps.num_vsi + 1; 365 int i; 366 367 /* enforce VLAN promiscuous mode for all SIs */ 368 for (i = 0; i < num_si; i++) 369 enetc4_pf_set_si_vlan_promisc(hw, i, true); 370 } 371 372 /* Allocate the number of MSI-X vectors for per SI. */ 373 static void enetc4_set_si_msix_num(struct enetc_pf *pf) 374 { 375 struct enetc_hw *hw = &pf->si->hw; 376 int i, num_msix, total_si; 377 u32 val; 378 379 total_si = pf->caps.num_vsi + 1; 380 381 num_msix = pf->caps.num_msix / total_si + 382 pf->caps.num_msix % total_si - 1; 383 val = num_msix & PSICFGR2_NUM_MSIX; 384 enetc_port_wr(hw, ENETC4_PSICFGR2(0), val); 385 386 num_msix = pf->caps.num_msix / total_si - 1; 387 val = num_msix & PSICFGR2_NUM_MSIX; 388 for (i = 0; i < pf->caps.num_vsi; i++) 389 enetc_port_wr(hw, ENETC4_PSICFGR2(i + 1), val); 390 } 391 392 static void enetc4_enable_all_si(struct enetc_pf *pf) 393 { 394 struct enetc_hw *hw = &pf->si->hw; 395 int num_si = pf->caps.num_vsi + 1; 396 u32 si_bitmap = 0; 397 int i; 398 399 /* Master enable for all SIs */ 400 for (i = 0; i < num_si; i++) 401 si_bitmap |= PMR_SI_EN(i); 402 403 enetc_port_wr(hw, ENETC4_PMR, si_bitmap); 404 } 405 406 static void enetc4_configure_port_si(struct enetc_pf *pf) 407 { 408 struct enetc_hw *hw = &pf->si->hw; 409 410 enetc4_allocate_si_rings(pf); 411 412 /* Outer VLAN tag will be used for VLAN filtering */ 413 enetc_port_wr(hw, ENETC4_PSIVLANFMR, PSIVLANFMR_VS); 414 415 enetc4_set_default_si_vlan_promisc(pf); 416 417 /* Disable SI MAC multicast & unicast promiscuous */ 418 enetc_port_wr(hw, ENETC4_PSIPMMR, 0); 419 420 enetc4_set_si_msix_num(pf); 421 422 enetc4_enable_all_si(pf); 423 } 424 425 static void enetc4_pf_reset_tc_msdu(struct enetc_hw *hw) 426 { 427 u32 val = ENETC_MAC_MAXFRM_SIZE; 428 int tc; 429 430 val = u32_replace_bits(val, SDU_TYPE_MPDU, PTCTMSDUR_SDU_TYPE); 431 432 for (tc = 0; tc < ENETC_NUM_TC; tc++) 433 enetc_port_wr(hw, ENETC4_PTCTMSDUR(tc), val); 434 } 435 436 static void enetc4_set_trx_frame_size(struct enetc_pf *pf) 437 { 438 struct enetc_si *si = pf->si; 439 440 enetc_port_mac_wr(si, ENETC4_PM_MAXFRM(0), 441 ENETC_SET_MAXFRM(ENETC_MAC_MAXFRM_SIZE)); 442 443 enetc4_pf_reset_tc_msdu(&si->hw); 444 } 445 446 static void enetc4_configure_port(struct enetc_pf *pf) 447 { 448 enetc4_configure_port_si(pf); 449 enetc4_set_trx_frame_size(pf); 450 enetc_set_default_rss_key(pf); 451 } 452 453 static int enetc4_init_ntmp_user(struct enetc_si *si) 454 { 455 struct ntmp_user *user = &si->ntmp_user; 456 457 /* For ENETC 4.1, all table versions are 0 */ 458 memset(&user->tbl, 0, sizeof(user->tbl)); 459 460 return enetc4_setup_cbdr(si); 461 } 462 463 static void enetc4_free_ntmp_user(struct enetc_si *si) 464 { 465 enetc4_teardown_cbdr(si); 466 } 467 468 static int enetc4_pf_init(struct enetc_pf *pf) 469 { 470 struct device *dev = &pf->si->pdev->dev; 471 int err; 472 473 /* Initialize the MAC address for PF and VFs */ 474 err = enetc_setup_mac_addresses(dev->of_node, pf); 475 if (err) { 476 dev_err(dev, "Failed to set MAC addresses\n"); 477 return err; 478 } 479 480 err = enetc4_init_ntmp_user(pf->si); 481 if (err) { 482 dev_err(dev, "Failed to init CBDR\n"); 483 return err; 484 } 485 486 enetc4_configure_port(pf); 487 488 return 0; 489 } 490 491 static void enetc4_pf_free(struct enetc_pf *pf) 492 { 493 enetc4_free_ntmp_user(pf->si); 494 } 495 496 static void enetc4_psi_do_set_rx_mode(struct work_struct *work) 497 { 498 struct enetc_si *si = container_of(work, struct enetc_si, rx_mode_task); 499 struct enetc_pf *pf = enetc_si_priv(si); 500 struct net_device *ndev = si->ndev; 501 struct enetc_hw *hw = &si->hw; 502 bool uc_promisc = false; 503 bool mc_promisc = false; 504 int type = 0; 505 506 rtnl_lock(); 507 508 if (ndev->flags & IFF_PROMISC) { 509 uc_promisc = true; 510 mc_promisc = true; 511 } else if (ndev->flags & IFF_ALLMULTI) { 512 mc_promisc = true; 513 type = ENETC_MAC_FILTER_TYPE_UC; 514 } else { 515 type = ENETC_MAC_FILTER_TYPE_ALL; 516 } 517 518 enetc4_pf_set_si_mac_promisc(hw, 0, uc_promisc, mc_promisc); 519 520 if (uc_promisc) { 521 enetc4_pf_set_si_uc_hash_filter(hw, 0, 0); 522 enetc4_pf_clear_maft_entries(pf); 523 } 524 525 if (mc_promisc) 526 enetc4_pf_set_si_mc_hash_filter(hw, 0, 0); 527 528 /* Set new MAC filter */ 529 enetc4_pf_set_mac_filter(pf, type); 530 531 rtnl_unlock(); 532 } 533 534 static void enetc4_pf_set_rx_mode(struct net_device *ndev) 535 { 536 struct enetc_ndev_priv *priv = netdev_priv(ndev); 537 struct enetc_si *si = priv->si; 538 539 queue_work(si->workqueue, &si->rx_mode_task); 540 } 541 542 static int enetc4_pf_set_features(struct net_device *ndev, 543 netdev_features_t features) 544 { 545 netdev_features_t changed = ndev->features ^ features; 546 struct enetc_ndev_priv *priv = netdev_priv(ndev); 547 struct enetc_hw *hw = &priv->si->hw; 548 549 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 550 bool promisc_en = !(features & NETIF_F_HW_VLAN_CTAG_FILTER); 551 552 enetc4_pf_set_si_vlan_promisc(hw, 0, promisc_en); 553 } 554 555 if (changed & NETIF_F_LOOPBACK) 556 enetc4_pf_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 557 558 enetc_set_features(ndev, features); 559 560 return 0; 561 } 562 563 static const struct net_device_ops enetc4_ndev_ops = { 564 .ndo_open = enetc_open, 565 .ndo_stop = enetc_close, 566 .ndo_start_xmit = enetc_xmit, 567 .ndo_get_stats = enetc_get_stats, 568 .ndo_set_mac_address = enetc_pf_set_mac_addr, 569 .ndo_set_rx_mode = enetc4_pf_set_rx_mode, 570 .ndo_set_features = enetc4_pf_set_features, 571 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 572 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 573 .ndo_eth_ioctl = enetc_ioctl, 574 .ndo_hwtstamp_get = enetc_hwtstamp_get, 575 .ndo_hwtstamp_set = enetc_hwtstamp_set, 576 }; 577 578 static struct phylink_pcs * 579 enetc4_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 580 { 581 struct enetc_pf *pf = phylink_to_enetc_pf(config); 582 583 return pf->pcs; 584 } 585 586 static void enetc4_mac_config(struct enetc_pf *pf, unsigned int mode, 587 phy_interface_t phy_mode) 588 { 589 struct enetc_ndev_priv *priv = netdev_priv(pf->si->ndev); 590 struct enetc_si *si = pf->si; 591 u32 val; 592 593 if (enetc_is_pseudo_mac(si)) 594 return; 595 596 val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 597 val &= ~(PM_IF_MODE_IFMODE | PM_IF_MODE_ENA); 598 599 switch (phy_mode) { 600 case PHY_INTERFACE_MODE_RGMII: 601 case PHY_INTERFACE_MODE_RGMII_ID: 602 case PHY_INTERFACE_MODE_RGMII_RXID: 603 case PHY_INTERFACE_MODE_RGMII_TXID: 604 val |= IFMODE_RGMII; 605 /* We need to enable auto-negotiation for the MAC 606 * if its RGMII interface support In-Band status. 607 */ 608 if (phylink_autoneg_inband(mode)) 609 val |= PM_IF_MODE_ENA; 610 break; 611 case PHY_INTERFACE_MODE_RMII: 612 val |= IFMODE_RMII; 613 break; 614 case PHY_INTERFACE_MODE_SGMII: 615 case PHY_INTERFACE_MODE_2500BASEX: 616 val |= IFMODE_SGMII; 617 break; 618 case PHY_INTERFACE_MODE_10GBASER: 619 case PHY_INTERFACE_MODE_XGMII: 620 case PHY_INTERFACE_MODE_USXGMII: 621 val |= IFMODE_XGMII; 622 break; 623 default: 624 dev_err(priv->dev, 625 "Unsupported PHY mode:%d\n", phy_mode); 626 return; 627 } 628 629 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 630 } 631 632 static void enetc4_pl_mac_config(struct phylink_config *config, unsigned int mode, 633 const struct phylink_link_state *state) 634 { 635 struct enetc_pf *pf = phylink_to_enetc_pf(config); 636 637 enetc4_mac_config(pf, mode, state->interface); 638 } 639 640 static void enetc4_set_port_speed(struct enetc_ndev_priv *priv, int speed) 641 { 642 u32 old_speed = priv->speed; 643 u32 val; 644 645 if (speed == old_speed) 646 return; 647 648 val = enetc_port_rd(&priv->si->hw, ENETC4_PCR); 649 val &= ~PCR_PSPEED; 650 651 switch (speed) { 652 case SPEED_100: 653 case SPEED_1000: 654 case SPEED_2500: 655 case SPEED_10000: 656 val |= (PCR_PSPEED & PCR_PSPEED_VAL(speed)); 657 break; 658 case SPEED_10: 659 default: 660 val |= (PCR_PSPEED & PCR_PSPEED_VAL(SPEED_10)); 661 } 662 663 priv->speed = speed; 664 enetc_port_wr(&priv->si->hw, ENETC4_PCR, val); 665 } 666 667 static void enetc4_set_rgmii_mac(struct enetc_pf *pf, int speed, int duplex) 668 { 669 struct enetc_si *si = pf->si; 670 u32 old_val, val; 671 672 old_val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 673 val = old_val & ~(PM_IF_MODE_ENA | PM_IF_MODE_M10 | PM_IF_MODE_REVMII); 674 675 switch (speed) { 676 case SPEED_1000: 677 val = u32_replace_bits(val, SSP_1G, PM_IF_MODE_SSP); 678 break; 679 case SPEED_100: 680 val = u32_replace_bits(val, SSP_100M, PM_IF_MODE_SSP); 681 break; 682 case SPEED_10: 683 val = u32_replace_bits(val, SSP_10M, PM_IF_MODE_SSP); 684 } 685 686 val = u32_replace_bits(val, duplex == DUPLEX_FULL ? 0 : 1, 687 PM_IF_MODE_HD); 688 689 if (val == old_val) 690 return; 691 692 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 693 } 694 695 static void enetc4_set_rmii_mac(struct enetc_pf *pf, int speed, int duplex) 696 { 697 struct enetc_si *si = pf->si; 698 u32 old_val, val; 699 700 old_val = enetc_port_mac_rd(si, ENETC4_PM_IF_MODE(0)); 701 val = old_val & ~(PM_IF_MODE_ENA | PM_IF_MODE_SSP); 702 703 switch (speed) { 704 case SPEED_100: 705 val &= ~PM_IF_MODE_M10; 706 break; 707 case SPEED_10: 708 val |= PM_IF_MODE_M10; 709 } 710 711 val = u32_replace_bits(val, duplex == DUPLEX_FULL ? 0 : 1, 712 PM_IF_MODE_HD); 713 714 if (val == old_val) 715 return; 716 717 enetc_port_mac_wr(si, ENETC4_PM_IF_MODE(0), val); 718 } 719 720 static void enetc4_set_hd_flow_control(struct enetc_pf *pf, bool enable) 721 { 722 struct enetc_si *si = pf->si; 723 u32 old_val, val; 724 725 if (!pf->caps.half_duplex) 726 return; 727 728 old_val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 729 val = u32_replace_bits(old_val, enable ? 1 : 0, PM_CMD_CFG_HD_FCEN); 730 if (val == old_val) 731 return; 732 733 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 734 } 735 736 static void enetc4_set_rx_pause(struct enetc_pf *pf, bool rx_pause) 737 { 738 struct enetc_si *si = pf->si; 739 u32 old_val, val; 740 741 old_val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 742 val = u32_replace_bits(old_val, rx_pause ? 0 : 1, PM_CMD_CFG_PAUSE_IGN); 743 if (val == old_val) 744 return; 745 746 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 747 } 748 749 static void enetc4_set_tx_pause(struct enetc_pf *pf, int num_rxbdr, bool tx_pause) 750 { 751 u32 pause_off_thresh = 0, pause_on_thresh = 0; 752 u32 init_quanta = 0, refresh_quanta = 0; 753 struct enetc_hw *hw = &pf->si->hw; 754 u32 rbmr, old_rbmr; 755 int i; 756 757 for (i = 0; i < num_rxbdr; i++) { 758 old_rbmr = enetc_rxbdr_rd(hw, i, ENETC_RBMR); 759 rbmr = u32_replace_bits(old_rbmr, tx_pause ? 1 : 0, ENETC_RBMR_CM); 760 if (rbmr == old_rbmr) 761 continue; 762 763 enetc_rxbdr_wr(hw, i, ENETC_RBMR, rbmr); 764 } 765 766 if (tx_pause) { 767 /* When the port first enters congestion, send a PAUSE request 768 * with the maximum number of quanta. When the port exits 769 * congestion, it will automatically send a PAUSE frame with 770 * zero quanta. 771 */ 772 init_quanta = 0xffff; 773 774 /* Also, set up the refresh timer to send follow-up PAUSE 775 * frames at half the quanta value, in case the congestion 776 * condition persists. 777 */ 778 refresh_quanta = 0xffff / 2; 779 780 /* Start emitting PAUSE frames when 3 large frames (or more 781 * smaller frames) have accumulated in the FIFO waiting to be 782 * DMAed to the RX ring. 783 */ 784 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 785 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 786 } 787 788 enetc_port_mac_wr(pf->si, ENETC4_PM_PAUSE_QUANTA(0), init_quanta); 789 enetc_port_mac_wr(pf->si, ENETC4_PM_PAUSE_THRESH(0), refresh_quanta); 790 enetc_port_wr(hw, ENETC4_PPAUONTR, pause_on_thresh); 791 enetc_port_wr(hw, ENETC4_PPAUOFFTR, pause_off_thresh); 792 } 793 794 static void enetc4_mac_wait_tx_empty(struct enetc_si *si, int mac) 795 { 796 u32 val; 797 798 if (read_poll_timeout(enetc_port_rd, val, 799 val & PM_IEVENT_TX_EMPTY, 800 100, 10000, false, &si->hw, 801 ENETC4_PM_IEVENT(mac))) 802 dev_warn(&si->pdev->dev, 803 "MAC %d TX is not empty\n", mac); 804 } 805 806 static void enetc4_mac_tx_graceful_stop(struct enetc_pf *pf) 807 { 808 struct enetc_hw *hw = &pf->si->hw; 809 struct enetc_si *si = pf->si; 810 u32 val; 811 812 val = enetc_port_rd(hw, ENETC4_POR); 813 val |= POR_TXDIS; 814 enetc_port_wr(hw, ENETC4_POR, val); 815 816 if (enetc_is_pseudo_mac(si)) 817 return; 818 819 enetc4_mac_wait_tx_empty(si, 0); 820 if (si->hw_features & ENETC_SI_F_QBU) 821 enetc4_mac_wait_tx_empty(si, 1); 822 823 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 824 val &= ~PM_CMD_CFG_TX_EN; 825 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 826 } 827 828 static void enetc4_mac_tx_enable(struct enetc_pf *pf) 829 { 830 struct enetc_hw *hw = &pf->si->hw; 831 struct enetc_si *si = pf->si; 832 u32 val; 833 834 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 835 val |= PM_CMD_CFG_TX_EN; 836 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 837 838 val = enetc_port_rd(hw, ENETC4_POR); 839 val &= ~POR_TXDIS; 840 enetc_port_wr(hw, ENETC4_POR, val); 841 } 842 843 static void enetc4_mac_wait_rx_empty(struct enetc_si *si, int mac) 844 { 845 u32 val; 846 847 if (read_poll_timeout(enetc_port_rd, val, 848 val & PM_IEVENT_RX_EMPTY, 849 100, 10000, false, &si->hw, 850 ENETC4_PM_IEVENT(mac))) 851 dev_warn(&si->pdev->dev, 852 "MAC %d RX is not empty\n", mac); 853 } 854 855 static void enetc4_mac_rx_graceful_stop(struct enetc_pf *pf) 856 { 857 struct enetc_hw *hw = &pf->si->hw; 858 struct enetc_si *si = pf->si; 859 u32 val; 860 861 if (enetc_is_pseudo_mac(si)) 862 goto check_rx_busy; 863 864 if (si->hw_features & ENETC_SI_F_QBU) { 865 val = enetc_port_rd(hw, ENETC4_PM_CMD_CFG(1)); 866 val &= ~PM_CMD_CFG_RX_EN; 867 enetc_port_wr(hw, ENETC4_PM_CMD_CFG(1), val); 868 enetc4_mac_wait_rx_empty(si, 1); 869 } 870 871 val = enetc_port_rd(hw, ENETC4_PM_CMD_CFG(0)); 872 val &= ~PM_CMD_CFG_RX_EN; 873 enetc_port_wr(hw, ENETC4_PM_CMD_CFG(0), val); 874 enetc4_mac_wait_rx_empty(si, 0); 875 876 check_rx_busy: 877 if (read_poll_timeout(enetc_port_rd, val, 878 !(val & PSR_RX_BUSY), 879 100, 10000, false, hw, 880 ENETC4_PSR)) 881 dev_warn(&si->pdev->dev, "Port RX busy\n"); 882 883 val = enetc_port_rd(hw, ENETC4_POR); 884 val |= POR_RXDIS; 885 enetc_port_wr(hw, ENETC4_POR, val); 886 } 887 888 static void enetc4_mac_rx_enable(struct enetc_pf *pf) 889 { 890 struct enetc_hw *hw = &pf->si->hw; 891 struct enetc_si *si = pf->si; 892 u32 val; 893 894 val = enetc_port_rd(hw, ENETC4_POR); 895 val &= ~POR_RXDIS; 896 enetc_port_wr(hw, ENETC4_POR, val); 897 898 val = enetc_port_mac_rd(si, ENETC4_PM_CMD_CFG(0)); 899 val |= PM_CMD_CFG_RX_EN; 900 enetc_port_mac_wr(si, ENETC4_PM_CMD_CFG(0), val); 901 } 902 903 static void enetc4_pl_mac_link_up(struct phylink_config *config, 904 struct phy_device *phy, unsigned int mode, 905 phy_interface_t interface, int speed, 906 int duplex, bool tx_pause, bool rx_pause) 907 { 908 struct enetc_pf *pf = phylink_to_enetc_pf(config); 909 struct enetc_si *si = pf->si; 910 struct enetc_ndev_priv *priv; 911 bool hd_fc = false; 912 913 priv = netdev_priv(si->ndev); 914 enetc4_set_port_speed(priv, speed); 915 916 if (!phylink_autoneg_inband(mode) && 917 phy_interface_mode_is_rgmii(interface)) 918 enetc4_set_rgmii_mac(pf, speed, duplex); 919 920 if (interface == PHY_INTERFACE_MODE_RMII) 921 enetc4_set_rmii_mac(pf, speed, duplex); 922 923 if (duplex == DUPLEX_FULL) { 924 /* When preemption is enabled, generation of PAUSE frames 925 * must be disabled, as stated in the IEEE 802.3 standard. 926 */ 927 if (priv->active_offloads & ENETC_F_QBU) 928 tx_pause = false; 929 } else { /* DUPLEX_HALF */ 930 if (tx_pause || rx_pause) 931 hd_fc = true; 932 933 /* As per 802.3 annex 31B, PAUSE frames are only supported 934 * when the link is configured for full duplex operation. 935 */ 936 tx_pause = false; 937 rx_pause = false; 938 } 939 940 enetc4_set_hd_flow_control(pf, hd_fc); 941 enetc4_set_tx_pause(pf, priv->num_rx_rings, tx_pause); 942 enetc4_set_rx_pause(pf, rx_pause); 943 enetc4_mac_tx_enable(pf); 944 enetc4_mac_rx_enable(pf); 945 } 946 947 static void enetc4_pl_mac_link_down(struct phylink_config *config, 948 unsigned int mode, 949 phy_interface_t interface) 950 { 951 struct enetc_pf *pf = phylink_to_enetc_pf(config); 952 953 enetc4_mac_rx_graceful_stop(pf); 954 enetc4_mac_tx_graceful_stop(pf); 955 } 956 957 static const struct phylink_mac_ops enetc_pl_mac_ops = { 958 .mac_select_pcs = enetc4_pl_mac_select_pcs, 959 .mac_config = enetc4_pl_mac_config, 960 .mac_link_up = enetc4_pl_mac_link_up, 961 .mac_link_down = enetc4_pl_mac_link_down, 962 }; 963 964 static void enetc4_pci_remove(void *data) 965 { 966 struct pci_dev *pdev = data; 967 968 enetc_pci_remove(pdev); 969 } 970 971 static int enetc4_link_init(struct enetc_ndev_priv *priv, 972 struct device_node *node) 973 { 974 struct enetc_pf *pf = enetc_si_priv(priv->si); 975 struct device *dev = priv->dev; 976 int err; 977 978 err = of_get_phy_mode(node, &pf->if_mode); 979 if (err) { 980 dev_err(dev, "Failed to get PHY mode\n"); 981 return err; 982 } 983 984 err = enetc_mdiobus_create(pf, node); 985 if (err) { 986 dev_err(dev, "Failed to create MDIO bus\n"); 987 return err; 988 } 989 990 err = enetc_phylink_create(priv, node, &enetc_pl_mac_ops); 991 if (err) { 992 dev_err(dev, "Failed to create phylink\n"); 993 goto err_phylink_create; 994 } 995 996 return 0; 997 998 err_phylink_create: 999 enetc_mdiobus_destroy(pf); 1000 1001 return err; 1002 } 1003 1004 static void enetc4_link_deinit(struct enetc_ndev_priv *priv) 1005 { 1006 struct enetc_pf *pf = enetc_si_priv(priv->si); 1007 1008 enetc_phylink_destroy(priv); 1009 enetc_mdiobus_destroy(pf); 1010 } 1011 1012 static int enetc4_psi_wq_task_init(struct enetc_si *si) 1013 { 1014 char wq_name[24]; 1015 1016 INIT_WORK(&si->rx_mode_task, enetc4_psi_do_set_rx_mode); 1017 snprintf(wq_name, sizeof(wq_name), "enetc-%s", pci_name(si->pdev)); 1018 si->workqueue = create_singlethread_workqueue(wq_name); 1019 if (!si->workqueue) 1020 return -ENOMEM; 1021 1022 return 0; 1023 } 1024 1025 static int enetc4_pf_netdev_create(struct enetc_si *si) 1026 { 1027 struct device *dev = &si->pdev->dev; 1028 struct enetc_ndev_priv *priv; 1029 struct net_device *ndev; 1030 int err; 1031 1032 ndev = alloc_etherdev_mqs(sizeof(struct enetc_ndev_priv), 1033 si->num_tx_rings, si->num_rx_rings); 1034 if (!ndev) 1035 return -ENOMEM; 1036 1037 priv = netdev_priv(ndev); 1038 priv->ref_clk = devm_clk_get_optional(dev, "ref"); 1039 if (IS_ERR(priv->ref_clk)) { 1040 dev_err(dev, "Get reference clock failed\n"); 1041 err = PTR_ERR(priv->ref_clk); 1042 goto err_clk_get; 1043 } 1044 1045 enetc_pf_netdev_setup(si, ndev, &enetc4_ndev_ops); 1046 1047 enetc_init_si_rings_params(priv); 1048 1049 err = enetc_configure_si(priv); 1050 if (err) { 1051 dev_err(dev, "Failed to configure SI\n"); 1052 goto err_config_si; 1053 } 1054 1055 err = enetc_alloc_msix(priv); 1056 if (err) { 1057 dev_err(dev, "Failed to alloc MSI-X\n"); 1058 goto err_alloc_msix; 1059 } 1060 1061 err = enetc4_link_init(priv, dev->of_node); 1062 if (err) 1063 goto err_link_init; 1064 1065 err = enetc4_psi_wq_task_init(si); 1066 if (err) { 1067 dev_err(dev, "Failed to init workqueue\n"); 1068 goto err_wq_init; 1069 } 1070 1071 err = register_netdev(ndev); 1072 if (err) { 1073 dev_err(dev, "Failed to register netdev\n"); 1074 goto err_reg_netdev; 1075 } 1076 1077 return 0; 1078 1079 err_reg_netdev: 1080 destroy_workqueue(si->workqueue); 1081 err_wq_init: 1082 enetc4_link_deinit(priv); 1083 err_link_init: 1084 enetc_free_msix(priv); 1085 err_alloc_msix: 1086 err_config_si: 1087 err_clk_get: 1088 free_netdev(ndev); 1089 1090 return err; 1091 } 1092 1093 static void enetc4_pf_netdev_destroy(struct enetc_si *si) 1094 { 1095 struct enetc_ndev_priv *priv = netdev_priv(si->ndev); 1096 struct net_device *ndev = si->ndev; 1097 1098 unregister_netdev(ndev); 1099 cancel_work(&si->rx_mode_task); 1100 destroy_workqueue(si->workqueue); 1101 enetc4_link_deinit(priv); 1102 enetc_free_msix(priv); 1103 free_netdev(ndev); 1104 } 1105 1106 static const struct enetc_si_ops enetc4_psi_ops = { 1107 .get_rss_table = enetc4_get_rss_table, 1108 .set_rss_table = enetc4_set_rss_table, 1109 }; 1110 1111 static int enetc4_pf_probe(struct pci_dev *pdev, 1112 const struct pci_device_id *ent) 1113 { 1114 struct device *dev = &pdev->dev; 1115 struct enetc_si *si; 1116 struct enetc_pf *pf; 1117 int err; 1118 1119 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf)); 1120 if (err) 1121 return dev_err_probe(dev, err, "PCIe probing failed\n"); 1122 1123 err = devm_add_action_or_reset(dev, enetc4_pci_remove, pdev); 1124 if (err) 1125 return err; 1126 1127 /* si is the private data. */ 1128 si = pci_get_drvdata(pdev); 1129 if (!si->hw.port || !si->hw.global) 1130 return dev_err_probe(dev, -ENODEV, 1131 "Couldn't map PF only space\n"); 1132 1133 si->revision = enetc_get_ip_revision(&si->hw); 1134 si->ops = &enetc4_psi_ops; 1135 err = enetc_get_driver_data(si); 1136 if (err) 1137 return dev_err_probe(dev, err, 1138 "Could not get PF driver data\n"); 1139 1140 err = enetc4_pf_struct_init(si); 1141 if (err) 1142 return err; 1143 1144 pf = enetc_si_priv(si); 1145 err = enetc4_pf_init(pf); 1146 if (err) 1147 return err; 1148 1149 enetc_get_si_caps(si); 1150 1151 err = enetc4_pf_netdev_create(si); 1152 if (err) 1153 goto err_netdev_create; 1154 1155 enetc_create_debugfs(si); 1156 1157 return 0; 1158 1159 err_netdev_create: 1160 enetc4_pf_free(pf); 1161 1162 return err; 1163 } 1164 1165 static void enetc4_pf_remove(struct pci_dev *pdev) 1166 { 1167 struct enetc_si *si = pci_get_drvdata(pdev); 1168 struct enetc_pf *pf = enetc_si_priv(si); 1169 1170 enetc_remove_debugfs(si); 1171 enetc4_pf_netdev_destroy(si); 1172 enetc4_pf_free(pf); 1173 } 1174 1175 static const struct pci_device_id enetc4_pf_id_table[] = { 1176 { PCI_DEVICE(NXP_ENETC_VENDOR_ID, NXP_ENETC_PF_DEV_ID) }, 1177 { PCI_DEVICE(NXP_ENETC_VENDOR_ID, NXP_ENETC_PPM_DEV_ID) }, 1178 { 0, } /* End of table. */ 1179 }; 1180 MODULE_DEVICE_TABLE(pci, enetc4_pf_id_table); 1181 1182 static struct pci_driver enetc4_pf_driver = { 1183 .name = KBUILD_MODNAME, 1184 .id_table = enetc4_pf_id_table, 1185 .probe = enetc4_pf_probe, 1186 .remove = enetc4_pf_remove, 1187 }; 1188 module_pci_driver(enetc4_pf_driver); 1189 1190 MODULE_DESCRIPTION("ENETC4 PF Driver"); 1191 MODULE_LICENSE("Dual BSD/GPL"); 1192