1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/cleanup.h>
9 #include <linux/device.h>
10 #include <linux/wait.h>
11 #include <linux/bitops.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/slimbus.h>
17 #include <sound/soc.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <sound/tlv.h>
24 #include <sound/info.h>
25 #include "wcd9335.h"
26 #include "wcd-clsh-v2.h"
27
28 #include <dt-bindings/sound/qcom,wcd9335.h>
29
30 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
31 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
32 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
33 /* Fractional Rates */
34 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
35 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE)
37
38 /* slave port water mark level
39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
40 */
41 #define SLAVE_PORT_WATER_MARK_6BYTES 0
42 #define SLAVE_PORT_WATER_MARK_9BYTES 1
43 #define SLAVE_PORT_WATER_MARK_12BYTES 2
44 #define SLAVE_PORT_WATER_MARK_15BYTES 3
45 #define SLAVE_PORT_WATER_MARK_SHIFT 1
46 #define SLAVE_PORT_ENABLE 1
47 #define SLAVE_PORT_DISABLE 0
48 #define WCD9335_SLIM_WATER_MARK_VAL \
49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
50 (SLAVE_PORT_ENABLE))
51
52 #define WCD9335_SLIM_NUM_PORT_REG 3
53 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
54
55 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
56 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
57
58 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
59 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
60 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
61 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
62
63 #define WCD9335_NUM_INTERPOLATORS 9
64 #define WCD9335_RX_START 16
65 #define WCD9335_SLIM_CH_START 128
66 #define WCD9335_MAX_MICBIAS 4
67 #define WCD9335_MAX_VALID_ADC_MUX 13
68 #define WCD9335_INVALID_ADC_MUX 9
69
70 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
71 #define CF_MIN_3DB_4HZ 0x0
72 #define CF_MIN_3DB_75HZ 0x1
73 #define CF_MIN_3DB_150HZ 0x2
74 #define WCD9335_DMIC_CLK_DIV_2 0x0
75 #define WCD9335_DMIC_CLK_DIV_3 0x1
76 #define WCD9335_DMIC_CLK_DIV_4 0x2
77 #define WCD9335_DMIC_CLK_DIV_6 0x3
78 #define WCD9335_DMIC_CLK_DIV_8 0x4
79 #define WCD9335_DMIC_CLK_DIV_16 0x5
80 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
81 #define WCD9335_AMIC_PWR_LEVEL_LP 0
82 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
83 #define WCD9335_AMIC_PWR_LEVEL_HP 2
84 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
85 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
86
87 #define WCD9335_DEC_PWR_LVL_MASK 0x06
88 #define WCD9335_DEC_PWR_LVL_LP 0x02
89 #define WCD9335_DEC_PWR_LVL_HP 0x04
90 #define WCD9335_DEC_PWR_LVL_DF 0x00
91
92 #define WCD9335_SLIM_RX_CH(p) \
93 {.port = p + WCD9335_RX_START, .shift = p,}
94
95 #define WCD9335_SLIM_TX_CH(p) \
96 {.port = p, .shift = p,}
97
98 /* vout step value */
99 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
100
101 #define WCD9335_INTERPOLATOR_PATH(id) \
102 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
107 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
108 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
109 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
115 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
116 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
117 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
123 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
124 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
125 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
129 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
130 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
131 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
132 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
133 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
136 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
138 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
139 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
140 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
141
142 #define WCD9335_ADC_MUX_PATH(id) \
143 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
144 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
145 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
146 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
147 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
148 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
149 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
150 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
151 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
152 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
153 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
154 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
155 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
156 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
157 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
158 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
159 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
160 {"AMIC MUX" #id, "ADC6", "ADC6"}
161
162 #define NUM_CODEC_DAIS 7
163
164 enum {
165 WCD9335_RX0 = 0,
166 WCD9335_RX1,
167 WCD9335_RX2,
168 WCD9335_RX3,
169 WCD9335_RX4,
170 WCD9335_RX5,
171 WCD9335_RX6,
172 WCD9335_RX7,
173 WCD9335_RX8,
174 WCD9335_RX9,
175 WCD9335_RX10,
176 WCD9335_RX11,
177 WCD9335_RX12,
178 WCD9335_RX_MAX,
179 };
180
181 enum {
182 WCD9335_TX0 = 0,
183 WCD9335_TX1,
184 WCD9335_TX2,
185 WCD9335_TX3,
186 WCD9335_TX4,
187 WCD9335_TX5,
188 WCD9335_TX6,
189 WCD9335_TX7,
190 WCD9335_TX8,
191 WCD9335_TX9,
192 WCD9335_TX10,
193 WCD9335_TX11,
194 WCD9335_TX12,
195 WCD9335_TX13,
196 WCD9335_TX14,
197 WCD9335_TX15,
198 WCD9335_TX_MAX,
199 };
200
201 enum {
202 SIDO_SOURCE_INTERNAL = 0,
203 SIDO_SOURCE_RCO_BG,
204 };
205
206 enum wcd9335_sido_voltage {
207 SIDO_VOLTAGE_SVS_MV = 950,
208 SIDO_VOLTAGE_NOMINAL_MV = 1100,
209 };
210
211 enum {
212 COMPANDER_1, /* HPH_L */
213 COMPANDER_2, /* HPH_R */
214 COMPANDER_3, /* LO1_DIFF */
215 COMPANDER_4, /* LO2_DIFF */
216 COMPANDER_5, /* LO3_SE */
217 COMPANDER_6, /* LO4_SE */
218 COMPANDER_7, /* SWR SPK CH1 */
219 COMPANDER_8, /* SWR SPK CH2 */
220 COMPANDER_MAX,
221 };
222
223 enum {
224 INTn_2_INP_SEL_ZERO = 0,
225 INTn_2_INP_SEL_RX0,
226 INTn_2_INP_SEL_RX1,
227 INTn_2_INP_SEL_RX2,
228 INTn_2_INP_SEL_RX3,
229 INTn_2_INP_SEL_RX4,
230 INTn_2_INP_SEL_RX5,
231 INTn_2_INP_SEL_RX6,
232 INTn_2_INP_SEL_RX7,
233 INTn_2_INP_SEL_PROXIMITY,
234 };
235
236 enum {
237 INTn_1_MIX_INP_SEL_ZERO = 0,
238 INTn_1_MIX_INP_SEL_DEC0,
239 INTn_1_MIX_INP_SEL_DEC1,
240 INTn_1_MIX_INP_SEL_IIR0,
241 INTn_1_MIX_INP_SEL_IIR1,
242 INTn_1_MIX_INP_SEL_RX0,
243 INTn_1_MIX_INP_SEL_RX1,
244 INTn_1_MIX_INP_SEL_RX2,
245 INTn_1_MIX_INP_SEL_RX3,
246 INTn_1_MIX_INP_SEL_RX4,
247 INTn_1_MIX_INP_SEL_RX5,
248 INTn_1_MIX_INP_SEL_RX6,
249 INTn_1_MIX_INP_SEL_RX7,
250
251 };
252
253 enum {
254 INTERP_EAR = 0,
255 INTERP_HPHL,
256 INTERP_HPHR,
257 INTERP_LO1,
258 INTERP_LO2,
259 INTERP_LO3,
260 INTERP_LO4,
261 INTERP_SPKR1,
262 INTERP_SPKR2,
263 };
264
265 enum wcd_clock_type {
266 WCD_CLK_OFF,
267 WCD_CLK_RCO,
268 WCD_CLK_MCLK,
269 };
270
271 enum {
272 MIC_BIAS_1 = 1,
273 MIC_BIAS_2,
274 MIC_BIAS_3,
275 MIC_BIAS_4
276 };
277
278 enum {
279 MICB_PULLUP_ENABLE,
280 MICB_PULLUP_DISABLE,
281 MICB_ENABLE,
282 MICB_DISABLE,
283 };
284
285 struct wcd9335_slim_ch {
286 u32 ch_num;
287 u16 port;
288 u16 shift;
289 struct list_head list;
290 };
291
292 struct wcd_slim_codec_dai_data {
293 struct list_head slim_ch_list;
294 struct slim_stream_config sconfig;
295 struct slim_stream_runtime *sruntime;
296 };
297
298 struct wcd9335_codec {
299 struct device *dev;
300 struct clk *mclk;
301 struct clk *native_clk;
302 u32 mclk_rate;
303
304 struct slim_device *slim;
305 struct slim_device *slim_ifc_dev;
306 struct regmap *regmap;
307 struct regmap *if_regmap;
308 struct regmap_irq_chip_data *irq_data;
309
310 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
311 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
312 u32 num_rx_port;
313 u32 num_tx_port;
314
315 enum wcd9335_sido_voltage sido_voltage;
316
317 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
318 struct snd_soc_component *component;
319
320 int master_bias_users;
321 int clk_mclk_users;
322 int clk_rco_users;
323 int sido_ccl_cnt;
324 enum wcd_clock_type clk_type;
325
326 struct wcd_clsh_ctrl *clsh_ctrl;
327 u32 hph_mode;
328 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
329
330 int comp_enabled[COMPANDER_MAX];
331
332 int intr1;
333 struct gpio_desc *reset_gpio;
334
335 unsigned int rx_port_value[WCD9335_RX_MAX];
336 unsigned int tx_port_value[WCD9335_TX_MAX];
337 int hph_l_gain;
338 int hph_r_gain;
339 u32 rx_bias_count;
340
341 /*TX*/
342 int micb_ref[WCD9335_MAX_MICBIAS];
343 int pullup_ref[WCD9335_MAX_MICBIAS];
344
345 int dmic_0_1_clk_cnt;
346 int dmic_2_3_clk_cnt;
347 int dmic_4_5_clk_cnt;
348 };
349
350 struct wcd9335_irq {
351 int irq;
352 irqreturn_t (*handler)(int irq, void *data);
353 char *name;
354 };
355
356 static const char * const wcd9335_supplies[] = {
357 "vdd-buck", "vdd-buck-sido", "vdd-tx", "vdd-rx", "vdd-io",
358 };
359
360 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
361 WCD9335_SLIM_TX_CH(0),
362 WCD9335_SLIM_TX_CH(1),
363 WCD9335_SLIM_TX_CH(2),
364 WCD9335_SLIM_TX_CH(3),
365 WCD9335_SLIM_TX_CH(4),
366 WCD9335_SLIM_TX_CH(5),
367 WCD9335_SLIM_TX_CH(6),
368 WCD9335_SLIM_TX_CH(7),
369 WCD9335_SLIM_TX_CH(8),
370 WCD9335_SLIM_TX_CH(9),
371 WCD9335_SLIM_TX_CH(10),
372 WCD9335_SLIM_TX_CH(11),
373 WCD9335_SLIM_TX_CH(12),
374 WCD9335_SLIM_TX_CH(13),
375 WCD9335_SLIM_TX_CH(14),
376 WCD9335_SLIM_TX_CH(15),
377 };
378
379 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
380 WCD9335_SLIM_RX_CH(0), /* 16 */
381 WCD9335_SLIM_RX_CH(1), /* 17 */
382 WCD9335_SLIM_RX_CH(2),
383 WCD9335_SLIM_RX_CH(3),
384 WCD9335_SLIM_RX_CH(4),
385 WCD9335_SLIM_RX_CH(5),
386 WCD9335_SLIM_RX_CH(6),
387 WCD9335_SLIM_RX_CH(7),
388 WCD9335_SLIM_RX_CH(8),
389 WCD9335_SLIM_RX_CH(9),
390 WCD9335_SLIM_RX_CH(10),
391 WCD9335_SLIM_RX_CH(11),
392 WCD9335_SLIM_RX_CH(12),
393 };
394
395 struct interp_sample_rate {
396 int rate;
397 int rate_val;
398 };
399
400 static const struct interp_sample_rate int_mix_rate_val[] = {
401 {48000, 0x4}, /* 48K */
402 {96000, 0x5}, /* 96K */
403 {192000, 0x6}, /* 192K */
404 };
405
406 static const struct interp_sample_rate int_prim_rate_val[] = {
407 {8000, 0x0}, /* 8K */
408 {16000, 0x1}, /* 16K */
409 {24000, -EINVAL},/* 24K */
410 {32000, 0x3}, /* 32K */
411 {48000, 0x4}, /* 48K */
412 {96000, 0x5}, /* 96K */
413 {192000, 0x6}, /* 192K */
414 {384000, 0x7}, /* 384K */
415 {44100, 0x8}, /* 44.1K */
416 };
417
418 struct wcd9335_reg_mask_val {
419 u16 reg;
420 u8 mask;
421 u8 val;
422 };
423
424 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
425 /* Rbuckfly/R_EAR(32) */
426 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
427 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
428 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
429 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
430 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
431 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
432 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
433 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
434 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
435 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
436 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
437 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
438 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
439 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
440 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
441 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
442 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
443 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
444 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
445 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
446 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
447 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
448 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
449 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
450 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
451 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
454 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
455 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
456 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
457 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
458 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
459 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
460 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
461 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
462 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
463 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
464 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
465 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
466 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
467 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
468 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
469 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
470 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
471 {WCD9335_HPH_L_TEST, 0x01, 0x01},
472 {WCD9335_HPH_R_TEST, 0x01, 0x01},
473 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
474 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
475 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
476 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
477 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
478 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
479 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
480 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
483 };
484
485 /* Cutoff frequency for high pass filter */
486 static const char * const cf_text[] = {
487 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
488 };
489
490 static const char * const rx_cf_text[] = {
491 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
492 "CF_NEG_3DB_0P48HZ"
493 };
494
495 static const char * const rx_int0_7_mix_mux_text[] = {
496 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
497 "RX6", "RX7", "PROXIMITY"
498 };
499
500 static const char * const rx_int_mix_mux_text[] = {
501 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
502 "RX6", "RX7"
503 };
504
505 static const char * const rx_prim_mix_text[] = {
506 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
507 "RX3", "RX4", "RX5", "RX6", "RX7"
508 };
509
510 static const char * const rx_int_dem_inp_mux_text[] = {
511 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
512 };
513
514 static const char * const rx_int0_interp_mux_text[] = {
515 "ZERO", "RX INT0 MIX2",
516 };
517
518 static const char * const rx_int1_interp_mux_text[] = {
519 "ZERO", "RX INT1 MIX2",
520 };
521
522 static const char * const rx_int2_interp_mux_text[] = {
523 "ZERO", "RX INT2 MIX2",
524 };
525
526 static const char * const rx_int3_interp_mux_text[] = {
527 "ZERO", "RX INT3 MIX2",
528 };
529
530 static const char * const rx_int4_interp_mux_text[] = {
531 "ZERO", "RX INT4 MIX2",
532 };
533
534 static const char * const rx_int5_interp_mux_text[] = {
535 "ZERO", "RX INT5 MIX2",
536 };
537
538 static const char * const rx_int6_interp_mux_text[] = {
539 "ZERO", "RX INT6 MIX2",
540 };
541
542 static const char * const rx_int7_interp_mux_text[] = {
543 "ZERO", "RX INT7 MIX2",
544 };
545
546 static const char * const rx_int8_interp_mux_text[] = {
547 "ZERO", "RX INT8 SEC MIX"
548 };
549
550 static const char * const rx_hph_mode_mux_text[] = {
551 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
552 "Class-H Hi-Fi Low Power"
553 };
554
555 static const char *const slim_rx_mux_text[] = {
556 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
557 };
558
559 static const char * const adc_mux_text[] = {
560 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
561 };
562
563 static const char * const dmic_mux_text[] = {
564 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
565 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
566 };
567
568 static const char * const dmic_mux_alt_text[] = {
569 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
570 };
571
572 static const char * const amic_mux_text[] = {
573 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
574 };
575
576 static const char * const sb_tx0_mux_text[] = {
577 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
578 };
579
580 static const char * const sb_tx1_mux_text[] = {
581 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
582 };
583
584 static const char * const sb_tx2_mux_text[] = {
585 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
586 };
587
588 static const char * const sb_tx3_mux_text[] = {
589 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
590 };
591
592 static const char * const sb_tx4_mux_text[] = {
593 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
594 };
595
596 static const char * const sb_tx5_mux_text[] = {
597 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
598 };
599
600 static const char * const sb_tx6_mux_text[] = {
601 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
602 };
603
604 static const char * const sb_tx7_mux_text[] = {
605 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
606 };
607
608 static const char * const sb_tx8_mux_text[] = {
609 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
610 };
611
612 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
613 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
614 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
615 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
616
617 static const struct soc_enum cf_dec0_enum =
618 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
619
620 static const struct soc_enum cf_dec1_enum =
621 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
622
623 static const struct soc_enum cf_dec2_enum =
624 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
625
626 static const struct soc_enum cf_dec3_enum =
627 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
628
629 static const struct soc_enum cf_dec4_enum =
630 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
631
632 static const struct soc_enum cf_dec5_enum =
633 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
634
635 static const struct soc_enum cf_dec6_enum =
636 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
637
638 static const struct soc_enum cf_dec7_enum =
639 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
640
641 static const struct soc_enum cf_dec8_enum =
642 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
643
644 static const struct soc_enum cf_int0_1_enum =
645 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
646
647 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
648 rx_cf_text);
649
650 static const struct soc_enum cf_int1_1_enum =
651 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
652
653 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
654 rx_cf_text);
655
656 static const struct soc_enum cf_int2_1_enum =
657 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
658
659 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
660 rx_cf_text);
661
662 static const struct soc_enum cf_int3_1_enum =
663 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
664
665 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
666 rx_cf_text);
667
668 static const struct soc_enum cf_int4_1_enum =
669 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
670
671 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
672 rx_cf_text);
673
674 static const struct soc_enum cf_int5_1_enum =
675 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
676
677 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
678 rx_cf_text);
679
680 static const struct soc_enum cf_int6_1_enum =
681 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
682
683 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
684 rx_cf_text);
685
686 static const struct soc_enum cf_int7_1_enum =
687 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
688
689 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
690 rx_cf_text);
691
692 static const struct soc_enum cf_int8_1_enum =
693 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
694
695 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
696 rx_cf_text);
697
698 static const struct soc_enum rx_hph_mode_mux_enum =
699 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
700 rx_hph_mode_mux_text);
701
702 static const struct soc_enum slim_rx_mux_enum =
703 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
704
705 static const struct soc_enum rx_int0_2_mux_chain_enum =
706 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
707 rx_int0_7_mix_mux_text);
708
709 static const struct soc_enum rx_int1_2_mux_chain_enum =
710 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
711 rx_int_mix_mux_text);
712
713 static const struct soc_enum rx_int2_2_mux_chain_enum =
714 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
715 rx_int_mix_mux_text);
716
717 static const struct soc_enum rx_int3_2_mux_chain_enum =
718 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
719 rx_int_mix_mux_text);
720
721 static const struct soc_enum rx_int4_2_mux_chain_enum =
722 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
723 rx_int_mix_mux_text);
724
725 static const struct soc_enum rx_int5_2_mux_chain_enum =
726 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
727 rx_int_mix_mux_text);
728
729 static const struct soc_enum rx_int6_2_mux_chain_enum =
730 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
731 rx_int_mix_mux_text);
732
733 static const struct soc_enum rx_int7_2_mux_chain_enum =
734 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
735 rx_int0_7_mix_mux_text);
736
737 static const struct soc_enum rx_int8_2_mux_chain_enum =
738 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
739 rx_int_mix_mux_text);
740
741 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
742 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
743 rx_prim_mix_text);
744
745 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
746 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
747 rx_prim_mix_text);
748
749 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
750 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
751 rx_prim_mix_text);
752
753 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
754 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
755 rx_prim_mix_text);
756
757 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
758 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
759 rx_prim_mix_text);
760
761 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
762 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
763 rx_prim_mix_text);
764
765 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
766 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
767 rx_prim_mix_text);
768
769 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
770 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
771 rx_prim_mix_text);
772
773 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
774 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
775 rx_prim_mix_text);
776
777 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
778 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
779 rx_prim_mix_text);
780
781 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
782 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
783 rx_prim_mix_text);
784
785 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
786 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
787 rx_prim_mix_text);
788
789 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
790 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
791 rx_prim_mix_text);
792
793 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
794 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
795 rx_prim_mix_text);
796
797 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
798 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
799 rx_prim_mix_text);
800
801 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
802 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
803 rx_prim_mix_text);
804
805 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
806 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
807 rx_prim_mix_text);
808
809 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
810 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
811 rx_prim_mix_text);
812
813 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
814 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
815 rx_prim_mix_text);
816
817 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
818 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
819 rx_prim_mix_text);
820
821 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
822 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
823 rx_prim_mix_text);
824
825 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
826 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
827 rx_prim_mix_text);
828
829 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
830 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
831 rx_prim_mix_text);
832
833 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
834 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
835 rx_prim_mix_text);
836
837 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
838 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
839 rx_prim_mix_text);
840
841 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
842 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
843 rx_prim_mix_text);
844
845 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
846 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
847 rx_prim_mix_text);
848
849 static const struct soc_enum rx_int0_dem_inp_mux_enum =
850 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
851 ARRAY_SIZE(rx_int_dem_inp_mux_text),
852 rx_int_dem_inp_mux_text);
853
854 static const struct soc_enum rx_int1_dem_inp_mux_enum =
855 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
856 ARRAY_SIZE(rx_int_dem_inp_mux_text),
857 rx_int_dem_inp_mux_text);
858
859 static const struct soc_enum rx_int2_dem_inp_mux_enum =
860 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
861 ARRAY_SIZE(rx_int_dem_inp_mux_text),
862 rx_int_dem_inp_mux_text);
863
864 static const struct soc_enum rx_int0_interp_mux_enum =
865 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
866 rx_int0_interp_mux_text);
867
868 static const struct soc_enum rx_int1_interp_mux_enum =
869 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
870 rx_int1_interp_mux_text);
871
872 static const struct soc_enum rx_int2_interp_mux_enum =
873 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
874 rx_int2_interp_mux_text);
875
876 static const struct soc_enum rx_int3_interp_mux_enum =
877 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
878 rx_int3_interp_mux_text);
879
880 static const struct soc_enum rx_int4_interp_mux_enum =
881 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
882 rx_int4_interp_mux_text);
883
884 static const struct soc_enum rx_int5_interp_mux_enum =
885 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
886 rx_int5_interp_mux_text);
887
888 static const struct soc_enum rx_int6_interp_mux_enum =
889 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
890 rx_int6_interp_mux_text);
891
892 static const struct soc_enum rx_int7_interp_mux_enum =
893 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
894 rx_int7_interp_mux_text);
895
896 static const struct soc_enum rx_int8_interp_mux_enum =
897 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
898 rx_int8_interp_mux_text);
899
900 static const struct soc_enum tx_adc_mux0_chain_enum =
901 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
902 adc_mux_text);
903
904 static const struct soc_enum tx_adc_mux1_chain_enum =
905 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
906 adc_mux_text);
907
908 static const struct soc_enum tx_adc_mux2_chain_enum =
909 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
910 adc_mux_text);
911
912 static const struct soc_enum tx_adc_mux3_chain_enum =
913 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
914 adc_mux_text);
915
916 static const struct soc_enum tx_adc_mux4_chain_enum =
917 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
918 adc_mux_text);
919
920 static const struct soc_enum tx_adc_mux5_chain_enum =
921 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
922 adc_mux_text);
923
924 static const struct soc_enum tx_adc_mux6_chain_enum =
925 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
926 adc_mux_text);
927
928 static const struct soc_enum tx_adc_mux7_chain_enum =
929 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
930 adc_mux_text);
931
932 static const struct soc_enum tx_adc_mux8_chain_enum =
933 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
934 adc_mux_text);
935
936 static const struct soc_enum tx_dmic_mux0_enum =
937 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
938 dmic_mux_text);
939
940 static const struct soc_enum tx_dmic_mux1_enum =
941 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
942 dmic_mux_text);
943
944 static const struct soc_enum tx_dmic_mux2_enum =
945 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
946 dmic_mux_text);
947
948 static const struct soc_enum tx_dmic_mux3_enum =
949 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
950 dmic_mux_text);
951
952 static const struct soc_enum tx_dmic_mux4_enum =
953 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
954 dmic_mux_alt_text);
955
956 static const struct soc_enum tx_dmic_mux5_enum =
957 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
958 dmic_mux_alt_text);
959
960 static const struct soc_enum tx_dmic_mux6_enum =
961 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
962 dmic_mux_alt_text);
963
964 static const struct soc_enum tx_dmic_mux7_enum =
965 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
966 dmic_mux_alt_text);
967
968 static const struct soc_enum tx_dmic_mux8_enum =
969 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
970 dmic_mux_alt_text);
971
972 static const struct soc_enum tx_amic_mux0_enum =
973 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
974 amic_mux_text);
975
976 static const struct soc_enum tx_amic_mux1_enum =
977 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
978 amic_mux_text);
979
980 static const struct soc_enum tx_amic_mux2_enum =
981 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
982 amic_mux_text);
983
984 static const struct soc_enum tx_amic_mux3_enum =
985 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
986 amic_mux_text);
987
988 static const struct soc_enum tx_amic_mux4_enum =
989 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
990 amic_mux_text);
991
992 static const struct soc_enum tx_amic_mux5_enum =
993 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
994 amic_mux_text);
995
996 static const struct soc_enum tx_amic_mux6_enum =
997 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
998 amic_mux_text);
999
1000 static const struct soc_enum tx_amic_mux7_enum =
1001 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1002 amic_mux_text);
1003
1004 static const struct soc_enum tx_amic_mux8_enum =
1005 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1006 amic_mux_text);
1007
1008 static const struct soc_enum sb_tx0_mux_enum =
1009 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1010 sb_tx0_mux_text);
1011
1012 static const struct soc_enum sb_tx1_mux_enum =
1013 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1014 sb_tx1_mux_text);
1015
1016 static const struct soc_enum sb_tx2_mux_enum =
1017 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1018 sb_tx2_mux_text);
1019
1020 static const struct soc_enum sb_tx3_mux_enum =
1021 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1022 sb_tx3_mux_text);
1023
1024 static const struct soc_enum sb_tx4_mux_enum =
1025 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1026 sb_tx4_mux_text);
1027
1028 static const struct soc_enum sb_tx5_mux_enum =
1029 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1030 sb_tx5_mux_text);
1031
1032 static const struct soc_enum sb_tx6_mux_enum =
1033 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1034 sb_tx6_mux_text);
1035
1036 static const struct soc_enum sb_tx7_mux_enum =
1037 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1038 sb_tx7_mux_text);
1039
1040 static const struct soc_enum sb_tx8_mux_enum =
1041 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1042 sb_tx8_mux_text);
1043
1044 static const struct snd_kcontrol_new rx_int0_2_mux =
1045 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1046
1047 static const struct snd_kcontrol_new rx_int1_2_mux =
1048 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1049
1050 static const struct snd_kcontrol_new rx_int2_2_mux =
1051 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1052
1053 static const struct snd_kcontrol_new rx_int3_2_mux =
1054 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int4_2_mux =
1057 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int5_2_mux =
1060 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int6_2_mux =
1063 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int7_2_mux =
1066 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int8_2_mux =
1069 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1072 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1081 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1090 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1099 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1108 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1117 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1126 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1135 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1144 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int0_interp_mux =
1153 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1154
1155 static const struct snd_kcontrol_new rx_int1_interp_mux =
1156 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1157
1158 static const struct snd_kcontrol_new rx_int2_interp_mux =
1159 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1160
1161 static const struct snd_kcontrol_new rx_int3_interp_mux =
1162 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int4_interp_mux =
1165 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int5_interp_mux =
1168 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int6_interp_mux =
1171 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int7_interp_mux =
1174 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int8_interp_mux =
1177 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new tx_dmic_mux0 =
1180 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1181
1182 static const struct snd_kcontrol_new tx_dmic_mux1 =
1183 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1184
1185 static const struct snd_kcontrol_new tx_dmic_mux2 =
1186 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux3 =
1189 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux4 =
1192 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux5 =
1195 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux6 =
1198 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux7 =
1201 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux8 =
1204 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1205
1206 static const struct snd_kcontrol_new tx_amic_mux0 =
1207 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1208
1209 static const struct snd_kcontrol_new tx_amic_mux1 =
1210 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1211
1212 static const struct snd_kcontrol_new tx_amic_mux2 =
1213 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux3 =
1216 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux4 =
1219 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux5 =
1222 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux6 =
1225 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux7 =
1228 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux8 =
1231 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1232
1233 static const struct snd_kcontrol_new sb_tx0_mux =
1234 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1235
1236 static const struct snd_kcontrol_new sb_tx1_mux =
1237 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1238
1239 static const struct snd_kcontrol_new sb_tx2_mux =
1240 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx3_mux =
1243 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx4_mux =
1246 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx5_mux =
1249 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx6_mux =
1252 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx7_mux =
1255 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx8_mux =
1258 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1259
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1260 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1261 struct snd_ctl_elem_value *ucontrol)
1262 {
1263 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1264 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1265 u32 port_id = w->shift;
1266
1267 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1268
1269 return 0;
1270 }
1271
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1272 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1273 struct snd_ctl_elem_value *ucontrol)
1274 {
1275 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1276 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1277 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1278 struct snd_soc_dapm_update *update = NULL;
1279 u32 port_id = w->shift;
1280
1281 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1282 return 0;
1283
1284 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1285
1286 /* Remove channel from any list it's in before adding it to a new one */
1287 list_del_init(&wcd->rx_chs[port_id].list);
1288
1289 switch (wcd->rx_port_value[port_id]) {
1290 case 0:
1291 /* Channel already removed from lists. Nothing to do here */
1292 break;
1293 case 1:
1294 list_add_tail(&wcd->rx_chs[port_id].list,
1295 &wcd->dai[AIF1_PB].slim_ch_list);
1296 break;
1297 case 2:
1298 list_add_tail(&wcd->rx_chs[port_id].list,
1299 &wcd->dai[AIF2_PB].slim_ch_list);
1300 break;
1301 case 3:
1302 list_add_tail(&wcd->rx_chs[port_id].list,
1303 &wcd->dai[AIF3_PB].slim_ch_list);
1304 break;
1305 case 4:
1306 list_add_tail(&wcd->rx_chs[port_id].list,
1307 &wcd->dai[AIF4_PB].slim_ch_list);
1308 break;
1309 default:
1310 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1311 goto err;
1312 }
1313
1314 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1315 e, update);
1316
1317 return 0;
1318 err:
1319 return -EINVAL;
1320 }
1321
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1322 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1323 struct snd_ctl_elem_value *ucontrol)
1324 {
1325
1326 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1327 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1328 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1329 struct soc_mixer_control *mixer =
1330 (struct soc_mixer_control *)kc->private_value;
1331 int dai_id = widget->shift;
1332 int port_id = mixer->shift;
1333
1334 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1335
1336 return 0;
1337 }
1338
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1339 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1340 struct snd_ctl_elem_value *ucontrol)
1341 {
1342
1343 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1344 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1345 struct snd_soc_dapm_update *update = NULL;
1346 struct soc_mixer_control *mixer =
1347 (struct soc_mixer_control *)kc->private_value;
1348 int enable = ucontrol->value.integer.value[0];
1349 int dai_id = widget->shift;
1350 int port_id = mixer->shift;
1351
1352 switch (dai_id) {
1353 case AIF1_CAP:
1354 case AIF2_CAP:
1355 case AIF3_CAP:
1356 /* only add to the list if value not set */
1357 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1358 wcd->tx_port_value[port_id] = dai_id;
1359 list_add_tail(&wcd->tx_chs[port_id].list,
1360 &wcd->dai[dai_id].slim_ch_list);
1361 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1362 wcd->tx_port_value[port_id] = -1;
1363 list_del_init(&wcd->tx_chs[port_id].list);
1364 }
1365 break;
1366 default:
1367 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1368 return -EINVAL;
1369 }
1370
1371 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1372
1373 return 0;
1374 }
1375
1376 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1377 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1378 slim_rx_mux_get, slim_rx_mux_put),
1379 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1380 slim_rx_mux_get, slim_rx_mux_put),
1381 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1382 slim_rx_mux_get, slim_rx_mux_put),
1383 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1384 slim_rx_mux_get, slim_rx_mux_put),
1385 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1386 slim_rx_mux_get, slim_rx_mux_put),
1387 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1388 slim_rx_mux_get, slim_rx_mux_put),
1389 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1390 slim_rx_mux_get, slim_rx_mux_put),
1391 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1392 slim_rx_mux_get, slim_rx_mux_put),
1393 };
1394
1395 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1396 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1397 slim_tx_mixer_get, slim_tx_mixer_put),
1398 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1399 slim_tx_mixer_get, slim_tx_mixer_put),
1400 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1401 slim_tx_mixer_get, slim_tx_mixer_put),
1402 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1403 slim_tx_mixer_get, slim_tx_mixer_put),
1404 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1405 slim_tx_mixer_get, slim_tx_mixer_put),
1406 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1407 slim_tx_mixer_get, slim_tx_mixer_put),
1408 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1409 slim_tx_mixer_get, slim_tx_mixer_put),
1410 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1411 slim_tx_mixer_get, slim_tx_mixer_put),
1412 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1413 slim_tx_mixer_get, slim_tx_mixer_put),
1414 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1415 slim_tx_mixer_get, slim_tx_mixer_put),
1416 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1417 slim_tx_mixer_get, slim_tx_mixer_put),
1418 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1419 slim_tx_mixer_get, slim_tx_mixer_put),
1420 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1421 slim_tx_mixer_get, slim_tx_mixer_put),
1422 };
1423
1424 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1425 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1426 slim_tx_mixer_get, slim_tx_mixer_put),
1427 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1428 slim_tx_mixer_get, slim_tx_mixer_put),
1429 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1430 slim_tx_mixer_get, slim_tx_mixer_put),
1431 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1432 slim_tx_mixer_get, slim_tx_mixer_put),
1433 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1434 slim_tx_mixer_get, slim_tx_mixer_put),
1435 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1436 slim_tx_mixer_get, slim_tx_mixer_put),
1437 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1438 slim_tx_mixer_get, slim_tx_mixer_put),
1439 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1440 slim_tx_mixer_get, slim_tx_mixer_put),
1441 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1442 slim_tx_mixer_get, slim_tx_mixer_put),
1443 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1444 slim_tx_mixer_get, slim_tx_mixer_put),
1445 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1446 slim_tx_mixer_get, slim_tx_mixer_put),
1447 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1448 slim_tx_mixer_get, slim_tx_mixer_put),
1449 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1450 slim_tx_mixer_get, slim_tx_mixer_put),
1451 };
1452
1453 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1454 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1455 slim_tx_mixer_get, slim_tx_mixer_put),
1456 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1457 slim_tx_mixer_get, slim_tx_mixer_put),
1458 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1459 slim_tx_mixer_get, slim_tx_mixer_put),
1460 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1461 slim_tx_mixer_get, slim_tx_mixer_put),
1462 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1463 slim_tx_mixer_get, slim_tx_mixer_put),
1464 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1465 slim_tx_mixer_get, slim_tx_mixer_put),
1466 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1467 slim_tx_mixer_get, slim_tx_mixer_put),
1468 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1469 slim_tx_mixer_get, slim_tx_mixer_put),
1470 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1471 slim_tx_mixer_get, slim_tx_mixer_put),
1472 };
1473
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1474 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1475 struct snd_ctl_elem_value *ucontrol)
1476 {
1477 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1478 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1479 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1480 unsigned int val, reg, sel;
1481
1482 val = ucontrol->value.enumerated.item[0];
1483
1484 switch (e->reg) {
1485 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1486 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1487 break;
1488 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1489 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1490 break;
1491 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1492 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1493 break;
1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1495 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1496 break;
1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1498 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1499 break;
1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1501 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1502 break;
1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1504 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1505 break;
1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1507 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1508 break;
1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1510 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1511 break;
1512 default:
1513 return -EINVAL;
1514 }
1515
1516 /* AMIC: 0, DMIC: 1 */
1517 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1518 snd_soc_component_update_bits(component, reg,
1519 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1520 sel);
1521
1522 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1523 }
1524
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1525 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1526 struct snd_ctl_elem_value *ucontrol)
1527 {
1528 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1529 struct snd_soc_component *component;
1530 int reg, val;
1531
1532 component = snd_soc_dapm_kcontrol_component(kc);
1533 val = ucontrol->value.enumerated.item[0];
1534
1535 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1536 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1537 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1538 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1539 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1540 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1541 else
1542 return -EINVAL;
1543
1544 /* Set Look Ahead Delay */
1545 snd_soc_component_update_bits(component, reg,
1546 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1547 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1548 /* Set DEM INP Select */
1549 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1550 }
1551
1552 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1553 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1554 snd_soc_dapm_get_enum_double,
1555 wcd9335_int_dem_inp_mux_put);
1556
1557 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1558 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1559 snd_soc_dapm_get_enum_double,
1560 wcd9335_int_dem_inp_mux_put);
1561
1562 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1563 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1564 snd_soc_dapm_get_enum_double,
1565 wcd9335_int_dem_inp_mux_put);
1566
1567 static const struct snd_kcontrol_new tx_adc_mux0 =
1568 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1569 snd_soc_dapm_get_enum_double,
1570 wcd9335_put_dec_enum);
1571
1572 static const struct snd_kcontrol_new tx_adc_mux1 =
1573 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1574 snd_soc_dapm_get_enum_double,
1575 wcd9335_put_dec_enum);
1576
1577 static const struct snd_kcontrol_new tx_adc_mux2 =
1578 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1579 snd_soc_dapm_get_enum_double,
1580 wcd9335_put_dec_enum);
1581
1582 static const struct snd_kcontrol_new tx_adc_mux3 =
1583 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1584 snd_soc_dapm_get_enum_double,
1585 wcd9335_put_dec_enum);
1586
1587 static const struct snd_kcontrol_new tx_adc_mux4 =
1588 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1589 snd_soc_dapm_get_enum_double,
1590 wcd9335_put_dec_enum);
1591
1592 static const struct snd_kcontrol_new tx_adc_mux5 =
1593 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1594 snd_soc_dapm_get_enum_double,
1595 wcd9335_put_dec_enum);
1596
1597 static const struct snd_kcontrol_new tx_adc_mux6 =
1598 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1599 snd_soc_dapm_get_enum_double,
1600 wcd9335_put_dec_enum);
1601
1602 static const struct snd_kcontrol_new tx_adc_mux7 =
1603 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1604 snd_soc_dapm_get_enum_double,
1605 wcd9335_put_dec_enum);
1606
1607 static const struct snd_kcontrol_new tx_adc_mux8 =
1608 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1609 snd_soc_dapm_get_enum_double,
1610 wcd9335_put_dec_enum);
1611
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1612 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1613 int rate_val,
1614 u32 rate)
1615 {
1616 struct snd_soc_component *component = dai->component;
1617 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1618 struct wcd9335_slim_ch *ch;
1619 int val, j;
1620
1621 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1622 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1623 val = snd_soc_component_read(component,
1624 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1625 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1626
1627 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1628 snd_soc_component_update_bits(component,
1629 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1630 WCD9335_CDC_MIX_PCM_RATE_MASK,
1631 rate_val);
1632 }
1633 }
1634
1635 return 0;
1636 }
1637
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1638 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1639 u8 rate_val,
1640 u32 rate)
1641 {
1642 struct snd_soc_component *comp = dai->component;
1643 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1644 struct wcd9335_slim_ch *ch;
1645 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1646 int inp, j;
1647
1648 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1649 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1650 /*
1651 * Loop through all interpolator MUX inputs and find out
1652 * to which interpolator input, the slim rx port
1653 * is connected
1654 */
1655 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1656 cfg0 = snd_soc_component_read(comp,
1657 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1658 cfg1 = snd_soc_component_read(comp,
1659 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1660
1661 inp0_sel = cfg0 &
1662 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1663 inp1_sel = (cfg0 >> 4) &
1664 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1665 inp2_sel = (cfg1 >> 4) &
1666 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1667
1668 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1669 (inp2_sel == inp)) {
1670 /* rate is in Hz */
1671 if ((j == 0) && (rate == 44100))
1672 dev_info(wcd->dev,
1673 "Cannot set 44.1KHz on INT0\n");
1674 else
1675 snd_soc_component_update_bits(comp,
1676 WCD9335_CDC_RX_PATH_CTL(j),
1677 WCD9335_CDC_MIX_PCM_RATE_MASK,
1678 rate_val);
1679 }
1680 }
1681 }
1682
1683 return 0;
1684 }
1685
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1686 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1687 {
1688 int i;
1689
1690 /* set mixing path rate */
1691 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1692 if (rate == int_mix_rate_val[i].rate) {
1693 wcd9335_set_mix_interpolator_rate(dai,
1694 int_mix_rate_val[i].rate_val, rate);
1695 break;
1696 }
1697 }
1698
1699 /* set primary path sample rate */
1700 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1701 if (rate == int_prim_rate_val[i].rate) {
1702 wcd9335_set_prim_interpolator_rate(dai,
1703 int_prim_rate_val[i].rate_val, rate);
1704 break;
1705 }
1706 }
1707
1708 return 0;
1709 }
1710
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1711 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1712 struct wcd_slim_codec_dai_data *dai_data,
1713 int direction)
1714 {
1715 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1716 struct slim_stream_config *cfg = &dai_data->sconfig;
1717 struct wcd9335_slim_ch *ch;
1718 u16 payload = 0;
1719 int ret, i;
1720
1721 cfg->ch_count = 0;
1722 cfg->direction = direction;
1723 cfg->port_mask = 0;
1724
1725 /* Configure slave interface device */
1726 list_for_each_entry(ch, slim_ch_list, list) {
1727 cfg->ch_count++;
1728 payload |= 1 << ch->shift;
1729 cfg->port_mask |= BIT(ch->port);
1730 }
1731
1732 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1733 if (!cfg->chs)
1734 return -ENOMEM;
1735
1736 i = 0;
1737 list_for_each_entry(ch, slim_ch_list, list) {
1738 cfg->chs[i++] = ch->ch_num;
1739 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1740 /* write to interface device */
1741 ret = regmap_write(wcd->if_regmap,
1742 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1743 payload);
1744
1745 if (ret < 0)
1746 goto err;
1747
1748 /* configure the slave port for water mark and enable*/
1749 ret = regmap_write(wcd->if_regmap,
1750 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1751 WCD9335_SLIM_WATER_MARK_VAL);
1752 if (ret < 0)
1753 goto err;
1754 } else {
1755 ret = regmap_write(wcd->if_regmap,
1756 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1757 payload & 0x00FF);
1758 if (ret < 0)
1759 goto err;
1760
1761 /* ports 8,9 */
1762 ret = regmap_write(wcd->if_regmap,
1763 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1764 (payload & 0xFF00)>>8);
1765 if (ret < 0)
1766 goto err;
1767
1768 /* configure the slave port for water mark and enable*/
1769 ret = regmap_write(wcd->if_regmap,
1770 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1771 WCD9335_SLIM_WATER_MARK_VAL);
1772
1773 if (ret < 0)
1774 goto err;
1775 }
1776 }
1777
1778 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1779
1780 return 0;
1781
1782 err:
1783 dev_err(wcd->dev, "Error Setting slim hw params\n");
1784 kfree(cfg->chs);
1785 cfg->chs = NULL;
1786
1787 return ret;
1788 }
1789
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1790 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1791 u8 rate_val, u32 rate)
1792 {
1793 struct snd_soc_component *comp = dai->component;
1794 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1795 u8 shift = 0, shift_val = 0, tx_mux_sel;
1796 struct wcd9335_slim_ch *ch;
1797 int tx_port, tx_port_reg;
1798 int decimator = -1;
1799
1800 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1801 tx_port = ch->port;
1802 if ((tx_port == 12) || (tx_port >= 14)) {
1803 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1804 tx_port, dai->id);
1805 return -EINVAL;
1806 }
1807 /* Find the SB TX MUX input - which decimator is connected */
1808 if (tx_port < 4) {
1809 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1810 shift = (tx_port << 1);
1811 shift_val = 0x03;
1812 } else if (tx_port < 8) {
1813 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1814 shift = ((tx_port - 4) << 1);
1815 shift_val = 0x03;
1816 } else if (tx_port < 11) {
1817 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1818 shift = ((tx_port - 8) << 1);
1819 shift_val = 0x03;
1820 } else if (tx_port == 11) {
1821 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1822 shift = 0;
1823 shift_val = 0x0F;
1824 } else /* (tx_port == 13) */ {
1825 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1826 shift = 4;
1827 shift_val = 0x03;
1828 }
1829
1830 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1831 (shift_val << shift);
1832
1833 tx_mux_sel = tx_mux_sel >> shift;
1834 if (tx_port <= 8) {
1835 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1836 decimator = tx_port;
1837 } else if (tx_port <= 10) {
1838 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1839 decimator = ((tx_port == 9) ? 7 : 6);
1840 } else if (tx_port == 11) {
1841 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1842 decimator = tx_mux_sel - 1;
1843 } else if (tx_port == 13) {
1844 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1845 decimator = 5;
1846 }
1847
1848 if (decimator >= 0) {
1849 snd_soc_component_update_bits(comp,
1850 WCD9335_CDC_TX_PATH_CTL(decimator),
1851 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1852 rate_val);
1853 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1854 /* Check if the TX Mux input is RX MIX TXn */
1855 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1856 tx_port, tx_port);
1857 } else {
1858 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1859 decimator);
1860 return -EINVAL;
1861 }
1862 }
1863
1864 return 0;
1865 }
1866
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1867 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1868 struct snd_pcm_hw_params *params,
1869 struct snd_soc_dai *dai)
1870 {
1871 struct wcd9335_codec *wcd;
1872 int ret, tx_fs_rate = 0;
1873
1874 wcd = snd_soc_component_get_drvdata(dai->component);
1875
1876 switch (substream->stream) {
1877 case SNDRV_PCM_STREAM_PLAYBACK:
1878 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1879 if (ret) {
1880 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1881 params_rate(params));
1882 return ret;
1883 }
1884 switch (params_width(params)) {
1885 case 16 ... 24:
1886 wcd->dai[dai->id].sconfig.bps = params_width(params);
1887 break;
1888 default:
1889 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1890 __func__, params_width(params));
1891 return -EINVAL;
1892 }
1893 break;
1894
1895 case SNDRV_PCM_STREAM_CAPTURE:
1896 switch (params_rate(params)) {
1897 case 8000:
1898 tx_fs_rate = 0;
1899 break;
1900 case 16000:
1901 tx_fs_rate = 1;
1902 break;
1903 case 32000:
1904 tx_fs_rate = 3;
1905 break;
1906 case 48000:
1907 tx_fs_rate = 4;
1908 break;
1909 case 96000:
1910 tx_fs_rate = 5;
1911 break;
1912 case 192000:
1913 tx_fs_rate = 6;
1914 break;
1915 case 384000:
1916 tx_fs_rate = 7;
1917 break;
1918 default:
1919 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1920 __func__, params_rate(params));
1921 return -EINVAL;
1922
1923 }
1924
1925 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1926 params_rate(params));
1927 if (ret < 0) {
1928 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1929 return ret;
1930 }
1931 switch (params_width(params)) {
1932 case 16 ... 32:
1933 wcd->dai[dai->id].sconfig.bps = params_width(params);
1934 break;
1935 default:
1936 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1937 __func__, params_width(params));
1938 return -EINVAL;
1939 }
1940 break;
1941 default:
1942 dev_err(wcd->dev, "Invalid stream type %d\n",
1943 substream->stream);
1944 return -EINVAL;
1945 }
1946
1947 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1948 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1949
1950 return 0;
1951 }
1952
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1953 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1954 struct snd_soc_dai *dai)
1955 {
1956 struct wcd_slim_codec_dai_data *dai_data;
1957 struct wcd9335_codec *wcd;
1958 struct slim_stream_config *cfg;
1959
1960 wcd = snd_soc_component_get_drvdata(dai->component);
1961
1962 dai_data = &wcd->dai[dai->id];
1963
1964 switch (cmd) {
1965 case SNDRV_PCM_TRIGGER_START:
1966 case SNDRV_PCM_TRIGGER_RESUME:
1967 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1968 cfg = &dai_data->sconfig;
1969 slim_stream_prepare(dai_data->sruntime, cfg);
1970 slim_stream_enable(dai_data->sruntime);
1971 break;
1972 case SNDRV_PCM_TRIGGER_STOP:
1973 case SNDRV_PCM_TRIGGER_SUSPEND:
1974 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1975 slim_stream_disable(dai_data->sruntime);
1976 slim_stream_unprepare(dai_data->sruntime);
1977 break;
1978 default:
1979 break;
1980 }
1981
1982 return 0;
1983 }
1984
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1985 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1986 unsigned int tx_num,
1987 const unsigned int *tx_slot,
1988 unsigned int rx_num,
1989 const unsigned int *rx_slot)
1990 {
1991 struct wcd9335_codec *wcd;
1992 int i;
1993
1994 wcd = snd_soc_component_get_drvdata(dai->component);
1995
1996 if (!tx_slot || !rx_slot) {
1997 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1998 tx_slot, rx_slot);
1999 return -EINVAL;
2000 }
2001
2002 wcd->num_rx_port = rx_num;
2003 for (i = 0; i < rx_num; i++) {
2004 wcd->rx_chs[i].ch_num = rx_slot[i];
2005 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2006 }
2007
2008 wcd->num_tx_port = tx_num;
2009 for (i = 0; i < tx_num; i++) {
2010 wcd->tx_chs[i].ch_num = tx_slot[i];
2011 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2012 }
2013
2014 return 0;
2015 }
2016
wcd9335_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2017 static int wcd9335_get_channel_map(const struct snd_soc_dai *dai,
2018 unsigned int *tx_num, unsigned int *tx_slot,
2019 unsigned int *rx_num, unsigned int *rx_slot)
2020 {
2021 struct wcd9335_slim_ch *ch;
2022 struct wcd9335_codec *wcd;
2023 int i = 0;
2024
2025 wcd = snd_soc_component_get_drvdata(dai->component);
2026
2027 switch (dai->id) {
2028 case AIF1_PB:
2029 case AIF2_PB:
2030 case AIF3_PB:
2031 case AIF4_PB:
2032 if (!rx_slot || !rx_num) {
2033 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2034 rx_slot, rx_num);
2035 return -EINVAL;
2036 }
2037
2038 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2039 rx_slot[i++] = ch->ch_num;
2040
2041 *rx_num = i;
2042 break;
2043 case AIF1_CAP:
2044 case AIF2_CAP:
2045 case AIF3_CAP:
2046 if (!tx_slot || !tx_num) {
2047 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2048 tx_slot, tx_num);
2049 return -EINVAL;
2050 }
2051 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2052 tx_slot[i++] = ch->ch_num;
2053
2054 *tx_num = i;
2055 break;
2056 default:
2057 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2058 break;
2059 }
2060
2061 return 0;
2062 }
2063
2064 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2065 .hw_params = wcd9335_hw_params,
2066 .trigger = wcd9335_trigger,
2067 .set_channel_map = wcd9335_set_channel_map,
2068 .get_channel_map = wcd9335_get_channel_map,
2069 };
2070
2071 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2072 [0] = {
2073 .name = "wcd9335_rx1",
2074 .id = AIF1_PB,
2075 .playback = {
2076 .stream_name = "AIF1 Playback",
2077 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2078 SNDRV_PCM_RATE_384000,
2079 .formats = WCD9335_FORMATS_S16_S24_LE,
2080 .rate_max = 384000,
2081 .rate_min = 8000,
2082 .channels_min = 1,
2083 .channels_max = 2,
2084 },
2085 .ops = &wcd9335_dai_ops,
2086 },
2087 [1] = {
2088 .name = "wcd9335_tx1",
2089 .id = AIF1_CAP,
2090 .capture = {
2091 .stream_name = "AIF1 Capture",
2092 .rates = WCD9335_RATES_MASK,
2093 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2094 .rate_min = 8000,
2095 .rate_max = 192000,
2096 .channels_min = 1,
2097 .channels_max = 4,
2098 },
2099 .ops = &wcd9335_dai_ops,
2100 },
2101 [2] = {
2102 .name = "wcd9335_rx2",
2103 .id = AIF2_PB,
2104 .playback = {
2105 .stream_name = "AIF2 Playback",
2106 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2107 SNDRV_PCM_RATE_384000,
2108 .formats = WCD9335_FORMATS_S16_S24_LE,
2109 .rate_min = 8000,
2110 .rate_max = 384000,
2111 .channels_min = 1,
2112 .channels_max = 2,
2113 },
2114 .ops = &wcd9335_dai_ops,
2115 },
2116 [3] = {
2117 .name = "wcd9335_tx2",
2118 .id = AIF2_CAP,
2119 .capture = {
2120 .stream_name = "AIF2 Capture",
2121 .rates = WCD9335_RATES_MASK,
2122 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2123 .rate_min = 8000,
2124 .rate_max = 192000,
2125 .channels_min = 1,
2126 .channels_max = 4,
2127 },
2128 .ops = &wcd9335_dai_ops,
2129 },
2130 [4] = {
2131 .name = "wcd9335_rx3",
2132 .id = AIF3_PB,
2133 .playback = {
2134 .stream_name = "AIF3 Playback",
2135 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2136 SNDRV_PCM_RATE_384000,
2137 .formats = WCD9335_FORMATS_S16_S24_LE,
2138 .rate_min = 8000,
2139 .rate_max = 384000,
2140 .channels_min = 1,
2141 .channels_max = 2,
2142 },
2143 .ops = &wcd9335_dai_ops,
2144 },
2145 [5] = {
2146 .name = "wcd9335_tx3",
2147 .id = AIF3_CAP,
2148 .capture = {
2149 .stream_name = "AIF3 Capture",
2150 .rates = WCD9335_RATES_MASK,
2151 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2152 .rate_min = 8000,
2153 .rate_max = 192000,
2154 .channels_min = 1,
2155 .channels_max = 4,
2156 },
2157 .ops = &wcd9335_dai_ops,
2158 },
2159 [6] = {
2160 .name = "wcd9335_rx4",
2161 .id = AIF4_PB,
2162 .playback = {
2163 .stream_name = "AIF4 Playback",
2164 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2165 SNDRV_PCM_RATE_384000,
2166 .formats = WCD9335_FORMATS_S16_S24_LE,
2167 .rate_min = 8000,
2168 .rate_max = 384000,
2169 .channels_min = 1,
2170 .channels_max = 2,
2171 },
2172 .ops = &wcd9335_dai_ops,
2173 },
2174 };
2175
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2176 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2177 struct snd_ctl_elem_value *ucontrol)
2178 {
2179
2180 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2181 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2182 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2183
2184 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2185 return 0;
2186 }
2187
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2188 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2189 struct snd_ctl_elem_value *ucontrol)
2190 {
2191 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2192 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2193 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2194 int value = ucontrol->value.integer.value[0];
2195 int sel;
2196
2197 wcd->comp_enabled[comp] = value;
2198 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2199 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2200
2201 /* Any specific register configuration for compander */
2202 switch (comp) {
2203 case COMPANDER_1:
2204 /* Set Gain Source Select based on compander enable/disable */
2205 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2206 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2207 break;
2208 case COMPANDER_2:
2209 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2210 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2211 break;
2212 case COMPANDER_5:
2213 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2214 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2215 break;
2216 case COMPANDER_6:
2217 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2218 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2219 break;
2220 default:
2221 break;
2222 }
2223
2224 return 0;
2225 }
2226
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2227 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2228 struct snd_ctl_elem_value *ucontrol)
2229 {
2230 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2231 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2232
2233 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2234
2235 return 0;
2236 }
2237
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2238 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2239 struct snd_ctl_elem_value *ucontrol)
2240 {
2241 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2242 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2243 u32 mode_val;
2244
2245 mode_val = ucontrol->value.enumerated.item[0];
2246
2247 if (mode_val == 0) {
2248 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2249 mode_val = CLS_H_HIFI;
2250 }
2251 wcd->hph_mode = mode_val;
2252
2253 return 0;
2254 }
2255
2256 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2257 /* -84dB min - 40dB max */
2258 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2259 -84, 40, digital_gain),
2260 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2261 -84, 40, digital_gain),
2262 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2263 -84, 40, digital_gain),
2264 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2265 -84, 40, digital_gain),
2266 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2267 -84, 40, digital_gain),
2268 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2269 -84, 40, digital_gain),
2270 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2271 -84, 40, digital_gain),
2272 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2273 -84, 40, digital_gain),
2274 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2275 -84, 40, digital_gain),
2276 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2277 -84, 40, digital_gain),
2278 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2279 -84, 40, digital_gain),
2280 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2281 -84, 40, digital_gain),
2282 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2283 -84, 40, digital_gain),
2284 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2285 -84, 40, digital_gain),
2286 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2287 -84, 40, digital_gain),
2288 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2289 -84, 40, digital_gain),
2290 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2291 -84, 40, digital_gain),
2292 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2293 -84, 40, digital_gain),
2294 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2295 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2296 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2297 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2298 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2299 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2300 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2301 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2302 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2303 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2304 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2305 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2306 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2307 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2308 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2309 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2310 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2311 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2312 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2313 wcd9335_get_compander, wcd9335_set_compander),
2314 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2315 wcd9335_get_compander, wcd9335_set_compander),
2316 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2317 wcd9335_get_compander, wcd9335_set_compander),
2318 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2319 wcd9335_get_compander, wcd9335_set_compander),
2320 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2321 wcd9335_get_compander, wcd9335_set_compander),
2322 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2323 wcd9335_get_compander, wcd9335_set_compander),
2324 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2325 wcd9335_get_compander, wcd9335_set_compander),
2326 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2327 wcd9335_get_compander, wcd9335_set_compander),
2328 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2329 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2330
2331 /* Gain Controls */
2332 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2333 ear_pa_gain),
2334 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2335 line_gain),
2336 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2337 line_gain),
2338 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2339 3, 16, 1, line_gain),
2340 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2341 3, 16, 1, line_gain),
2342 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2343 line_gain),
2344 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2345 line_gain),
2346
2347 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2348 analog_gain),
2349 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2350 analog_gain),
2351 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2352 analog_gain),
2353 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2354 analog_gain),
2355 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2356 analog_gain),
2357 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2358 analog_gain),
2359
2360 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2361 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2362 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2363 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2364 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2365 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2366 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2367 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2368 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2369 };
2370
2371 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2372 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2373 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2374 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2375 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2376 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2377 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2378 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2379 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2380
2381 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2382 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2383 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2384 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2385 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2386 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2387 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2388 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2389
2390 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2391 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2392 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2393 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2394 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2395 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2396 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2397 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2398
2399 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2400 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2401 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2402 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2403 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2404 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2405 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2406 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2407
2408 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2409 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2410 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2411 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2412 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2413 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2414 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2415 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2416
2417 WCD9335_INTERPOLATOR_PATH(0),
2418 WCD9335_INTERPOLATOR_PATH(1),
2419 WCD9335_INTERPOLATOR_PATH(2),
2420 WCD9335_INTERPOLATOR_PATH(3),
2421 WCD9335_INTERPOLATOR_PATH(4),
2422 WCD9335_INTERPOLATOR_PATH(5),
2423 WCD9335_INTERPOLATOR_PATH(6),
2424 WCD9335_INTERPOLATOR_PATH(7),
2425 WCD9335_INTERPOLATOR_PATH(8),
2426
2427 /* EAR PA */
2428 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2429 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2430 {"RX INT0 DAC", NULL, "RX_BIAS"},
2431 {"EAR PA", NULL, "RX INT0 DAC"},
2432 {"EAR", NULL, "EAR PA"},
2433
2434 /* HPHL */
2435 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2436 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2437 {"RX INT1 DAC", NULL, "RX_BIAS"},
2438 {"HPHL PA", NULL, "RX INT1 DAC"},
2439 {"HPHL", NULL, "HPHL PA"},
2440
2441 /* HPHR */
2442 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2443 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2444 {"RX INT2 DAC", NULL, "RX_BIAS"},
2445 {"HPHR PA", NULL, "RX INT2 DAC"},
2446 {"HPHR", NULL, "HPHR PA"},
2447
2448 /* LINEOUT1 */
2449 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2450 {"RX INT3 DAC", NULL, "RX_BIAS"},
2451 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2452 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2453
2454 /* LINEOUT2 */
2455 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2456 {"RX INT4 DAC", NULL, "RX_BIAS"},
2457 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2458 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2459
2460 /* LINEOUT3 */
2461 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2462 {"RX INT5 DAC", NULL, "RX_BIAS"},
2463 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2464 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2465
2466 /* LINEOUT4 */
2467 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2468 {"RX INT6 DAC", NULL, "RX_BIAS"},
2469 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2470 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2471
2472 /* SLIMBUS Connections */
2473 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2474 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2475 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2476
2477 /* ADC Mux */
2478 WCD9335_ADC_MUX_PATH(0),
2479 WCD9335_ADC_MUX_PATH(1),
2480 WCD9335_ADC_MUX_PATH(2),
2481 WCD9335_ADC_MUX_PATH(3),
2482 WCD9335_ADC_MUX_PATH(4),
2483 WCD9335_ADC_MUX_PATH(5),
2484 WCD9335_ADC_MUX_PATH(6),
2485 WCD9335_ADC_MUX_PATH(7),
2486 WCD9335_ADC_MUX_PATH(8),
2487
2488 /* ADC Connections */
2489 {"ADC1", NULL, "AMIC1"},
2490 {"ADC2", NULL, "AMIC2"},
2491 {"ADC3", NULL, "AMIC3"},
2492 {"ADC4", NULL, "AMIC4"},
2493 {"ADC5", NULL, "AMIC5"},
2494 {"ADC6", NULL, "AMIC6"},
2495 };
2496
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2497 static int wcd9335_micbias_control(struct snd_soc_component *component,
2498 int micb_num, int req, bool is_dapm)
2499 {
2500 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2501 int micb_index = micb_num - 1;
2502 u16 micb_reg;
2503
2504 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2505 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2506 micb_index);
2507 return -EINVAL;
2508 }
2509
2510 switch (micb_num) {
2511 case MIC_BIAS_1:
2512 micb_reg = WCD9335_ANA_MICB1;
2513 break;
2514 case MIC_BIAS_2:
2515 micb_reg = WCD9335_ANA_MICB2;
2516 break;
2517 case MIC_BIAS_3:
2518 micb_reg = WCD9335_ANA_MICB3;
2519 break;
2520 case MIC_BIAS_4:
2521 micb_reg = WCD9335_ANA_MICB4;
2522 break;
2523 default:
2524 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2525 __func__, micb_num);
2526 return -EINVAL;
2527 }
2528
2529 switch (req) {
2530 case MICB_PULLUP_ENABLE:
2531 wcd->pullup_ref[micb_index]++;
2532 if ((wcd->pullup_ref[micb_index] == 1) &&
2533 (wcd->micb_ref[micb_index] == 0))
2534 snd_soc_component_update_bits(component, micb_reg,
2535 0xC0, 0x80);
2536 break;
2537 case MICB_PULLUP_DISABLE:
2538 wcd->pullup_ref[micb_index]--;
2539 if ((wcd->pullup_ref[micb_index] == 0) &&
2540 (wcd->micb_ref[micb_index] == 0))
2541 snd_soc_component_update_bits(component, micb_reg,
2542 0xC0, 0x00);
2543 break;
2544 case MICB_ENABLE:
2545 wcd->micb_ref[micb_index]++;
2546 if (wcd->micb_ref[micb_index] == 1)
2547 snd_soc_component_update_bits(component, micb_reg,
2548 0xC0, 0x40);
2549 break;
2550 case MICB_DISABLE:
2551 wcd->micb_ref[micb_index]--;
2552 if ((wcd->micb_ref[micb_index] == 0) &&
2553 (wcd->pullup_ref[micb_index] > 0))
2554 snd_soc_component_update_bits(component, micb_reg,
2555 0xC0, 0x80);
2556 else if ((wcd->micb_ref[micb_index] == 0) &&
2557 (wcd->pullup_ref[micb_index] == 0)) {
2558 snd_soc_component_update_bits(component, micb_reg,
2559 0xC0, 0x00);
2560 }
2561 break;
2562 }
2563
2564 return 0;
2565 }
2566
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2567 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2568 int event)
2569 {
2570 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2571 int micb_num;
2572
2573 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2574 micb_num = MIC_BIAS_1;
2575 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2576 micb_num = MIC_BIAS_2;
2577 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2578 micb_num = MIC_BIAS_3;
2579 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2580 micb_num = MIC_BIAS_4;
2581 else
2582 return -EINVAL;
2583
2584 switch (event) {
2585 case SND_SOC_DAPM_PRE_PMU:
2586 /*
2587 * MIC BIAS can also be requested by MBHC,
2588 * so use ref count to handle micbias pullup
2589 * and enable requests
2590 */
2591 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2592 break;
2593 case SND_SOC_DAPM_POST_PMU:
2594 /* wait for cnp time */
2595 usleep_range(1000, 1100);
2596 break;
2597 case SND_SOC_DAPM_POST_PMD:
2598 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2599 break;
2600 }
2601
2602 return 0;
2603 }
2604
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2605 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2606 struct snd_kcontrol *kc, int event)
2607 {
2608 return __wcd9335_codec_enable_micbias(w, event);
2609 }
2610
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2611 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2612 u16 amic_reg, bool set)
2613 {
2614 u8 mask = 0x20;
2615 u8 val;
2616
2617 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2618 amic_reg == WCD9335_ANA_AMIC5)
2619 mask = 0x40;
2620
2621 val = set ? mask : 0x00;
2622
2623 switch (amic_reg) {
2624 case WCD9335_ANA_AMIC1:
2625 case WCD9335_ANA_AMIC2:
2626 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2627 val);
2628 break;
2629 case WCD9335_ANA_AMIC3:
2630 case WCD9335_ANA_AMIC4:
2631 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2632 val);
2633 break;
2634 case WCD9335_ANA_AMIC5:
2635 case WCD9335_ANA_AMIC6:
2636 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2637 val);
2638 break;
2639 default:
2640 dev_err(comp->dev, "%s: invalid amic: %d\n",
2641 __func__, amic_reg);
2642 break;
2643 }
2644 }
2645
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2646 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2647 struct snd_kcontrol *kc, int event)
2648 {
2649 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2650
2651 switch (event) {
2652 case SND_SOC_DAPM_PRE_PMU:
2653 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2654 break;
2655 default:
2656 break;
2657 }
2658
2659 return 0;
2660 }
2661
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2662 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2663 int adc_mux_n)
2664 {
2665 int mux_sel, reg, mreg;
2666
2667 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2668 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2669 return 0;
2670
2671 /* Check whether adc mux input is AMIC or DMIC */
2672 if (adc_mux_n < 4) {
2673 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2674 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2675 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2676 } else {
2677 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2678 mreg = reg;
2679 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2680 }
2681
2682 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2683 return 0;
2684
2685 return snd_soc_component_read(comp, mreg) & 0x07;
2686 }
2687
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2688 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2689 int amic)
2690 {
2691 u16 pwr_level_reg = 0;
2692
2693 switch (amic) {
2694 case 1:
2695 case 2:
2696 pwr_level_reg = WCD9335_ANA_AMIC1;
2697 break;
2698
2699 case 3:
2700 case 4:
2701 pwr_level_reg = WCD9335_ANA_AMIC3;
2702 break;
2703
2704 case 5:
2705 case 6:
2706 pwr_level_reg = WCD9335_ANA_AMIC5;
2707 break;
2708 default:
2709 dev_err(comp->dev, "invalid amic: %d\n", amic);
2710 break;
2711 }
2712
2713 return pwr_level_reg;
2714 }
2715
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2716 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2717 struct snd_kcontrol *kc, int event)
2718 {
2719 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2720 unsigned int decimator;
2721 char *dec_adc_mux_name = NULL;
2722 char *widget_name;
2723 int ret = 0, amic_n;
2724 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2725 u16 tx_gain_ctl_reg;
2726 char *dec;
2727 u8 hpf_coff_freq;
2728
2729 char *wname __free(kfree) = kmemdup_nul(w->name, 15, GFP_KERNEL);
2730 if (!wname)
2731 return -ENOMEM;
2732
2733 widget_name = wname;
2734 dec_adc_mux_name = strsep(&widget_name, " ");
2735 if (!dec_adc_mux_name) {
2736 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2737 __func__, w->name);
2738 return -EINVAL;
2739 }
2740 dec_adc_mux_name = widget_name;
2741
2742 dec = strpbrk(dec_adc_mux_name, "012345678");
2743 if (!dec) {
2744 dev_err(comp->dev, "%s: decimator index not found\n",
2745 __func__);
2746 return -EINVAL;
2747 }
2748
2749 ret = kstrtouint(dec, 10, &decimator);
2750 if (ret < 0) {
2751 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2752 __func__, wname);
2753 return -EINVAL;
2754 }
2755
2756 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2757 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2758 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2759 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2760
2761 switch (event) {
2762 case SND_SOC_DAPM_PRE_PMU:
2763 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2764 if (amic_n)
2765 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2766 amic_n);
2767
2768 if (pwr_level_reg) {
2769 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2770 WCD9335_AMIC_PWR_LVL_MASK) >>
2771 WCD9335_AMIC_PWR_LVL_SHIFT) {
2772 case WCD9335_AMIC_PWR_LEVEL_LP:
2773 snd_soc_component_update_bits(comp, dec_cfg_reg,
2774 WCD9335_DEC_PWR_LVL_MASK,
2775 WCD9335_DEC_PWR_LVL_LP);
2776 break;
2777
2778 case WCD9335_AMIC_PWR_LEVEL_HP:
2779 snd_soc_component_update_bits(comp, dec_cfg_reg,
2780 WCD9335_DEC_PWR_LVL_MASK,
2781 WCD9335_DEC_PWR_LVL_HP);
2782 break;
2783 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2784 default:
2785 snd_soc_component_update_bits(comp, dec_cfg_reg,
2786 WCD9335_DEC_PWR_LVL_MASK,
2787 WCD9335_DEC_PWR_LVL_DF);
2788 break;
2789 }
2790 }
2791 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2792 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2793
2794 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2795 snd_soc_component_update_bits(comp, dec_cfg_reg,
2796 TX_HPF_CUT_OFF_FREQ_MASK,
2797 CF_MIN_3DB_150HZ << 5);
2798 /* Enable TX PGA Mute */
2799 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2800 0x10, 0x10);
2801 /* Enable APC */
2802 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2803 break;
2804 case SND_SOC_DAPM_POST_PMU:
2805 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2806
2807 if (decimator == 0) {
2808 snd_soc_component_write(comp,
2809 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2810 snd_soc_component_write(comp,
2811 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2812 snd_soc_component_write(comp,
2813 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2814 snd_soc_component_write(comp,
2815 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2816 }
2817
2818 snd_soc_component_update_bits(comp, hpf_gate_reg,
2819 0x01, 0x01);
2820 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2821 0x10, 0x00);
2822 snd_soc_component_write(comp, tx_gain_ctl_reg,
2823 snd_soc_component_read(comp, tx_gain_ctl_reg));
2824 break;
2825 case SND_SOC_DAPM_PRE_PMD:
2826 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2827 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2828 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2829 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2830 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2831 snd_soc_component_update_bits(comp, dec_cfg_reg,
2832 TX_HPF_CUT_OFF_FREQ_MASK,
2833 hpf_coff_freq << 5);
2834 }
2835 break;
2836 case SND_SOC_DAPM_POST_PMD:
2837 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2838 break;
2839 }
2840
2841 return ret;
2842 }
2843
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate)2844 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2845 u32 mclk_rate)
2846 {
2847 u8 dmic_ctl_val;
2848
2849 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2850 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2851 else
2852 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2853
2854 return dmic_ctl_val;
2855 }
2856
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2857 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2858 struct snd_kcontrol *kc, int event)
2859 {
2860 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2861 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2862 u8 dmic_clk_en = 0x01;
2863 u16 dmic_clk_reg;
2864 s32 *dmic_clk_cnt;
2865 u8 dmic_rate_val, dmic_rate_shift = 1;
2866 unsigned int dmic;
2867 int ret;
2868 char *wname;
2869
2870 wname = strpbrk(w->name, "012345");
2871 if (!wname) {
2872 dev_err(comp->dev, "%s: widget not found\n", __func__);
2873 return -EINVAL;
2874 }
2875
2876 ret = kstrtouint(wname, 10, &dmic);
2877 if (ret < 0) {
2878 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2879 __func__);
2880 return -EINVAL;
2881 }
2882
2883 switch (dmic) {
2884 case 0:
2885 case 1:
2886 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2887 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2888 break;
2889 case 2:
2890 case 3:
2891 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2892 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2893 break;
2894 case 4:
2895 case 5:
2896 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2897 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2898 break;
2899 default:
2900 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2901 __func__);
2902 return -EINVAL;
2903 }
2904
2905 switch (event) {
2906 case SND_SOC_DAPM_PRE_PMU:
2907 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2908 (*dmic_clk_cnt)++;
2909 if (*dmic_clk_cnt == 1) {
2910 snd_soc_component_update_bits(comp, dmic_clk_reg,
2911 0x07 << dmic_rate_shift,
2912 dmic_rate_val << dmic_rate_shift);
2913 snd_soc_component_update_bits(comp, dmic_clk_reg,
2914 dmic_clk_en, dmic_clk_en);
2915 }
2916
2917 break;
2918 case SND_SOC_DAPM_POST_PMD:
2919 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2920 (*dmic_clk_cnt)--;
2921 if (*dmic_clk_cnt == 0) {
2922 snd_soc_component_update_bits(comp, dmic_clk_reg,
2923 dmic_clk_en, 0);
2924 snd_soc_component_update_bits(comp, dmic_clk_reg,
2925 0x07 << dmic_rate_shift,
2926 dmic_rate_val << dmic_rate_shift);
2927 }
2928 break;
2929 }
2930
2931 return 0;
2932 }
2933
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2934 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2935 struct snd_soc_component *component)
2936 {
2937 int port_num = 0;
2938 unsigned short reg = 0;
2939 unsigned int val = 0;
2940 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2941 struct wcd9335_slim_ch *ch;
2942
2943 list_for_each_entry(ch, &dai->slim_ch_list, list) {
2944 if (ch->port >= WCD9335_RX_START) {
2945 port_num = ch->port - WCD9335_RX_START;
2946 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
2947 } else {
2948 port_num = ch->port;
2949 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
2950 }
2951
2952 regmap_read(wcd->if_regmap, reg, &val);
2953 if (!(val & BIT(port_num % 8)))
2954 regmap_write(wcd->if_regmap, reg,
2955 val | BIT(port_num % 8));
2956 }
2957 }
2958
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2959 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
2960 struct snd_kcontrol *kc,
2961 int event)
2962 {
2963 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2964 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2965 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
2966
2967 switch (event) {
2968 case SND_SOC_DAPM_POST_PMU:
2969 wcd9335_codec_enable_int_port(dai, comp);
2970 break;
2971 case SND_SOC_DAPM_POST_PMD:
2972 kfree(dai->sconfig.chs);
2973
2974 break;
2975 }
2976
2977 return 0;
2978 }
2979
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2980 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
2981 struct snd_kcontrol *kc, int event)
2982 {
2983 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2984 u16 gain_reg;
2985 int val = 0;
2986
2987 switch (w->reg) {
2988 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
2989 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
2990 break;
2991 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
2992 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
2993 break;
2994 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
2995 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
2996 break;
2997 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
2998 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
2999 break;
3000 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3001 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3002 break;
3003 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3004 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3005 break;
3006 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3007 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3008 break;
3009 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3010 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3011 break;
3012 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3013 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3014 break;
3015 default:
3016 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3017 __func__, w->name);
3018 return 0;
3019 }
3020
3021 switch (event) {
3022 case SND_SOC_DAPM_POST_PMU:
3023 val = snd_soc_component_read(comp, gain_reg);
3024 snd_soc_component_write(comp, gain_reg, val);
3025 break;
3026 case SND_SOC_DAPM_POST_PMD:
3027 break;
3028 }
3029
3030 return 0;
3031 }
3032
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3033 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3034 {
3035 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3036
3037 switch (reg) {
3038 case WCD9335_CDC_RX0_RX_PATH_CTL:
3039 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3040 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3041 *ind = 0;
3042 break;
3043 case WCD9335_CDC_RX1_RX_PATH_CTL:
3044 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3045 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3046 *ind = 1;
3047 break;
3048 case WCD9335_CDC_RX2_RX_PATH_CTL:
3049 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3050 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3051 *ind = 2;
3052 break;
3053 case WCD9335_CDC_RX3_RX_PATH_CTL:
3054 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3055 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3056 *ind = 3;
3057 break;
3058 case WCD9335_CDC_RX4_RX_PATH_CTL:
3059 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3060 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3061 *ind = 4;
3062 break;
3063 case WCD9335_CDC_RX5_RX_PATH_CTL:
3064 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3065 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3066 *ind = 5;
3067 break;
3068 case WCD9335_CDC_RX6_RX_PATH_CTL:
3069 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3070 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3071 *ind = 6;
3072 break;
3073 case WCD9335_CDC_RX7_RX_PATH_CTL:
3074 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3075 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3076 *ind = 7;
3077 break;
3078 case WCD9335_CDC_RX8_RX_PATH_CTL:
3079 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3080 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3081 *ind = 8;
3082 break;
3083 }
3084
3085 return prim_int_reg;
3086 }
3087
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3088 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3089 u16 prim_int_reg, int event)
3090 {
3091 u16 hd2_scale_reg;
3092 u16 hd2_enable_reg = 0;
3093
3094 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3095 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3096 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3097 }
3098 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3099 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3100 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3101 }
3102
3103 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3104 snd_soc_component_update_bits(component, hd2_scale_reg,
3105 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3106 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3107 snd_soc_component_update_bits(component, hd2_scale_reg,
3108 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3109 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3110 snd_soc_component_update_bits(component, hd2_enable_reg,
3111 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3112 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3113 }
3114
3115 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3116 snd_soc_component_update_bits(component, hd2_enable_reg,
3117 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3118 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3119 snd_soc_component_update_bits(component, hd2_scale_reg,
3120 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3121 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3122 snd_soc_component_update_bits(component, hd2_scale_reg,
3123 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3124 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3125 }
3126 }
3127
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3128 static int wcd9335_codec_enable_prim_interpolator(
3129 struct snd_soc_component *comp,
3130 u16 reg, int event)
3131 {
3132 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3133 u16 ind = 0;
3134 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3135
3136 switch (event) {
3137 case SND_SOC_DAPM_PRE_PMU:
3138 wcd->prim_int_users[ind]++;
3139 if (wcd->prim_int_users[ind] == 1) {
3140 snd_soc_component_update_bits(comp, prim_int_reg,
3141 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3142 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3143 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3144 snd_soc_component_update_bits(comp, prim_int_reg,
3145 WCD9335_CDC_RX_CLK_EN_MASK,
3146 WCD9335_CDC_RX_CLK_ENABLE);
3147 }
3148
3149 if ((reg != prim_int_reg) &&
3150 ((snd_soc_component_read(comp, prim_int_reg)) &
3151 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3152 snd_soc_component_update_bits(comp, reg,
3153 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3154 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3155 break;
3156 case SND_SOC_DAPM_POST_PMD:
3157 wcd->prim_int_users[ind]--;
3158 if (wcd->prim_int_users[ind] == 0) {
3159 snd_soc_component_update_bits(comp, prim_int_reg,
3160 WCD9335_CDC_RX_CLK_EN_MASK,
3161 WCD9335_CDC_RX_CLK_DISABLE);
3162 snd_soc_component_update_bits(comp, prim_int_reg,
3163 WCD9335_CDC_RX_RESET_MASK,
3164 WCD9335_CDC_RX_RESET_ENABLE);
3165 snd_soc_component_update_bits(comp, prim_int_reg,
3166 WCD9335_CDC_RX_RESET_MASK,
3167 WCD9335_CDC_RX_RESET_DISABLE);
3168 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3169 }
3170 break;
3171 }
3172
3173 return 0;
3174 }
3175
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3176 static int wcd9335_config_compander(struct snd_soc_component *component,
3177 int interp_n, int event)
3178 {
3179 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3180 int comp;
3181 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3182
3183 /* EAR does not have compander */
3184 if (!interp_n)
3185 return 0;
3186
3187 comp = interp_n - 1;
3188 if (!wcd->comp_enabled[comp])
3189 return 0;
3190
3191 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3192 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3193
3194 if (SND_SOC_DAPM_EVENT_ON(event)) {
3195 /* Enable Compander Clock */
3196 snd_soc_component_update_bits(component, comp_ctl0_reg,
3197 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3198 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3199 /* Reset comander */
3200 snd_soc_component_update_bits(component, comp_ctl0_reg,
3201 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3202 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3203 snd_soc_component_update_bits(component, comp_ctl0_reg,
3204 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3205 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3206 /* Enables DRE in this path */
3207 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3208 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3209 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3210 }
3211
3212 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3213 snd_soc_component_update_bits(component, comp_ctl0_reg,
3214 WCD9335_CDC_COMPANDER_HALT_MASK,
3215 WCD9335_CDC_COMPANDER_HALT);
3216 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3217 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3218 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3219
3220 snd_soc_component_update_bits(component, comp_ctl0_reg,
3221 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3222 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3223 snd_soc_component_update_bits(component, comp_ctl0_reg,
3224 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3225 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3226 snd_soc_component_update_bits(component, comp_ctl0_reg,
3227 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3228 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3229 snd_soc_component_update_bits(component, comp_ctl0_reg,
3230 WCD9335_CDC_COMPANDER_HALT_MASK,
3231 WCD9335_CDC_COMPANDER_NOHALT);
3232 }
3233
3234 return 0;
3235 }
3236
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3237 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3238 struct snd_kcontrol *kc, int event)
3239 {
3240 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3241 u16 gain_reg;
3242 u16 reg;
3243 int val;
3244
3245 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) {
3246 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3247 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3248 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) {
3249 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3250 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3251 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) {
3252 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3253 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3254 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) {
3255 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3256 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3257 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) {
3258 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3259 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3260 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) {
3261 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3262 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3263 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) {
3264 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3265 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3266 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) {
3267 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3268 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3269 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) {
3270 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3271 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3272 } else {
3273 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3274 __func__);
3275 return -EINVAL;
3276 }
3277
3278 switch (event) {
3279 case SND_SOC_DAPM_PRE_PMU:
3280 /* Reset if needed */
3281 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3282 break;
3283 case SND_SOC_DAPM_POST_PMU:
3284 wcd9335_config_compander(comp, w->shift, event);
3285 val = snd_soc_component_read(comp, gain_reg);
3286 snd_soc_component_write(comp, gain_reg, val);
3287 break;
3288 case SND_SOC_DAPM_POST_PMD:
3289 wcd9335_config_compander(comp, w->shift, event);
3290 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3291 break;
3292 }
3293
3294 return 0;
3295 }
3296
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3297 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3298 u8 gain)
3299 {
3300 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3301 u8 hph_l_en, hph_r_en;
3302 u8 l_val, r_val;
3303 u8 hph_pa_status;
3304 bool is_hphl_pa, is_hphr_pa;
3305
3306 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3307 is_hphl_pa = hph_pa_status >> 7;
3308 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3309
3310 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3311 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3312
3313 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3314 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3315
3316 /*
3317 * Set HPH_L & HPH_R gain source selection to REGISTER
3318 * for better click and pop only if corresponding PAs are
3319 * not enabled. Also cache the values of the HPHL/R
3320 * PA gains to be applied after PAs are enabled
3321 */
3322 if ((l_val != hph_l_en) && !is_hphl_pa) {
3323 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3324 wcd->hph_l_gain = hph_l_en & 0x1F;
3325 }
3326
3327 if ((r_val != hph_r_en) && !is_hphr_pa) {
3328 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3329 wcd->hph_r_gain = hph_r_en & 0x1F;
3330 }
3331 }
3332
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3333 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3334 int event)
3335 {
3336 if (SND_SOC_DAPM_EVENT_ON(event)) {
3337 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3338 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3339 0x06);
3340 snd_soc_component_update_bits(comp,
3341 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3342 0xF0, 0x40);
3343 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3344 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3345 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3346 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3347 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3348 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3349 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3350 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3351 0x0C);
3352 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3353 }
3354
3355 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3356 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3357 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3358 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3359 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3360 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3361 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3362 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3363 0x8A);
3364 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3365 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3366 0x0A);
3367 }
3368 }
3369
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3370 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3371 int event)
3372 {
3373 if (SND_SOC_DAPM_EVENT_ON(event)) {
3374 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3375 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3376 0x0C);
3377 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3378 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3379 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3380 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3381 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3382 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3383 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3384 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3385 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3386 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3387 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3388 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3389 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3390 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3391 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3392 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3393 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3394 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3395 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3396 snd_soc_component_update_bits(comp,
3397 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3398 snd_soc_component_update_bits(comp,
3399 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3400 }
3401
3402 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3403 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3404 0x88);
3405 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3406 0x33);
3407 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3408 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3409 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3410 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3411 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3412 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3413 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3414 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3415 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3416 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3417 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3418 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3419 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3420 WCD9335_HPH_CONST_SEL_L_MASK,
3421 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3422 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3423 WCD9335_HPH_CONST_SEL_L_MASK,
3424 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3425 }
3426 }
3427
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3428 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3429 int event)
3430 {
3431 if (SND_SOC_DAPM_EVENT_ON(event)) {
3432 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3433 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3434 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3435 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3436 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3437 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3438 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3439 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3440 0x0C);
3441 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3442 }
3443
3444 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3445 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3446 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3447 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3448 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3449 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3450 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3451 }
3452 }
3453
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3454 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3455 int event, int mode)
3456 {
3457 switch (mode) {
3458 case CLS_H_LP:
3459 wcd9335_codec_hph_lp_config(component, event);
3460 break;
3461 case CLS_H_LOHIFI:
3462 wcd9335_codec_hph_lohifi_config(component, event);
3463 break;
3464 case CLS_H_HIFI:
3465 wcd9335_codec_hph_hifi_config(component, event);
3466 break;
3467 }
3468 }
3469
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3470 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3471 struct snd_kcontrol *kc,
3472 int event)
3473 {
3474 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3475 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3476 int hph_mode = wcd->hph_mode;
3477 u8 dem_inp;
3478
3479 switch (event) {
3480 case SND_SOC_DAPM_PRE_PMU:
3481 /* Read DEM INP Select */
3482 dem_inp = snd_soc_component_read(comp,
3483 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3484 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3485 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3486 dev_err(comp->dev, "Incorrect DEM Input\n");
3487 return -EINVAL;
3488 }
3489 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3490 WCD_CLSH_STATE_HPHL,
3491 ((hph_mode == CLS_H_LOHIFI) ?
3492 CLS_H_HIFI : hph_mode));
3493
3494 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3495
3496 break;
3497 case SND_SOC_DAPM_POST_PMU:
3498 usleep_range(1000, 1100);
3499 break;
3500 case SND_SOC_DAPM_PRE_PMD:
3501 break;
3502 case SND_SOC_DAPM_POST_PMD:
3503 /* 1000us required as per HW requirement */
3504 usleep_range(1000, 1100);
3505
3506 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3507 WCD_CLSH_STATE_HPHR))
3508 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3509
3510 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3511 WCD_CLSH_STATE_HPHL,
3512 ((hph_mode == CLS_H_LOHIFI) ?
3513 CLS_H_HIFI : hph_mode));
3514 break;
3515 }
3516
3517 return 0;
3518 }
3519
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3520 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3521 struct snd_kcontrol *kc, int event)
3522 {
3523 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3524 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3525
3526 switch (event) {
3527 case SND_SOC_DAPM_PRE_PMU:
3528 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3529 WCD_CLSH_STATE_LO, CLS_AB);
3530 break;
3531 case SND_SOC_DAPM_POST_PMD:
3532 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3533 WCD_CLSH_STATE_LO, CLS_AB);
3534 break;
3535 }
3536
3537 return 0;
3538 }
3539
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3540 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3541 struct snd_kcontrol *kc, int event)
3542 {
3543 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3544 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3545
3546 switch (event) {
3547 case SND_SOC_DAPM_PRE_PMU:
3548 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3549 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3550
3551 break;
3552 case SND_SOC_DAPM_POST_PMD:
3553 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3554 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3555 break;
3556 }
3557
3558 return 0;
3559 }
3560
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3561 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3562 int mode, int event)
3563 {
3564 u8 scale_val = 0;
3565
3566 switch (event) {
3567 case SND_SOC_DAPM_POST_PMU:
3568 switch (mode) {
3569 case CLS_H_HIFI:
3570 scale_val = 0x3;
3571 break;
3572 case CLS_H_LOHIFI:
3573 scale_val = 0x1;
3574 break;
3575 }
3576 break;
3577 case SND_SOC_DAPM_PRE_PMD:
3578 scale_val = 0x6;
3579 break;
3580 }
3581
3582 if (scale_val)
3583 snd_soc_component_update_bits(wcd->component,
3584 WCD9335_HPH_PA_CTL1,
3585 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3586 scale_val << 1);
3587 if (SND_SOC_DAPM_EVENT_ON(event)) {
3588 if (wcd->comp_enabled[COMPANDER_1] ||
3589 wcd->comp_enabled[COMPANDER_2]) {
3590 /* GAIN Source Selection */
3591 snd_soc_component_update_bits(wcd->component,
3592 WCD9335_HPH_L_EN,
3593 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3594 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3595 snd_soc_component_update_bits(wcd->component,
3596 WCD9335_HPH_R_EN,
3597 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3598 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3599 snd_soc_component_update_bits(wcd->component,
3600 WCD9335_HPH_AUTO_CHOP,
3601 WCD9335_HPH_AUTO_CHOP_MASK,
3602 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3603 }
3604 snd_soc_component_update_bits(wcd->component,
3605 WCD9335_HPH_L_EN,
3606 WCD9335_HPH_PA_GAIN_MASK,
3607 wcd->hph_l_gain);
3608 snd_soc_component_update_bits(wcd->component,
3609 WCD9335_HPH_R_EN,
3610 WCD9335_HPH_PA_GAIN_MASK,
3611 wcd->hph_r_gain);
3612 }
3613
3614 if (SND_SOC_DAPM_EVENT_OFF(event))
3615 snd_soc_component_update_bits(wcd->component,
3616 WCD9335_HPH_AUTO_CHOP,
3617 WCD9335_HPH_AUTO_CHOP_MASK,
3618 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3619 }
3620
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3621 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3622 struct snd_kcontrol *kc,
3623 int event)
3624 {
3625 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3626 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3627 int hph_mode = wcd->hph_mode;
3628 u8 dem_inp;
3629
3630 switch (event) {
3631 case SND_SOC_DAPM_PRE_PMU:
3632
3633 /* Read DEM INP Select */
3634 dem_inp = snd_soc_component_read(comp,
3635 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3636 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3637 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3638 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3639 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3640 hph_mode);
3641 return -EINVAL;
3642 }
3643
3644 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3645 WCD_CLSH_EVENT_PRE_DAC,
3646 WCD_CLSH_STATE_HPHR,
3647 ((hph_mode == CLS_H_LOHIFI) ?
3648 CLS_H_HIFI : hph_mode));
3649
3650 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3651
3652 break;
3653 case SND_SOC_DAPM_POST_PMD:
3654 /* 1000us required as per HW requirement */
3655 usleep_range(1000, 1100);
3656
3657 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3658 WCD_CLSH_STATE_HPHL))
3659 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3660
3661 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3662 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3663 CLS_H_HIFI : hph_mode));
3664 break;
3665 }
3666
3667 return 0;
3668 }
3669
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3670 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3671 struct snd_kcontrol *kc,
3672 int event)
3673 {
3674 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3675 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3676 int hph_mode = wcd->hph_mode;
3677
3678 switch (event) {
3679 case SND_SOC_DAPM_PRE_PMU:
3680 break;
3681 case SND_SOC_DAPM_POST_PMU:
3682 /*
3683 * 7ms sleep is required after PA is enabled as per
3684 * HW requirement
3685 */
3686 usleep_range(7000, 7100);
3687
3688 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3689 snd_soc_component_update_bits(comp,
3690 WCD9335_CDC_RX1_RX_PATH_CTL,
3691 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3692 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3693
3694 /* Remove mix path mute if it is enabled */
3695 if ((snd_soc_component_read(comp,
3696 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3697 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3698 snd_soc_component_update_bits(comp,
3699 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3700 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3701 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3702
3703 break;
3704 case SND_SOC_DAPM_PRE_PMD:
3705 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3706 break;
3707 case SND_SOC_DAPM_POST_PMD:
3708 /* 5ms sleep is required after PA is disabled as per
3709 * HW requirement
3710 */
3711 usleep_range(5000, 5500);
3712 break;
3713 }
3714
3715 return 0;
3716 }
3717
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3718 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3719 struct snd_kcontrol *kc,
3720 int event)
3721 {
3722 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3723 int vol_reg = 0, mix_vol_reg = 0;
3724
3725 if (w->reg == WCD9335_ANA_LO_1_2) {
3726 if (w->shift == 7) {
3727 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3728 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3729 } else if (w->shift == 6) {
3730 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3731 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3732 }
3733 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3734 if (w->shift == 7) {
3735 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3736 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3737 } else if (w->shift == 6) {
3738 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3739 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3740 }
3741 } else {
3742 dev_err(comp->dev, "Error enabling lineout PA\n");
3743 return -EINVAL;
3744 }
3745
3746 switch (event) {
3747 case SND_SOC_DAPM_POST_PMU:
3748 /* 5ms sleep is required after PA is enabled as per
3749 * HW requirement
3750 */
3751 usleep_range(5000, 5500);
3752 snd_soc_component_update_bits(comp, vol_reg,
3753 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3754 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3755
3756 /* Remove mix path mute if it is enabled */
3757 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3758 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3759 snd_soc_component_update_bits(comp, mix_vol_reg,
3760 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3761 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3762 break;
3763 case SND_SOC_DAPM_POST_PMD:
3764 /* 5ms sleep is required after PA is disabled as per
3765 * HW requirement
3766 */
3767 usleep_range(5000, 5500);
3768 break;
3769 }
3770
3771 return 0;
3772 }
3773
wcd9335_codec_init_flyback(struct snd_soc_component * component)3774 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3775 {
3776 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3777 WCD9335_HPH_CONST_SEL_L_MASK,
3778 WCD9335_HPH_CONST_SEL_L_BYPASS);
3779 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3780 WCD9335_HPH_CONST_SEL_L_MASK,
3781 WCD9335_HPH_CONST_SEL_L_BYPASS);
3782 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3783 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3784 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3785 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3786 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3787 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3788 }
3789
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3790 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3791 struct snd_kcontrol *kc, int event)
3792 {
3793 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3794 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3795
3796 switch (event) {
3797 case SND_SOC_DAPM_PRE_PMU:
3798 wcd->rx_bias_count++;
3799 if (wcd->rx_bias_count == 1) {
3800 wcd9335_codec_init_flyback(comp);
3801 snd_soc_component_update_bits(comp,
3802 WCD9335_ANA_RX_SUPPLIES,
3803 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3804 WCD9335_ANA_RX_BIAS_ENABLE);
3805 }
3806 break;
3807 case SND_SOC_DAPM_POST_PMD:
3808 wcd->rx_bias_count--;
3809 if (!wcd->rx_bias_count)
3810 snd_soc_component_update_bits(comp,
3811 WCD9335_ANA_RX_SUPPLIES,
3812 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3813 WCD9335_ANA_RX_BIAS_DISABLE);
3814 break;
3815 }
3816
3817 return 0;
3818 }
3819
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3820 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3821 struct snd_kcontrol *kc, int event)
3822 {
3823 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3824 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3825 int hph_mode = wcd->hph_mode;
3826
3827 switch (event) {
3828 case SND_SOC_DAPM_PRE_PMU:
3829 break;
3830 case SND_SOC_DAPM_POST_PMU:
3831 /*
3832 * 7ms sleep is required after PA is enabled as per
3833 * HW requirement
3834 */
3835 usleep_range(7000, 7100);
3836 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3837 snd_soc_component_update_bits(comp,
3838 WCD9335_CDC_RX2_RX_PATH_CTL,
3839 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3840 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3841 /* Remove mix path mute if it is enabled */
3842 if ((snd_soc_component_read(comp,
3843 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3844 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3845 snd_soc_component_update_bits(comp,
3846 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3847 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3848 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3849
3850 break;
3851
3852 case SND_SOC_DAPM_PRE_PMD:
3853 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3854 break;
3855 case SND_SOC_DAPM_POST_PMD:
3856 /* 5ms sleep is required after PA is disabled as per
3857 * HW requirement
3858 */
3859 usleep_range(5000, 5500);
3860 break;
3861 }
3862
3863 return 0;
3864 }
3865
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3866 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3867 struct snd_kcontrol *kc, int event)
3868 {
3869 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3870
3871 switch (event) {
3872 case SND_SOC_DAPM_POST_PMU:
3873 /* 5ms sleep is required after PA is enabled as per
3874 * HW requirement
3875 */
3876 usleep_range(5000, 5500);
3877 snd_soc_component_update_bits(comp,
3878 WCD9335_CDC_RX0_RX_PATH_CTL,
3879 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3880 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3881 /* Remove mix path mute if it is enabled */
3882 if ((snd_soc_component_read(comp,
3883 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3884 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3885 snd_soc_component_update_bits(comp,
3886 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3887 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3888 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3889 break;
3890 case SND_SOC_DAPM_POST_PMD:
3891 /* 5ms sleep is required after PA is disabled as per
3892 * HW requirement
3893 */
3894 usleep_range(5000, 5500);
3895
3896 break;
3897 }
3898
3899 return 0;
3900 }
3901
wcd9335_slimbus_irq(int irq,void * data)3902 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3903 {
3904 struct wcd9335_codec *wcd = data;
3905 unsigned long status = 0;
3906 int i, j, port_id;
3907 unsigned int val, int_val = 0;
3908 irqreturn_t ret = IRQ_NONE;
3909 bool tx;
3910 unsigned short reg = 0;
3911
3912 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3913 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3914 regmap_read(wcd->if_regmap, i, &val);
3915 status |= ((u32)val << (8 * j));
3916 }
3917
3918 for_each_set_bit(j, &status, 32) {
3919 tx = (j >= 16);
3920 port_id = (tx ? j - 16 : j);
3921 regmap_read(wcd->if_regmap,
3922 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3923 if (val) {
3924 if (!tx)
3925 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3926 (port_id / 8);
3927 else
3928 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3929 (port_id / 8);
3930 regmap_read(
3931 wcd->if_regmap, reg, &int_val);
3932 /*
3933 * Ignore interrupts for ports for which the
3934 * interrupts are not specifically enabled.
3935 */
3936 if (!(int_val & (1 << (port_id % 8))))
3937 continue;
3938 }
3939
3940 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3941 dev_err_ratelimited(wcd->dev,
3942 "%s: overflow error on %s port %d, value %x\n",
3943 __func__, (tx ? "TX" : "RX"), port_id, val);
3944
3945 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
3946 dev_err_ratelimited(wcd->dev,
3947 "%s: underflow error on %s port %d, value %x\n",
3948 __func__, (tx ? "TX" : "RX"), port_id, val);
3949
3950 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
3951 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
3952 if (!tx)
3953 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3954 (port_id / 8);
3955 else
3956 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3957 (port_id / 8);
3958 regmap_read(
3959 wcd->if_regmap, reg, &int_val);
3960 if (int_val & (1 << (port_id % 8))) {
3961 int_val = int_val ^ (1 << (port_id % 8));
3962 regmap_write(wcd->if_regmap,
3963 reg, int_val);
3964 }
3965 }
3966
3967 regmap_write(wcd->if_regmap,
3968 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
3969 BIT(j % 8));
3970 ret = IRQ_HANDLED;
3971 }
3972
3973 return ret;
3974 }
3975
3976 static const struct wcd9335_irq wcd9335_irqs[] = {
3977 {
3978 .irq = WCD9335_IRQ_SLIMBUS,
3979 .handler = wcd9335_slimbus_irq,
3980 .name = "SLIM Slave",
3981 },
3982 };
3983
wcd9335_setup_irqs(struct wcd9335_codec * wcd)3984 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
3985 {
3986 int irq, ret, i;
3987
3988 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
3989 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
3990 if (irq < 0) {
3991 dev_err(wcd->dev, "Failed to get %s\n",
3992 wcd9335_irqs[i].name);
3993 return irq;
3994 }
3995
3996 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
3997 wcd9335_irqs[i].handler,
3998 IRQF_TRIGGER_RISING |
3999 IRQF_ONESHOT,
4000 wcd9335_irqs[i].name, wcd);
4001 if (ret) {
4002 dev_err(wcd->dev, "Failed to request %s\n",
4003 wcd9335_irqs[i].name);
4004 return ret;
4005 }
4006 }
4007
4008 /* enable interrupts on all slave ports */
4009 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4010 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4011 0xFF);
4012
4013 return ret;
4014 }
4015
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4016 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4017 {
4018 int i;
4019
4020 /* disable interrupts on all slave ports */
4021 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4022 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4023 0x00);
4024 }
4025
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4026 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4027 bool ccl_flag)
4028 {
4029 struct snd_soc_component *comp = wcd->component;
4030
4031 if (ccl_flag) {
4032 if (++wcd->sido_ccl_cnt == 1)
4033 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4034 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4035 } else {
4036 if (wcd->sido_ccl_cnt == 0) {
4037 dev_err(wcd->dev, "sido_ccl already disabled\n");
4038 return;
4039 }
4040 if (--wcd->sido_ccl_cnt == 0)
4041 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4042 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4043 }
4044 }
4045
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4046 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4047 {
4048 wcd->master_bias_users++;
4049 if (wcd->master_bias_users == 1) {
4050 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4051 WCD9335_ANA_BIAS_EN_MASK,
4052 WCD9335_ANA_BIAS_ENABLE);
4053 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4054 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4055 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4056 /*
4057 * 1ms delay is required after pre-charge is enabled
4058 * as per HW requirement
4059 */
4060 usleep_range(1000, 1100);
4061 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4062 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4063 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4064 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4065 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4066 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4067 }
4068
4069 return 0;
4070 }
4071
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4072 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4073 {
4074 /* Enable mclk requires master bias to be enabled first */
4075 if (wcd->master_bias_users <= 0)
4076 return -EINVAL;
4077
4078 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4079 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4080 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4081 wcd->clk_type);
4082 return -EINVAL;
4083 }
4084
4085 if (++wcd->clk_mclk_users == 1) {
4086 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4087 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4088 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4089 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4090 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4091 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4092 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4093 WCD9335_ANA_CLK_MCLK_EN_MASK,
4094 WCD9335_ANA_CLK_MCLK_ENABLE);
4095 regmap_update_bits(wcd->regmap,
4096 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4097 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4098 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4099 regmap_update_bits(wcd->regmap,
4100 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4101 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4102 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4103 /*
4104 * 10us sleep is required after clock is enabled
4105 * as per HW requirement
4106 */
4107 usleep_range(10, 15);
4108 }
4109
4110 wcd->clk_type = WCD_CLK_MCLK;
4111
4112 return 0;
4113 }
4114
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4115 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4116 {
4117 if (wcd->clk_mclk_users <= 0)
4118 return -EINVAL;
4119
4120 if (--wcd->clk_mclk_users == 0) {
4121 if (wcd->clk_rco_users > 0) {
4122 /* MCLK to RCO switch */
4123 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4124 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4125 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4126 wcd->clk_type = WCD_CLK_RCO;
4127 } else {
4128 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4129 WCD9335_ANA_CLK_MCLK_EN_MASK,
4130 WCD9335_ANA_CLK_MCLK_DISABLE);
4131 wcd->clk_type = WCD_CLK_OFF;
4132 }
4133
4134 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4135 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4136 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4137 }
4138
4139 return 0;
4140 }
4141
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4142 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4143 {
4144 if (wcd->master_bias_users <= 0)
4145 return -EINVAL;
4146
4147 wcd->master_bias_users--;
4148 if (wcd->master_bias_users == 0) {
4149 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4150 WCD9335_ANA_BIAS_EN_MASK,
4151 WCD9335_ANA_BIAS_DISABLE);
4152 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4153 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4154 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4155 }
4156 return 0;
4157 }
4158
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4159 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4160 bool enable)
4161 {
4162 int ret = 0;
4163
4164 if (enable) {
4165 wcd9335_cdc_sido_ccl_enable(wcd, true);
4166 ret = clk_prepare_enable(wcd->mclk);
4167 if (ret) {
4168 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4169 __func__);
4170 goto err;
4171 }
4172 /* get BG */
4173 wcd9335_enable_master_bias(wcd);
4174 /* get MCLK */
4175 wcd9335_enable_mclk(wcd);
4176
4177 } else {
4178 /* put MCLK */
4179 wcd9335_disable_mclk(wcd);
4180 /* put BG */
4181 wcd9335_disable_master_bias(wcd);
4182 clk_disable_unprepare(wcd->mclk);
4183 wcd9335_cdc_sido_ccl_enable(wcd, false);
4184 }
4185 err:
4186 return ret;
4187 }
4188
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4189 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4190 enum wcd9335_sido_voltage req_mv)
4191 {
4192 struct snd_soc_component *comp = wcd->component;
4193 int vout_d_val;
4194
4195 if (req_mv == wcd->sido_voltage)
4196 return;
4197
4198 /* compute the vout_d step value */
4199 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4200 WCD9335_ANA_BUCK_VOUT_MASK;
4201 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4202 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4203 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4204 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4205
4206 /* 1 msec sleep required after SIDO Vout_D voltage change */
4207 usleep_range(1000, 1100);
4208 wcd->sido_voltage = req_mv;
4209 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4210 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4211 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4212 }
4213
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4214 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4215 enum wcd9335_sido_voltage req_mv)
4216 {
4217 int ret = 0;
4218
4219 /* enable mclk before setting SIDO voltage */
4220 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4221 if (ret) {
4222 dev_err(wcd->dev, "Ext clk enable failed\n");
4223 goto err;
4224 }
4225
4226 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4227 wcd9335_cdc_req_mclk_enable(wcd, false);
4228
4229 err:
4230 return ret;
4231 }
4232
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4233 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4234 int enable)
4235 {
4236 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4237 int ret;
4238
4239 if (enable) {
4240 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4241 if (ret)
4242 return ret;
4243
4244 wcd9335_codec_apply_sido_voltage(wcd,
4245 SIDO_VOLTAGE_NOMINAL_MV);
4246 } else {
4247 wcd9335_codec_update_sido_voltage(wcd,
4248 wcd->sido_voltage);
4249 wcd9335_cdc_req_mclk_enable(wcd, false);
4250 }
4251
4252 return 0;
4253 }
4254
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4255 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4256 struct snd_kcontrol *kc, int event)
4257 {
4258 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4259
4260 switch (event) {
4261 case SND_SOC_DAPM_PRE_PMU:
4262 return _wcd9335_codec_enable_mclk(comp, true);
4263 case SND_SOC_DAPM_POST_PMD:
4264 return _wcd9335_codec_enable_mclk(comp, false);
4265 }
4266
4267 return 0;
4268 }
4269
4270 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4271 /* TODO SPK1 & SPK2 OUT*/
4272 SND_SOC_DAPM_OUTPUT("EAR"),
4273 SND_SOC_DAPM_OUTPUT("HPHL"),
4274 SND_SOC_DAPM_OUTPUT("HPHR"),
4275 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4276 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4277 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4278 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4279 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4280 AIF1_PB, 0, wcd9335_codec_enable_slim,
4281 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4282 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4283 AIF2_PB, 0, wcd9335_codec_enable_slim,
4284 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4285 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4286 AIF3_PB, 0, wcd9335_codec_enable_slim,
4287 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4288 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4289 AIF4_PB, 0, wcd9335_codec_enable_slim,
4290 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4291 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4292 &slim_rx_mux[WCD9335_RX0]),
4293 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4294 &slim_rx_mux[WCD9335_RX1]),
4295 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4296 &slim_rx_mux[WCD9335_RX2]),
4297 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4298 &slim_rx_mux[WCD9335_RX3]),
4299 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4300 &slim_rx_mux[WCD9335_RX4]),
4301 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4302 &slim_rx_mux[WCD9335_RX5]),
4303 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4304 &slim_rx_mux[WCD9335_RX6]),
4305 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4306 &slim_rx_mux[WCD9335_RX7]),
4307 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4308 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4309 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4310 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4311 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4312 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4313 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4314 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4315 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4316 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4317 SND_SOC_DAPM_POST_PMU),
4318 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4319 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4320 SND_SOC_DAPM_POST_PMU),
4321 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4322 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4323 SND_SOC_DAPM_POST_PMU),
4324 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4325 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4326 SND_SOC_DAPM_POST_PMU),
4327 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4328 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4329 SND_SOC_DAPM_POST_PMU),
4330 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4331 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4332 SND_SOC_DAPM_POST_PMU),
4333 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4334 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4335 SND_SOC_DAPM_POST_PMU),
4336 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4337 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4338 SND_SOC_DAPM_POST_PMU),
4339 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4340 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4341 SND_SOC_DAPM_POST_PMU),
4342 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4343 &rx_int0_1_mix_inp0_mux),
4344 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4345 &rx_int0_1_mix_inp1_mux),
4346 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4347 &rx_int0_1_mix_inp2_mux),
4348 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4349 &rx_int1_1_mix_inp0_mux),
4350 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4351 &rx_int1_1_mix_inp1_mux),
4352 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4353 &rx_int1_1_mix_inp2_mux),
4354 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4355 &rx_int2_1_mix_inp0_mux),
4356 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4357 &rx_int2_1_mix_inp1_mux),
4358 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4359 &rx_int2_1_mix_inp2_mux),
4360 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4361 &rx_int3_1_mix_inp0_mux),
4362 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4363 &rx_int3_1_mix_inp1_mux),
4364 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4365 &rx_int3_1_mix_inp2_mux),
4366 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4367 &rx_int4_1_mix_inp0_mux),
4368 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4369 &rx_int4_1_mix_inp1_mux),
4370 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4371 &rx_int4_1_mix_inp2_mux),
4372 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4373 &rx_int5_1_mix_inp0_mux),
4374 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4375 &rx_int5_1_mix_inp1_mux),
4376 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4377 &rx_int5_1_mix_inp2_mux),
4378 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4379 &rx_int6_1_mix_inp0_mux),
4380 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4381 &rx_int6_1_mix_inp1_mux),
4382 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4383 &rx_int6_1_mix_inp2_mux),
4384 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4385 &rx_int7_1_mix_inp0_mux),
4386 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4387 &rx_int7_1_mix_inp1_mux),
4388 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4389 &rx_int7_1_mix_inp2_mux),
4390 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4391 &rx_int8_1_mix_inp0_mux),
4392 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4393 &rx_int8_1_mix_inp1_mux),
4394 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4395 &rx_int8_1_mix_inp2_mux),
4396
4397 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4398 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4399 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4400 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4401 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4402 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4403 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4404 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4405 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4406 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4407 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4408 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4409 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4410 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4411 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4412 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4413 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4414 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4415
4416 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4417 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4418 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4419 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4420 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4421 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4422 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4423 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4424 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4425
4426 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4427 &rx_int0_dem_inp_mux),
4428 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4429 &rx_int1_dem_inp_mux),
4430 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4431 &rx_int2_dem_inp_mux),
4432
4433 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4434 INTERP_EAR, 0, &rx_int0_interp_mux,
4435 wcd9335_codec_enable_interpolator,
4436 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4437 SND_SOC_DAPM_POST_PMD),
4438 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4439 INTERP_HPHL, 0, &rx_int1_interp_mux,
4440 wcd9335_codec_enable_interpolator,
4441 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4442 SND_SOC_DAPM_POST_PMD),
4443 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4444 INTERP_HPHR, 0, &rx_int2_interp_mux,
4445 wcd9335_codec_enable_interpolator,
4446 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4447 SND_SOC_DAPM_POST_PMD),
4448 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4449 INTERP_LO1, 0, &rx_int3_interp_mux,
4450 wcd9335_codec_enable_interpolator,
4451 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4452 SND_SOC_DAPM_POST_PMD),
4453 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4454 INTERP_LO2, 0, &rx_int4_interp_mux,
4455 wcd9335_codec_enable_interpolator,
4456 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4457 SND_SOC_DAPM_POST_PMD),
4458 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4459 INTERP_LO3, 0, &rx_int5_interp_mux,
4460 wcd9335_codec_enable_interpolator,
4461 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4462 SND_SOC_DAPM_POST_PMD),
4463 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4464 INTERP_LO4, 0, &rx_int6_interp_mux,
4465 wcd9335_codec_enable_interpolator,
4466 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4467 SND_SOC_DAPM_POST_PMD),
4468 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4469 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4470 wcd9335_codec_enable_interpolator,
4471 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4472 SND_SOC_DAPM_POST_PMD),
4473 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4474 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4475 wcd9335_codec_enable_interpolator,
4476 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4477 SND_SOC_DAPM_POST_PMD),
4478
4479 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4480 0, 0, wcd9335_codec_ear_dac_event,
4481 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4482 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4483 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4484 5, 0, wcd9335_codec_hphl_dac_event,
4485 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4486 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4487 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4488 4, 0, wcd9335_codec_hphr_dac_event,
4489 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4490 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4491 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4492 0, 0, wcd9335_codec_lineout_dac_event,
4493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4494 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4495 0, 0, wcd9335_codec_lineout_dac_event,
4496 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4497 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4498 0, 0, wcd9335_codec_lineout_dac_event,
4499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4500 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4501 0, 0, wcd9335_codec_lineout_dac_event,
4502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4503 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4504 wcd9335_codec_enable_hphl_pa,
4505 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4506 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4507 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4508 wcd9335_codec_enable_hphr_pa,
4509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4510 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4511 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4512 wcd9335_codec_enable_ear_pa,
4513 SND_SOC_DAPM_POST_PMU |
4514 SND_SOC_DAPM_POST_PMD),
4515 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4516 wcd9335_codec_enable_lineout_pa,
4517 SND_SOC_DAPM_POST_PMU |
4518 SND_SOC_DAPM_POST_PMD),
4519 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4520 wcd9335_codec_enable_lineout_pa,
4521 SND_SOC_DAPM_POST_PMU |
4522 SND_SOC_DAPM_POST_PMD),
4523 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4524 wcd9335_codec_enable_lineout_pa,
4525 SND_SOC_DAPM_POST_PMU |
4526 SND_SOC_DAPM_POST_PMD),
4527 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4528 wcd9335_codec_enable_lineout_pa,
4529 SND_SOC_DAPM_POST_PMU |
4530 SND_SOC_DAPM_POST_PMD),
4531 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4532 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4533 SND_SOC_DAPM_POST_PMD),
4534 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4535 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4536 SND_SOC_DAPM_POST_PMD),
4537
4538 /* TX */
4539 SND_SOC_DAPM_INPUT("AMIC1"),
4540 SND_SOC_DAPM_INPUT("AMIC2"),
4541 SND_SOC_DAPM_INPUT("AMIC3"),
4542 SND_SOC_DAPM_INPUT("AMIC4"),
4543 SND_SOC_DAPM_INPUT("AMIC5"),
4544 SND_SOC_DAPM_INPUT("AMIC6"),
4545
4546 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4547 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4548 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4549
4550 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4551 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4552 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4553
4554 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4555 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4556 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4557
4558 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4559 wcd9335_codec_enable_micbias,
4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4561 SND_SOC_DAPM_POST_PMD),
4562 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4563 wcd9335_codec_enable_micbias,
4564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4565 SND_SOC_DAPM_POST_PMD),
4566 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4567 wcd9335_codec_enable_micbias,
4568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4569 SND_SOC_DAPM_POST_PMD),
4570 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4571 wcd9335_codec_enable_micbias,
4572 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4573 SND_SOC_DAPM_POST_PMD),
4574
4575 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4576 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4577 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4578 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4579 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4580 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4581 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4582 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4583 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4584 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4585 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4586 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4587
4588 /* Digital Mic Inputs */
4589 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4590 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4591 SND_SOC_DAPM_POST_PMD),
4592
4593 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4594 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4595 SND_SOC_DAPM_POST_PMD),
4596
4597 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4598 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4599 SND_SOC_DAPM_POST_PMD),
4600
4601 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4602 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4603 SND_SOC_DAPM_POST_PMD),
4604
4605 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4606 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4607 SND_SOC_DAPM_POST_PMD),
4608
4609 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4610 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4611 SND_SOC_DAPM_POST_PMD),
4612
4613 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4614 &tx_dmic_mux0),
4615 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4616 &tx_dmic_mux1),
4617 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4618 &tx_dmic_mux2),
4619 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4620 &tx_dmic_mux3),
4621 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4622 &tx_dmic_mux4),
4623 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4624 &tx_dmic_mux5),
4625 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4626 &tx_dmic_mux6),
4627 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4628 &tx_dmic_mux7),
4629 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4630 &tx_dmic_mux8),
4631
4632 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4633 &tx_amic_mux0),
4634 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4635 &tx_amic_mux1),
4636 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4637 &tx_amic_mux2),
4638 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4639 &tx_amic_mux3),
4640 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4641 &tx_amic_mux4),
4642 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4643 &tx_amic_mux5),
4644 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4645 &tx_amic_mux6),
4646 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4647 &tx_amic_mux7),
4648 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4649 &tx_amic_mux8),
4650
4651 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4652 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4653
4654 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4655 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4656
4657 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4658 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4659
4660 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4661 &sb_tx0_mux),
4662 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4663 &sb_tx1_mux),
4664 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4665 &sb_tx2_mux),
4666 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4667 &sb_tx3_mux),
4668 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4669 &sb_tx4_mux),
4670 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4671 &sb_tx5_mux),
4672 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4673 &sb_tx6_mux),
4674 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4675 &sb_tx7_mux),
4676 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4677 &sb_tx8_mux),
4678
4679 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4680 &tx_adc_mux0, wcd9335_codec_enable_dec,
4681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4682 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4683
4684 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4685 &tx_adc_mux1, wcd9335_codec_enable_dec,
4686 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4687 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4688
4689 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4690 &tx_adc_mux2, wcd9335_codec_enable_dec,
4691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4692 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4693
4694 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4695 &tx_adc_mux3, wcd9335_codec_enable_dec,
4696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4697 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4698
4699 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4700 &tx_adc_mux4, wcd9335_codec_enable_dec,
4701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4702 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4703
4704 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4705 &tx_adc_mux5, wcd9335_codec_enable_dec,
4706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4707 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4708
4709 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4710 &tx_adc_mux6, wcd9335_codec_enable_dec,
4711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4712 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4713
4714 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4715 &tx_adc_mux7, wcd9335_codec_enable_dec,
4716 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4717 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4718
4719 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4720 &tx_adc_mux8, wcd9335_codec_enable_dec,
4721 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4722 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4723 };
4724
wcd9335_enable_sido_buck(struct snd_soc_component * component)4725 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4726 {
4727 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4728 WCD9335_ANA_RCO_BG_EN_MASK,
4729 WCD9335_ANA_RCO_BG_ENABLE);
4730 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4731 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4732 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4733 /* 100us sleep needed after IREF settings */
4734 usleep_range(100, 110);
4735 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4736 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4737 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4738 /* 100us sleep needed after VREF settings */
4739 usleep_range(100, 110);
4740 }
4741
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4742 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4743 {
4744 _wcd9335_codec_enable_mclk(comp, true);
4745 snd_soc_component_update_bits(comp,
4746 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4747 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4748 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4749 /*
4750 * 5ms sleep required after enabling efuse control
4751 * before checking the status.
4752 */
4753 usleep_range(5000, 5500);
4754
4755 if (!(snd_soc_component_read(comp,
4756 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4757 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4758 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4759
4760 wcd9335_enable_sido_buck(comp);
4761 _wcd9335_codec_enable_mclk(comp, false);
4762
4763 return 0;
4764 }
4765
wcd9335_codec_init(struct snd_soc_component * component)4766 static void wcd9335_codec_init(struct snd_soc_component *component)
4767 {
4768 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4769 int i;
4770
4771 /* ungate MCLK and set clk rate */
4772 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4773 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4774
4775 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4776 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4777 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4778
4779 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4780 snd_soc_component_update_bits(component,
4781 wcd9335_codec_reg_init[i].reg,
4782 wcd9335_codec_reg_init[i].mask,
4783 wcd9335_codec_reg_init[i].val);
4784
4785 wcd9335_enable_efuse_sensing(component);
4786 }
4787
wcd9335_codec_probe(struct snd_soc_component * component)4788 static int wcd9335_codec_probe(struct snd_soc_component *component)
4789 {
4790 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4791 int ret;
4792 int i;
4793
4794 snd_soc_component_init_regmap(component, wcd->regmap);
4795 /* Class-H Init*/
4796 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4797 if (IS_ERR(wcd->clsh_ctrl))
4798 return PTR_ERR(wcd->clsh_ctrl);
4799
4800 /* Default HPH Mode to Class-H HiFi */
4801 wcd->hph_mode = CLS_H_HIFI;
4802 wcd->component = component;
4803
4804 wcd9335_codec_init(component);
4805
4806 for (i = 0; i < NUM_CODEC_DAIS; i++)
4807 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4808
4809 ret = wcd9335_setup_irqs(wcd);
4810 if (ret)
4811 goto free_clsh_ctrl;
4812
4813 return 0;
4814
4815 free_clsh_ctrl:
4816 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4817 return ret;
4818 }
4819
wcd9335_codec_remove(struct snd_soc_component * comp)4820 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4821 {
4822 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4823
4824 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4825 wcd9335_teardown_irqs(wcd);
4826 }
4827
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4828 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4829 int clk_id, int source,
4830 unsigned int freq, int dir)
4831 {
4832 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4833
4834 wcd->mclk_rate = freq;
4835
4836 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4837 snd_soc_component_update_bits(comp,
4838 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4839 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4840 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4841 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4842 snd_soc_component_update_bits(comp,
4843 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4844 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4845 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4846
4847 return clk_set_rate(wcd->mclk, freq);
4848 }
4849
4850 static const struct snd_soc_component_driver wcd9335_component_drv = {
4851 .probe = wcd9335_codec_probe,
4852 .remove = wcd9335_codec_remove,
4853 .set_sysclk = wcd9335_codec_set_sysclk,
4854 .controls = wcd9335_snd_controls,
4855 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4856 .dapm_widgets = wcd9335_dapm_widgets,
4857 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4858 .dapm_routes = wcd9335_audio_map,
4859 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4860 .endianness = 1,
4861 };
4862
wcd9335_probe(struct wcd9335_codec * wcd)4863 static int wcd9335_probe(struct wcd9335_codec *wcd)
4864 {
4865 struct device *dev = wcd->dev;
4866
4867 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4868 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4869
4870 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4871
4872 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4873 wcd9335_slim_dais,
4874 ARRAY_SIZE(wcd9335_slim_dais));
4875 }
4876
4877 static const struct regmap_range_cfg wcd9335_ranges[] = {
4878 {
4879 .name = "WCD9335",
4880 .range_min = 0x0,
4881 .range_max = WCD9335_MAX_REGISTER,
4882 .selector_reg = WCD9335_SEL_REGISTER,
4883 .selector_mask = 0xff,
4884 .selector_shift = 0,
4885 .window_start = 0x800,
4886 .window_len = 0x100,
4887 },
4888 };
4889
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4890 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4891 {
4892 switch (reg) {
4893 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4894 case WCD9335_ANA_MBHC_RESULT_3:
4895 case WCD9335_ANA_MBHC_RESULT_2:
4896 case WCD9335_ANA_MBHC_RESULT_1:
4897 case WCD9335_ANA_MBHC_MECH:
4898 case WCD9335_ANA_MBHC_ELECT:
4899 case WCD9335_ANA_MBHC_ZDET:
4900 case WCD9335_ANA_MICB2:
4901 case WCD9335_ANA_RCO:
4902 case WCD9335_ANA_BIAS:
4903 return true;
4904 default:
4905 return false;
4906 }
4907 }
4908
4909 static const struct regmap_config wcd9335_regmap_config = {
4910 .reg_bits = 16,
4911 .val_bits = 8,
4912 .cache_type = REGCACHE_MAPLE,
4913 .max_register = WCD9335_MAX_REGISTER,
4914 .can_multi_write = true,
4915 .ranges = wcd9335_ranges,
4916 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4917 .volatile_reg = wcd9335_is_volatile_register,
4918 };
4919
4920 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4921 {
4922 .name = "WCD9335-IFC-DEV",
4923 .range_min = 0x0,
4924 .range_max = WCD9335_MAX_REGISTER,
4925 .selector_reg = WCD9335_SEL_REGISTER,
4926 .selector_mask = 0xfff,
4927 .selector_shift = 0,
4928 .window_start = 0x800,
4929 .window_len = 0x400,
4930 },
4931 };
4932
4933 static const struct regmap_config wcd9335_ifc_regmap_config = {
4934 .reg_bits = 16,
4935 .val_bits = 8,
4936 .can_multi_write = true,
4937 .max_register = WCD9335_MAX_REGISTER,
4938 .ranges = wcd9335_ifc_ranges,
4939 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4940 };
4941
4942 static const struct regmap_irq wcd9335_codec_irqs[] = {
4943 /* INTR_REG 0 */
4944 [WCD9335_IRQ_SLIMBUS] = {
4945 .reg_offset = 0,
4946 .mask = BIT(0),
4947 .type = {
4948 .type_reg_offset = 0,
4949 .types_supported = IRQ_TYPE_EDGE_BOTH,
4950 .type_reg_mask = BIT(0),
4951 },
4952 },
4953 };
4954
4955 static const unsigned int wcd9335_config_regs[] = {
4956 WCD9335_INTR_LEVEL0,
4957 };
4958
4959 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
4960 .name = "wcd9335_pin1_irq",
4961 .status_base = WCD9335_INTR_PIN1_STATUS0,
4962 .mask_base = WCD9335_INTR_PIN1_MASK0,
4963 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
4964 .num_regs = 4,
4965 .irqs = wcd9335_codec_irqs,
4966 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
4967 .config_base = wcd9335_config_regs,
4968 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
4969 .num_config_regs = 4,
4970 .set_type_config = regmap_irq_set_type_config_simple,
4971 };
4972
wcd9335_parse_dt(struct wcd9335_codec * wcd)4973 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
4974 {
4975 struct device *dev = wcd->dev;
4976 int ret;
4977
4978 wcd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
4979 if (IS_ERR(wcd->reset_gpio))
4980 return dev_err_probe(dev, PTR_ERR(wcd->reset_gpio), "Reset GPIO missing from DT\n");
4981
4982 wcd->mclk = devm_clk_get(dev, "mclk");
4983 if (IS_ERR(wcd->mclk))
4984 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n");
4985
4986 wcd->native_clk = devm_clk_get(dev, "slimbus");
4987 if (IS_ERR(wcd->native_clk))
4988 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n");
4989
4990 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd9335_supplies),
4991 wcd9335_supplies);
4992 if (ret)
4993 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
4994
4995 return 0;
4996 }
4997
wcd9335_power_on_reset(struct wcd9335_codec * wcd)4998 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
4999 {
5000 /*
5001 * For WCD9335, it takes about 600us for the Vout_A and
5002 * Vout_D to be ready after BUCK_SIDO is powered up.
5003 * SYS_RST_N shouldn't be pulled high during this time
5004 * Toggle the reset line to make sure the reset pulse is
5005 * correctly applied
5006 */
5007 usleep_range(600, 650);
5008
5009 gpiod_set_value(wcd->reset_gpio, 1);
5010 msleep(20);
5011 gpiod_set_value(wcd->reset_gpio, 0);
5012 msleep(20);
5013
5014 return 0;
5015 }
5016
wcd9335_bring_up(struct wcd9335_codec * wcd)5017 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5018 {
5019 struct regmap *rm = wcd->regmap;
5020 int val, byte0;
5021
5022 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5023 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5024
5025 if ((val < 0) || (byte0 < 0)) {
5026 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5027 return -EINVAL;
5028 }
5029
5030 if (byte0 == 0x1) {
5031 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5032 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5033 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5034 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5035 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5036 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5037 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5038 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5039 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5040 } else {
5041 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5042 return -EINVAL;
5043 }
5044
5045 return 0;
5046 }
5047
wcd9335_irq_init(struct wcd9335_codec * wcd)5048 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5049 {
5050 int ret;
5051
5052 /*
5053 * INTR1 consists of all possible interrupt sources Ear OCP,
5054 * HPH OCP, MBHC, MAD, VBAT, and SVA
5055 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5056 */
5057 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5058 if (wcd->intr1 < 0)
5059 return dev_err_probe(wcd->dev, wcd->intr1,
5060 "Unable to configure IRQ\n");
5061
5062 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5063 IRQF_TRIGGER_HIGH, 0,
5064 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5065 if (ret)
5066 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
5067
5068 return 0;
5069 }
5070
wcd9335_slim_probe(struct slim_device * slim)5071 static int wcd9335_slim_probe(struct slim_device *slim)
5072 {
5073 struct device *dev = &slim->dev;
5074 struct wcd9335_codec *wcd;
5075 int ret;
5076
5077 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5078 if (!wcd)
5079 return -ENOMEM;
5080
5081 wcd->dev = dev;
5082 ret = wcd9335_parse_dt(wcd);
5083 if (ret)
5084 return ret;
5085
5086 ret = wcd9335_power_on_reset(wcd);
5087 if (ret)
5088 return ret;
5089
5090 dev_set_drvdata(dev, wcd);
5091
5092 return 0;
5093 }
5094
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5095 static int wcd9335_slim_status(struct slim_device *sdev,
5096 enum slim_device_status status)
5097 {
5098 struct device *dev = &sdev->dev;
5099 struct device_node *ifc_dev_np;
5100 struct wcd9335_codec *wcd;
5101 int ret;
5102
5103 wcd = dev_get_drvdata(dev);
5104
5105 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5106 if (!ifc_dev_np) {
5107 dev_err(dev, "No Interface device found\n");
5108 return -EINVAL;
5109 }
5110
5111 wcd->slim = sdev;
5112 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5113 of_node_put(ifc_dev_np);
5114 if (!wcd->slim_ifc_dev) {
5115 dev_err(dev, "Unable to get SLIM Interface device\n");
5116 return -EINVAL;
5117 }
5118
5119 slim_get_logical_addr(wcd->slim_ifc_dev);
5120
5121 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5122 if (IS_ERR(wcd->regmap))
5123 return dev_err_probe(dev, PTR_ERR(wcd->regmap),
5124 "Failed to allocate slim register map\n");
5125
5126 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5127 &wcd9335_ifc_regmap_config);
5128 if (IS_ERR(wcd->if_regmap))
5129 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5130 "Failed to allocate ifc register map\n");
5131
5132 ret = wcd9335_bring_up(wcd);
5133 if (ret) {
5134 dev_err(dev, "Failed to bringup WCD9335\n");
5135 return ret;
5136 }
5137
5138 ret = wcd9335_irq_init(wcd);
5139 if (ret)
5140 return ret;
5141
5142 wcd9335_probe(wcd);
5143
5144 return 0;
5145 }
5146
5147 static const struct slim_device_id wcd9335_slim_id[] = {
5148 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5149 {}
5150 };
5151 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5152
5153 static struct slim_driver wcd9335_slim_driver = {
5154 .driver = {
5155 .name = "wcd9335-slim",
5156 },
5157 .probe = wcd9335_slim_probe,
5158 .device_status = wcd9335_slim_status,
5159 .id_table = wcd9335_slim_id,
5160 };
5161
5162 module_slim_driver(wcd9335_slim_driver);
5163 MODULE_DESCRIPTION("WCD9335 slim driver");
5164 MODULE_LICENSE("GPL v2");
5165