1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_DP_HTT_H 8 #define ATH12K_DP_HTT_H 9 10 struct ath12k_dp; 11 12 /* HTT definitions */ 13 #define HTT_TAG_TCL_METADATA_VERSION 5 14 15 #define HTT_TCL_META_DATA_TYPE GENMASK(1, 0) 16 #define HTT_TCL_META_DATA_VALID_HTT BIT(2) 17 18 /* vdev meta data */ 19 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3) 20 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11) 21 #define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) 22 23 /* peer meta data */ 24 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3) 25 26 /* Global sequence number */ 27 #define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 28 #define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) 29 #define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) 30 #define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 31 32 /* HTT tx completion is overlaid in wbm_release_ring */ 33 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 34 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 35 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 36 37 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 38 39 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 40 41 struct htt_tx_wbm_completion { 42 __le32 rsvd0[2]; 43 __le32 info0; 44 __le32 info1; 45 __le32 info2; 46 __le32 info3; 47 __le32 info4; 48 __le32 rsvd1; 49 50 } __packed; 51 52 enum htt_h2t_msg_type { 53 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 54 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 55 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 56 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 57 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 58 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 59 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 60 }; 61 62 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 63 #define HTT_OPTION_TCL_METADATA_VER_V1 1 64 #define HTT_OPTION_TCL_METADATA_VER_V2 2 65 #define HTT_OPTION_TAG GENMASK(7, 0) 66 #define HTT_OPTION_LEN GENMASK(15, 8) 67 #define HTT_OPTION_VALUE GENMASK(31, 16) 68 #define HTT_TCL_METADATA_VER_SZ 4 69 70 struct htt_ver_req_cmd { 71 __le32 ver_reg_info; 72 __le32 tcl_metadata_version; 73 } __packed; 74 75 enum htt_srng_ring_type { 76 HTT_HW_TO_SW_RING, 77 HTT_SW_TO_HW_RING, 78 HTT_SW_TO_SW_RING, 79 }; 80 81 enum htt_srng_ring_id { 82 HTT_RXDMA_HOST_BUF_RING, 83 HTT_RXDMA_MONITOR_STATUS_RING, 84 HTT_RXDMA_MONITOR_BUF_RING, 85 HTT_RXDMA_MONITOR_DESC_RING, 86 HTT_RXDMA_MONITOR_DEST_RING, 87 HTT_HOST1_TO_FW_RXBUF_RING, 88 HTT_HOST2_TO_FW_RXBUF_RING, 89 HTT_RXDMA_NON_MONITOR_DEST_RING, 90 HTT_RXDMA_HOST_BUF_RING2, 91 HTT_TX_MON_HOST2MON_BUF_RING, 92 HTT_TX_MON_MON2HOST_DEST_RING, 93 HTT_RX_MON_HOST2MON_BUF_RING, 94 HTT_RX_MON_MON2HOST_DEST_RING, 95 }; 96 97 /* host -> target HTT_SRING_SETUP message 98 * 99 * After target is booted up, Host can send SRING setup message for 100 * each host facing LMAC SRING. Target setups up HW registers based 101 * on setup message and confirms back to Host if response_required is set. 102 * Host should wait for confirmation message before sending new SRING 103 * setup message 104 * 105 * The message would appear as follows: 106 * 107 * |31 24|23 20|19|18 16|15|14 8|7 0| 108 * |--------------- +-----------------+----------------+------------------| 109 * | ring_type | ring_id | pdev_id | msg_type | 110 * |----------------------------------------------------------------------| 111 * | ring_base_addr_lo | 112 * |----------------------------------------------------------------------| 113 * | ring_base_addr_hi | 114 * |----------------------------------------------------------------------| 115 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 116 * |----------------------------------------------------------------------| 117 * | ring_head_offset32_remote_addr_lo | 118 * |----------------------------------------------------------------------| 119 * | ring_head_offset32_remote_addr_hi | 120 * |----------------------------------------------------------------------| 121 * | ring_tail_offset32_remote_addr_lo | 122 * |----------------------------------------------------------------------| 123 * | ring_tail_offset32_remote_addr_hi | 124 * |----------------------------------------------------------------------| 125 * | ring_msi_addr_lo | 126 * |----------------------------------------------------------------------| 127 * | ring_msi_addr_hi | 128 * |----------------------------------------------------------------------| 129 * | ring_msi_data | 130 * |----------------------------------------------------------------------| 131 * | intr_timer_th |IM| intr_batch_counter_th | 132 * |----------------------------------------------------------------------| 133 * | reserved |RR|PTCF| intr_low_threshold | 134 * |----------------------------------------------------------------------| 135 * Where 136 * IM = sw_intr_mode 137 * RR = response_required 138 * PTCF = prefetch_timer_cfg 139 * 140 * The message is interpreted as follows: 141 * dword0 - b'0:7 - msg_type: This will be set to 142 * HTT_H2T_MSG_TYPE_SRING_SETUP 143 * b'8:15 - pdev_id: 144 * 0 (for rings at SOC/UMAC level), 145 * 1/2/3 mac id (for rings at LMAC level) 146 * b'16:23 - ring_id: identify which ring is to setup, 147 * more details can be got from enum htt_srng_ring_id 148 * b'24:31 - ring_type: identify type of host rings, 149 * more details can be got from enum htt_srng_ring_type 150 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 151 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 152 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 153 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 154 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 155 * SW_TO_HW_RING. 156 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 157 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 158 * Lower 32 bits of memory address of the remote variable 159 * storing the 4-byte word offset that identifies the head 160 * element within the ring. 161 * (The head offset variable has type u32.) 162 * Valid for HW_TO_SW and SW_TO_SW rings. 163 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 164 * Upper 32 bits of memory address of the remote variable 165 * storing the 4-byte word offset that identifies the head 166 * element within the ring. 167 * (The head offset variable has type u32.) 168 * Valid for HW_TO_SW and SW_TO_SW rings. 169 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 170 * Lower 32 bits of memory address of the remote variable 171 * storing the 4-byte word offset that identifies the tail 172 * element within the ring. 173 * (The tail offset variable has type u32.) 174 * Valid for HW_TO_SW and SW_TO_SW rings. 175 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 176 * Upper 32 bits of memory address of the remote variable 177 * storing the 4-byte word offset that identifies the tail 178 * element within the ring. 179 * (The tail offset variable has type u32.) 180 * Valid for HW_TO_SW and SW_TO_SW rings. 181 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 182 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 183 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 184 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 185 * dword10 - b'0:31 - ring_msi_data: MSI data 186 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 187 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 188 * dword11 - b'0:14 - intr_batch_counter_th: 189 * batch counter threshold is in units of 4-byte words. 190 * HW internally maintains and increments batch count. 191 * (see SRING spec for detail description). 192 * When batch count reaches threshold value, an interrupt 193 * is generated by HW. 194 * b'15 - sw_intr_mode: 195 * This configuration shall be static. 196 * Only programmed at power up. 197 * 0: generate pulse style sw interrupts 198 * 1: generate level style sw interrupts 199 * b'16:31 - intr_timer_th: 200 * The timer init value when timer is idle or is 201 * initialized to start downcounting. 202 * In 8us units (to cover a range of 0 to 524 ms) 203 * dword12 - b'0:15 - intr_low_threshold: 204 * Used only by Consumer ring to generate ring_sw_int_p. 205 * Ring entries low threshold water mark, that is used 206 * in combination with the interrupt timer as well as 207 * the clearing of the level interrupt. 208 * b'16:18 - prefetch_timer_cfg: 209 * Used only by Consumer ring to set timer mode to 210 * support Application prefetch handling. 211 * The external tail offset/pointer will be updated 212 * at following intervals: 213 * 3'b000: (Prefetch feature disabled; used only for debug) 214 * 3'b001: 1 usec 215 * 3'b010: 4 usec 216 * 3'b011: 8 usec (default) 217 * 3'b100: 16 usec 218 * Others: Reserved 219 * b'19 - response_required: 220 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 221 * b'20:31 - reserved: reserved for future use 222 */ 223 224 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 225 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 226 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 227 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 228 229 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 230 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 231 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 232 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 233 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 234 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 235 236 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 237 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 238 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 239 240 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 241 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 242 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 243 244 struct htt_srng_setup_cmd { 245 __le32 info0; 246 __le32 ring_base_addr_lo; 247 __le32 ring_base_addr_hi; 248 __le32 info1; 249 __le32 ring_head_off32_remote_addr_lo; 250 __le32 ring_head_off32_remote_addr_hi; 251 __le32 ring_tail_off32_remote_addr_lo; 252 __le32 ring_tail_off32_remote_addr_hi; 253 __le32 ring_msi_addr_lo; 254 __le32 ring_msi_addr_hi; 255 __le32 msi_data; 256 __le32 intr_info; 257 __le32 info2; 258 } __packed; 259 260 /* host -> target FW PPDU_STATS config message 261 * 262 * @details 263 * The following field definitions describe the format of the HTT host 264 * to target FW for PPDU_STATS_CFG msg. 265 * The message allows the host to configure the PPDU_STATS_IND messages 266 * produced by the target. 267 * 268 * |31 24|23 16|15 8|7 0| 269 * |-----------------------------------------------------------| 270 * | REQ bit mask | pdev_mask | msg type | 271 * |-----------------------------------------------------------| 272 * Header fields: 273 * - MSG_TYPE 274 * Bits 7:0 275 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 276 * Value: 0x11 277 * - PDEV_MASK 278 * Bits 8:15 279 * Purpose: identifies which pdevs this PPDU stats configuration applies to 280 * Value: This is a overloaded field, refer to usage and interpretation of 281 * PDEV in interface document. 282 * Bit 8 : Reserved for SOC stats 283 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 284 * Indicates MACID_MASK in DBS 285 * - REQ_TLV_BIT_MASK 286 * Bits 16:31 287 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 288 * needs to be included in the target's PPDU_STATS_IND messages. 289 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 290 * 291 */ 292 293 struct htt_ppdu_stats_cfg_cmd { 294 __le32 msg; 295 } __packed; 296 297 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 298 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 299 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 300 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 301 302 enum htt_ppdu_stats_tag_type { 303 HTT_PPDU_STATS_TAG_COMMON, 304 HTT_PPDU_STATS_TAG_USR_COMMON, 305 HTT_PPDU_STATS_TAG_USR_RATE, 306 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 307 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 308 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 309 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 310 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 311 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 312 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 313 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 314 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 315 HTT_PPDU_STATS_TAG_INFO, 316 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 317 318 /* New TLV's are added above to this line */ 319 HTT_PPDU_STATS_TAG_MAX, 320 }; 321 322 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 323 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 324 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 325 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 326 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 327 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 328 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 329 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 330 331 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 332 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 333 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 334 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 335 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 336 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 337 HTT_PPDU_STATS_TAG_DEFAULT) 338 339 enum htt_stats_internal_ppdu_frametype { 340 HTT_STATS_PPDU_FTYPE_CTRL, 341 HTT_STATS_PPDU_FTYPE_DATA, 342 HTT_STATS_PPDU_FTYPE_BAR, 343 HTT_STATS_PPDU_FTYPE_MAX 344 }; 345 346 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 347 * 348 * details: 349 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 350 * configure RXDMA rings. 351 * The configuration is per ring based and includes both packet subtypes 352 * and PPDU/MPDU TLVs. 353 * 354 * The message would appear as follows: 355 * 356 * |31 29|28|27|26|25|24|23 16|15 8|7 0| 357 * |-------+--+--+--+--+--+-----------+----------------+---------------| 358 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 359 * |-------------------------------------------------------------------| 360 * | rsvd2 | ring_buffer_size | 361 * |-------------------------------------------------------------------| 362 * | packet_type_enable_flags_0 | 363 * |-------------------------------------------------------------------| 364 * | packet_type_enable_flags_1 | 365 * |-------------------------------------------------------------------| 366 * | packet_type_enable_flags_2 | 367 * |-------------------------------------------------------------------| 368 * | packet_type_enable_flags_3 | 369 * |-------------------------------------------------------------------| 370 * | tlv_filter_in_flags | 371 * |-------------------------------------------------------------------| 372 * Where: 373 * PS = pkt_swap 374 * SS = status_swap 375 * The message is interpreted as follows: 376 * dword0 - b'0:7 - msg_type: This will be set to 377 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 378 * b'8:15 - pdev_id: 379 * 0 (for rings at SOC/UMAC level), 380 * 1/2/3 mac id (for rings at LMAC level) 381 * b'16:23 - ring_id : Identify the ring to configure. 382 * More details can be got from enum htt_srng_ring_id 383 * b'24 - status_swap: 1 is to swap status TLV 384 * b'25 - pkt_swap: 1 is to swap packet TLV 385 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 386 * configuration fields are valid 387 * b'27 - drop_thresh_valid (DT): flag to indicate if the 388 * rx_drop_threshold field is valid 389 * b'28 - rx_mon_global_en: Enable/Disable global register 390 * configuration in Rx monitor module. 391 * b'29:31 - rsvd1: reserved for future use 392 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 393 * in byte units. 394 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 395 * - b'16:31 - rsvd2: Reserved for future use 396 * dword2 - b'0:31 - packet_type_enable_flags_0: 397 * Enable MGMT packet from 0b0000 to 0b1001 398 * bits from low to high: FP, MD, MO - 3 bits 399 * FP: Filter_Pass 400 * MD: Monitor_Direct 401 * MO: Monitor_Other 402 * 10 mgmt subtypes * 3 bits -> 30 bits 403 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 404 * dword3 - b'0:31 - packet_type_enable_flags_1: 405 * Enable MGMT packet from 0b1010 to 0b1111 406 * bits from low to high: FP, MD, MO - 3 bits 407 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 408 * dword4 - b'0:31 - packet_type_enable_flags_2: 409 * Enable CTRL packet from 0b0000 to 0b1001 410 * bits from low to high: FP, MD, MO - 3 bits 411 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 412 * dword5 - b'0:31 - packet_type_enable_flags_3: 413 * Enable CTRL packet from 0b1010 to 0b1111, 414 * MCAST_DATA, UCAST_DATA, NULL_DATA 415 * bits from low to high: FP, MD, MO - 3 bits 416 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 417 * dword6 - b'0:31 - tlv_filter_in_flags: 418 * Filter in Attention/MPDU/PPDU/Header/User tlvs 419 * Refer to CFG_TLV_FILTER_IN_FLAG defs 420 */ 421 422 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 423 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 424 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 425 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 426 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 427 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26) 428 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27) 429 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28) 430 431 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 432 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) 433 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) 434 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) 435 436 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0) 437 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17) 438 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18) 439 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19) 440 441 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0) 442 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1) 443 444 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 445 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 446 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 447 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 448 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 449 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 450 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 451 452 #define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 453 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 454 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 455 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 456 457 enum htt_rx_filter_tlv_flags { 458 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 459 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 460 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 461 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 462 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 463 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 464 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 465 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 466 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 467 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 468 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 469 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 470 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 471 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), 472 }; 473 474 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 475 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 476 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 477 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 478 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 479 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 480 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 481 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 482 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 483 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 484 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 485 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 486 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 487 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 488 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 489 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 490 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 491 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 492 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 493 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 494 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 495 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 496 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 497 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 498 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 499 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 500 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 501 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 502 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 503 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 504 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 505 }; 506 507 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 508 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 509 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 510 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 511 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 512 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 513 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 514 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 515 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 516 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 517 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 518 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 519 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 520 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 521 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 522 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 523 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 524 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 525 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 526 }; 527 528 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 529 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 530 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 531 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 532 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 533 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 534 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 535 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 536 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 537 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 538 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 539 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 540 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 541 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 542 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 543 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 544 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 545 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 546 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 547 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 548 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 549 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 550 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 551 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 552 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 553 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 554 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 555 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 556 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 557 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 558 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 559 }; 560 561 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 562 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 563 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 564 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 565 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 566 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 567 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 568 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 569 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 570 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 571 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 572 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 573 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 574 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 575 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 576 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 577 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 578 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 579 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 580 }; 581 582 enum htt_rx_data_pkt_filter_tlv_flasg3 { 583 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 584 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 585 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 586 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 587 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 588 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 589 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 590 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 591 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 592 }; 593 594 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 595 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 596 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 597 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 598 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 599 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 600 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 601 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 602 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 603 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 604 605 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 606 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 607 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 608 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 609 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 610 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 611 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 612 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 613 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 614 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 615 616 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 617 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 618 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 619 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 620 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 621 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 622 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 623 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 624 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 625 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 626 627 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 628 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 629 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 630 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 631 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 632 633 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 634 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 635 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 636 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 637 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 638 639 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 640 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 641 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 642 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 643 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 644 645 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 646 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 647 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 648 649 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 650 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 651 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 652 653 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 654 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 655 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 656 657 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 658 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 659 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 660 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 661 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 662 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 663 664 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 665 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 666 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 667 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 668 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 669 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 670 671 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 672 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 673 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 674 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 675 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 676 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 677 678 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 679 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 680 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 681 682 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 683 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 684 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 685 686 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 687 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 688 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 689 690 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 691 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 692 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 693 694 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 695 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 696 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 697 698 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 699 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 700 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 701 702 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 703 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 704 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 705 706 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 707 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 708 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 709 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 710 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 711 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 712 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 713 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 714 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 715 716 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 717 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 718 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 719 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 720 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 721 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 722 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 723 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 724 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 725 726 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 727 728 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 729 730 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 731 732 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 733 734 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 735 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 736 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 737 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 738 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 739 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 740 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 741 742 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 743 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 744 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 745 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 746 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 747 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 748 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 749 750 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 751 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 752 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 753 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 754 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 755 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 756 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 757 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 758 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 759 760 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ 761 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 762 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 763 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 764 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 765 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 766 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 767 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 768 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 769 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 770 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 771 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 772 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ 773 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) 774 775 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 776 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 777 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 778 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 779 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 780 781 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 782 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 783 784 struct htt_rx_ring_selection_cfg_cmd { 785 __le32 info0; 786 __le32 info1; 787 __le32 pkt_type_en_flags0; 788 __le32 pkt_type_en_flags1; 789 __le32 pkt_type_en_flags2; 790 __le32 pkt_type_en_flags3; 791 __le32 rx_filter_tlv; 792 __le32 rx_packet_offset; 793 __le32 rx_mpdu_offset; 794 __le32 rx_msdu_offset; 795 __le32 rx_attn_offset; 796 __le32 info2; 797 __le32 reserved[2]; 798 __le32 rx_mpdu_start_end_mask; 799 __le32 rx_msdu_end_word_mask; 800 __le32 info3; 801 } __packed; 802 803 #define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 804 #define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 805 #define HTT_RX_RING_PKT_TLV_OFFSET 0x1 806 807 struct htt_rx_ring_tlv_filter { 808 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 809 u32 pkt_filter_flags0; /* MGMT */ 810 u32 pkt_filter_flags1; /* MGMT */ 811 u32 pkt_filter_flags2; /* CTRL */ 812 u32 pkt_filter_flags3; /* DATA */ 813 bool offset_valid; 814 u16 rx_packet_offset; 815 u16 rx_header_offset; 816 u16 rx_mpdu_end_offset; 817 u16 rx_mpdu_start_offset; 818 u16 rx_msdu_end_offset; 819 u16 rx_msdu_start_offset; 820 u16 rx_attn_offset; 821 u16 rx_mpdu_start_wmask; 822 u16 rx_mpdu_end_wmask; 823 u32 rx_msdu_end_wmask; 824 u32 conf_len_ctrl; 825 u32 conf_len_mgmt; 826 u32 conf_len_data; 827 u16 rx_drop_threshold; 828 bool enable_log_mgmt_type; 829 bool enable_log_ctrl_type; 830 bool enable_log_data_type; 831 bool enable_rx_tlv_offset; 832 u16 rx_tlv_offset; 833 bool drop_threshold_valid; 834 bool rxmon_disable; 835 }; 836 837 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 838 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 839 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 840 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 841 842 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 843 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 844 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 845 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 846 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 847 848 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 849 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 850 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 851 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 852 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 853 854 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 855 856 struct htt_tx_ring_selection_cfg_cmd { 857 __le32 info0; 858 __le32 info1; 859 __le32 info2; 860 __le32 tlv_filter_mask_in0; 861 __le32 tlv_filter_mask_in1; 862 __le32 tlv_filter_mask_in2; 863 __le32 tlv_filter_mask_in3; 864 __le32 reserved[3]; 865 } __packed; 866 867 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 868 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 869 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 870 871 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 872 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 873 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 874 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 875 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 876 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 877 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 878 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 879 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 880 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 881 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 882 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 883 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 884 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 885 886 struct htt_tx_ring_tlv_filter { 887 u32 tx_mon_downstream_tlv_flags; 888 u32 tx_mon_upstream_tlv_flags0; 889 u32 tx_mon_upstream_tlv_flags1; 890 u32 tx_mon_upstream_tlv_flags2; 891 bool tx_mon_mgmt_filter; 892 bool tx_mon_data_filter; 893 bool tx_mon_ctrl_filter; 894 u16 tx_mon_pkt_dma_len; 895 } __packed; 896 897 enum htt_tx_mon_upstream_tlv_flags0 { 898 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 899 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 900 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 901 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 902 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 903 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 904 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 905 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 906 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 907 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 908 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 909 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 910 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 911 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 912 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 913 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 914 }; 915 916 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 917 918 /* HTT message target->host */ 919 920 enum htt_t2h_msg_type { 921 HTT_T2H_MSG_TYPE_VERSION_CONF, 922 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 923 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 924 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 925 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 926 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 927 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 928 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 929 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 930 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 931 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 932 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 933 HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29, 934 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 935 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 936 }; 937 938 #define HTT_TARGET_VERSION_MAJOR 3 939 940 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 941 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 942 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 943 944 struct htt_t2h_version_conf_msg { 945 __le32 version; 946 } __packed; 947 948 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 949 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 950 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 951 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 952 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 953 #define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0) 954 #define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16) 955 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 956 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 957 958 struct htt_t2h_peer_map_event { 959 __le32 info; 960 __le32 mac_addr_l32; 961 __le32 info1; 962 __le32 info2; 963 } __packed; 964 965 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 966 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 967 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 968 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 969 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 970 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 971 972 struct htt_t2h_peer_unmap_event { 973 __le32 info; 974 __le32 mac_addr_l32; 975 __le32 info1; 976 } __packed; 977 978 #define HTT_T2H_MLO_PEER_MAP_INFO0_MLO_PEER_ID GENMASK(23, 8) 979 #define HTT_T2H_MLO_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 980 981 struct htt_t2h_mlo_peer_map_event { 982 __le32 info0; 983 __le32 mac_addr_l32; 984 __le32 info1; 985 __le32 reserved[5]; 986 } __packed; 987 988 struct htt_resp_msg { 989 union { 990 struct htt_t2h_version_conf_msg version_msg; 991 struct htt_t2h_peer_map_event peer_map_ev; 992 struct htt_t2h_peer_unmap_event peer_unmap_ev; 993 struct htt_t2h_mlo_peer_map_event mlo_peer_map_ev; 994 }; 995 } __packed; 996 997 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 998 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 999 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1000 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1001 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1002 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1003 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1004 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1005 1006 struct htt_t2h_vdev_txrx_stats_ind { 1007 __le32 vdev_id; 1008 __le32 rx_msdu_byte_cnt_lo; 1009 __le32 rx_msdu_byte_cnt_hi; 1010 __le32 rx_msdu_cnt_lo; 1011 __le32 rx_msdu_cnt_hi; 1012 __le32 tx_msdu_byte_cnt_lo; 1013 __le32 tx_msdu_byte_cnt_hi; 1014 __le32 tx_msdu_cnt_lo; 1015 __le32 tx_msdu_cnt_hi; 1016 __le32 tx_retry_cnt_lo; 1017 __le32 tx_retry_cnt_hi; 1018 __le32 tx_retry_byte_cnt_lo; 1019 __le32 tx_retry_byte_cnt_hi; 1020 __le32 tx_drop_cnt_lo; 1021 __le32 tx_drop_cnt_hi; 1022 __le32 tx_drop_byte_cnt_lo; 1023 __le32 tx_drop_byte_cnt_hi; 1024 __le32 msdu_ttl_cnt_lo; 1025 __le32 msdu_ttl_cnt_hi; 1026 __le32 msdu_ttl_byte_cnt_lo; 1027 __le32 msdu_ttl_byte_cnt_hi; 1028 } __packed; 1029 1030 struct htt_t2h_vdev_common_stats_tlv { 1031 __le32 soc_drop_count_lo; 1032 __le32 soc_drop_count_hi; 1033 } __packed; 1034 1035 /* ppdu stats 1036 * 1037 * @details 1038 * The following field definitions describe the format of the HTT target 1039 * to host ppdu stats indication message. 1040 * 1041 * 1042 * |31 16|15 12|11 10|9 8|7 0 | 1043 * |----------------------------------------------------------------------| 1044 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1045 * |----------------------------------------------------------------------| 1046 * | ppdu_id | 1047 * |----------------------------------------------------------------------| 1048 * | Timestamp in us | 1049 * |----------------------------------------------------------------------| 1050 * | reserved | 1051 * |----------------------------------------------------------------------| 1052 * | type-specific stats info | 1053 * | (see htt_ppdu_stats.h) | 1054 * |----------------------------------------------------------------------| 1055 * Header fields: 1056 * - MSG_TYPE 1057 * Bits 7:0 1058 * Purpose: Identifies this is a PPDU STATS indication 1059 * message. 1060 * Value: 0x1d 1061 * - mac_id 1062 * Bits 9:8 1063 * Purpose: mac_id of this ppdu_id 1064 * Value: 0-3 1065 * - pdev_id 1066 * Bits 11:10 1067 * Purpose: pdev_id of this ppdu_id 1068 * Value: 0-3 1069 * 0 (for rings at SOC level), 1070 * 1/2/3 PDEV -> 0/1/2 1071 * - payload_size 1072 * Bits 31:16 1073 * Purpose: total tlv size 1074 * Value: payload_size in bytes 1075 */ 1076 1077 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1078 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1079 1080 struct ath12k_htt_ppdu_stats_msg { 1081 __le32 info; 1082 __le32 ppdu_id; 1083 __le32 timestamp; 1084 __le32 rsvd; 1085 u8 data[]; 1086 } __packed; 1087 1088 struct htt_tlv { 1089 __le32 header; 1090 u8 value[]; 1091 } __packed; 1092 1093 #define HTT_TLV_TAG GENMASK(11, 0) 1094 #define HTT_TLV_LEN GENMASK(23, 12) 1095 1096 enum HTT_PPDU_STATS_BW { 1097 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1098 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1099 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1100 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1101 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1102 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1103 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1104 }; 1105 1106 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1107 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1108 /* bw - HTT_PPDU_STATS_BW */ 1109 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1110 1111 struct htt_ppdu_stats_common { 1112 __le32 ppdu_id; 1113 __le16 sched_cmdid; 1114 u8 ring_id; 1115 u8 num_users; 1116 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1117 __le32 chain_mask; 1118 __le32 fes_duration_us; /* frame exchange sequence */ 1119 __le32 ppdu_sch_eval_start_tstmp_us; 1120 __le32 ppdu_sch_end_tstmp_us; 1121 __le32 ppdu_start_tstmp_us; 1122 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1123 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1124 */ 1125 __le16 phy_mode; 1126 __le16 bw_mhz; 1127 } __packed; 1128 1129 enum htt_ppdu_stats_gi { 1130 HTT_PPDU_STATS_SGI_0_8_US, 1131 HTT_PPDU_STATS_SGI_0_4_US, 1132 HTT_PPDU_STATS_SGI_1_6_US, 1133 HTT_PPDU_STATS_SGI_3_2_US, 1134 }; 1135 1136 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1137 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1138 1139 enum HTT_PPDU_STATS_PPDU_TYPE { 1140 HTT_PPDU_STATS_PPDU_TYPE_SU, 1141 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1142 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1143 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1144 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1145 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1146 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1147 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1148 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1149 HTT_PPDU_STATS_PPDU_TYPE_MAX 1150 }; 1151 1152 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1153 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1154 1155 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1156 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1157 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1158 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1159 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1160 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1161 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1162 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1163 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1164 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1165 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1166 1167 #define HTT_USR_RATE_PPDU_TYPE(_val) \ 1168 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M) 1169 #define HTT_USR_RATE_PREAMBLE(_val) \ 1170 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1171 #define HTT_USR_RATE_BW(_val) \ 1172 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1173 #define HTT_USR_RATE_NSS(_val) \ 1174 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1175 #define HTT_USR_RATE_MCS(_val) \ 1176 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1177 #define HTT_USR_RATE_GI(_val) \ 1178 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1179 #define HTT_USR_RATE_DCM(_val) \ 1180 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1181 1182 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1183 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1184 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1185 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1186 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1187 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1188 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1189 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1190 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1191 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1192 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1193 1194 struct htt_ppdu_stats_user_rate { 1195 u8 tid_num; 1196 u8 reserved0; 1197 __le16 sw_peer_id; 1198 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1199 __le16 ru_end; 1200 __le16 ru_start; 1201 __le16 resp_ru_end; 1202 __le16 resp_ru_start; 1203 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1204 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1205 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1206 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1207 } __packed; 1208 1209 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1210 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1211 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1212 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1213 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1214 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1215 1216 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1217 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1218 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1219 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1220 #define HTT_TX_INFO_RATECODE(_flags) \ 1221 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1222 #define HTT_TX_INFO_PEERID(_flags) \ 1223 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1224 1225 enum htt_ppdu_stats_usr_compln_status { 1226 HTT_PPDU_STATS_USER_STATUS_OK, 1227 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1228 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1229 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1230 HTT_PPDU_STATS_USER_STATUS_ABORT, 1231 }; 1232 1233 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1234 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1235 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1236 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1237 1238 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1239 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1240 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1241 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1242 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1243 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1244 1245 struct htt_ppdu_stats_usr_cmpltn_cmn { 1246 u8 status; 1247 u8 tid_num; 1248 __le16 sw_peer_id; 1249 /* RSSI value of last ack packet (units = dB above noise floor) */ 1250 __le32 ack_rssi; 1251 __le16 mpdu_tried; 1252 __le16 mpdu_success; 1253 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1254 } __packed; 1255 1256 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1257 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1258 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1259 1260 #define HTT_PPDU_STATS_NON_QOS_TID 16 1261 1262 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1263 __le32 ppdu_id; 1264 __le16 sw_peer_id; 1265 __le16 reserved0; 1266 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1267 __le16 current_seq; 1268 __le16 start_seq; 1269 __le32 success_bytes; 1270 } __packed; 1271 1272 struct htt_ppdu_user_stats { 1273 u16 peer_id; 1274 u16 delay_ba; 1275 u32 tlv_flags; 1276 bool is_valid_peer_id; 1277 struct htt_ppdu_stats_user_rate rate; 1278 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1279 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1280 }; 1281 1282 #define HTT_PPDU_STATS_MAX_USERS 8 1283 #define HTT_PPDU_DESC_MAX_DEPTH 16 1284 1285 struct htt_ppdu_stats { 1286 struct htt_ppdu_stats_common common; 1287 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1288 }; 1289 1290 struct htt_ppdu_stats_info { 1291 u32 tlv_bitmap; 1292 u32 ppdu_id; 1293 u32 frame_type; 1294 u32 frame_ctrl; 1295 u32 delay_ba; 1296 u32 bar_num_users; 1297 struct htt_ppdu_stats ppdu_stats; 1298 struct list_head list; 1299 }; 1300 1301 /* @brief target -> host MLO offset indiciation message 1302 * 1303 * @details 1304 * The following field definitions describe the format of the HTT target 1305 * to host mlo offset indication message. 1306 * 1307 * 1308 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1309 * |---------------------------------------------------------------------| 1310 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1311 * |---------------------------------------------------------------------| 1312 * | sync_timestamp_lo_us | 1313 * |---------------------------------------------------------------------| 1314 * | sync_timestamp_hi_us | 1315 * |---------------------------------------------------------------------| 1316 * | mlo_offset_lo | 1317 * |---------------------------------------------------------------------| 1318 * | mlo_offset_hi | 1319 * |---------------------------------------------------------------------| 1320 * | mlo_offset_clcks | 1321 * |---------------------------------------------------------------------| 1322 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1323 * |---------------------------------------------------------------------| 1324 * | rsvd3 |mlo_comp_timer | 1325 * |---------------------------------------------------------------------| 1326 * Header fields 1327 * - MSG_TYPE 1328 * Bits 7:0 1329 * Purpose: Identifies this is a MLO offset indication msg 1330 * - PDEV_ID 1331 * Bits 9:8 1332 * Purpose: Pdev of this MLO offset 1333 * - CHIP_ID 1334 * Bits 12:10 1335 * Purpose: chip_id of this MLO offset 1336 * - MAC_FREQ 1337 * Bits 28:13 1338 * - SYNC_TIMESTAMP_LO_US 1339 * Purpose: clock frequency of the mac HW block in MHz 1340 * Bits: 31:0 1341 * Purpose: lower 32 bits of the WLAN global time stamp at which 1342 * last sync interrupt was received 1343 * - SYNC_TIMESTAMP_HI_US 1344 * Bits: 31:0 1345 * Purpose: upper 32 bits of WLAN global time stamp at which 1346 * last sync interrupt was received 1347 * - MLO_OFFSET_LO 1348 * Bits: 31:0 1349 * Purpose: lower 32 bits of the MLO offset in us 1350 * - MLO_OFFSET_HI 1351 * Bits: 31:0 1352 * Purpose: upper 32 bits of the MLO offset in us 1353 * - MLO_COMP_US 1354 * Bits: 15:0 1355 * Purpose: MLO time stamp compensation applied in us 1356 * - MLO_COMP_CLCKS 1357 * Bits: 25:16 1358 * Purpose: MLO time stamp compensation applied in clock ticks 1359 * - MLO_COMP_TIMER 1360 * Bits: 21:0 1361 * Purpose: Periodic timer at which compensation is applied 1362 */ 1363 1364 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1365 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1366 1367 struct ath12k_htt_mlo_offset_msg { 1368 __le32 info; 1369 __le32 sync_timestamp_lo_us; 1370 __le32 sync_timestamp_hi_us; 1371 __le32 mlo_offset_hi; 1372 __le32 mlo_offset_lo; 1373 __le32 mlo_offset_clks; 1374 __le32 mlo_comp_clks; 1375 __le32 mlo_comp_timer; 1376 } __packed; 1377 1378 /* @brief host -> target FW extended statistics retrieve 1379 * 1380 * @details 1381 * The following field definitions describe the format of the HTT host 1382 * to target FW extended stats retrieve message. 1383 * The message specifies the type of stats the host wants to retrieve. 1384 * 1385 * |31 24|23 16|15 8|7 0| 1386 * |-----------------------------------------------------------| 1387 * | reserved | stats type | pdev_mask | msg type | 1388 * |-----------------------------------------------------------| 1389 * | config param [0] | 1390 * |-----------------------------------------------------------| 1391 * | config param [1] | 1392 * |-----------------------------------------------------------| 1393 * | config param [2] | 1394 * |-----------------------------------------------------------| 1395 * | config param [3] | 1396 * |-----------------------------------------------------------| 1397 * | reserved | 1398 * |-----------------------------------------------------------| 1399 * | cookie LSBs | 1400 * |-----------------------------------------------------------| 1401 * | cookie MSBs | 1402 * |-----------------------------------------------------------| 1403 * Header fields: 1404 * - MSG_TYPE 1405 * Bits 7:0 1406 * Purpose: identifies this is a extended stats upload request message 1407 * Value: 0x10 1408 * - PDEV_MASK 1409 * Bits 8:15 1410 * Purpose: identifies the mask of PDEVs to retrieve stats from 1411 * Value: This is a overloaded field, refer to usage and interpretation of 1412 * PDEV in interface document. 1413 * Bit 8 : Reserved for SOC stats 1414 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1415 * Indicates MACID_MASK in DBS 1416 * - STATS_TYPE 1417 * Bits 23:16 1418 * Purpose: identifies which FW statistics to upload 1419 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1420 * - Reserved 1421 * Bits 31:24 1422 * - CONFIG_PARAM [0] 1423 * Bits 31:0 1424 * Purpose: give an opaque configuration value to the specified stats type 1425 * Value: stats-type specific configuration value 1426 * Refer to htt_stats.h for interpretation for each stats sub_type 1427 * - CONFIG_PARAM [1] 1428 * Bits 31:0 1429 * Purpose: give an opaque configuration value to the specified stats type 1430 * Value: stats-type specific configuration value 1431 * Refer to htt_stats.h for interpretation for each stats sub_type 1432 * - CONFIG_PARAM [2] 1433 * Bits 31:0 1434 * Purpose: give an opaque configuration value to the specified stats type 1435 * Value: stats-type specific configuration value 1436 * Refer to htt_stats.h for interpretation for each stats sub_type 1437 * - CONFIG_PARAM [3] 1438 * Bits 31:0 1439 * Purpose: give an opaque configuration value to the specified stats type 1440 * Value: stats-type specific configuration value 1441 * Refer to htt_stats.h for interpretation for each stats sub_type 1442 * - Reserved [31:0] for future use. 1443 * - COOKIE_LSBS 1444 * Bits 31:0 1445 * Purpose: Provide a mechanism to match a target->host stats confirmation 1446 * message with its preceding host->target stats request message. 1447 * Value: LSBs of the opaque cookie specified by the host-side requestor 1448 * - COOKIE_MSBS 1449 * Bits 31:0 1450 * Purpose: Provide a mechanism to match a target->host stats confirmation 1451 * message with its preceding host->target stats request message. 1452 * Value: MSBs of the opaque cookie specified by the host-side requestor 1453 */ 1454 1455 struct htt_ext_stats_cfg_hdr { 1456 u8 msg_type; 1457 u8 pdev_mask; 1458 u8 stats_type; 1459 u8 reserved; 1460 } __packed; 1461 1462 struct htt_ext_stats_cfg_cmd { 1463 struct htt_ext_stats_cfg_hdr hdr; 1464 __le32 cfg_param0; 1465 __le32 cfg_param1; 1466 __le32 cfg_param2; 1467 __le32 cfg_param3; 1468 __le32 reserved; 1469 __le32 cookie_lsb; 1470 __le32 cookie_msb; 1471 } __packed; 1472 1473 /* htt stats config default params */ 1474 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1475 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1476 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1477 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1478 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1479 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1480 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1481 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1482 1483 /* HTT_DBG_EXT_STATS_PEER_INFO 1484 * PARAMS: 1485 * @config_param0: 1486 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1487 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1488 * [Bit31 : Bit16] sw_peer_id 1489 * @config_param1: 1490 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1491 * 0 bit htt_peer_stats_cmn_tlv 1492 * 1 bit htt_peer_details_tlv 1493 * 2 bit htt_tx_peer_rate_stats_tlv 1494 * 3 bit htt_rx_peer_rate_stats_tlv 1495 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1496 * 5 bit htt_rx_tid_stats_tlv 1497 * 6 bit htt_msdu_flow_stats_tlv 1498 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1499 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1500 * [Bit31 : Bit16] reserved 1501 */ 1502 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1503 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1504 1505 /* Used to set different configs to the specified stats type.*/ 1506 struct htt_ext_stats_cfg_params { 1507 u32 cfg0; 1508 u32 cfg1; 1509 u32 cfg2; 1510 u32 cfg3; 1511 }; 1512 1513 enum vdev_stats_offload_timer_duration { 1514 ATH12K_STATS_TIMER_DUR_500MS = 1, 1515 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1516 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1517 }; 1518 1519 #define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1520 #define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1521 #define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1522 #define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1523 #define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1524 #define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1525 1526 struct htt_mac_addr { 1527 __le32 mac_addr_l32; 1528 __le32 mac_addr_h16; 1529 } __packed; 1530 1531 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1532 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1533 int mac_id, enum hal_ring_type ring_type); 1534 1535 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1536 struct sk_buff *skb); 1537 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1538 int (*iter)(struct ath12k_base *ab, u16 tag, u16 len, 1539 const void *ptr, void *data), 1540 void *data); 1541 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab); 1542 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask); 1543 int 1544 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 1545 struct htt_ext_stats_cfg_params *cfg_params, 1546 u64 cookie); 1547 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset); 1548 1549 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1550 int mac_id, enum hal_ring_type ring_type, 1551 int rx_buf_size, 1552 struct htt_rx_ring_tlv_filter *tlv_filter); 1553 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1554 int mac_id, enum hal_ring_type ring_type, 1555 int tx_buf_size, 1556 struct htt_tx_ring_tlv_filter *htt_tlv_filter); 1557 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset); 1558 #endif 1559