1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2025 David Yang 4 */ 5 6 #ifndef __YT921X_H 7 #define __YT921X_H 8 9 #include <net/dsa.h> 10 11 #define YT921X_SMI_SWITCHID_M GENMASK(3, 2) 12 #define YT921X_SMI_SWITCHID(x) FIELD_PREP(YT921X_SMI_SWITCHID_M, (x)) 13 #define YT921X_SMI_AD BIT(1) 14 #define YT921X_SMI_ADDR 0 15 #define YT921X_SMI_DATA YT921X_SMI_AD 16 #define YT921X_SMI_RW BIT(0) 17 #define YT921X_SMI_WRITE 0 18 #define YT921X_SMI_READ YT921X_SMI_RW 19 20 #define YT921X_SWITCHID_NUM 4 21 22 #define YT921X_RST 0x80000 23 #define YT921X_RST_HW BIT(31) 24 #define YT921X_RST_SW BIT(1) 25 #define YT921X_FUNC 0x80004 26 #define YT921X_FUNC_METER BIT(4) 27 #define YT921X_FUNC_ACL BIT(2) 28 #define YT921X_FUNC_MIB BIT(1) 29 #define YT921X_CHIP_ID 0x80008 30 #define YT921X_CHIP_ID_MAJOR GENMASK(31, 16) 31 #define YT921X_EXT_CPU_PORT 0x8000c 32 #define YT921X_EXT_CPU_PORT_TAG_EN BIT(15) 33 #define YT921X_EXT_CPU_PORT_PORT_EN BIT(14) 34 #define YT921X_EXT_CPU_PORT_PORT_M GENMASK(3, 0) 35 #define YT921X_EXT_CPU_PORT_PORT(x) FIELD_PREP(YT921X_EXT_CPU_PORT_PORT_M, (x)) 36 #define YT921X_CPU_TAG_TPID 0x80010 37 #define YT921X_CPU_TAG_TPID_TPID_M GENMASK(15, 0) 38 /* Same as ETH_P_YT921X, but this represents the true HW default, while the 39 * former is a local convention chosen by us. 40 */ 41 #define YT921X_CPU_TAG_TPID_TPID_DEFAULT 0x9988 42 #define YT921X_PVID_SEL 0x80014 43 #define YT921X_PVID_SEL_SVID_PORTn(port) BIT(port) 44 #define YT921X_SERDES_CTRL 0x80028 45 #define YT921X_SERDES_CTRL_PORTn_TEST(port) BIT((port) - 3) 46 #define YT921X_SERDES_CTRL_PORTn(port) BIT((port) - 8) 47 #define YT921X_IO_LEVEL 0x80030 48 #define YT9215_IO_LEVEL_NORMAL_M GENMASK(5, 4) 49 #define YT9215_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9215_IO_LEVEL_NORMAL_M, (x)) 50 #define YT9215_IO_LEVEL_NORMAL_3V3 YT9215_IO_LEVEL_NORMAL(0) 51 #define YT9215_IO_LEVEL_NORMAL_1V8 YT9215_IO_LEVEL_NORMAL(3) 52 #define YT9215_IO_LEVEL_RGMII1_M GENMASK(3, 2) 53 #define YT9215_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII1_M, (x)) 54 #define YT9215_IO_LEVEL_RGMII1_3V3 YT9215_IO_LEVEL_RGMII1(0) 55 #define YT9215_IO_LEVEL_RGMII1_2V5 YT9215_IO_LEVEL_RGMII1(1) 56 #define YT9215_IO_LEVEL_RGMII1_1V8 YT9215_IO_LEVEL_RGMII1(2) 57 #define YT9215_IO_LEVEL_RGMII0_M GENMASK(1, 0) 58 #define YT9215_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII0_M, (x)) 59 #define YT9215_IO_LEVEL_RGMII0_3V3 YT9215_IO_LEVEL_RGMII0(0) 60 #define YT9215_IO_LEVEL_RGMII0_2V5 YT9215_IO_LEVEL_RGMII0(1) 61 #define YT9215_IO_LEVEL_RGMII0_1V8 YT9215_IO_LEVEL_RGMII0(2) 62 #define YT9218_IO_LEVEL_RGMII1_M GENMASK(5, 4) 63 #define YT9218_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII1_M, (x)) 64 #define YT9218_IO_LEVEL_RGMII1_3V3 YT9218_IO_LEVEL_RGMII1(0) 65 #define YT9218_IO_LEVEL_RGMII1_2V5 YT9218_IO_LEVEL_RGMII1(1) 66 #define YT9218_IO_LEVEL_RGMII1_1V8 YT9218_IO_LEVEL_RGMII1(2) 67 #define YT9218_IO_LEVEL_RGMII0_M GENMASK(3, 2) 68 #define YT9218_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII0_M, (x)) 69 #define YT9218_IO_LEVEL_RGMII0_3V3 YT9218_IO_LEVEL_RGMII0(0) 70 #define YT9218_IO_LEVEL_RGMII0_2V5 YT9218_IO_LEVEL_RGMII0(1) 71 #define YT9218_IO_LEVEL_RGMII0_1V8 YT9218_IO_LEVEL_RGMII0(2) 72 #define YT9218_IO_LEVEL_NORMAL_M GENMASK(1, 0) 73 #define YT9218_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9218_IO_LEVEL_NORMAL_M, (x)) 74 #define YT9218_IO_LEVEL_NORMAL_3V3 YT9218_IO_LEVEL_NORMAL(0) 75 #define YT9218_IO_LEVEL_NORMAL_1V8 YT9218_IO_LEVEL_NORMAL(3) 76 #define YT921X_MAC_ADDR_HI2 0x80080 77 #define YT921X_MAC_ADDR_LO4 0x80084 78 #define YT921X_SERDESn(port) (0x8008c + 4 * ((port) - 8)) 79 #define YT921X_SERDES_MODE_M GENMASK(9, 7) 80 #define YT921X_SERDES_MODE(x) FIELD_PREP(YT921X_SERDES_MODE_M, (x)) 81 #define YT921X_SERDES_MODE_SGMII YT921X_SERDES_MODE(0) 82 #define YT921X_SERDES_MODE_REVSGMII YT921X_SERDES_MODE(1) 83 #define YT921X_SERDES_MODE_1000BASEX YT921X_SERDES_MODE(2) 84 #define YT921X_SERDES_MODE_100BASEX YT921X_SERDES_MODE(3) 85 #define YT921X_SERDES_MODE_2500BASEX YT921X_SERDES_MODE(4) 86 #define YT921X_SERDES_RX_PAUSE BIT(6) 87 #define YT921X_SERDES_TX_PAUSE BIT(5) 88 #define YT921X_SERDES_LINK BIT(4) /* force link */ 89 #define YT921X_SERDES_DUPLEX_FULL BIT(3) 90 #define YT921X_SERDES_SPEED_M GENMASK(2, 0) 91 #define YT921X_SERDES_SPEED(x) FIELD_PREP(YT921X_SERDES_SPEED_M, (x)) 92 #define YT921X_SERDES_SPEED_10 YT921X_SERDES_SPEED(0) 93 #define YT921X_SERDES_SPEED_100 YT921X_SERDES_SPEED(1) 94 #define YT921X_SERDES_SPEED_1000 YT921X_SERDES_SPEED(2) 95 #define YT921X_SERDES_SPEED_10000 YT921X_SERDES_SPEED(3) 96 #define YT921X_SERDES_SPEED_2500 YT921X_SERDES_SPEED(4) 97 #define YT921X_PORTn_CTRL(port) (0x80100 + 4 * (port)) 98 #define YT921X_PORT_CTRL_PAUSE_AN BIT(10) 99 #define YT921X_PORTn_STATUS(port) (0x80200 + 4 * (port)) 100 #define YT921X_PORT_LINK BIT(9) /* CTRL: auto negotiation */ 101 #define YT921X_PORT_HALF_PAUSE BIT(8) /* Half-duplex back pressure mode */ 102 #define YT921X_PORT_DUPLEX_FULL BIT(7) 103 #define YT921X_PORT_RX_PAUSE BIT(6) 104 #define YT921X_PORT_TX_PAUSE BIT(5) 105 #define YT921X_PORT_RX_MAC_EN BIT(4) 106 #define YT921X_PORT_TX_MAC_EN BIT(3) 107 #define YT921X_PORT_SPEED_M GENMASK(2, 0) 108 #define YT921X_PORT_SPEED(x) FIELD_PREP(YT921X_PORT_SPEED_M, (x)) 109 #define YT921X_PORT_SPEED_10 YT921X_PORT_SPEED(0) 110 #define YT921X_PORT_SPEED_100 YT921X_PORT_SPEED(1) 111 #define YT921X_PORT_SPEED_1000 YT921X_PORT_SPEED(2) 112 #define YT921X_PORT_SPEED_10000 YT921X_PORT_SPEED(3) 113 #define YT921X_PORT_SPEED_2500 YT921X_PORT_SPEED(4) 114 #define YT921X_PON_STRAP_FUNC 0x80320 115 #define YT921X_PON_STRAP_VAL 0x80324 116 #define YT921X_PON_STRAP_CAP 0x80328 117 #define YT921X_PON_STRAP_EEE BIT(16) 118 #define YT921X_PON_STRAP_LOOP_DETECT BIT(7) 119 #define YT921X_MDIO_POLLINGn(port) (0x80364 + 4 * ((port) - 8)) 120 #define YT921X_MDIO_POLLING_DUPLEX_FULL BIT(4) 121 #define YT921X_MDIO_POLLING_LINK BIT(3) 122 #define YT921X_MDIO_POLLING_SPEED_M GENMASK(2, 0) 123 #define YT921X_MDIO_POLLING_SPEED(x) FIELD_PREP(YT921X_MDIO_POLLING_SPEED_M, (x)) 124 #define YT921X_MDIO_POLLING_SPEED_10 YT921X_MDIO_POLLING_SPEED(0) 125 #define YT921X_MDIO_POLLING_SPEED_100 YT921X_MDIO_POLLING_SPEED(1) 126 #define YT921X_MDIO_POLLING_SPEED_1000 YT921X_MDIO_POLLING_SPEED(2) 127 #define YT921X_MDIO_POLLING_SPEED_10000 YT921X_MDIO_POLLING_SPEED(3) 128 #define YT921X_MDIO_POLLING_SPEED_2500 YT921X_MDIO_POLLING_SPEED(4) 129 #define YT921X_SENSOR 0x8036c 130 #define YT921X_SENSOR_TEMP BIT(18) 131 #define YT921X_TEMP 0x80374 132 #define YT921X_CHIP_MODE 0x80388 133 #define YT921X_CHIP_MODE_MODE GENMASK(1, 0) 134 #define YT921X_XMII_CTRL 0x80394 135 #define YT921X_XMII_CTRL_PORTn(port) BIT(9 - (port)) /* Yes, it's reversed */ 136 #define YT921X_XMIIn(port) (0x80400 + 8 * ((port) - 8)) 137 #define YT921X_XMII_MODE_M GENMASK(31, 29) 138 #define YT921X_XMII_MODE(x) FIELD_PREP(YT921X_XMII_MODE_M, (x)) 139 #define YT921X_XMII_MODE_MII YT921X_XMII_MODE(0) 140 #define YT921X_XMII_MODE_REVMII YT921X_XMII_MODE(1) 141 #define YT921X_XMII_MODE_RMII YT921X_XMII_MODE(2) 142 #define YT921X_XMII_MODE_REVRMII YT921X_XMII_MODE(3) 143 #define YT921X_XMII_MODE_RGMII YT921X_XMII_MODE(4) 144 #define YT921X_XMII_MODE_DISABLE YT921X_XMII_MODE(5) 145 #define YT921X_XMII_LINK BIT(19) /* force link */ 146 #define YT921X_XMII_EN BIT(18) 147 #define YT921X_XMII_SOFT_RST BIT(17) 148 #define YT921X_XMII_RGMII_TX_DELAY_150PS_M GENMASK(16, 13) 149 #define YT921X_XMII_RGMII_TX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_TX_DELAY_150PS_M, (x)) 150 #define YT921X_XMII_TX_CLK_IN BIT(11) 151 #define YT921X_XMII_RX_CLK_IN BIT(10) 152 #define YT921X_XMII_RGMII_TX_DELAY_2NS BIT(8) 153 #define YT921X_XMII_RGMII_TX_CLK_OUT BIT(7) 154 #define YT921X_XMII_RGMII_RX_DELAY_150PS_M GENMASK(6, 3) 155 #define YT921X_XMII_RGMII_RX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_RX_DELAY_150PS_M, (x)) 156 #define YT921X_XMII_RMII_PHY_TX_CLK_OUT BIT(2) 157 #define YT921X_XMII_REVMII_TX_CLK_OUT BIT(1) 158 #define YT921X_XMII_REVMII_RX_CLK_OUT BIT(0) 159 160 #define YT921X_MACn_FRAME(port) (0x81008 + 0x1000 * (port)) 161 #define YT921X_MAC_FRAME_SIZE_M GENMASK(21, 8) 162 #define YT921X_MAC_FRAME_SIZE(x) FIELD_PREP(YT921X_MAC_FRAME_SIZE_M, (x)) 163 164 #define YT921X_EEEn_VAL(port) (0xa0000 + 0x40 * (port)) 165 #define YT921X_EEE_VAL_DATA BIT(1) 166 167 #define YT921X_EEE_CTRL 0xb0000 168 #define YT921X_EEE_CTRL_ENn(port) BIT(port) 169 170 #define YT921X_MIB_CTRL 0xc0004 171 #define YT921X_MIB_CTRL_CLEAN BIT(30) 172 #define YT921X_MIB_CTRL_PORT_M GENMASK(6, 3) 173 #define YT921X_MIB_CTRL_PORT(x) FIELD_PREP(YT921X_MIB_CTRL_PORT_M, (x)) 174 #define YT921X_MIB_CTRL_ONE_PORT BIT(1) 175 #define YT921X_MIB_CTRL_ALL_PORT BIT(0) 176 #define YT921X_MIBn_DATA0(port) (0xc0100 + 0x100 * (port)) 177 #define YT921X_MIBn_DATAm(port, x) (YT921X_MIBn_DATA0(port) + 4 * (x)) 178 #define YT921X_MIB_DATA_RX_BROADCAST 0x00 179 #define YT921X_MIB_DATA_RX_PAUSE 0x04 180 #define YT921X_MIB_DATA_RX_MULTICAST 0x08 181 #define YT921X_MIB_DATA_RX_CRC_ERR 0x0c 182 183 #define YT921X_MIB_DATA_RX_ALIGN_ERR 0x10 184 #define YT921X_MIB_DATA_RX_UNDERSIZE_ERR 0x14 185 #define YT921X_MIB_DATA_RX_FRAG_ERR 0x18 186 #define YT921X_MIB_DATA_RX_PKT_SZ_64 0x1c 187 188 #define YT921X_MIB_DATA_RX_PKT_SZ_65_TO_127 0x20 189 #define YT921X_MIB_DATA_RX_PKT_SZ_128_TO_255 0x24 190 #define YT921X_MIB_DATA_RX_PKT_SZ_256_TO_511 0x28 191 #define YT921X_MIB_DATA_RX_PKT_SZ_512_TO_1023 0x2c 192 193 #define YT921X_MIB_DATA_RX_PKT_SZ_1024_TO_1518 0x30 194 #define YT921X_MIB_DATA_RX_PKT_SZ_1519_TO_MAX 0x34 195 /* 0x38: unused */ 196 #define YT921X_MIB_DATA_RX_GOOD_BYTES 0x3c 197 198 /* 0x40: 64 bytes */ 199 #define YT921X_MIB_DATA_RX_BAD_BYTES 0x44 200 /* 0x48: 64 bytes */ 201 #define YT921X_MIB_DATA_RX_OVERSIZE_ERR 0x4c 202 203 #define YT921X_MIB_DATA_RX_DROPPED 0x50 204 #define YT921X_MIB_DATA_TX_BROADCAST 0x54 205 #define YT921X_MIB_DATA_TX_PAUSE 0x58 206 #define YT921X_MIB_DATA_TX_MULTICAST 0x5c 207 208 #define YT921X_MIB_DATA_TX_UNDERSIZE_ERR 0x60 209 #define YT921X_MIB_DATA_TX_PKT_SZ_64 0x64 210 #define YT921X_MIB_DATA_TX_PKT_SZ_65_TO_127 0x68 211 #define YT921X_MIB_DATA_TX_PKT_SZ_128_TO_255 0x6c 212 213 #define YT921X_MIB_DATA_TX_PKT_SZ_256_TO_511 0x70 214 #define YT921X_MIB_DATA_TX_PKT_SZ_512_TO_1023 0x74 215 #define YT921X_MIB_DATA_TX_PKT_SZ_1024_TO_1518 0x78 216 #define YT921X_MIB_DATA_TX_PKT_SZ_1519_TO_MAX 0x7c 217 218 /* 0x80: unused */ 219 #define YT921X_MIB_DATA_TX_GOOD_BYTES 0x84 220 /* 0x88: 64 bytes */ 221 #define YT921X_MIB_DATA_TX_COLLISION 0x8c 222 223 #define YT921X_MIB_DATA_TX_EXCESSIVE_COLLISION 0x90 224 #define YT921X_MIB_DATA_TX_MULTIPLE_COLLISION 0x94 225 #define YT921X_MIB_DATA_TX_SINGLE_COLLISION 0x98 226 #define YT921X_MIB_DATA_TX_PKT 0x9c 227 228 #define YT921X_MIB_DATA_TX_DEFERRED 0xa0 229 #define YT921X_MIB_DATA_TX_LATE_COLLISION 0xa4 230 #define YT921X_MIB_DATA_RX_OAM 0xa8 231 #define YT921X_MIB_DATA_TX_OAM 0xac 232 233 #define YT921X_EDATA_CTRL 0xe0000 234 #define YT921X_EDATA_CTRL_ADDR_M GENMASK(15, 8) 235 #define YT921X_EDATA_CTRL_ADDR(x) FIELD_PREP(YT921X_EDATA_CTRL_ADDR_M, (x)) 236 #define YT921X_EDATA_CTRL_OP_M GENMASK(3, 0) 237 #define YT921X_EDATA_CTRL_OP(x) FIELD_PREP(YT921X_EDATA_CTRL_OP_M, (x)) 238 #define YT921X_EDATA_CTRL_READ YT921X_EDATA_CTRL_OP(5) 239 #define YT921X_EDATA_DATA 0xe0004 240 #define YT921X_EDATA_DATA_DATA_M GENMASK(31, 24) 241 #define YT921X_EDATA_DATA_STATUS_M GENMASK(3, 0) 242 #define YT921X_EDATA_DATA_STATUS(x) FIELD_PREP(YT921X_EDATA_DATA_STATUS_M, (x)) 243 #define YT921X_EDATA_DATA_IDLE YT921X_EDATA_DATA_STATUS(3) 244 #define YT921X_SYS_CLK 0xe0040 245 #define YT921X_SYS_CLK_SEL_M GENMASK(1, 0) /* unknown: 167M */ 246 #define YT9215_SYS_CLK_125M 0 247 #define YT9218_SYS_CLK_167M 0 248 #define YT921X_SYS_CLK_143M 1 249 250 #define YT921X_EXT_MBUS_OP 0x6a000 251 #define YT921X_INT_MBUS_OP 0xf0000 252 #define YT921X_MBUS_OP_START BIT(0) 253 #define YT921X_EXT_MBUS_CTRL 0x6a004 254 #define YT921X_INT_MBUS_CTRL 0xf0004 255 #define YT921X_MBUS_CTRL_PORT_M GENMASK(25, 21) 256 #define YT921X_MBUS_CTRL_PORT(x) FIELD_PREP(YT921X_MBUS_CTRL_PORT_M, (x)) 257 #define YT921X_MBUS_CTRL_REG_M GENMASK(20, 16) 258 #define YT921X_MBUS_CTRL_REG(x) FIELD_PREP(YT921X_MBUS_CTRL_REG_M, (x)) 259 #define YT921X_MBUS_CTRL_TYPE_M GENMASK(11, 8) /* wild guess */ 260 #define YT921X_MBUS_CTRL_TYPE(x) FIELD_PREP(YT921X_MBUS_CTRL_TYPE_M, (x)) 261 #define YT921X_MBUS_CTRL_TYPE_C22 YT921X_MBUS_CTRL_TYPE(4) 262 #define YT921X_MBUS_CTRL_OP_M GENMASK(3, 2) /* wild guess */ 263 #define YT921X_MBUS_CTRL_OP(x) FIELD_PREP(YT921X_MBUS_CTRL_OP_M, (x)) 264 #define YT921X_MBUS_CTRL_WRITE YT921X_MBUS_CTRL_OP(1) 265 #define YT921X_MBUS_CTRL_READ YT921X_MBUS_CTRL_OP(2) 266 #define YT921X_EXT_MBUS_DOUT 0x6a008 267 #define YT921X_INT_MBUS_DOUT 0xf0008 268 #define YT921X_EXT_MBUS_DIN 0x6a00c 269 #define YT921X_INT_MBUS_DIN 0xf000c 270 271 #define YT921X_PORTn_EGR(port) (0x100000 + 4 * (port)) 272 #define YT921X_PORT_EGR_TPID_CTAG_M GENMASK(5, 4) 273 #define YT921X_PORT_EGR_TPID_CTAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_CTAG_M, (x)) 274 #define YT921X_PORT_EGR_TPID_STAG_M GENMASK(3, 2) 275 #define YT921X_PORT_EGR_TPID_STAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_STAG_M, (x)) 276 #define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */ 277 #define YT921X_TPID_EGR_TPID_M GENMASK(15, 0) 278 279 #define YT921X_IPM_DSCPn(n) (0x180000 + 4 * (n)) /* Internal Priority Map */ 280 #define YT921X_IPM_PCPn(map, dei, pcp) (0x180100 + 4 * (16 * (map) + 8 * (dei) + (pcp))) 281 #define YT921X_IPM_PRIO_M GENMASK(4, 2) 282 #define YT921X_IPM_PRIO(x) FIELD_PREP(YT921X_IPM_PRIO_M, (x)) 283 #define YT921X_IPM_COLOR_M GENMASK(1, 0) 284 #define YT921X_IPM_COLOR(x) FIELD_PREP(YT921X_IPM_COLOR_M, (x)) 285 #define YT921X_IPM_COLOR_GREEN YT921X_IPM_COLOR(0) 286 #define YT921X_IPM_COLOR_YELLOW YT921X_IPM_COLOR(1) 287 #define YT921X_IPM_COLOR_RED YT921X_IPM_COLOR(2) 288 #define YT921X_PORTn_QOS(port) (0x180180 + 4 * (port)) 289 #define YT921X_PORT_QOS_CVLAN_PRIO_MAP_ID BIT(5) 290 #define YT921X_PORT_QOS_SVLAN_PRIO_MAP_ID BIT(4) 291 #define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1) 292 #define YT921X_PORT_QOS_PRIO(x) FIELD_PREP(YT921X_PORT_QOS_PRIO_M, (x)) 293 #define YT921X_PORT_QOS_PRIO_EN BIT(0) 294 #define YT921X_PORTn_PRIO_ORD(port) (0x180200 + 4 * (port)) 295 #define YT921X_PORT_PRIO_ORD_APPm_M(m) GENMASK(3 * (m) + 2, 3 * (m)) 296 #define YT921X_PORT_PRIO_ORD_APPm(m, x) ((x) << (3 * (m))) /* 0: disabled, except PORT_QOS_PRIO */ 297 298 enum yt921x_app_selector { 299 YT921X_APP_SEL_MAC_SA, 300 YT921X_APP_SEL_MAC_DA, 301 YT921X_APP_SEL_VID, 302 YT921X_APP_SEL_ACL, 303 YT921X_APP_SEL_DSCP, 304 YT921X_APP_SEL_CVLAN_PCP, 305 YT921X_APP_SEL_SVLAN_PCP, 306 /* The physical port, i.e. YT921X_PORT_QOS_PRIO */ 307 YT921X_APP_SEL_PORT, 308 YT921X_APP_SEL_NUM 309 }; 310 311 #define YT921X_VLAN_IGR_FILTER 0x180280 312 #define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11) 313 #define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port) 314 #define YT921X_PORTn_ISOLATION(port) (0x180294 + 4 * (port)) 315 #define YT921X_PORT_ISOLATION_BLOCKn(port) BIT(port) 316 #define YT921X_STPn(n) (0x18038c + 4 * (n)) 317 #define YT921X_STP_PORTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 318 #define YT921X_STP_PORTn(port, x) ((x) << (2 * (port))) 319 #define YT921X_STP_PORTn_DISABLED(port) YT921X_STP_PORTn(port, 0) 320 #define YT921X_STP_PORTn_LEARNING(port) YT921X_STP_PORTn(port, 1) 321 #define YT921X_STP_PORTn_BLOCKING(port) YT921X_STP_PORTn(port, 2) 322 #define YT921X_STP_PORTn_FORWARD(port) YT921X_STP_PORTn(port, 3) 323 #define YT921X_PORTn_LEARN(port) (0x1803d0 + 4 * (port)) 324 #define YT921X_PORT_LEARN_VID_LEARN_MULTI_EN BIT(22) 325 #define YT921X_PORT_LEARN_VID_LEARN_MODE BIT(21) 326 #define YT921X_PORT_LEARN_VID_LEARN_EN BIT(20) 327 #define YT921X_PORT_LEARN_SUSPEND_COPY_EN BIT(19) 328 #define YT921X_PORT_LEARN_SUSPEND_DROP_EN BIT(18) 329 #define YT921X_PORT_LEARN_DIS BIT(17) 330 #define YT921X_PORT_LEARN_LIMIT_EN BIT(16) 331 #define YT921X_PORT_LEARN_LIMIT_M GENMASK(15, 8) 332 #define YT921X_PORT_LEARN_LIMIT(x) FIELD_PREP(YT921X_PORT_LEARN_LIMIT_M, (x)) 333 #define YT921X_PORT_LEARN_DROP_ON_EXCEEDED BIT(2) 334 #define YT921X_PORT_LEARN_MODE_M GENMASK(1, 0) 335 #define YT921X_PORT_LEARN_MODE(x) FIELD_PREP(YT921X_PORT_LEARN_MODE_M, (x)) 336 #define YT921X_PORT_LEARN_MODE_AUTO YT921X_PORT_LEARN_MODE(0) 337 #define YT921X_PORT_LEARN_MODE_AUTO_AND_COPY YT921X_PORT_LEARN_MODE(1) 338 #define YT921X_PORT_LEARN_MODE_CPU_CONTROL YT921X_PORT_LEARN_MODE(2) 339 #define YT921X_AGEING 0x180440 340 #define YT921X_AGEING_INTERVAL_M GENMASK(15, 0) 341 #define YT921X_FDB_IN0 0x180454 342 #define YT921X_FDB_IN1 0x180458 343 #define YT921X_FDB_IN2 0x18045c 344 #define YT921X_FDB_OP 0x180460 345 #define YT921X_FDB_OP_INDEX_M GENMASK(22, 11) 346 #define YT921X_FDB_OP_INDEX(x) FIELD_PREP(YT921X_FDB_OP_INDEX_M, (x)) 347 #define YT921X_FDB_OP_MODE_INDEX BIT(10) /* mac+fid / index */ 348 #define YT921X_FDB_OP_FLUSH_MCAST BIT(9) /* ucast / mcast */ 349 #define YT921X_FDB_OP_FLUSH_M GENMASK(8, 7) 350 #define YT921X_FDB_OP_FLUSH(x) FIELD_PREP(YT921X_FDB_OP_FLUSH_M, (x)) 351 #define YT921X_FDB_OP_FLUSH_ALL YT921X_FDB_OP_FLUSH(0) 352 #define YT921X_FDB_OP_FLUSH_PORT YT921X_FDB_OP_FLUSH(1) 353 #define YT921X_FDB_OP_FLUSH_PORT_VID YT921X_FDB_OP_FLUSH(2) 354 #define YT921X_FDB_OP_FLUSH_VID YT921X_FDB_OP_FLUSH(3) 355 #define YT921X_FDB_OP_FLUSH_STATIC BIT(6) 356 #define YT921X_FDB_OP_NEXT_TYPE_M GENMASK(5, 4) 357 #define YT921X_FDB_OP_NEXT_TYPE(x) FIELD_PREP(YT921X_FDB_OP_NEXT_TYPE_M, (x)) 358 #define YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT YT921X_FDB_OP_NEXT_TYPE(0) 359 #define YT921X_FDB_OP_NEXT_TYPE_UCAST_VID YT921X_FDB_OP_NEXT_TYPE(1) 360 #define YT921X_FDB_OP_NEXT_TYPE_UCAST YT921X_FDB_OP_NEXT_TYPE(2) 361 #define YT921X_FDB_OP_NEXT_TYPE_MCAST YT921X_FDB_OP_NEXT_TYPE(3) 362 #define YT921X_FDB_OP_OP_M GENMASK(3, 1) 363 #define YT921X_FDB_OP_OP(x) FIELD_PREP(YT921X_FDB_OP_OP_M, (x)) 364 #define YT921X_FDB_OP_OP_ADD YT921X_FDB_OP_OP(0) 365 #define YT921X_FDB_OP_OP_DEL YT921X_FDB_OP_OP(1) 366 #define YT921X_FDB_OP_OP_GET_ONE YT921X_FDB_OP_OP(2) 367 #define YT921X_FDB_OP_OP_GET_NEXT YT921X_FDB_OP_OP(3) 368 #define YT921X_FDB_OP_OP_FLUSH YT921X_FDB_OP_OP(4) 369 #define YT921X_FDB_OP_START BIT(0) 370 #define YT921X_FDB_RESULT 0x180464 371 #define YT921X_FDB_RESULT_DONE BIT(15) 372 #define YT921X_FDB_RESULT_NOTFOUND BIT(14) 373 #define YT921X_FDB_RESULT_OVERWRITED BIT(13) 374 #define YT921X_FDB_RESULT_INDEX_M GENMASK(11, 0) 375 #define YT921X_FDB_RESULT_INDEX(x) FIELD_PREP(YT921X_FDB_RESULT_INDEX_M, (x)) 376 #define YT921X_FDB_OUT0 0x1804b0 377 #define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0) 378 #define YT921X_FDB_OUT1 0x1804b4 379 #define YT921X_FDB_IO1_EGR_PRIO_EN BIT(31) 380 #define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28) 381 #define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (x)) 382 #define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0) 383 #define YT921X_FDB_IO1_STATUS_MIN_TIME YT921X_FDB_IO1_STATUS(1) 384 #define YT921X_FDB_IO1_STATUS_MOVE_AGING_MAX_TIME YT921X_FDB_IO1_STATUS(3) 385 #define YT921X_FDB_IO1_STATUS_MAX_TIME YT921X_FDB_IO1_STATUS(5) 386 #define YT921X_FDB_IO1_STATUS_PENDING YT921X_FDB_IO1_STATUS(6) 387 #define YT921X_FDB_IO1_STATUS_STATIC YT921X_FDB_IO1_STATUS(7) 388 #define YT921X_FDB_IO1_FID_M GENMASK(27, 16) /* filtering ID (VID) */ 389 #define YT921X_FDB_IO1_FID(x) FIELD_PREP(YT921X_FDB_IO1_FID_M, (x)) 390 #define YT921X_FDB_IO1_ADDR_LO2_M GENMASK(15, 0) 391 #define YT921X_FDB_OUT2 0x1804b8 392 #define YT921X_FDB_IO2_MOVE_AGING_STATUS_M GENMASK(31, 30) 393 #define YT921X_FDB_IO2_IGR_DROP BIT(29) 394 #define YT921X_FDB_IO2_EGR_PORTS_M GENMASK(28, 18) 395 #define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORTS_M, (x)) 396 #define YT921X_FDB_IO2_EGR_DROP BIT(17) 397 #define YT921X_FDB_IO2_COPY_TO_CPU BIT(16) 398 #define YT921X_FDB_IO2_IGR_PRIO_EN BIT(15) 399 #define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12) 400 #define YT921X_FDB_IO2_PRIO(x) FIELD_PREP(YT921X_FDB_IO2_PRIO_M, (x)) 401 #define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0) 402 #define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M, (x)) 403 #define YT921X_FILTER_UNK_UCAST 0x180508 404 #define YT921X_FILTER_UNK_MCAST 0x18050c 405 #define YT921X_FILTER_MCAST 0x180510 406 #define YT921X_FILTER_BCAST 0x180514 407 #define YT921X_FILTER_PORTS_M GENMASK(10, 0) 408 #define YT921X_FILTER_PORTS(x) FIELD_PREP(YT921X_FILTER_PORTS_M, (x)) 409 #define YT921X_FILTER_PORTn(port) BIT(port) 410 #define YT921X_VLAN_EGR_FILTER 0x180598 411 #define YT921X_VLAN_EGR_FILTER_PORTn(port) BIT(port) 412 #define YT921X_LAG_GROUPn(n) (0x1805a8 + 4 * (n)) 413 #define YT921X_LAG_GROUP_PORTS_M GENMASK(13, 3) 414 #define YT921X_LAG_GROUP_PORTS(x) FIELD_PREP(YT921X_LAG_GROUP_PORTS_M, (x)) 415 #define YT921X_LAG_GROUP_MEMBER_NUM_M GENMASK(2, 0) 416 #define YT921X_LAG_GROUP_MEMBER_NUM(x) FIELD_PREP(YT921X_LAG_GROUP_MEMBER_NUM_M, (x)) 417 #define YT921X_LAG_MEMBERnm(n, m) (0x1805b0 + 4 * (4 * (n) + (m))) 418 #define YT921X_LAG_MEMBER_PORT_M GENMASK(3, 0) 419 #define YT921X_LAG_MEMBER_PORT(x) FIELD_PREP(YT921X_LAG_MEMBER_PORT_M, (x)) 420 #define YT921X_CPU_COPY 0x180690 421 #define YT921X_CPU_COPY_FORCE_INT_PORT BIT(2) 422 #define YT921X_CPU_COPY_TO_INT_CPU BIT(1) 423 #define YT921X_CPU_COPY_TO_EXT_CPU BIT(0) 424 #define YT921X_ACL_PERMIT_UNMATCH 0x1806a0 425 #define YT921X_ACL_PERMIT_UNMATCH_PORTS_M GENMASK(10, 0) 426 #define YT921X_ACL_PERMIT_UNMATCH_PORTS(x) FIELD_PREP(YT921X_ACL_PERMIT_UNMATCH_PORTS_M, (x)) 427 #define YT921X_ACL_PERMIT_UNMATCH_PORTn(port) BIT(port) 428 #define YT921X_ACT_UNK_UCAST 0x180734 429 #define YT921X_ACT_UNK_MCAST 0x180738 430 #define YT921X_ACT_UNK_MCAST_BYPASS_DROP_RMA BIT(23) 431 #define YT921X_ACT_UNK_MCAST_BYPASS_DROP_IGMP BIT(22) 432 #define YT921X_ACT_UNK_ACTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 433 #define YT921X_ACT_UNK_ACTn(port, x) ((x) << (2 * (port))) 434 #define YT921X_ACT_UNK_ACTn_FORWARD(port) YT921X_ACT_UNK_ACTn(port, 0) /* flood */ 435 #define YT921X_ACT_UNK_ACTn_TRAP(port) YT921X_ACT_UNK_ACTn(port, 1) /* steer to CPU */ 436 #define YT921X_ACT_UNK_ACTn_DROP(port) YT921X_ACT_UNK_ACTn(port, 2) /* discard */ 437 /* NEVER use this action; see comments in the tag driver */ 438 #define YT921X_ACT_UNK_ACTn_COPY(port) YT921X_ACT_UNK_ACTn(port, 3) /* flood and copy */ 439 #define YT921X_FDB_HW_FLUSH 0x180958 440 #define YT921X_FDB_HW_FLUSH_ON_LINKDOWN BIT(0) 441 442 #define YT921X_VLANn_CTRL(vlan) (0x188000 + 8 * (vlan)) 443 #define YT921X_VLAN_CTRLb_UNTAG_PORTS_M GENMASK(18, 8) 444 #define YT921X_VLAN_CTRLb_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLb_UNTAG_PORTS_M, (x)) 445 #define YT921X_VLAN_CTRLb_UNTAG_PORTn(port) BIT((port) + 8) 446 #define YT921X_VLAN_CTRLb_STP_ID_M GENMASK(7, 4) 447 #define YT921X_VLAN_CTRLb_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRLb_STP_ID_M, (x)) 448 #define YT921X_VLAN_CTRLb_SVLAN_EN BIT(3) 449 #define YT921X_VLAN_CTRLab_FID_M GENMASK_ULL(34, 23) 450 #define YT921X_VLAN_CTRLab_FID(x) FIELD_PREP(YT921X_VLAN_CTRLab_FID_M, (x)) 451 #define YT921X_VLAN_CTRLa_LEARN_DIS BIT(22) 452 #define YT921X_VLAN_CTRLa_PRIO_EN BIT(21) 453 #define YT921X_VLAN_CTRLa_PRIO_M GENMASK(20, 18) 454 #define YT921X_VLAN_CTRLa_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRLa_PRIO_M, (x)) 455 #define YT921X_VLAN_CTRLa_PORTS_M GENMASK(17, 7) 456 #define YT921X_VLAN_CTRLa_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLa_PORTS_M, (x)) 457 #define YT921X_VLAN_CTRLa_PORTn(port) BIT((port) + 7) 458 #define YT921X_VLAN_CTRLa_BYPASS_1X_AC BIT(6) 459 #define YT921X_VLAN_CTRLa_METER_EN BIT(5) 460 #define YT921X_VLAN_CTRLa_METER_ID_M GENMASK(4, 0) 461 462 #define YT921X_ACLn_ACT(n) (0x1c0000 + 0x10 * (n)) 463 #define YT921X_ACL_ACTc_STAG_M GENMASK(26, 25) 464 #define YT921X_ACL_ACTc_STAG(x) FIELD_PREP(YT921X_ACL_ACTc_STAG_M, (x)) 465 #define YT921X_ACL_ACTc_STAG_DONTCARE YT921X_ACL_ACTc_STAG(0) 466 #define YT921X_ACL_ACTc_STAG_UNTAG YT921X_ACL_ACTc_STAG(1) 467 #define YT921X_ACL_ACTc_STAG_TAG YT921X_ACL_ACTc_STAG(2) 468 #define YT921X_ACL_ACTc_STAG_KEEP YT921X_ACL_ACTc_STAG(3) 469 #define YT921X_ACL_ACTc_CTAG_M GENMASK(24, 23) 470 #define YT921X_ACL_ACTc_CTAG(x) FIELD_PREP(YT921X_ACL_ACTc_CTAG_M, (x)) 471 #define YT921X_ACL_ACTc_CTAG_DONTCARE YT921X_ACL_ACTc_CTAG(0) 472 #define YT921X_ACL_ACTc_CTAG_UNTAG YT921X_ACL_ACTc_CTAG(1) 473 #define YT921X_ACL_ACTc_CTAG_TAG YT921X_ACL_ACTc_CTAG(2) 474 #define YT921X_ACL_ACTc_CTAG_KEEP YT921X_ACL_ACTc_CTAG(3) 475 #define YT921X_ACL_ACTc_FWD_M GENMASK(22, 21) 476 #define YT921X_ACL_ACTc_FWD(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_M, (x)) 477 #define YT921X_ACL_ACTc_FWD_FWD YT921X_ACL_ACTc_FWD(0) 478 #define YT921X_ACL_ACTc_FWD_COPY YT921X_ACL_ACTc_FWD(1) 479 #define YT921X_ACL_ACTc_FWD_REDIR YT921X_ACL_ACTc_FWD(2) 480 #define YT921X_ACL_ACTc_FWD_TRAP YT921X_ACL_ACTc_FWD(3) 481 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M GENMASK(20, 10) 482 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M, (x)) 483 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTn(port) BIT((port) + 10) 484 #define YT921X_ACL_ACTc_FWD_EN BIT(9) 485 #define YT921X_ACL_ACTc_SDEI BIT(8) 486 #define YT921X_ACL_ACTc_SDEI_REPLACE BIT(7) 487 #define YT921X_ACL_ACTc_SPRI_M GENMASK(6, 4) 488 #define YT921X_ACL_ACTc_SPRI(x) FIELD_PREP(YT921X_ACL_ACTc_SPRI_M, (x)) 489 #define YT921X_ACL_ACTc_SPRI_REPLACE BIT(3) 490 #define YT921X_ACL_ACTbc_SVID_M GENMASK_ULL(34, 23) 491 #define YT921X_ACL_ACTbc_SVID(x) FIELD_PREP(YT921X_ACL_ACTbc_SVID_M, (x)) 492 #define YT921X_ACL_ACTb_SVID_REPLACE BIT(22) 493 #define YT921X_ACL_ACTb_CDEI BIT(21) 494 #define YT921X_ACL_ACTb_CDEI_REPLACE BIT(20) 495 #define YT921X_ACL_ACTb_CPRI_M GENMASK(19, 17) 496 #define YT921X_ACL_ACTb_CPRI(x) FIELD_PREP(YT921X_ACL_ACTb_CPRI_M, (x)) 497 #define YT921X_ACL_ACTb_CPRI_REPLACE BIT(16) 498 #define YT921X_ACL_ACTb_CVID_M GENMASK(15, 4) 499 #define YT921X_ACL_ACTb_CVID(x) FIELD_PREP(YT921X_ACL_ACTb_CVID_M, (x)) 500 #define YT921X_ACL_ACTb_CVID_REPLACE BIT(3) 501 #define YT921X_ACL_ACTb_PRIO_M GENMASK(2, 0) 502 #define YT921X_ACL_ACTb_PRIO(x) FIELD_PREP(YT921X_ACL_ACTb_PRIO_M, (x)) 503 #define YT921X_ACL_ACTa_PRIO_EN BIT(31) 504 #define YT921X_ACL_ACTa_COLOR_M GENMASK(30, 29) 505 #define YT921X_ACL_ACTa_COLOR(x) FIELD_PREP(YT921X_ACL_ACTa_COLOR_M, (x)) 506 #define YT921X_ACL_ACTa_COLOR_GREEN YT921X_ACL_ACTa_COLOR(0) 507 #define YT921X_ACL_ACTa_COLOR_YELLOW YT921X_ACL_ACTa_COLOR(1) 508 #define YT921X_ACL_ACTa_COLOR_RED YT921X_ACL_ACTa_COLOR(2) 509 #define YT921X_ACL_ACTa_COLOR_EN BIT(28) 510 #define YT921X_ACL_ACTa_DSCP_M GENMASK(27, 22) 511 #define YT921X_ACL_ACTa_DSCP(x) FIELD_PREP(YT921X_ACL_ACTa_DSCP_M, (x)) 512 #define YT921X_ACL_ACTa_DSCP_REPLACE BIT(21) 513 #define YT921X_ACL_ACTa_METER_ID_M GENMASK(20, 15) 514 #define YT921X_ACL_ACTa_METER_ID(x) FIELD_PREP(YT921X_ACL_ACTa_METER_ID_M, (x)) 515 #define YT921X_ACL_ACTa_METER_EN BIT(14) 516 #define YT921X_ACL_ACTa_MIRROR_EN BIT(13) 517 #define YT921X_ACL_ACTa_FLOWSTAT_EN BIT(12) 518 #define YT921X_ACL_ACTa_FLOWSTAT_ID_M GENMASK(11, 6) 519 #define YT921X_ACL_ACTa_FLOWSTAT_ID(x) FIELD_PREP(YT921X_ACL_ACTa_FLOWSTAT_ID_M, (x)) 520 #define YT921X_ACL_ACTa_GPIO_EN BIT(5) 521 #define YT921X_ACL_ACTa_GPIO_PIN_M GENMASK(4, 1) 522 #define YT921X_ACL_ACTa_GPIO_PIN(x) FIELD_PREP(YT921X_ACL_ACTa_GPIO_PIN_M, (x)) 523 #define YT921X_ACL_ACTa_INTR_EN BIT(0) 524 #define YT921X_ACL_BLK_KEEP 0x201000 525 #define YT921X_ACL_BLK_KEEP_GRPIDn_M(bin) (7 << (4 * (bin) + 1)) 526 #define YT921X_ACL_BLK_KEEP_GRPIDn(bin, x) ((x) << (4 * (bin) + 1)) 527 #define YT921X_ACL_BLK_KEEP_KEEPn(bin) BIT(4 * (bin)) 528 #define YT921X_ACL_PORT 0x202000 529 #define YT921X_ACL_PORT_PORTS_M GENMASK(10, 0) 530 #define YT921X_ACL_PORT_PORTS(x) FIELD_PREP(YT921X_ACL_PORT_PORTS_M, (x)) 531 #define YT921X_ACL_PORT_PORTn(port) BIT(port) 532 #define YT921X_ACL_BLK_CMD 0x202004 533 #define YT921X_ACL_BLK_CMD_BLKID_M GENMASK(6, 1) 534 #define YT921X_ACL_BLK_CMD_BLKID(x) FIELD_PREP(YT921X_ACL_BLK_CMD_BLKID_M, (x)) 535 #define YT921X_ACL_BLK_CMD_MODIFY BIT(0) 536 #define YT921X_ACLn_ENTRY(blk) (0x203000 + 4 * (blk)) 537 #define YT921X_ACL_ENTRY_GRPIDm_M(bin) (7 << (4 * (bin) + 1)) 538 #define YT921X_ACL_ENTRY_GRPIDm(bin, x) ((x) << (4 * (bin) + 1)) 539 #define YT921X_ACL_ENTRY_ENm(bin) BIT(4 * (bin)) 540 #define YT921X_ACLn_KEYm(blk, bin) (0x204000 + 0x200 * (bin) + 8 * (blk)) 541 #define YT921X_ACL_KEYb_ORD_M GENMASK(29, 21) 542 #define YT921X_ACL_KEYb_ORD(x) FIELD_PREP(YT921X_ACL_KEYb_ORD_M, (x)) 543 #define YT921X_ACL_KEYb_SPORTS_M GENMASK(20, 10) 544 #define YT921X_ACL_KEYb_SPORTS(x) FIELD_PREP(YT921X_ACL_KEYb_SPORTS_M, (x)) 545 #define YT921X_ACL_KEYb_SPORTn(port) BIT((port) + 10) 546 #define YT921X_ACL_KEYb_REVERSE BIT(9) /* reverse match */ 547 #define YT921X_ACL_KEYb_TYPE_M GENMASK(8, 4) 548 #define YT921X_ACL_KEYb_TYPE(x) FIELD_PREP(YT921X_ACL_KEYb_TYPE_M, (x)) 549 /* KEY_* fields need no masks */ 550 #define YT921X_ACLn_MASKm(blk, bin) (0x205000 + 0x200 * (bin) + 8 * (blk)) 551 552 enum yt921x_acl_type { 553 YT921X_ACL_TYPE_NA, 554 YT921X_ACL_TYPE_MAC_DA0, 555 YT921X_ACL_TYPE_MAC_SA0, 556 YT921X_ACL_TYPE_MAC_DA1_SA1, 557 YT921X_ACL_TYPE_VLAN, 558 YT921X_ACL_TYPE_VTAG, 559 YT921X_ACL_TYPE_IPV4_DA, 560 YT921X_ACL_TYPE_IPV4_SA, 561 YT921X_ACL_TYPE_IPV6_DA0, 562 YT921X_ACL_TYPE_IPV6_DA1, 563 YT921X_ACL_TYPE_IPV6_DA2, 564 YT921X_ACL_TYPE_IPV6_DA3, 565 YT921X_ACL_TYPE_IPV6_SA0, 566 YT921X_ACL_TYPE_IPV6_SA1, 567 YT921X_ACL_TYPE_IPV6_SA2, 568 YT921X_ACL_TYPE_IPV6_SA3, 569 YT921X_ACL_TYPE_MISC, 570 YT921X_ACL_TYPE_L4, 571 YT921X_ACL_TYPE_UDF0, 572 YT921X_ACL_TYPE_UDF1, 573 YT921X_ACL_TYPE_UDF2, 574 YT921X_ACL_TYPE_UDF3, 575 YT921X_ACL_TYPE_UDF4, 576 YT921X_ACL_TYPE_UDF5, 577 YT921X_ACL_TYPE_UDF6, 578 YT921X_ACL_TYPE_UDF7, 579 YT921X_ACL_TYPE_ETHERTYPE, 580 YT921X_ACL_TYPE_NUM 581 }; 582 583 /* Range: turn KEY:MASK into MIN:MAX */ 584 585 #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M GENMASK(3, 0) 586 #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M, (x)) 587 #define YT921X_ACL_BINa_MAC_xA0_MAC_xA0_M GENMASK(31, 0) 588 589 #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M GENMASK(2, 0) 590 #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M, (x)) 591 #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_DA1_M GENMASK(31, 16) 592 #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_SA1_M GENMASK(15, 0) 593 594 #define YT921X_ACL_KEYb_VLAN_SVID_RANGE_EN BIT(31) 595 #define YT921X_ACL_KEYb_VLAN_CVID_RANGE_EN BIT(30) 596 #define YT921X_ACL_BINb_VLAN_CDEI BIT(3) 597 #define YT921X_ACL_BINb_VLAN_CPRI_M GENMASK(2, 0) 598 #define YT921X_ACL_BINb_VLAN_CPRI(x) FIELD_PREP(YT921X_ACL_BINb_VLAN_CPRI_M, (x)) 599 #define YT921X_ACL_BINa_VLAN_CTAG_FMT_M GENMASK(31, 30) 600 #define YT921X_ACL_BINa_VLAN_CTAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CTAG_FMT_M, (x)) 601 #define YT921X_ACL_BINa_VLAN_SDEI BIT(29) 602 #define YT921X_ACL_BINa_VLAN_SPRI_M GENMASK(28, 26) 603 #define YT921X_ACL_BINa_VLAN_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SPRI_M, (x)) 604 #define YT921X_ACL_BINa_VLAN_STAG_FMT_M GENMASK(25, 24) 605 #define YT921X_ACL_BINa_VLAN_STAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_STAG_FMT_M, (x)) 606 #define YT921X_ACL_BINa_VLAN_SVID_M GENMASK(23, 12) 607 #define YT921X_ACL_BINa_VLAN_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SVID_M, (x)) 608 #define YT921X_ACL_BINa_VLAN_CVID_M GENMASK(11, 0) 609 #define YT921X_ACL_BINa_VLAN_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CVID_M, (x)) 610 611 #define YT921X_ACL_KEYb_VTAG_SVID_RANGE_EN BIT(31) 612 #define YT921X_ACL_KEYb_VTAG_CVID_RANGE_EN BIT(30) 613 #define YT921X_ACL_BINa_VTAG_CDEI BIT(31) 614 #define YT921X_ACL_BINa_VTAG_CPRI_M GENMASK(30, 28) 615 #define YT921X_ACL_BINa_VTAG_CPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CPRI_M, (x)) 616 #define YT921X_ACL_BINa_VTAG_SDEI BIT(27) 617 #define YT921X_ACL_BINa_VTAG_SPRI_M GENMASK(26, 24) 618 #define YT921X_ACL_BINa_VTAG_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SPRI_M, (x)) 619 #define YT921X_ACL_BINa_VTAG_SVID_M GENMASK(23, 12) 620 #define YT921X_ACL_BINa_VTAG_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SVID_M, (x)) 621 #define YT921X_ACL_BINa_VTAG_CVID_M GENMASK(11, 0) 622 #define YT921X_ACL_BINa_VTAG_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CVID_M, (x)) 623 624 #define YT921X_ACL_KEYb_IPV4_ADDR_RANGE_EN BIT(30) 625 #define YT921X_ACL_BINb_IPV4_FRAG BIT(3) 626 #define YT921X_ACL_BINb_IPV4_L4_TYPE_M GENMASK(2, 0) 627 #define YT921X_ACL_BINb_IPV4_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV4_L4_TYPE_M, (x)) 628 #define YT921X_ACL_BINa_IPV4_ADDR_M GENMASK(31, 0) 629 630 #define YT921X_ACL_BINb_IPV6_L4_TYPE_M GENMASK(2, 0) 631 #define YT921X_ACL_BINb_IPV6_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV6_L4_TYPE_M, (x)) 632 #define YT921X_ACL_BINa_IPV6_ADDRx_M GENMASK(31, 0) 633 634 #define YT921X_ACL_BINb_IPV6_xA1_IP_OPTION BIT(3) 635 636 #define YT921X_ACL_BINb_IPV6_xA2_FIRST_FRAG BIT(3) 637 638 #define YT921X_ACL_KEYb_IPV6_xA3_ADDR_RANGE_EN BIT(30) 639 #define YT921X_ACL_BINb_IPV6_xA3_FRAG BIT(3) 640 641 #define YT921X_ACL_BINb_MISC_FRAG BIT(3) 642 #define YT921X_ACL_BINb_MISC_L4_TYPE_M GENMASK(2, 0) 643 #define YT921X_ACL_BINb_MISC_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MISC_L4_TYPE_M, (x)) 644 #define YT921X_ACL_BINa_MISC_PPPOE_FLAG BIT(30) 645 #define YT921X_ACL_BINa_MISC_FIRST_FRAG BIT(29) 646 #define YT921X_ACL_BINa_MISC_IP_OPTION BIT(28) 647 #define YT921X_ACL_BINa_MISC_TCP_FLAGS_M GENMASK(27, 20) 648 #define YT921X_ACL_BINa_MISC_TCP_FLAGS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TCP_FLAGS_M, (x)) 649 #define YT921X_ACL_BINa_MISC_IP_PROTO_M GENMASK(19, 12) 650 #define YT921X_ACL_BINa_MISC_IP_PROTO(x) FIELD_PREP(YT921X_ACL_BINa_MISC_IP_PROTO_M, (x)) 651 #define YT921X_ACL_BINa_MISC_TOS_M GENMASK(11, 4) 652 #define YT921X_ACL_BINa_MISC_TOS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TOS_M, (x)) 653 #define YT921X_ACL_BINa_MISC_L3_TYPE_M GENMASK(3, 0) 654 #define YT921X_ACL_BINa_MISC_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINa_MISC_L3_TYPE_M, (x)) 655 656 #define YT921X_ACL_KEYb_L4_DPORT_RANGE_EN BIT(31) 657 #define YT921X_ACL_KEYb_L4_SPORT_RANGE_EN BIT(30) 658 #define YT921X_ACL_BINb_L4_FRAG BIT(3) 659 #define YT921X_ACL_BINb_L4_TYPE_M GENMASK(2, 0) 660 #define YT921X_ACL_BINb_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_L4_TYPE_M, (x)) 661 #define YT921X_ACL_BINa_L4_DPORT_M GENMASK(31, 16) 662 #define YT921X_ACL_BINa_L4_SPORT_M GENMASK(15, 0) 663 664 #define YT921X_ACL_BINb_UDF_IS_IGMP BIT(0) 665 #define YT921X_ACL_BINa_UDF_UDF0_M GENMASK(31, 16) 666 #define YT921X_ACL_BINa_UDF_UDF0(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF0_M, (x)) 667 #define YT921X_ACL_BINa_UDF_UDF1_M GENMASK(15, 0) 668 #define YT921X_ACL_BINa_UDF_UDF1(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF1_M, (x)) 669 670 #define YT921X_ACL_KEYb_ETHERTYPE_ETHERTYPE_RANGE_EN BIT(30) 671 #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M GENMASK(2, 0) 672 #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M, (x)) 673 #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M GENMASK(15, 0) 674 #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE(x) FIELD_PREP(YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M, (x)) 675 676 enum yt921x_l2_type { 677 YT921X_L2_TYPE_ETH, 678 YT921X_L2_TYPE_ETHV2, 679 YT921X_L2_TYPE_ETHSAP, 680 YT921X_L2_TYPE_ETHSNAP, 681 }; 682 683 enum yt921x_l3_type { 684 YT921X_L3_TYPE_OTHER, 685 YT921X_L3_TYPE_IPV4, 686 YT921X_L3_TYPE_IPV6, 687 YT921X_L3_TYPE_ARP, 688 YT921X_L3_TYPE_LLDP, 689 YT921X_L3_TYPE_PAE, 690 YT921X_L3_TYPE_ERP, 691 YT921X_L3_TYPE_SLOW_PROTOCOL, 692 }; 693 694 enum yt921x_l4_type { 695 YT921X_L4_TYPE_OTHER, 696 YT921X_L4_TYPE_TCP, 697 YT921X_L4_TYPE_UDP, 698 YT921X_L4_TYPE_UDPLITE, 699 YT921X_L4_TYPE_ICMP, 700 YT921X_L4_TYPE_IGMP, 701 YT921X_L4_TYPE_MLD, 702 YT921X_L4_TYPE_ND, 703 }; 704 705 #define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */ 706 #define YT921X_TPID_IGR_TPID_M GENMASK(15, 0) 707 #define YT921X_PORTn_IGR_TPID(port) (0x210010 + 4 * (port)) 708 #define YT921X_PORT_IGR_TPIDn_STAG_M GENMASK(7, 4) 709 #define YT921X_PORT_IGR_TPIDn_STAG(x) BIT((x) + 4) 710 #define YT921X_PORT_IGR_TPIDn_CTAG_M GENMASK(3, 0) 711 #define YT921X_PORT_IGR_TPIDn_CTAG(x) BIT(x) 712 #define YT921X_LAG_HASH 0x210090 713 #define YT921X_LAG_HASH_L4_SPORT BIT(7) 714 #define YT921X_LAG_HASH_L4_DPORT BIT(6) 715 #define YT921X_LAG_HASH_IP_PROTO BIT(5) 716 #define YT921X_LAG_HASH_IP_SRC BIT(4) 717 #define YT921X_LAG_HASH_IP_DST BIT(3) 718 #define YT921X_LAG_HASH_MAC_SA BIT(2) 719 #define YT921X_LAG_HASH_MAC_DA BIT(1) 720 #define YT921X_LAG_HASH_SRC_PORT BIT(0) 721 #define YT921X_UDFn_CTRL(x) (0x210094 + 4 * (x)) 722 #define YT921X_UDF_CTRL_UDF_TYPE_M GENMASK(8, 7) 723 #define YT921X_UDF_CTRL_UDF_TYPE(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_TYPE_M, (x)) 724 #define YT921X_UDF_CTRL_UDF_TYPE_ETH YT921X_UDF_CTRL_UDF_TYPE(0) 725 #define YT921X_UDF_CTRL_UDF_TYPE_L3 YT921X_UDF_CTRL_UDF_TYPE(1) 726 #define YT921X_UDF_CTRL_UDF_TYPE_L4 YT921X_UDF_CTRL_UDF_TYPE(2) 727 #define YT921X_UDF_CTRL_UDF_OFFSET_M GENMASK(6, 0) 728 #define YT921X_UDF_CTRL_UDF_OFFSET(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_OFFSET_M, (x)) 729 730 #define YT921X_PORTn_RATE(port) (0x220000 + 4 * (port)) 731 #define YT921X_PORT_RATE_GAP_VALUE GENMASK(4, 0) /* default 20 */ 732 #define YT921X_METER_SLOT 0x220104 733 #define YT921X_METER_SLOT_SLOT_M GENMASK(11, 0) 734 #define YT921X_PORTn_METER(port) (0x220108 + 4 * (port)) 735 #define YT921X_PORT_METER_EN BIT(4) 736 #define YT921X_PORT_METER_ID_M GENMASK(3, 0) 737 #define YT921X_PORT_METER_ID(x) FIELD_PREP(YT921X_PORT_METER_ID_M, (x)) 738 #define YT921X_METERn_CTRL(x) (0x220800 + 0x10 * (x)) 739 #define YT921X_METER_CTRLc_METER_EN BIT(14) 740 #define YT921X_METER_CTRLc_TOKEN_OVERFLOW_EN BIT(13) /* RFC4115: yellow use unused green bw */ 741 #define YT921X_METER_CTRLc_DROP_M GENMASK(12, 11) 742 #define YT921X_METER_CTRLc_DROP(x) FIELD_PREP(YT921X_METER_CTRLc_DROP_M, (x)) 743 #define YT921X_METER_CTRLc_DROP_GYR YT921X_METER_CTRLc_DROP(0) 744 #define YT921X_METER_CTRLc_DROP_YR YT921X_METER_CTRLc_DROP(1) 745 #define YT921X_METER_CTRLc_DROP_R YT921X_METER_CTRLc_DROP(2) 746 #define YT921X_METER_CTRLc_DROP_NONE YT921X_METER_CTRLc_DROP(3) 747 #define YT921X_METER_CTRLc_COLOR_BLIND BIT(10) 748 #define YT921X_METER_CTRLc_UNIT_M GENMASK(9, 7) 749 #define YT921X_METER_CTRLc_UNIT(x) FIELD_PREP(YT921X_METER_CTRLc_UNIT_M, (x)) 750 #define YT921X_METER_CTRLc_BYTE_MODE_INCLUDE_GAP BIT(6) /* +GAP_VALUE bytes each packet */ 751 #define YT921X_METER_CTRLc_PKT_MODE BIT(5) /* 0: byte rate mode */ 752 #define YT921X_METER_CTRLc_RFC2698 BIT(4) /* 0: RFC4115 */ 753 #define YT921X_METER_CTRLbc_CBS_M GENMASK_ULL(35, 20) 754 #define YT921X_METER_CTRLbc_CBS(x) FIELD_PREP(YT921X_METER_CTRLbc_CBS_M, (x)) 755 #define YT921X_METER_CTRLb_CIR_M GENMASK(19, 2) 756 #define YT921X_METER_CTRLb_CIR(x) FIELD_PREP(YT921X_METER_CTRLb_CIR_M, (x)) 757 #define YT921X_METER_CTRLab_EBS_M GENMASK_ULL(33, 18) 758 #define YT921X_METER_CTRLab_EBS(x) FIELD_PREP(YT921X_METER_CTRLab_EBS_M, (x)) 759 #define YT921X_METER_CTRLa_EIR_M GENMASK(17, 0) 760 #define YT921X_METER_CTRLa_EIR(x) FIELD_PREP(YT921X_METER_CTRLa_EIR_M, (x)) 761 #define YT921X_METERn_STAT(x) (0x221000 + 8 * (x)) 762 763 #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) 764 #define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31) 765 #define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30) 766 #define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18) 767 #define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_SVID_M, (x)) 768 #define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6) 769 #define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_CVID_M, (x)) 770 #define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3) 771 #define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0) 772 #define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port)) 773 #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8) 774 #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4) 775 #define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_TAGGED BIT(3) 776 #define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_UNTAGGED BIT(2) 777 #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED BIT(1) 778 #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED BIT(0) 779 780 #define YT921X_MIRROR 0x300300 781 #define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) 782 #define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_M, (x)) 783 #define YT921X_MIRROR_IGR_PORTn(port) BIT((port) + 16) 784 #define YT921X_MIRROR_EGR_PORTS_M GENMASK(14, 4) 785 #define YT921X_MIRROR_EGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_EGR_PORTS_M, (x)) 786 #define YT921X_MIRROR_EGR_PORTn(port) BIT((port) + 4) 787 #define YT921X_MIRROR_PORT_M GENMASK(3, 0) 788 #define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) 789 790 #define YT921X_PORT_SHAPE_SLOT 0x34000c 791 #define YT921X_PORT_SHAPE_SLOT_SLOT_M GENMASK(11, 0) 792 #define YT921X_PORTn_SHAPE_CTRL(port) (0x354000 + 8 * (port)) 793 #define YT921X_PORT_SHAPE_CTRLb_EN BIT(4) 794 #define YT921X_PORT_SHAPE_CTRLb_PKT_MODE BIT(3) /* 0: byte rate mode */ 795 #define YT921X_PORT_SHAPE_CTRLb_UNIT_M GENMASK(2, 0) 796 #define YT921X_PORT_SHAPE_CTRLb_UNIT(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLb_UNIT_M, (x)) 797 #define YT921X_PORT_SHAPE_CTRLa_CBS_M GENMASK(31, 18) 798 #define YT921X_PORT_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CBS_M, (x)) 799 #define YT921X_PORT_SHAPE_CTRLa_CIR_M GENMASK(17, 0) 800 #define YT921X_PORT_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CIR_M, (x)) 801 #define YT921X_PORTn_SHAPE_STAT(port) (0x356000 + 4 * (port)) 802 803 #define YT921X_EDATA_EXTMODE 0xfb 804 #define YT921X_EDATA_LEN 0x100 805 806 #define YT921X_FDB_NUM 4096 807 808 enum yt921x_fdb_entry_status { 809 YT921X_FDB_ENTRY_STATUS_INVALID = 0, 810 YT921X_FDB_ENTRY_STATUS_MIN_TIME = 1, 811 YT921X_FDB_ENTRY_STATUS_MOVE_AGING_MAX_TIME = 3, 812 YT921X_FDB_ENTRY_STATUS_MAX_TIME = 5, 813 YT921X_FDB_ENTRY_STATUS_PENDING = 6, 814 YT921X_FDB_ENTRY_STATUS_STATIC = 7, 815 }; 816 817 #define YT921X_MSTI_NUM 16 818 819 #define YT921X_TOKEN_BYTE_C 1 /* 1 token = 2^1 byte */ 820 #define YT921X_TOKEN_PKT_C -6 /* 1 token = 2^-6 packets */ 821 #define YT921X_TOKEN_RATE_C -15 822 /* Custom meters only, not including dedicated port meters (11) */ 823 #define YT921X_METER_NUM 64 824 #define YT921X_METER_SLOT_MIN 80 825 #define YT921X_METER_UNIT_MAX ((1 << 3) - 1) 826 #define YT921X_METER_CIR_MAX ((1 << 18) - 1) 827 #define YT921X_METER_CBS_MAX ((1 << 16) - 1) 828 #define YT921X_PORT_SHAPE_SLOT_MIN 80 829 #define YT921X_SHAPE_UNIT_MAX ((1 << 3) - 1) 830 #define YT921X_SHAPE_CIR_MAX ((1 << 18) - 1) 831 #define YT921X_SHAPE_CBS_MAX ((1 << 14) - 1) 832 833 #define YT921X_LAG_NUM 2 834 #define YT921X_LAG_PORT_NUM 4 835 836 #define YT921X_PRIO_NUM 8 837 838 #define YT9215_MAJOR 0x9002 839 #define YT9218_MAJOR 0x9001 840 841 /* required for a hard reset */ 842 #define YT921X_RST_DELAY_US 10000 843 844 #define YT921X_FRAME_SIZE_MAX 0x2400 /* 9216 */ 845 846 #define YT921X_TAG_LEN 8 847 848 #define YT921X_ACL_BLK_NUM 48 849 #define YT921X_ACL_ENT_PER_BLK 8 850 #define YT921X_ACL_NUM (YT921X_ACL_BLK_NUM * YT921X_ACL_ENT_PER_BLK) 851 #define YT921X_UDF_NUM 8 852 853 /* 8 internal + 2 external + 1 mcu */ 854 #define YT921X_PORT_NUM 11 855 856 #define yt921x_port_is_internal(port) ((port) < 8) 857 #define yt921x_port_is_external(port) ((port) == 8 || (port) == 9) 858 859 struct yt921x_mib { 860 u64 rx_broadcast; 861 u64 rx_pause; 862 u64 rx_multicast; 863 u64 rx_crc_errors; 864 865 u64 rx_alignment_errors; 866 u64 rx_undersize_errors; 867 u64 rx_fragment_errors; 868 u64 rx_64byte; 869 870 u64 rx_65_127byte; 871 u64 rx_128_255byte; 872 u64 rx_256_511byte; 873 u64 rx_512_1023byte; 874 875 u64 rx_1024_1518byte; 876 u64 rx_jumbo; 877 u64 rx_good_bytes; 878 879 u64 rx_bad_bytes; 880 u64 rx_oversize_errors; 881 882 u64 rx_dropped; 883 u64 tx_broadcast; 884 u64 tx_pause; 885 u64 tx_multicast; 886 887 u64 tx_undersize_errors; 888 u64 tx_64byte; 889 u64 tx_65_127byte; 890 u64 tx_128_255byte; 891 892 u64 tx_256_511byte; 893 u64 tx_512_1023byte; 894 u64 tx_1024_1518byte; 895 u64 tx_jumbo; 896 897 u64 tx_good_bytes; 898 u64 tx_collisions; 899 900 u64 tx_aborted_errors; 901 u64 tx_multiple_collisions; 902 u64 tx_single_collisions; 903 u64 tx_good; 904 905 u64 tx_deferred; 906 u64 tx_late_collisions; 907 u64 rx_oam; 908 u64 tx_oam; 909 }; 910 911 struct yt921x_acl_entry { 912 u32 key[2]; 913 u32 mask[2]; 914 }; 915 916 struct yt921x_acl_rule { 917 unsigned long tag; 918 enum tc_setup_type type; 919 920 u32 action[3]; 921 bool sw_assisted; 922 923 u8 mask; 924 struct yt921x_acl_entry entries[YT921X_ACL_ENT_PER_BLK]; 925 }; 926 927 struct yt921x_acl_blk { 928 struct yt921x_acl_rule *rules[YT921X_ACL_ENT_PER_BLK]; 929 }; 930 931 struct yt921x_port { 932 unsigned char index; 933 934 bool hairpin; 935 bool isolated; 936 937 struct delayed_work mib_read; 938 struct yt921x_mib mib; 939 u64 rx_frames; 940 u64 tx_frames; 941 }; 942 943 struct yt921x_reg_ops { 944 int (*read)(void *context, u32 reg, u32 *valp); 945 int (*write)(void *context, u32 reg, u32 val); 946 }; 947 948 struct yt921x_priv { 949 struct dsa_switch ds; 950 951 const struct yt921x_info *info; 952 unsigned int meter_slot_ns; 953 unsigned int port_shape_slot_ns; 954 /* cache of dsa_cpu_ports(ds) */ 955 u16 cpu_ports_mask; 956 unsigned char cycle_ns; 957 958 /* protect the access to the switch registers */ 959 struct mutex reg_lock; 960 const struct yt921x_reg_ops *reg_ops; 961 void *reg_ctx; 962 963 /* mdio master bus */ 964 struct mii_bus *mbus_int; 965 struct mii_bus *mbus_ext; 966 967 struct yt921x_port ports[YT921X_PORT_NUM]; 968 969 u16 eee_ports_mask; 970 971 DECLARE_BITMAP(meters_map, YT921X_METER_NUM); 972 973 u8 acl_masks[YT921X_ACL_BLK_NUM]; 974 struct yt921x_acl_blk *acl_blks[YT921X_ACL_BLK_NUM]; 975 }; 976 977 #endif 978