1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2023 Intel Corporation */ 3 4 #ifndef _ICE_ETHTOOL_H_ 5 #define _ICE_ETHTOOL_H_ 6 7 struct ice_phy_type_to_ethtool { 8 u64 aq_link_speed; 9 u8 link_mode; 10 }; 11 12 struct ice_serdes_equalization_to_ethtool { 13 int rx_equ_pre2; 14 int rx_equ_pre1; 15 int rx_equ_post1; 16 int rx_equ_bflf; 17 int rx_equ_bfhf; 18 int rx_equ_ctle_gainhf; 19 int rx_equ_ctle_gainlf; 20 int rx_equ_ctle_gaindc; 21 int rx_equ_ctle_bw; 22 int rx_equ_dfe_gain; 23 int rx_equ_dfe_gain_2; 24 int rx_equ_dfe_2; 25 int rx_equ_dfe_3; 26 int rx_equ_dfe_4; 27 int rx_equ_dfe_5; 28 int rx_equ_dfe_6; 29 int rx_equ_dfe_7; 30 int rx_equ_dfe_8; 31 int rx_equ_dfe_9; 32 int rx_equ_dfe_10; 33 int rx_equ_dfe_11; 34 int rx_equ_dfe_12; 35 int tx_equ_pre1; 36 int tx_equ_pre3; 37 int tx_equ_atten; 38 int tx_equ_post1; 39 int tx_equ_pre2; 40 }; 41 42 struct ice_regdump_to_ethtool { 43 /* A multilane port can have max 4 serdes */ 44 struct ice_serdes_equalization_to_ethtool equalization[4]; 45 }; 46 47 /* Port topology from lport i.e. 48 * serdes mapping, pcsquad, macport, cage etc... 49 */ 50 struct ice_port_topology { 51 u16 pcs_port; 52 u16 primary_serdes_lane; 53 u16 serdes_lane_count; 54 u16 pcs_quad_select; 55 }; 56 57 /* Macro to make PHY type to Ethtool link mode table entry. 58 * The index is the PHY type. 59 */ 60 #define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\ 61 .aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \ 62 .link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \ 63 } 64 65 /* Lookup table mapping PHY type low to link speed and Ethtool link modes. 66 * Array index corresponds to HW PHY type bit, see 67 * ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*. 68 */ 69 static const struct ice_phy_type_to_ethtool 70 phy_type_low_lkup[] = { 71 [0] = ICE_PHY_TYPE(100MB, 100baseT_Full), 72 [1] = ICE_PHY_TYPE(100MB, 100baseT_Full), 73 [2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full), 74 [3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full), 75 [4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full), 76 [5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full), 77 [6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full), 78 [7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full), 79 [8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full), 80 [9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full), 81 [10] = ICE_PHY_TYPE(5GB, 5000baseT_Full), 82 [11] = ICE_PHY_TYPE(5GB, 5000baseT_Full), 83 [12] = ICE_PHY_TYPE(10GB, 10000baseT_Full), 84 [13] = ICE_PHY_TYPE(10GB, 10000baseCR_Full), 85 [14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full), 86 [15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full), 87 [16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full), 88 [17] = ICE_PHY_TYPE(10GB, 10000baseCR_Full), 89 [18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full), 90 [19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 91 [20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 92 [21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 93 [22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 94 [23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 95 [24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 96 [25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 97 [26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 98 [27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full), 99 [28] = ICE_PHY_TYPE(25GB, 25000baseSR_Full), 100 [29] = ICE_PHY_TYPE(25GB, 25000baseCR_Full), 101 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full), 102 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full), 103 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full), 104 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full), 105 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full), 106 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full), 107 [36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 108 [37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 109 [38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 110 [39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full), 111 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 112 [41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 113 [42] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full), 114 [43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full), 115 [44] = ICE_PHY_TYPE(50GB, 50000baseCR_Full), 116 [45] = ICE_PHY_TYPE(50GB, 50000baseSR_Full), 117 [46] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full), 118 [47] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full), 119 [48] = ICE_PHY_TYPE(50GB, 50000baseKR_Full), 120 [49] = ICE_PHY_TYPE(50GB, 50000baseSR_Full), 121 [50] = ICE_PHY_TYPE(50GB, 50000baseCR_Full), 122 [51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 123 [52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full), 124 [53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full), 125 [54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full), 126 [55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 127 [56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 128 [57] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full), 129 [58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 130 [59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full), 131 [60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full), 132 [61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 133 [62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 134 [63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full), 135 }; 136 137 /* Lookup table mapping PHY type high to link speed and Ethtool link modes. 138 * Array index corresponds to HW PHY type bit, see 139 * ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_* 140 */ 141 static const struct ice_phy_type_to_ethtool 142 phy_type_high_lkup[] = { 143 [0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full), 144 [1] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 145 [2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 146 [3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full), 147 [4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full), 148 [5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full), 149 [6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full), 150 [7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full), 151 [8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full), 152 [9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full), 153 [10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full), 154 [11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full), 155 [12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full), 156 }; 157 158 #endif /* !_ICE_ETHTOOL_H_ */ 159