1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/bcd.h> 12 #include <linux/i2c.h> 13 #include <linux/init.h> 14 #include <linux/kstrtox.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/rtc/ds1307.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/string.h> 22 #include <linux/hwmon.h> 23 #include <linux/hwmon-sysfs.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* 29 * We can't determine type by probing, but if we expect pre-Linux code 30 * to have set the chip up as a clock (turning on the oscillator and 31 * setting the date and time), Linux can ignore the non-clock features. 32 * That's a natural job for a factory or repair bench. 33 */ 34 enum ds_type { 35 unknown_ds_type, /* always first and 0 */ 36 ds_1307, 37 ds_1308, 38 ds_1337, 39 ds_1338, 40 ds_1339, 41 ds_1340, 42 ds_1341, 43 ds_1388, 44 ds_3231, 45 m41t0, 46 m41t00, 47 m41t11, 48 mcp794xx, 49 rx_8025, 50 rx_8130, 51 last_ds_type /* always last */ 52 /* rs5c372 too? different address... */ 53 }; 54 55 /* RTC registers don't differ much, except for the century flag */ 56 #define DS1307_REG_SECS 0x00 /* 00-59 */ 57 # define DS1307_BIT_CH 0x80 58 # define DS1340_BIT_nEOSC 0x80 59 # define MCP794XX_BIT_ST 0x80 60 #define DS1307_REG_MIN 0x01 /* 00-59 */ 61 # define M41T0_BIT_OF 0x80 62 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 63 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 64 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 65 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 66 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 67 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 68 # define MCP794XX_BIT_OSCRUN BIT(5) 69 # define MCP794XX_BIT_VBATEN 0x08 70 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 71 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 72 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 73 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 74 75 /* 76 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 77 * start at 7, and they differ a LOT. Only control and status matter for 78 * basic RTC date and time functionality; be careful using them. 79 */ 80 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 81 # define DS1307_BIT_OUT 0x80 82 # define DS1338_BIT_OSF 0x20 83 # define DS1307_BIT_SQWE 0x10 84 # define DS1307_BIT_RS1 0x02 85 # define DS1307_BIT_RS0 0x01 86 #define DS1337_REG_CONTROL 0x0e 87 # define DS1337_BIT_nEOSC 0x80 88 # define DS1339_BIT_BBSQI 0x20 89 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 90 # define DS1337_BIT_RS2 0x10 91 # define DS1337_BIT_RS1 0x08 92 # define DS1337_BIT_INTCN 0x04 93 # define DS1337_BIT_A2IE 0x02 94 # define DS1337_BIT_A1IE 0x01 95 #define DS1340_REG_CONTROL 0x07 96 # define DS1340_BIT_OUT 0x80 97 # define DS1340_BIT_FT 0x40 98 # define DS1340_BIT_CALIB_SIGN 0x20 99 # define DS1340_M_CALIBRATION 0x1f 100 #define DS1340_REG_FLAG 0x09 101 # define DS1340_BIT_OSF 0x80 102 #define DS1337_REG_STATUS 0x0f 103 # define DS1337_BIT_OSF 0x80 104 # define DS3231_BIT_EN32KHZ 0x08 105 # define DS1337_BIT_A2I 0x02 106 # define DS1337_BIT_A1I 0x01 107 #define DS1339_REG_ALARM1_SECS 0x07 108 109 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 110 111 #define RX8025_REG_CTRL1 0x0e 112 # define RX8025_BIT_2412 0x20 113 #define RX8025_REG_CTRL2 0x0f 114 # define RX8025_BIT_PON 0x10 115 # define RX8025_BIT_VDET 0x40 116 # define RX8025_BIT_XST 0x20 117 118 #define RX8130_REG_ALARM_MIN 0x17 119 #define RX8130_REG_ALARM_HOUR 0x18 120 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 121 #define RX8130_REG_EXTENSION 0x1c 122 #define RX8130_REG_EXTENSION_WADA BIT(3) 123 #define RX8130_REG_FLAG 0x1d 124 #define RX8130_REG_FLAG_VLF BIT(1) 125 #define RX8130_REG_FLAG_AF BIT(3) 126 #define RX8130_REG_CONTROL0 0x1e 127 #define RX8130_REG_CONTROL0_AIE BIT(3) 128 #define RX8130_REG_CONTROL1 0x1f 129 #define RX8130_REG_CONTROL1_INIEN BIT(4) 130 #define RX8130_REG_CONTROL1_CHGEN BIT(5) 131 132 #define MCP794XX_REG_CONTROL 0x07 133 # define MCP794XX_BIT_ALM0_EN 0x10 134 # define MCP794XX_BIT_ALM1_EN 0x20 135 #define MCP794XX_REG_ALARM0_BASE 0x0a 136 #define MCP794XX_REG_ALARM0_CTRL 0x0d 137 #define MCP794XX_REG_ALARM1_BASE 0x11 138 #define MCP794XX_REG_ALARM1_CTRL 0x14 139 # define MCP794XX_BIT_ALMX_IF BIT(3) 140 # define MCP794XX_BIT_ALMX_C0 BIT(4) 141 # define MCP794XX_BIT_ALMX_C1 BIT(5) 142 # define MCP794XX_BIT_ALMX_C2 BIT(6) 143 # define MCP794XX_BIT_ALMX_POL BIT(7) 144 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 145 MCP794XX_BIT_ALMX_C1 | \ 146 MCP794XX_BIT_ALMX_C2) 147 148 #define M41TXX_REG_CONTROL 0x07 149 # define M41TXX_BIT_OUT BIT(7) 150 # define M41TXX_BIT_FT BIT(6) 151 # define M41TXX_BIT_CALIB_SIGN BIT(5) 152 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 153 154 #define DS1388_REG_WDOG_HUN_SECS 0x08 155 #define DS1388_REG_WDOG_SECS 0x09 156 #define DS1388_REG_FLAG 0x0b 157 # define DS1388_BIT_WF BIT(6) 158 # define DS1388_BIT_OSF BIT(7) 159 #define DS1388_REG_CONTROL 0x0c 160 # define DS1388_BIT_RST BIT(0) 161 # define DS1388_BIT_WDE BIT(1) 162 # define DS1388_BIT_nEOSC BIT(7) 163 164 /* negative offset step is -2.034ppm */ 165 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 166 /* positive offset step is +4.068ppm */ 167 #define M41TXX_POS_OFFSET_STEP_PPB 4068 168 /* Min and max values supported with 'offset' interface by M41TXX */ 169 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 170 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 171 172 struct ds1307 { 173 enum ds_type type; 174 struct device *dev; 175 struct regmap *regmap; 176 const char *name; 177 struct rtc_device *rtc; 178 #ifdef CONFIG_COMMON_CLK 179 struct clk_hw clks[2]; 180 #endif 181 }; 182 183 struct chip_desc { 184 unsigned alarm:1; 185 u16 nvram_offset; 186 u16 nvram_size; 187 u8 offset; /* register's offset */ 188 u8 century_reg; 189 u8 century_enable_bit; 190 u8 century_bit; 191 u8 bbsqi_bit; 192 irq_handler_t irq_handler; 193 const struct rtc_class_ops *rtc_ops; 194 u16 trickle_charger_reg; 195 u8 (*do_trickle_setup)(struct ds1307 *, u32, 196 bool); 197 /* Does the RTC require trickle-resistor-ohms to select the value of 198 * the resistor between Vcc and Vbackup? 199 */ 200 bool requires_trickle_resistor; 201 /* Some RTC's batteries and supercaps were charged by default, others 202 * allow charging but were not configured previously to do so. 203 * Remember this behavior to stay backwards compatible. 204 */ 205 bool charge_default; 206 }; 207 208 static const struct chip_desc chips[last_ds_type]; 209 210 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 211 { 212 struct ds1307 *ds1307 = dev_get_drvdata(dev); 213 int tmp, ret; 214 const struct chip_desc *chip = &chips[ds1307->type]; 215 u8 regs[7]; 216 217 if (ds1307->type == rx_8130) { 218 unsigned int regflag; 219 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 220 if (ret) { 221 dev_err(dev, "%s error %d\n", "read", ret); 222 return ret; 223 } 224 225 if (regflag & RX8130_REG_FLAG_VLF) { 226 dev_warn_once(dev, "oscillator failed, set time!\n"); 227 return -EINVAL; 228 } 229 } 230 231 /* read the RTC date and time registers all at once */ 232 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 233 sizeof(regs)); 234 if (ret) { 235 dev_err(dev, "%s error %d\n", "read", ret); 236 return ret; 237 } 238 239 dev_dbg(dev, "%s: %7ph\n", "read", regs); 240 241 /* if oscillator fail bit is set, no data can be trusted */ 242 if (ds1307->type == m41t0 && 243 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 244 dev_warn_once(dev, "oscillator failed, set time!\n"); 245 return -EINVAL; 246 } else if (ds1307->type == mcp794xx && 247 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) { 248 dev_warn_once(dev, "oscillator failed, set time!\n"); 249 return -EINVAL; 250 } 251 252 tmp = regs[DS1307_REG_SECS]; 253 switch (ds1307->type) { 254 case ds_1307: 255 case m41t0: 256 case m41t00: 257 case m41t11: 258 if (tmp & DS1307_BIT_CH) 259 return -EINVAL; 260 break; 261 case ds_1308: 262 case ds_1338: 263 if (tmp & DS1307_BIT_CH) 264 return -EINVAL; 265 266 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp); 267 if (ret) 268 return ret; 269 if (tmp & DS1338_BIT_OSF) 270 return -EINVAL; 271 break; 272 case ds_1337: 273 case ds_1339: 274 case ds_1341: 275 case ds_3231: 276 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &tmp); 277 if (ret) 278 return ret; 279 if (tmp & DS1337_BIT_OSF) 280 return -EINVAL; 281 break; 282 case ds_1340: 283 if (tmp & DS1340_BIT_nEOSC) 284 return -EINVAL; 285 286 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 287 if (ret) 288 return ret; 289 if (tmp & DS1340_BIT_OSF) 290 return -EINVAL; 291 break; 292 case ds_1388: 293 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp); 294 if (ret) 295 return ret; 296 if (tmp & DS1388_BIT_OSF) 297 return -EINVAL; 298 break; 299 case mcp794xx: 300 if (!(tmp & MCP794XX_BIT_ST)) 301 return -EINVAL; 302 303 break; 304 default: 305 break; 306 } 307 308 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 309 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 310 tmp = regs[DS1307_REG_HOUR] & 0x3f; 311 t->tm_hour = bcd2bin(tmp); 312 /* rx8130 is bit position, not BCD */ 313 if (ds1307->type == rx_8130) 314 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f) - 1; 315 else 316 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 317 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 318 tmp = regs[DS1307_REG_MONTH] & 0x1f; 319 t->tm_mon = bcd2bin(tmp) - 1; 320 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 321 322 if (regs[chip->century_reg] & chip->century_bit && 323 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 324 t->tm_year += 100; 325 326 dev_dbg(dev, "%s secs=%d, mins=%d, " 327 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 328 "read", t->tm_sec, t->tm_min, 329 t->tm_hour, t->tm_mday, 330 t->tm_mon, t->tm_year, t->tm_wday); 331 332 return 0; 333 } 334 335 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 336 { 337 struct ds1307 *ds1307 = dev_get_drvdata(dev); 338 const struct chip_desc *chip = &chips[ds1307->type]; 339 int result; 340 int tmp; 341 u8 regs[7]; 342 343 dev_dbg(dev, "%s secs=%d, mins=%d, " 344 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 345 "write", t->tm_sec, t->tm_min, 346 t->tm_hour, t->tm_mday, 347 t->tm_mon, t->tm_year, t->tm_wday); 348 349 if (t->tm_year < 100) 350 return -EINVAL; 351 352 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 353 if (t->tm_year > (chip->century_bit ? 299 : 199)) 354 return -EINVAL; 355 #else 356 if (t->tm_year > 199) 357 return -EINVAL; 358 #endif 359 360 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 361 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 362 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 363 /* rx8130 is bit position, not BCD */ 364 if (ds1307->type == rx_8130) 365 regs[DS1307_REG_WDAY] = 1 << t->tm_wday; 366 else 367 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 368 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 369 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 370 371 /* assume 20YY not 19YY */ 372 tmp = t->tm_year % 100; 373 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 374 375 if (chip->century_enable_bit) 376 regs[chip->century_reg] |= chip->century_enable_bit; 377 if (t->tm_year > 199 && chip->century_bit) 378 regs[chip->century_reg] |= chip->century_bit; 379 380 switch (ds1307->type) { 381 case ds_1308: 382 case ds_1338: 383 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 384 DS1338_BIT_OSF, 0); 385 break; 386 case ds_1337: 387 case ds_1339: 388 case ds_1341: 389 case ds_3231: 390 regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 391 DS1337_BIT_OSF, 0); 392 break; 393 case ds_1340: 394 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG, 395 DS1340_BIT_OSF, 0); 396 break; 397 case ds_1388: 398 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 399 DS1388_BIT_OSF, 0); 400 break; 401 case mcp794xx: 402 /* 403 * these bits were cleared when preparing the date/time 404 * values and need to be set again before writing the 405 * regsfer out to the device. 406 */ 407 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 408 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 409 break; 410 default: 411 break; 412 } 413 414 dev_dbg(dev, "%s: %7ph\n", "write", regs); 415 416 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 417 sizeof(regs)); 418 if (result) { 419 dev_err(dev, "%s error %d\n", "write", result); 420 return result; 421 } 422 423 if (ds1307->type == rx_8130) { 424 /* clear Voltage Loss Flag as data is available now */ 425 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 426 ~(u8)RX8130_REG_FLAG_VLF); 427 if (result) { 428 dev_err(dev, "%s error %d\n", "write", result); 429 return result; 430 } 431 } 432 433 return 0; 434 } 435 436 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 437 { 438 struct ds1307 *ds1307 = dev_get_drvdata(dev); 439 int ret; 440 u8 regs[9]; 441 442 /* read all ALARM1, ALARM2, and status registers at once */ 443 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 444 regs, sizeof(regs)); 445 if (ret) { 446 dev_err(dev, "%s error %d\n", "alarm read", ret); 447 return ret; 448 } 449 450 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 451 ®s[0], ®s[4], ®s[7]); 452 453 /* 454 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 455 * and that all four fields are checked matches 456 */ 457 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 458 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 459 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 460 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 461 462 /* ... and status */ 463 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 464 t->pending = !!(regs[8] & DS1337_BIT_A1I); 465 466 dev_dbg(dev, "%s secs=%d, mins=%d, " 467 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 468 "alarm read", t->time.tm_sec, t->time.tm_min, 469 t->time.tm_hour, t->time.tm_mday, 470 t->enabled, t->pending); 471 472 return 0; 473 } 474 475 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 476 { 477 struct ds1307 *ds1307 = dev_get_drvdata(dev); 478 unsigned char regs[9]; 479 u8 control, status; 480 int ret; 481 482 dev_dbg(dev, "%s secs=%d, mins=%d, " 483 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 484 "alarm set", t->time.tm_sec, t->time.tm_min, 485 t->time.tm_hour, t->time.tm_mday, 486 t->enabled, t->pending); 487 488 /* read current status of both alarms and the chip */ 489 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 490 sizeof(regs)); 491 if (ret) { 492 dev_err(dev, "%s error %d\n", "alarm write", ret); 493 return ret; 494 } 495 control = regs[7]; 496 status = regs[8]; 497 498 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 499 ®s[0], ®s[4], control, status); 500 501 /* set ALARM1, using 24 hour and day-of-month modes */ 502 regs[0] = bin2bcd(t->time.tm_sec); 503 regs[1] = bin2bcd(t->time.tm_min); 504 regs[2] = bin2bcd(t->time.tm_hour); 505 regs[3] = bin2bcd(t->time.tm_mday); 506 507 /* set ALARM2 to non-garbage */ 508 regs[4] = 0; 509 regs[5] = 0; 510 regs[6] = 0; 511 512 /* disable alarms */ 513 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 514 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 515 516 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 517 sizeof(regs)); 518 if (ret) { 519 dev_err(dev, "can't set alarm time\n"); 520 return ret; 521 } 522 523 /* optionally enable ALARM1 */ 524 if (t->enabled) { 525 dev_dbg(dev, "alarm IRQ armed\n"); 526 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 527 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 528 } 529 530 return 0; 531 } 532 533 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 534 { 535 struct ds1307 *ds1307 = dev_get_drvdata(dev); 536 537 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 538 DS1337_BIT_A1IE, 539 enabled ? DS1337_BIT_A1IE : 0); 540 } 541 542 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 543 { 544 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 545 DS1307_TRICKLE_CHARGER_NO_DIODE; 546 547 setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 548 549 switch (ohms) { 550 case 250: 551 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 552 break; 553 case 2000: 554 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 555 break; 556 case 4000: 557 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 558 break; 559 default: 560 dev_warn(ds1307->dev, 561 "Unsupported ohm value %u in dt\n", ohms); 562 return 0; 563 } 564 return setup; 565 } 566 567 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode) 568 { 569 /* make sure that the backup battery is enabled */ 570 u8 setup = RX8130_REG_CONTROL1_INIEN; 571 if (diode) 572 setup |= RX8130_REG_CONTROL1_CHGEN; 573 574 return setup; 575 } 576 577 static irqreturn_t rx8130_irq(int irq, void *dev_id) 578 { 579 struct ds1307 *ds1307 = dev_id; 580 u8 ctl[3]; 581 int ret; 582 583 rtc_lock(ds1307->rtc); 584 585 /* Read control registers. */ 586 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 587 sizeof(ctl)); 588 if (ret < 0) 589 goto out; 590 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 591 goto out; 592 ctl[1] &= ~RX8130_REG_FLAG_AF; 593 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 594 595 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 596 sizeof(ctl)); 597 if (ret < 0) 598 goto out; 599 600 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 601 602 out: 603 rtc_unlock(ds1307->rtc); 604 605 return IRQ_HANDLED; 606 } 607 608 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 609 { 610 struct ds1307 *ds1307 = dev_get_drvdata(dev); 611 u8 ald[3], ctl[3]; 612 int ret; 613 614 /* Read alarm registers. */ 615 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 616 sizeof(ald)); 617 if (ret < 0) 618 return ret; 619 620 /* Read control registers. */ 621 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 622 sizeof(ctl)); 623 if (ret < 0) 624 return ret; 625 626 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 627 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 628 629 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 630 t->time.tm_sec = -1; 631 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 632 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 633 t->time.tm_wday = -1; 634 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 635 t->time.tm_mon = -1; 636 t->time.tm_year = -1; 637 t->time.tm_yday = -1; 638 t->time.tm_isdst = -1; 639 640 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 641 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 642 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 643 644 return 0; 645 } 646 647 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 648 { 649 struct ds1307 *ds1307 = dev_get_drvdata(dev); 650 u8 ald[3], ctl[3]; 651 int ret; 652 653 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 654 "enabled=%d pending=%d\n", __func__, 655 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 656 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 657 t->enabled, t->pending); 658 659 /* Read control registers. */ 660 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 661 sizeof(ctl)); 662 if (ret < 0) 663 return ret; 664 665 ctl[0] &= RX8130_REG_EXTENSION_WADA; 666 ctl[1] &= ~RX8130_REG_FLAG_AF; 667 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 668 669 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 670 sizeof(ctl)); 671 if (ret < 0) 672 return ret; 673 674 /* Hardware alarm precision is 1 minute! */ 675 ald[0] = bin2bcd(t->time.tm_min); 676 ald[1] = bin2bcd(t->time.tm_hour); 677 ald[2] = bin2bcd(t->time.tm_mday); 678 679 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 680 sizeof(ald)); 681 if (ret < 0) 682 return ret; 683 684 if (!t->enabled) 685 return 0; 686 687 ctl[2] |= RX8130_REG_CONTROL0_AIE; 688 689 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 690 } 691 692 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 693 { 694 struct ds1307 *ds1307 = dev_get_drvdata(dev); 695 int ret, reg; 696 697 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 698 if (ret < 0) 699 return ret; 700 701 if (enabled) 702 reg |= RX8130_REG_CONTROL0_AIE; 703 else 704 reg &= ~RX8130_REG_CONTROL0_AIE; 705 706 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 707 } 708 709 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 710 { 711 struct ds1307 *ds1307 = dev_id; 712 struct mutex *lock = &ds1307->rtc->ops_lock; 713 int reg, ret; 714 715 mutex_lock(lock); 716 717 /* Check and clear alarm 0 interrupt flag. */ 718 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 719 if (ret) 720 goto out; 721 if (!(reg & MCP794XX_BIT_ALMX_IF)) 722 goto out; 723 reg &= ~MCP794XX_BIT_ALMX_IF; 724 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 725 if (ret) 726 goto out; 727 728 /* Disable alarm 0. */ 729 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 730 MCP794XX_BIT_ALM0_EN, 0); 731 if (ret) 732 goto out; 733 734 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 735 736 out: 737 mutex_unlock(lock); 738 739 return IRQ_HANDLED; 740 } 741 742 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 743 { 744 struct ds1307 *ds1307 = dev_get_drvdata(dev); 745 u8 regs[10]; 746 int ret; 747 748 /* Read control and alarm 0 registers. */ 749 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 750 sizeof(regs)); 751 if (ret) 752 return ret; 753 754 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 755 756 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 757 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 758 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 759 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 760 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 761 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 762 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 763 t->time.tm_year = -1; 764 t->time.tm_yday = -1; 765 t->time.tm_isdst = -1; 766 767 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 768 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 769 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 770 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 771 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 772 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 773 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 774 775 return 0; 776 } 777 778 /* 779 * We may have a random RTC weekday, therefore calculate alarm weekday based 780 * on current weekday we read from the RTC timekeeping regs 781 */ 782 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 783 { 784 struct rtc_time tm_now; 785 int days_now, days_alarm, ret; 786 787 ret = ds1307_get_time(dev, &tm_now); 788 if (ret) 789 return ret; 790 791 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 792 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 793 794 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 795 } 796 797 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 798 { 799 struct ds1307 *ds1307 = dev_get_drvdata(dev); 800 unsigned char regs[10]; 801 int wday, ret; 802 803 wday = mcp794xx_alm_weekday(dev, &t->time); 804 if (wday < 0) 805 return wday; 806 807 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 808 "enabled=%d pending=%d\n", __func__, 809 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 810 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 811 t->enabled, t->pending); 812 813 /* Read control and alarm 0 registers. */ 814 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 815 sizeof(regs)); 816 if (ret) 817 return ret; 818 819 /* Set alarm 0, using 24-hour and day-of-month modes. */ 820 regs[3] = bin2bcd(t->time.tm_sec); 821 regs[4] = bin2bcd(t->time.tm_min); 822 regs[5] = bin2bcd(t->time.tm_hour); 823 regs[6] = wday; 824 regs[7] = bin2bcd(t->time.tm_mday); 825 regs[8] = bin2bcd(t->time.tm_mon + 1); 826 827 /* Clear the alarm 0 interrupt flag. */ 828 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 829 /* Set alarm match: second, minute, hour, day, date, month. */ 830 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 831 /* Disable interrupt. We will not enable until completely programmed */ 832 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 833 834 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 835 sizeof(regs)); 836 if (ret) 837 return ret; 838 839 if (!t->enabled) 840 return 0; 841 regs[0] |= MCP794XX_BIT_ALM0_EN; 842 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 843 } 844 845 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 846 { 847 struct ds1307 *ds1307 = dev_get_drvdata(dev); 848 849 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 850 MCP794XX_BIT_ALM0_EN, 851 enabled ? MCP794XX_BIT_ALM0_EN : 0); 852 } 853 854 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 855 { 856 struct ds1307 *ds1307 = dev_get_drvdata(dev); 857 unsigned int ctrl_reg; 858 u8 val; 859 860 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 861 862 val = ctrl_reg & M41TXX_M_CALIBRATION; 863 864 /* check if positive */ 865 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 866 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 867 else 868 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 869 870 return 0; 871 } 872 873 static int m41txx_rtc_set_offset(struct device *dev, long offset) 874 { 875 struct ds1307 *ds1307 = dev_get_drvdata(dev); 876 unsigned int ctrl_reg; 877 878 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 879 return -ERANGE; 880 881 if (offset >= 0) { 882 ctrl_reg = DIV_ROUND_CLOSEST(offset, 883 M41TXX_POS_OFFSET_STEP_PPB); 884 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 885 } else { 886 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 887 M41TXX_NEG_OFFSET_STEP_PPB); 888 } 889 890 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 891 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 892 ctrl_reg); 893 } 894 895 #ifdef CONFIG_WATCHDOG_CORE 896 static int ds1388_wdt_start(struct watchdog_device *wdt_dev) 897 { 898 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 899 u8 regs[2]; 900 int ret; 901 902 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 903 DS1388_BIT_WF, 0); 904 if (ret) 905 return ret; 906 907 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 908 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 909 if (ret) 910 return ret; 911 912 /* 913 * watchdog timeouts are measured in seconds. So ignore hundredths of 914 * seconds field. 915 */ 916 regs[0] = 0; 917 regs[1] = bin2bcd(wdt_dev->timeout); 918 919 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 920 sizeof(regs)); 921 if (ret) 922 return ret; 923 924 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 925 DS1388_BIT_WDE | DS1388_BIT_RST, 926 DS1388_BIT_WDE | DS1388_BIT_RST); 927 } 928 929 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) 930 { 931 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 932 933 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 934 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 935 } 936 937 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) 938 { 939 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 940 u8 regs[2]; 941 942 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 943 sizeof(regs)); 944 } 945 946 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, 947 unsigned int val) 948 { 949 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 950 u8 regs[2]; 951 952 wdt_dev->timeout = val; 953 regs[0] = 0; 954 regs[1] = bin2bcd(wdt_dev->timeout); 955 956 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 957 sizeof(regs)); 958 } 959 #endif 960 961 static const struct rtc_class_ops rx8130_rtc_ops = { 962 .read_time = ds1307_get_time, 963 .set_time = ds1307_set_time, 964 .read_alarm = rx8130_read_alarm, 965 .set_alarm = rx8130_set_alarm, 966 .alarm_irq_enable = rx8130_alarm_irq_enable, 967 }; 968 969 static const struct rtc_class_ops mcp794xx_rtc_ops = { 970 .read_time = ds1307_get_time, 971 .set_time = ds1307_set_time, 972 .read_alarm = mcp794xx_read_alarm, 973 .set_alarm = mcp794xx_set_alarm, 974 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 975 }; 976 977 static const struct rtc_class_ops m41txx_rtc_ops = { 978 .read_time = ds1307_get_time, 979 .set_time = ds1307_set_time, 980 .read_alarm = ds1337_read_alarm, 981 .set_alarm = ds1337_set_alarm, 982 .alarm_irq_enable = ds1307_alarm_irq_enable, 983 .read_offset = m41txx_rtc_read_offset, 984 .set_offset = m41txx_rtc_set_offset, 985 }; 986 987 static const struct chip_desc chips[last_ds_type] = { 988 [ds_1307] = { 989 .nvram_offset = 8, 990 .nvram_size = 56, 991 }, 992 [ds_1308] = { 993 .nvram_offset = 8, 994 .nvram_size = 56, 995 }, 996 [ds_1337] = { 997 .alarm = 1, 998 .century_reg = DS1307_REG_MONTH, 999 .century_bit = DS1337_BIT_CENTURY, 1000 }, 1001 [ds_1338] = { 1002 .nvram_offset = 8, 1003 .nvram_size = 56, 1004 }, 1005 [ds_1339] = { 1006 .alarm = 1, 1007 .century_reg = DS1307_REG_MONTH, 1008 .century_bit = DS1337_BIT_CENTURY, 1009 .bbsqi_bit = DS1339_BIT_BBSQI, 1010 .trickle_charger_reg = 0x10, 1011 .do_trickle_setup = &do_trickle_setup_ds1339, 1012 .requires_trickle_resistor = true, 1013 .charge_default = true, 1014 }, 1015 [ds_1340] = { 1016 .century_reg = DS1307_REG_HOUR, 1017 .century_enable_bit = DS1340_BIT_CENTURY_EN, 1018 .century_bit = DS1340_BIT_CENTURY, 1019 .do_trickle_setup = &do_trickle_setup_ds1339, 1020 .trickle_charger_reg = 0x08, 1021 .requires_trickle_resistor = true, 1022 .charge_default = true, 1023 }, 1024 [ds_1341] = { 1025 .century_reg = DS1307_REG_MONTH, 1026 .century_bit = DS1337_BIT_CENTURY, 1027 }, 1028 [ds_1388] = { 1029 .offset = 1, 1030 .trickle_charger_reg = 0x0a, 1031 }, 1032 [ds_3231] = { 1033 .alarm = 1, 1034 .century_reg = DS1307_REG_MONTH, 1035 .century_bit = DS1337_BIT_CENTURY, 1036 .bbsqi_bit = DS3231_BIT_BBSQW, 1037 }, 1038 [rx_8130] = { 1039 .alarm = 1, 1040 /* this is battery backed SRAM */ 1041 .nvram_offset = 0x20, 1042 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 1043 .offset = 0x10, 1044 .irq_handler = rx8130_irq, 1045 .rtc_ops = &rx8130_rtc_ops, 1046 .trickle_charger_reg = RX8130_REG_CONTROL1, 1047 .do_trickle_setup = &do_trickle_setup_rx8130, 1048 }, 1049 [m41t0] = { 1050 .rtc_ops = &m41txx_rtc_ops, 1051 }, 1052 [m41t00] = { 1053 .rtc_ops = &m41txx_rtc_ops, 1054 }, 1055 [m41t11] = { 1056 /* this is battery backed SRAM */ 1057 .nvram_offset = 8, 1058 .nvram_size = 56, 1059 .rtc_ops = &m41txx_rtc_ops, 1060 }, 1061 [mcp794xx] = { 1062 .alarm = 1, 1063 /* this is battery backed SRAM */ 1064 .nvram_offset = 0x20, 1065 .nvram_size = 0x40, 1066 .irq_handler = mcp794xx_irq, 1067 .rtc_ops = &mcp794xx_rtc_ops, 1068 }, 1069 }; 1070 1071 static const struct i2c_device_id ds1307_id[] = { 1072 { .name = "ds1307", .driver_data = ds_1307 }, 1073 { .name = "ds1308", .driver_data = ds_1308 }, 1074 { .name = "ds1337", .driver_data = ds_1337 }, 1075 { .name = "ds1338", .driver_data = ds_1338 }, 1076 { .name = "ds1339", .driver_data = ds_1339 }, 1077 { .name = "ds1388", .driver_data = ds_1388 }, 1078 { .name = "ds1340", .driver_data = ds_1340 }, 1079 { .name = "ds1341", .driver_data = ds_1341 }, 1080 { .name = "ds3231", .driver_data = ds_3231 }, 1081 { .name = "m41t0", .driver_data = m41t0 }, 1082 { .name = "m41t00", .driver_data = m41t00 }, 1083 { .name = "m41t11", .driver_data = m41t11 }, 1084 { .name = "mcp7940x", .driver_data = mcp794xx }, 1085 { .name = "mcp7941x", .driver_data = mcp794xx }, 1086 { .name = "pt7c4338", .driver_data = ds_1307 }, 1087 { .name = "rx8025", .driver_data = rx_8025 }, 1088 { .name = "isl12057", .driver_data = ds_1337 }, 1089 { .name = "rx8130", .driver_data = rx_8130 }, 1090 { } 1091 }; 1092 MODULE_DEVICE_TABLE(i2c, ds1307_id); 1093 1094 static const struct of_device_id ds1307_of_match[] = { 1095 { 1096 .compatible = "dallas,ds1307", 1097 .data = (void *)ds_1307 1098 }, 1099 { 1100 .compatible = "dallas,ds1308", 1101 .data = (void *)ds_1308 1102 }, 1103 { 1104 .compatible = "dallas,ds1337", 1105 .data = (void *)ds_1337 1106 }, 1107 { 1108 .compatible = "dallas,ds1338", 1109 .data = (void *)ds_1338 1110 }, 1111 { 1112 .compatible = "dallas,ds1339", 1113 .data = (void *)ds_1339 1114 }, 1115 { 1116 .compatible = "dallas,ds1388", 1117 .data = (void *)ds_1388 1118 }, 1119 { 1120 .compatible = "dallas,ds1340", 1121 .data = (void *)ds_1340 1122 }, 1123 { 1124 .compatible = "dallas,ds1341", 1125 .data = (void *)ds_1341 1126 }, 1127 { 1128 .compatible = "maxim,ds3231", 1129 .data = (void *)ds_3231 1130 }, 1131 { 1132 .compatible = "st,m41t0", 1133 .data = (void *)m41t0 1134 }, 1135 { 1136 .compatible = "st,m41t00", 1137 .data = (void *)m41t00 1138 }, 1139 { 1140 .compatible = "st,m41t11", 1141 .data = (void *)m41t11 1142 }, 1143 { 1144 .compatible = "microchip,mcp7940x", 1145 .data = (void *)mcp794xx 1146 }, 1147 { 1148 .compatible = "microchip,mcp7941x", 1149 .data = (void *)mcp794xx 1150 }, 1151 { 1152 .compatible = "pericom,pt7c4338", 1153 .data = (void *)ds_1307 1154 }, 1155 { 1156 .compatible = "epson,rx8025", 1157 .data = (void *)rx_8025 1158 }, 1159 { 1160 .compatible = "isil,isl12057", 1161 .data = (void *)ds_1337 1162 }, 1163 { 1164 .compatible = "epson,rx8130", 1165 .data = (void *)rx_8130 1166 }, 1167 { } 1168 }; 1169 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1170 1171 /* 1172 * The ds1337 and ds1339 both have two alarms, but we only use the first 1173 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1174 * signal; ds1339 chips have only one alarm signal. 1175 */ 1176 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1177 { 1178 struct ds1307 *ds1307 = dev_id; 1179 struct mutex *lock = &ds1307->rtc->ops_lock; 1180 int stat, ret; 1181 1182 mutex_lock(lock); 1183 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1184 if (ret) 1185 goto out; 1186 1187 if (stat & DS1337_BIT_A1I) { 1188 stat &= ~DS1337_BIT_A1I; 1189 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1190 1191 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1192 DS1337_BIT_A1IE, 0); 1193 if (ret) 1194 goto out; 1195 1196 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1197 } 1198 1199 out: 1200 mutex_unlock(lock); 1201 1202 return IRQ_HANDLED; 1203 } 1204 1205 /*----------------------------------------------------------------------*/ 1206 1207 static const struct rtc_class_ops ds13xx_rtc_ops = { 1208 .read_time = ds1307_get_time, 1209 .set_time = ds1307_set_time, 1210 .read_alarm = ds1337_read_alarm, 1211 .set_alarm = ds1337_set_alarm, 1212 .alarm_irq_enable = ds1307_alarm_irq_enable, 1213 }; 1214 1215 static ssize_t frequency_test_store(struct device *dev, 1216 struct device_attribute *attr, 1217 const char *buf, size_t count) 1218 { 1219 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1220 bool freq_test_en; 1221 int ret; 1222 1223 ret = kstrtobool(buf, &freq_test_en); 1224 if (ret) { 1225 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1226 return ret; 1227 } 1228 1229 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1230 freq_test_en ? M41TXX_BIT_FT : 0); 1231 1232 return count; 1233 } 1234 1235 static ssize_t frequency_test_show(struct device *dev, 1236 struct device_attribute *attr, 1237 char *buf) 1238 { 1239 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1240 unsigned int ctrl_reg; 1241 1242 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1243 1244 return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n"); 1245 } 1246 1247 static DEVICE_ATTR_RW(frequency_test); 1248 1249 static struct attribute *rtc_freq_test_attrs[] = { 1250 &dev_attr_frequency_test.attr, 1251 NULL, 1252 }; 1253 1254 static const struct attribute_group rtc_freq_test_attr_group = { 1255 .attrs = rtc_freq_test_attrs, 1256 }; 1257 1258 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1259 { 1260 int err; 1261 1262 switch (ds1307->type) { 1263 case m41t0: 1264 case m41t00: 1265 case m41t11: 1266 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1267 if (err) 1268 return err; 1269 break; 1270 default: 1271 break; 1272 } 1273 1274 return 0; 1275 } 1276 1277 /*----------------------------------------------------------------------*/ 1278 1279 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1280 size_t bytes) 1281 { 1282 struct ds1307 *ds1307 = priv; 1283 const struct chip_desc *chip = &chips[ds1307->type]; 1284 1285 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1286 val, bytes); 1287 } 1288 1289 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1290 size_t bytes) 1291 { 1292 struct ds1307 *ds1307 = priv; 1293 const struct chip_desc *chip = &chips[ds1307->type]; 1294 1295 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1296 val, bytes); 1297 } 1298 1299 /*----------------------------------------------------------------------*/ 1300 1301 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1302 const struct chip_desc *chip) 1303 { 1304 u32 ohms, chargeable; 1305 bool diode = chip->charge_default; 1306 1307 if (!chip->do_trickle_setup) 1308 return 0; 1309 1310 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1311 &ohms) && chip->requires_trickle_resistor) 1312 return 0; 1313 1314 /* aux-voltage-chargeable takes precedence over the deprecated 1315 * trickle-diode-disable 1316 */ 1317 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable", 1318 &chargeable)) { 1319 switch (chargeable) { 1320 case 0: 1321 diode = false; 1322 break; 1323 case 1: 1324 diode = true; 1325 break; 1326 default: 1327 dev_warn(ds1307->dev, 1328 "unsupported aux-voltage-chargeable value\n"); 1329 break; 1330 } 1331 } else if (device_property_read_bool(ds1307->dev, 1332 "trickle-diode-disable")) { 1333 diode = false; 1334 } 1335 1336 return chip->do_trickle_setup(ds1307, ohms, diode); 1337 } 1338 1339 /*----------------------------------------------------------------------*/ 1340 1341 #if IS_REACHABLE(CONFIG_HWMON) 1342 1343 /* 1344 * Temperature sensor support for ds3231 devices. 1345 */ 1346 1347 #define DS3231_REG_TEMPERATURE 0x11 1348 1349 /* 1350 * A user-initiated temperature conversion is not started by this function, 1351 * so the temperature is updated once every 64 seconds. 1352 */ 1353 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1354 { 1355 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1356 u8 temp_buf[2]; 1357 s16 temp; 1358 int ret; 1359 1360 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1361 temp_buf, sizeof(temp_buf)); 1362 if (ret) 1363 return ret; 1364 /* 1365 * Temperature is represented as a 10-bit code with a resolution of 1366 * 0.25 degree celsius and encoded in two's complement format. 1367 */ 1368 temp = (temp_buf[0] << 8) | temp_buf[1]; 1369 temp >>= 6; 1370 *mC = temp * 250; 1371 1372 return 0; 1373 } 1374 1375 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1376 struct device_attribute *attr, char *buf) 1377 { 1378 int ret; 1379 s32 temp; 1380 1381 ret = ds3231_hwmon_read_temp(dev, &temp); 1382 if (ret) 1383 return ret; 1384 1385 return sprintf(buf, "%d\n", temp); 1386 } 1387 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1388 NULL, 0); 1389 1390 static struct attribute *ds3231_hwmon_attrs[] = { 1391 &sensor_dev_attr_temp1_input.dev_attr.attr, 1392 NULL, 1393 }; 1394 ATTRIBUTE_GROUPS(ds3231_hwmon); 1395 1396 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1397 { 1398 struct device *dev; 1399 1400 if (ds1307->type != ds_3231) 1401 return; 1402 1403 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1404 ds1307, 1405 ds3231_hwmon_groups); 1406 if (IS_ERR(dev)) { 1407 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1408 PTR_ERR(dev)); 1409 } 1410 } 1411 1412 #else 1413 1414 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1415 { 1416 } 1417 1418 #endif /* IS_REACHABLE(CONFIG_HWMON) */ 1419 1420 /*----------------------------------------------------------------------*/ 1421 1422 /* 1423 * Square-wave output support for DS3231 1424 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1425 */ 1426 #ifdef CONFIG_COMMON_CLK 1427 1428 enum { 1429 DS3231_CLK_SQW = 0, 1430 DS3231_CLK_32KHZ, 1431 }; 1432 1433 #define clk_sqw_to_ds1307(clk) \ 1434 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1435 #define clk_32khz_to_ds1307(clk) \ 1436 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1437 1438 static int ds3231_clk_sqw_rates[] = { 1439 1, 1440 1024, 1441 4096, 1442 8192, 1443 }; 1444 1445 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1446 { 1447 struct mutex *lock = &ds1307->rtc->ops_lock; 1448 int ret; 1449 1450 mutex_lock(lock); 1451 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1452 mask, value); 1453 mutex_unlock(lock); 1454 1455 return ret; 1456 } 1457 1458 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1459 unsigned long parent_rate) 1460 { 1461 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1462 int control, ret; 1463 int rate_sel = 0; 1464 1465 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1466 if (ret) 1467 return ret; 1468 if (control & DS1337_BIT_RS1) 1469 rate_sel += 1; 1470 if (control & DS1337_BIT_RS2) 1471 rate_sel += 2; 1472 1473 return ds3231_clk_sqw_rates[rate_sel]; 1474 } 1475 1476 static int ds3231_clk_sqw_determine_rate(struct clk_hw *hw, 1477 struct clk_rate_request *req) 1478 { 1479 int i; 1480 1481 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1482 if (ds3231_clk_sqw_rates[i] <= req->rate) { 1483 req->rate = ds3231_clk_sqw_rates[i]; 1484 1485 return 0; 1486 } 1487 } 1488 1489 req->rate = ds3231_clk_sqw_rates[ARRAY_SIZE(ds3231_clk_sqw_rates) - 1]; 1490 1491 return 0; 1492 } 1493 1494 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1495 unsigned long parent_rate) 1496 { 1497 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1498 int control = 0; 1499 int rate_sel; 1500 1501 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1502 rate_sel++) { 1503 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1504 break; 1505 } 1506 1507 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1508 return -EINVAL; 1509 1510 if (rate_sel & 1) 1511 control |= DS1337_BIT_RS1; 1512 if (rate_sel & 2) 1513 control |= DS1337_BIT_RS2; 1514 1515 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1516 control); 1517 } 1518 1519 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1520 { 1521 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1522 1523 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1524 } 1525 1526 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1527 { 1528 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1529 1530 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1531 } 1532 1533 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1534 { 1535 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1536 int control, ret; 1537 1538 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1539 if (ret) 1540 return ret; 1541 1542 return !(control & DS1337_BIT_INTCN); 1543 } 1544 1545 static const struct clk_ops ds3231_clk_sqw_ops = { 1546 .prepare = ds3231_clk_sqw_prepare, 1547 .unprepare = ds3231_clk_sqw_unprepare, 1548 .is_prepared = ds3231_clk_sqw_is_prepared, 1549 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1550 .determine_rate = ds3231_clk_sqw_determine_rate, 1551 .set_rate = ds3231_clk_sqw_set_rate, 1552 }; 1553 1554 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1555 unsigned long parent_rate) 1556 { 1557 return 32768; 1558 } 1559 1560 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1561 { 1562 struct mutex *lock = &ds1307->rtc->ops_lock; 1563 int ret; 1564 1565 mutex_lock(lock); 1566 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1567 DS3231_BIT_EN32KHZ, 1568 enable ? DS3231_BIT_EN32KHZ : 0); 1569 mutex_unlock(lock); 1570 1571 return ret; 1572 } 1573 1574 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1575 { 1576 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1577 1578 return ds3231_clk_32khz_control(ds1307, true); 1579 } 1580 1581 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1582 { 1583 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1584 1585 ds3231_clk_32khz_control(ds1307, false); 1586 } 1587 1588 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1589 { 1590 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1591 int status, ret; 1592 1593 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1594 if (ret) 1595 return ret; 1596 1597 return !!(status & DS3231_BIT_EN32KHZ); 1598 } 1599 1600 static const struct clk_ops ds3231_clk_32khz_ops = { 1601 .prepare = ds3231_clk_32khz_prepare, 1602 .unprepare = ds3231_clk_32khz_unprepare, 1603 .is_prepared = ds3231_clk_32khz_is_prepared, 1604 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1605 }; 1606 1607 static const char *ds3231_clks_names[] = { 1608 [DS3231_CLK_SQW] = "ds3231_clk_sqw", 1609 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz", 1610 }; 1611 1612 static struct clk_init_data ds3231_clks_init[] = { 1613 [DS3231_CLK_SQW] = { 1614 .ops = &ds3231_clk_sqw_ops, 1615 }, 1616 [DS3231_CLK_32KHZ] = { 1617 .ops = &ds3231_clk_32khz_ops, 1618 }, 1619 }; 1620 1621 static int ds3231_clks_register(struct ds1307 *ds1307) 1622 { 1623 struct device_node *node = ds1307->dev->of_node; 1624 struct clk_onecell_data *onecell; 1625 int i; 1626 1627 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1628 if (!onecell) 1629 return -ENOMEM; 1630 1631 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1632 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1633 sizeof(onecell->clks[0]), GFP_KERNEL); 1634 if (!onecell->clks) 1635 return -ENOMEM; 1636 1637 /* optional override of the clockname */ 1638 device_property_read_string_array(ds1307->dev, "clock-output-names", 1639 ds3231_clks_names, 1640 ARRAY_SIZE(ds3231_clks_names)); 1641 1642 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1643 struct clk_init_data init = ds3231_clks_init[i]; 1644 1645 /* 1646 * Interrupt signal due to alarm conditions and square-wave 1647 * output share same pin, so don't initialize both. 1648 */ 1649 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features)) 1650 continue; 1651 1652 init.name = ds3231_clks_names[i]; 1653 ds1307->clks[i].init = &init; 1654 1655 onecell->clks[i] = devm_clk_register(ds1307->dev, 1656 &ds1307->clks[i]); 1657 if (IS_ERR(onecell->clks[i])) 1658 return PTR_ERR(onecell->clks[i]); 1659 } 1660 1661 if (node) 1662 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1663 1664 return 0; 1665 } 1666 1667 /* ds1307 RTC clock output support */ 1668 static unsigned long ds1307_clk_rates[] = { 1669 1, 1670 4096, 1671 8192, 1672 32768, 1673 }; 1674 1675 static unsigned long ds1307_clk_sqw_recalc_rate(struct clk_hw *hw, 1676 unsigned long parent_rate) 1677 { 1678 int ret; 1679 unsigned int rate_id; 1680 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1681 1682 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &rate_id); 1683 if (ret) 1684 return ret; 1685 1686 rate_id &= (DS1307_BIT_RS1 | DS1307_BIT_RS0); 1687 1688 return ds1307_clk_rates[rate_id]; 1689 } 1690 1691 static int ds1307_clk_sqw_determine_rate(struct clk_hw *hw, 1692 struct clk_rate_request *req) 1693 { 1694 int i; 1695 1696 for (i = 0; i < ARRAY_SIZE(ds1307_clk_rates); i++) { 1697 if (req->rate <= ds1307_clk_rates[i]) { 1698 req->rate = ds1307_clk_rates[i]; 1699 return 0; 1700 } 1701 } 1702 1703 /* Default rate 1Hz */ 1704 req->rate = ds1307_clk_rates[0]; 1705 1706 return 0; 1707 } 1708 1709 static int ds1307_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1710 unsigned long parent_rate) 1711 { 1712 int id, ret; 1713 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1714 1715 for (id = 0; id < ARRAY_SIZE(ds1307_clk_rates); id++) { 1716 if (ds1307_clk_rates[id] == rate) 1717 break; 1718 } 1719 1720 if (id >= ARRAY_SIZE(ds1307_clk_rates)) 1721 return -EINVAL; 1722 1723 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1724 DS1307_BIT_RS0 | DS1307_BIT_RS1, id); 1725 1726 return ret; 1727 } 1728 1729 static int ds1307_clk_sqw_prepare(struct clk_hw *hw) 1730 { 1731 int ret; 1732 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1733 1734 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1735 DS1307_BIT_SQWE, DS1307_BIT_SQWE); 1736 1737 return ret; 1738 } 1739 1740 static void ds1307_clk_sqw_unprepare(struct clk_hw *hw) 1741 { 1742 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1743 1744 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1745 DS1307_BIT_SQWE, ~DS1307_BIT_SQWE); 1746 } 1747 1748 static int ds1307_clk_sqw_is_prepared(struct clk_hw *hw) 1749 { 1750 int ret; 1751 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1752 unsigned int status; 1753 1754 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &status); 1755 if (ret) 1756 return ret; 1757 1758 return !!(status & DS1307_BIT_SQWE); 1759 } 1760 1761 static const struct clk_ops ds1307_clk_sqw_ops = { 1762 .prepare = ds1307_clk_sqw_prepare, 1763 .unprepare = ds1307_clk_sqw_unprepare, 1764 .is_prepared = ds1307_clk_sqw_is_prepared, 1765 .recalc_rate = ds1307_clk_sqw_recalc_rate, 1766 .set_rate = ds1307_clk_sqw_set_rate, 1767 .determine_rate = ds1307_clk_sqw_determine_rate, 1768 }; 1769 1770 static int rtc_ds1307_clks_register(struct ds1307 *ds1307) 1771 { 1772 struct device_node *node = ds1307->dev->of_node; 1773 struct clk *clk; 1774 struct clk_init_data init = {0}; 1775 1776 init.name = "ds1307_clk_sqw"; 1777 init.ops = &ds1307_clk_sqw_ops; 1778 1779 ds1307->clks[0].init = &init; 1780 1781 /* Register the clock with CCF */ 1782 clk = devm_clk_register(ds1307->dev, &ds1307->clks[0]); 1783 if (IS_ERR(clk)) 1784 return PTR_ERR(clk); 1785 1786 if (node) 1787 of_clk_add_provider(node, of_clk_src_simple_get, clk); 1788 1789 return 0; 1790 } 1791 1792 static void ds1307_clks_register(struct ds1307 *ds1307) 1793 { 1794 int ret; 1795 1796 switch (ds1307->type) { 1797 case ds_3231: 1798 ret = ds3231_clks_register(ds1307); 1799 break; 1800 1801 case ds_1307: 1802 ret = rtc_ds1307_clks_register(ds1307); 1803 break; 1804 1805 default: 1806 return; 1807 } 1808 1809 if (ret) { 1810 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1811 ret); 1812 } 1813 1814 } 1815 1816 #else 1817 1818 static void ds1307_clks_register(struct ds1307 *ds1307) 1819 { 1820 } 1821 1822 #endif /* CONFIG_COMMON_CLK */ 1823 1824 #ifdef CONFIG_WATCHDOG_CORE 1825 static const struct watchdog_info ds1388_wdt_info = { 1826 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 1827 .identity = "DS1388 watchdog", 1828 }; 1829 1830 static const struct watchdog_ops ds1388_wdt_ops = { 1831 .owner = THIS_MODULE, 1832 .start = ds1388_wdt_start, 1833 .stop = ds1388_wdt_stop, 1834 .ping = ds1388_wdt_ping, 1835 .set_timeout = ds1388_wdt_set_timeout, 1836 1837 }; 1838 1839 static void ds1307_wdt_register(struct ds1307 *ds1307) 1840 { 1841 struct watchdog_device *wdt; 1842 int err; 1843 int val; 1844 1845 if (ds1307->type != ds_1388) 1846 return; 1847 1848 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL); 1849 if (!wdt) 1850 return; 1851 1852 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val); 1853 if (!err && val & DS1388_BIT_WF) 1854 wdt->bootstatus = WDIOF_CARDRESET; 1855 1856 wdt->info = &ds1388_wdt_info; 1857 wdt->ops = &ds1388_wdt_ops; 1858 wdt->timeout = 99; 1859 wdt->max_timeout = 99; 1860 wdt->min_timeout = 1; 1861 1862 watchdog_init_timeout(wdt, 0, ds1307->dev); 1863 watchdog_set_drvdata(wdt, ds1307); 1864 devm_watchdog_register_device(ds1307->dev, wdt); 1865 } 1866 #else 1867 static void ds1307_wdt_register(struct ds1307 *ds1307) 1868 { 1869 } 1870 #endif /* CONFIG_WATCHDOG_CORE */ 1871 1872 static const struct regmap_config regmap_config = { 1873 .reg_bits = 8, 1874 .val_bits = 8, 1875 }; 1876 1877 static int ds1307_probe(struct i2c_client *client) 1878 { 1879 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1880 struct ds1307 *ds1307; 1881 const void *match; 1882 int err = -ENODEV; 1883 int tmp; 1884 const struct chip_desc *chip; 1885 bool want_irq; 1886 bool ds1307_can_wakeup_device = false; 1887 unsigned char regs[8]; 1888 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1889 u8 trickle_charger_setup = 0; 1890 1891 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1892 if (!ds1307) 1893 return -ENOMEM; 1894 1895 dev_set_drvdata(&client->dev, ds1307); 1896 ds1307->dev = &client->dev; 1897 ds1307->name = client->name; 1898 1899 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1900 if (IS_ERR(ds1307->regmap)) { 1901 dev_err(ds1307->dev, "regmap allocation failed\n"); 1902 return PTR_ERR(ds1307->regmap); 1903 } 1904 1905 i2c_set_clientdata(client, ds1307); 1906 1907 match = device_get_match_data(&client->dev); 1908 if (match) { 1909 ds1307->type = (uintptr_t)match; 1910 chip = &chips[ds1307->type]; 1911 } else if (id) { 1912 chip = &chips[id->driver_data]; 1913 ds1307->type = id->driver_data; 1914 } else { 1915 return -ENODEV; 1916 } 1917 1918 want_irq = client->irq > 0 && chip->alarm; 1919 1920 if (!pdata) 1921 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1922 else if (pdata->trickle_charger_setup) 1923 trickle_charger_setup = pdata->trickle_charger_setup; 1924 1925 if (trickle_charger_setup && chip->trickle_charger_reg) { 1926 dev_dbg(ds1307->dev, 1927 "writing trickle charger info 0x%x to 0x%x\n", 1928 trickle_charger_setup, chip->trickle_charger_reg); 1929 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1930 trickle_charger_setup); 1931 } 1932 1933 /* 1934 * For devices with no IRQ directly connected to the SoC, the RTC chip 1935 * can be forced as a wakeup source by stating that explicitly in 1936 * the device's .dts file using the "wakeup-source" boolean property. 1937 * If the "wakeup-source" property is set, don't request an IRQ. 1938 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1939 * if supported by the RTC. 1940 */ 1941 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source")) 1942 ds1307_can_wakeup_device = true; 1943 1944 switch (ds1307->type) { 1945 case ds_1337: 1946 case ds_1339: 1947 case ds_1341: 1948 case ds_3231: 1949 /* get registers that the "rtc" read below won't read... */ 1950 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1951 regs, 2); 1952 if (err) { 1953 dev_dbg(ds1307->dev, "read error %d\n", err); 1954 goto exit; 1955 } 1956 1957 /* oscillator off? turn it on, so clock can tick. */ 1958 if (regs[0] & DS1337_BIT_nEOSC) 1959 regs[0] &= ~DS1337_BIT_nEOSC; 1960 1961 /* 1962 * Using IRQ or defined as wakeup-source? 1963 * Disable the square wave and both alarms. 1964 * For some variants, be sure alarms can trigger when we're 1965 * running on Vbackup (BBSQI/BBSQW) 1966 */ 1967 if (want_irq || ds1307_can_wakeup_device) 1968 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1969 1970 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1971 regs[0]); 1972 1973 /* oscillator fault? warn */ 1974 if (regs[1] & DS1337_BIT_OSF) { 1975 dev_warn(ds1307->dev, "SET TIME!\n"); 1976 } 1977 break; 1978 1979 case rx_8025: 1980 err = regmap_bulk_read(ds1307->regmap, 1981 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1982 if (err) { 1983 dev_dbg(ds1307->dev, "read error %d\n", err); 1984 goto exit; 1985 } 1986 1987 /* oscillator off? turn it on, so clock can tick. */ 1988 if (!(regs[1] & RX8025_BIT_XST)) { 1989 regs[1] |= RX8025_BIT_XST; 1990 regmap_write(ds1307->regmap, 1991 RX8025_REG_CTRL2 << 4 | 0x08, 1992 regs[1]); 1993 dev_warn(ds1307->dev, 1994 "oscillator stop detected - SET TIME!\n"); 1995 } 1996 1997 if (regs[1] & RX8025_BIT_PON) { 1998 regs[1] &= ~RX8025_BIT_PON; 1999 regmap_write(ds1307->regmap, 2000 RX8025_REG_CTRL2 << 4 | 0x08, 2001 regs[1]); 2002 dev_warn(ds1307->dev, "power-on detected\n"); 2003 } 2004 2005 if (regs[1] & RX8025_BIT_VDET) { 2006 regs[1] &= ~RX8025_BIT_VDET; 2007 regmap_write(ds1307->regmap, 2008 RX8025_REG_CTRL2 << 4 | 0x08, 2009 regs[1]); 2010 dev_warn(ds1307->dev, "voltage drop detected\n"); 2011 } 2012 2013 /* make sure we are running in 24hour mode */ 2014 if (!(regs[0] & RX8025_BIT_2412)) { 2015 u8 hour; 2016 2017 /* switch to 24 hour mode */ 2018 regmap_write(ds1307->regmap, 2019 RX8025_REG_CTRL1 << 4 | 0x08, 2020 regs[0] | RX8025_BIT_2412); 2021 2022 err = regmap_bulk_read(ds1307->regmap, 2023 RX8025_REG_CTRL1 << 4 | 0x08, 2024 regs, 2); 2025 if (err) { 2026 dev_dbg(ds1307->dev, "read error %d\n", err); 2027 goto exit; 2028 } 2029 2030 /* correct hour */ 2031 hour = bcd2bin(regs[DS1307_REG_HOUR]); 2032 if (hour == 12) 2033 hour = 0; 2034 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 2035 hour += 12; 2036 2037 regmap_write(ds1307->regmap, 2038 DS1307_REG_HOUR << 4 | 0x08, hour); 2039 } 2040 break; 2041 case ds_1388: 2042 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp); 2043 if (err) { 2044 dev_dbg(ds1307->dev, "read error %d\n", err); 2045 goto exit; 2046 } 2047 2048 /* oscillator off? turn it on, so clock can tick. */ 2049 if (tmp & DS1388_BIT_nEOSC) { 2050 tmp &= ~DS1388_BIT_nEOSC; 2051 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp); 2052 } 2053 break; 2054 default: 2055 break; 2056 } 2057 2058 /* read RTC registers */ 2059 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 2060 sizeof(regs)); 2061 if (err) { 2062 dev_dbg(ds1307->dev, "read error %d\n", err); 2063 goto exit; 2064 } 2065 2066 if (ds1307->type == mcp794xx && 2067 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 2068 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 2069 regs[DS1307_REG_WDAY] | 2070 MCP794XX_BIT_VBATEN); 2071 } 2072 2073 tmp = regs[DS1307_REG_HOUR]; 2074 switch (ds1307->type) { 2075 case ds_1340: 2076 case m41t0: 2077 case m41t00: 2078 case m41t11: 2079 /* 2080 * NOTE: ignores century bits; fix before deploying 2081 * systems that will run through year 2100. 2082 */ 2083 break; 2084 case rx_8025: 2085 break; 2086 default: 2087 if (!(tmp & DS1307_BIT_12HR)) 2088 break; 2089 2090 /* 2091 * Be sure we're in 24 hour mode. Multi-master systems 2092 * take note... 2093 */ 2094 tmp = bcd2bin(tmp & 0x1f); 2095 if (tmp == 12) 2096 tmp = 0; 2097 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 2098 tmp += 12; 2099 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 2100 bin2bcd(tmp)); 2101 } 2102 2103 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 2104 if (IS_ERR(ds1307->rtc)) 2105 return PTR_ERR(ds1307->rtc); 2106 2107 if (want_irq || ds1307_can_wakeup_device) 2108 device_set_wakeup_capable(ds1307->dev, true); 2109 else 2110 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 2111 2112 if (ds1307_can_wakeup_device && !want_irq) { 2113 dev_info(ds1307->dev, 2114 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 2115 /* We cannot support UIE mode if we do not have an IRQ line */ 2116 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features); 2117 } 2118 2119 if (want_irq) { 2120 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 2121 chip->irq_handler ?: ds1307_irq, 2122 IRQF_SHARED | IRQF_ONESHOT, 2123 ds1307->name, ds1307); 2124 if (err) { 2125 client->irq = 0; 2126 device_set_wakeup_capable(ds1307->dev, false); 2127 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 2128 dev_err(ds1307->dev, "unable to request IRQ!\n"); 2129 } else { 2130 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 2131 } 2132 } 2133 2134 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 2135 err = ds1307_add_frequency_test(ds1307); 2136 if (err) 2137 return err; 2138 2139 err = devm_rtc_register_device(ds1307->rtc); 2140 if (err) 2141 return err; 2142 2143 if (chip->nvram_size) { 2144 struct nvmem_config nvmem_cfg = { 2145 .name = "ds1307_nvram", 2146 .word_size = 1, 2147 .stride = 1, 2148 .size = chip->nvram_size, 2149 .reg_read = ds1307_nvram_read, 2150 .reg_write = ds1307_nvram_write, 2151 .priv = ds1307, 2152 }; 2153 2154 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 2155 } 2156 2157 ds1307_hwmon_register(ds1307); 2158 ds1307_clks_register(ds1307); 2159 ds1307_wdt_register(ds1307); 2160 2161 return 0; 2162 2163 exit: 2164 return err; 2165 } 2166 2167 static struct i2c_driver ds1307_driver = { 2168 .driver = { 2169 .name = "rtc-ds1307", 2170 .of_match_table = ds1307_of_match, 2171 }, 2172 .probe = ds1307_probe, 2173 .id_table = ds1307_id, 2174 }; 2175 2176 module_i2c_driver(ds1307_driver); 2177 2178 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 2179 MODULE_LICENSE("GPL"); 2180