1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of.h>
25 #include <linux/of_platform.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/irqchip/chained_irq.h>
32 #include <linux/clk.h>
33 #include <linux/regmap.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/string_helpers.h>
36
37 #include <dt-bindings/pinctrl/rockchip.h>
38
39 #include "core.h"
40 #include "pinconf.h"
41 #include "pinctrl-rockchip.h"
42
43 /*
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
45 * register 31:16 area.
46 */
47 #define WRITE_MASK_VAL(h, l, v) \
48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
49
50 /*
51 * Encode variants of iomux registers into a type variable
52 */
53 #define IOMUX_GPIO_ONLY BIT(0)
54 #define IOMUX_WIDTH_4BIT BIT(1)
55 #define IOMUX_SOURCE_PMU BIT(2)
56 #define IOMUX_UNROUTED BIT(3)
57 #define IOMUX_WIDTH_3BIT BIT(4)
58 #define IOMUX_WIDTH_2BIT BIT(5)
59 #define IOMUX_L_SOURCE_PMU BIT(6)
60
61 #define PIN_BANK(id, pins, label) \
62 { \
63 .bank_num = id, \
64 .nr_pins = pins, \
65 .name = label, \
66 .iomux = { \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
71 }, \
72 }
73
74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
75 { \
76 .bank_num = id, \
77 .nr_pins = pins, \
78 .name = label, \
79 .iomux = { \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
84 }, \
85 }
86
87 #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88 iom1, iom2, iom3, \
89 offset0, offset1, \
90 offset2, offset3, pull0, \
91 pull1, pull2, pull3) \
92 { \
93 .bank_num = id, \
94 .nr_pins = pins, \
95 .name = label, \
96 .iomux = { \
97 { .type = iom0, .offset = offset0 }, \
98 { .type = iom1, .offset = offset1 }, \
99 { .type = iom2, .offset = offset2 }, \
100 { .type = iom3, .offset = offset3 }, \
101 }, \
102 .pull_type[0] = pull0, \
103 .pull_type[1] = pull1, \
104 .pull_type[2] = pull2, \
105 .pull_type[3] = pull3, \
106 }
107
108 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \
109 iom1, iom2, iom3, \
110 offset0, offset1, \
111 offset2, offset3, drv0, \
112 drv1, drv2, drv3) \
113 { \
114 .bank_num = id, \
115 .nr_pins = pins, \
116 .name = label, \
117 .iomux = { \
118 { .type = iom0, .offset = offset0 }, \
119 { .type = iom1, .offset = offset1 }, \
120 { .type = iom2, .offset = offset2 }, \
121 { .type = iom3, .offset = offset3 }, \
122 }, \
123 .drv = { \
124 { .drv_type = drv0, .offset = -1 }, \
125 { .drv_type = drv1, .offset = -1 }, \
126 { .drv_type = drv2, .offset = -1 }, \
127 { .drv_type = drv3, .offset = -1 }, \
128 }, \
129 }
130
131 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
132 { \
133 .bank_num = id, \
134 .nr_pins = pins, \
135 .name = label, \
136 .iomux = { \
137 { .offset = -1 }, \
138 { .offset = -1 }, \
139 { .offset = -1 }, \
140 { .offset = -1 }, \
141 }, \
142 .drv = { \
143 { .drv_type = type0, .offset = -1 }, \
144 { .drv_type = type1, .offset = -1 }, \
145 { .drv_type = type2, .offset = -1 }, \
146 { .drv_type = type3, .offset = -1 }, \
147 }, \
148 }
149
150 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
151 iom2, iom3, pull0, pull1, \
152 pull2, pull3) \
153 { \
154 .bank_num = id, \
155 .nr_pins = pins, \
156 .name = label, \
157 .iomux = { \
158 { .type = iom0, .offset = -1 }, \
159 { .type = iom1, .offset = -1 }, \
160 { .type = iom2, .offset = -1 }, \
161 { .type = iom3, .offset = -1 }, \
162 }, \
163 .pull_type[0] = pull0, \
164 .pull_type[1] = pull1, \
165 .pull_type[2] = pull2, \
166 .pull_type[3] = pull3, \
167 }
168
169 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
170 drv2, drv3, pull0, pull1, \
171 pull2, pull3) \
172 { \
173 .bank_num = id, \
174 .nr_pins = pins, \
175 .name = label, \
176 .iomux = { \
177 { .offset = -1 }, \
178 { .offset = -1 }, \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 }, \
182 .drv = { \
183 { .drv_type = drv0, .offset = -1 }, \
184 { .drv_type = drv1, .offset = -1 }, \
185 { .drv_type = drv2, .offset = -1 }, \
186 { .drv_type = drv3, .offset = -1 }, \
187 }, \
188 .pull_type[0] = pull0, \
189 .pull_type[1] = pull1, \
190 .pull_type[2] = pull2, \
191 .pull_type[3] = pull3, \
192 }
193
194 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
195 iom3, offset0, offset1, offset2, \
196 offset3) \
197 { \
198 .bank_num = id, \
199 .nr_pins = pins, \
200 .name = label, \
201 .iomux = { \
202 { .type = iom0, .offset = offset0 }, \
203 { .type = iom1, .offset = offset1 }, \
204 { .type = iom2, .offset = offset2 }, \
205 { .type = iom3, .offset = offset3 }, \
206 }, \
207 }
208
209 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
210 iom2, iom3, drv0, drv1, drv2, \
211 drv3, offset0, offset1, \
212 offset2, offset3) \
213 { \
214 .bank_num = id, \
215 .nr_pins = pins, \
216 .name = label, \
217 .iomux = { \
218 { .type = iom0, .offset = -1 }, \
219 { .type = iom1, .offset = -1 }, \
220 { .type = iom2, .offset = -1 }, \
221 { .type = iom3, .offset = -1 }, \
222 }, \
223 .drv = { \
224 { .drv_type = drv0, .offset = offset0 }, \
225 { .drv_type = drv1, .offset = offset1 }, \
226 { .drv_type = drv2, .offset = offset2 }, \
227 { .drv_type = drv3, .offset = offset3 }, \
228 }, \
229 }
230
231 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
232 label, iom0, iom1, iom2, \
233 iom3, drv0, drv1, drv2, \
234 drv3, offset0, offset1, \
235 offset2, offset3, pull0, \
236 pull1, pull2, pull3) \
237 { \
238 .bank_num = id, \
239 .nr_pins = pins, \
240 .name = label, \
241 .iomux = { \
242 { .type = iom0, .offset = -1 }, \
243 { .type = iom1, .offset = -1 }, \
244 { .type = iom2, .offset = -1 }, \
245 { .type = iom3, .offset = -1 }, \
246 }, \
247 .drv = { \
248 { .drv_type = drv0, .offset = offset0 }, \
249 { .drv_type = drv1, .offset = offset1 }, \
250 { .drv_type = drv2, .offset = offset2 }, \
251 { .drv_type = drv3, .offset = offset3 }, \
252 }, \
253 .pull_type[0] = pull0, \
254 .pull_type[1] = pull1, \
255 .pull_type[2] = pull2, \
256 .pull_type[3] = pull3, \
257 }
258
259 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \
260 label, iom0, iom1, \
261 iom2, iom3, offset0, \
262 offset1, offset2, \
263 offset3, drv0, drv1, \
264 drv2, drv3, pull0, \
265 pull1, pull2, pull3) \
266 { \
267 .bank_num = id, \
268 .nr_pins = pins, \
269 .name = label, \
270 .iomux = { \
271 { .type = iom0, .offset = offset0 }, \
272 { .type = iom1, .offset = offset1 }, \
273 { .type = iom2, .offset = offset2 }, \
274 { .type = iom3, .offset = offset3 }, \
275 }, \
276 .drv = { \
277 { .drv_type = drv0, .offset = -1 }, \
278 { .drv_type = drv1, .offset = -1 }, \
279 { .drv_type = drv2, .offset = -1 }, \
280 { .drv_type = drv3, .offset = -1 }, \
281 }, \
282 .pull_type[0] = pull0, \
283 .pull_type[1] = pull1, \
284 .pull_type[2] = pull2, \
285 .pull_type[3] = pull3, \
286 }
287
288 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
289 { \
290 .bank_num = ID, \
291 .pin = PIN, \
292 .func = FUNC, \
293 .route_offset = REG, \
294 .route_val = VAL, \
295 .route_location = FLAG, \
296 }
297
298 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
299 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
300
301 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
302 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
303
304 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
305 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
306
307 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
308 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
309
310 static struct regmap_config rockchip_regmap_config = {
311 .reg_bits = 32,
312 .val_bits = 32,
313 .reg_stride = 4,
314 };
315
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)316 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
317 const struct rockchip_pinctrl *info,
318 const char *name)
319 {
320 int i;
321
322 for (i = 0; i < info->ngroups; i++) {
323 if (!strcmp(info->groups[i].name, name))
324 return &info->groups[i];
325 }
326
327 return NULL;
328 }
329
330 /*
331 * given a pin number that is local to a pin controller, find out the pin bank
332 * and the register base of the pin bank.
333 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)334 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
335 unsigned pin)
336 {
337 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
338
339 while (pin >= (b->pin_base + b->nr_pins))
340 b++;
341
342 return b;
343 }
344
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)345 static struct rockchip_pin_bank *bank_num_to_bank(
346 struct rockchip_pinctrl *info,
347 unsigned num)
348 {
349 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
350 int i;
351
352 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
353 if (b->bank_num == num)
354 return b;
355 }
356
357 return ERR_PTR(-EINVAL);
358 }
359
360 /*
361 * Pinctrl_ops handling
362 */
363
rockchip_get_groups_count(struct pinctrl_dev * pctldev)364 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
365 {
366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367
368 return info->ngroups;
369 }
370
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)371 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
372 unsigned selector)
373 {
374 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
375
376 return info->groups[selector].name;
377 }
378
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)379 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
380 unsigned selector, const unsigned **pins,
381 unsigned *npins)
382 {
383 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
384
385 if (selector >= info->ngroups)
386 return -EINVAL;
387
388 *pins = info->groups[selector].pins;
389 *npins = info->groups[selector].npins;
390
391 return 0;
392 }
393
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)394 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
395 struct device_node *np,
396 struct pinctrl_map **map, unsigned *num_maps)
397 {
398 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
399 const struct rockchip_pin_group *grp;
400 struct device *dev = info->dev;
401 struct pinctrl_map *new_map;
402 struct device_node *parent;
403 int map_num = 1;
404 int i;
405
406 /*
407 * first find the group of this node and check if we need to create
408 * config maps for pins
409 */
410 grp = pinctrl_name_to_group(info, np->name);
411 if (!grp) {
412 dev_err(dev, "unable to find group for node %pOFn\n", np);
413 return -EINVAL;
414 }
415
416 map_num += grp->npins;
417
418 new_map = kzalloc_objs(*new_map, map_num);
419 if (!new_map)
420 return -ENOMEM;
421
422 *map = new_map;
423 *num_maps = map_num;
424
425 /* create mux map */
426 parent = of_get_parent(np);
427 if (!parent) {
428 kfree(new_map);
429 return -EINVAL;
430 }
431 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
432 new_map[0].data.mux.function = parent->name;
433 new_map[0].data.mux.group = np->name;
434 of_node_put(parent);
435
436 /* create config map */
437 new_map++;
438 for (i = 0; i < grp->npins; i++) {
439 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
440 new_map[i].data.configs.group_or_pin =
441 pin_get_name(pctldev, grp->pins[i]);
442 new_map[i].data.configs.configs = grp->data[i].configs;
443 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
444 }
445
446 dev_dbg(dev, "maps: function %s group %s num %d\n",
447 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
448
449 return 0;
450 }
451
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)452 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
453 struct pinctrl_map *map, unsigned num_maps)
454 {
455 kfree(map);
456 }
457
458 static const struct pinctrl_ops rockchip_pctrl_ops = {
459 .get_groups_count = rockchip_get_groups_count,
460 .get_group_name = rockchip_get_group_name,
461 .get_group_pins = rockchip_get_group_pins,
462 .dt_node_to_map = rockchip_dt_node_to_map,
463 .dt_free_map = rockchip_dt_free_map,
464 };
465
466 /*
467 * Hardware access
468 */
469
470 static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
471 {
472 .num = 1,
473 .pin = 6,
474 .reg = 0x10024,
475 .bit = 8,
476 .mask = 0xf
477 }, {
478 .num = 1,
479 .pin = 7,
480 .reg = 0x10024,
481 .bit = 12,
482 .mask = 0xf
483 },
484 };
485
486 static const struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
487 {
488 .num = 1,
489 .pin = 0,
490 .reg = 0x418,
491 .bit = 0,
492 .mask = 0x3
493 }, {
494 .num = 1,
495 .pin = 1,
496 .reg = 0x418,
497 .bit = 2,
498 .mask = 0x3
499 }, {
500 .num = 1,
501 .pin = 2,
502 .reg = 0x418,
503 .bit = 4,
504 .mask = 0x3
505 }, {
506 .num = 1,
507 .pin = 3,
508 .reg = 0x418,
509 .bit = 6,
510 .mask = 0x3
511 }, {
512 .num = 1,
513 .pin = 4,
514 .reg = 0x418,
515 .bit = 8,
516 .mask = 0x3
517 }, {
518 .num = 1,
519 .pin = 5,
520 .reg = 0x418,
521 .bit = 10,
522 .mask = 0x3
523 }, {
524 .num = 1,
525 .pin = 6,
526 .reg = 0x418,
527 .bit = 12,
528 .mask = 0x3
529 }, {
530 .num = 1,
531 .pin = 7,
532 .reg = 0x418,
533 .bit = 14,
534 .mask = 0x3
535 }, {
536 .num = 1,
537 .pin = 8,
538 .reg = 0x41c,
539 .bit = 0,
540 .mask = 0x3
541 }, {
542 .num = 1,
543 .pin = 9,
544 .reg = 0x41c,
545 .bit = 2,
546 .mask = 0x3
547 },
548 };
549
550 static const struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
551 {
552 .num = 0,
553 .pin = 20,
554 .reg = 0x10000,
555 .bit = 0,
556 .mask = 0xf
557 },
558 {
559 .num = 0,
560 .pin = 21,
561 .reg = 0x10000,
562 .bit = 4,
563 .mask = 0xf
564 },
565 {
566 .num = 0,
567 .pin = 22,
568 .reg = 0x10000,
569 .bit = 8,
570 .mask = 0xf
571 },
572 {
573 .num = 0,
574 .pin = 23,
575 .reg = 0x10000,
576 .bit = 12,
577 .mask = 0xf
578 },
579 };
580
581 static const struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
582 {
583 .num = 2,
584 .pin = 20,
585 .reg = 0xe8,
586 .bit = 0,
587 .mask = 0x7
588 }, {
589 .num = 2,
590 .pin = 21,
591 .reg = 0xe8,
592 .bit = 4,
593 .mask = 0x7
594 }, {
595 .num = 2,
596 .pin = 22,
597 .reg = 0xe8,
598 .bit = 8,
599 .mask = 0x7
600 }, {
601 .num = 2,
602 .pin = 23,
603 .reg = 0xe8,
604 .bit = 12,
605 .mask = 0x7
606 }, {
607 .num = 2,
608 .pin = 24,
609 .reg = 0xd4,
610 .bit = 12,
611 .mask = 0x7
612 },
613 };
614
615 static const struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
616 {
617 /* gpio1b6_sel */
618 .num = 1,
619 .pin = 14,
620 .reg = 0x28,
621 .bit = 12,
622 .mask = 0xf
623 }, {
624 /* gpio1b7_sel */
625 .num = 1,
626 .pin = 15,
627 .reg = 0x2c,
628 .bit = 0,
629 .mask = 0x3
630 }, {
631 /* gpio1c2_sel */
632 .num = 1,
633 .pin = 18,
634 .reg = 0x30,
635 .bit = 4,
636 .mask = 0xf
637 }, {
638 /* gpio1c3_sel */
639 .num = 1,
640 .pin = 19,
641 .reg = 0x30,
642 .bit = 8,
643 .mask = 0xf
644 }, {
645 /* gpio1c4_sel */
646 .num = 1,
647 .pin = 20,
648 .reg = 0x30,
649 .bit = 12,
650 .mask = 0xf
651 }, {
652 /* gpio1c5_sel */
653 .num = 1,
654 .pin = 21,
655 .reg = 0x34,
656 .bit = 0,
657 .mask = 0xf
658 }, {
659 /* gpio1c6_sel */
660 .num = 1,
661 .pin = 22,
662 .reg = 0x34,
663 .bit = 4,
664 .mask = 0xf
665 }, {
666 /* gpio1c7_sel */
667 .num = 1,
668 .pin = 23,
669 .reg = 0x34,
670 .bit = 8,
671 .mask = 0xf
672 }, {
673 /* gpio2a2_sel */
674 .num = 2,
675 .pin = 2,
676 .reg = 0x40,
677 .bit = 4,
678 .mask = 0x3
679 }, {
680 /* gpio2a3_sel */
681 .num = 2,
682 .pin = 3,
683 .reg = 0x40,
684 .bit = 6,
685 .mask = 0x3
686 }, {
687 /* gpio2c0_sel */
688 .num = 2,
689 .pin = 16,
690 .reg = 0x50,
691 .bit = 0,
692 .mask = 0x3
693 }, {
694 /* gpio3b2_sel */
695 .num = 3,
696 .pin = 10,
697 .reg = 0x68,
698 .bit = 4,
699 .mask = 0x3
700 }, {
701 /* gpio3b3_sel */
702 .num = 3,
703 .pin = 11,
704 .reg = 0x68,
705 .bit = 6,
706 .mask = 0x3
707 }, {
708 /* gpio3b4_sel */
709 .num = 3,
710 .pin = 12,
711 .reg = 0x68,
712 .bit = 8,
713 .mask = 0xf
714 }, {
715 /* gpio3b5_sel */
716 .num = 3,
717 .pin = 13,
718 .reg = 0x68,
719 .bit = 12,
720 .mask = 0xf
721 },
722 };
723
724 static const struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = {
725 {
726 /* gpio1b6_sel */
727 .num = 1,
728 .pin = 14,
729 .reg = 0x28,
730 .bit = 12,
731 .mask = 0xf
732 }, {
733 /* gpio1b7_sel */
734 .num = 1,
735 .pin = 15,
736 .reg = 0x2c,
737 .bit = 0,
738 .mask = 0x3
739 }, {
740 /* gpio1c2_sel */
741 .num = 1,
742 .pin = 18,
743 .reg = 0x30,
744 .bit = 4,
745 .mask = 0xf
746 }, {
747 /* gpio1c3_sel */
748 .num = 1,
749 .pin = 19,
750 .reg = 0x30,
751 .bit = 8,
752 .mask = 0xf
753 }, {
754 /* gpio1c4_sel */
755 .num = 1,
756 .pin = 20,
757 .reg = 0x30,
758 .bit = 12,
759 .mask = 0xf
760 }, {
761 /* gpio1c5_sel */
762 .num = 1,
763 .pin = 21,
764 .reg = 0x34,
765 .bit = 0,
766 .mask = 0xf
767 }, {
768 /* gpio1c6_sel */
769 .num = 1,
770 .pin = 22,
771 .reg = 0x34,
772 .bit = 4,
773 .mask = 0xf
774 }, {
775 /* gpio1c7_sel */
776 .num = 1,
777 .pin = 23,
778 .reg = 0x34,
779 .bit = 8,
780 .mask = 0xf
781 }, {
782 /* gpio2a2_sel_plus */
783 .num = 2,
784 .pin = 2,
785 .reg = 0x608,
786 .bit = 0,
787 .mask = 0x7
788 }, {
789 /* gpio2a3_sel_plus */
790 .num = 2,
791 .pin = 3,
792 .reg = 0x608,
793 .bit = 4,
794 .mask = 0x7
795 }, {
796 /* gpio2c0_sel_plus */
797 .num = 2,
798 .pin = 16,
799 .reg = 0x610,
800 .bit = 8,
801 .mask = 0x7
802 }, {
803 /* gpio3b2_sel_plus */
804 .num = 3,
805 .pin = 10,
806 .reg = 0x610,
807 .bit = 0,
808 .mask = 0x7
809 }, {
810 /* gpio3b3_sel_plus */
811 .num = 3,
812 .pin = 11,
813 .reg = 0x610,
814 .bit = 4,
815 .mask = 0x7
816 }, {
817 /* gpio3b4_sel */
818 .num = 3,
819 .pin = 12,
820 .reg = 0x68,
821 .bit = 8,
822 .mask = 0xf
823 }, {
824 /* gpio3b5_sel */
825 .num = 3,
826 .pin = 13,
827 .reg = 0x68,
828 .bit = 12,
829 .mask = 0xf
830 },
831 };
832
833 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
834 {
835 /* gpio2_b7_sel */
836 .num = 2,
837 .pin = 15,
838 .reg = 0x28,
839 .bit = 0,
840 .mask = 0x7
841 }, {
842 /* gpio2_c7_sel */
843 .num = 2,
844 .pin = 23,
845 .reg = 0x30,
846 .bit = 14,
847 .mask = 0x3
848 }, {
849 /* gpio3_b1_sel */
850 .num = 3,
851 .pin = 9,
852 .reg = 0x44,
853 .bit = 2,
854 .mask = 0x3
855 }, {
856 /* gpio3_b2_sel */
857 .num = 3,
858 .pin = 10,
859 .reg = 0x44,
860 .bit = 4,
861 .mask = 0x3
862 }, {
863 /* gpio3_b3_sel */
864 .num = 3,
865 .pin = 11,
866 .reg = 0x44,
867 .bit = 6,
868 .mask = 0x3
869 }, {
870 /* gpio3_b4_sel */
871 .num = 3,
872 .pin = 12,
873 .reg = 0x44,
874 .bit = 8,
875 .mask = 0x3
876 }, {
877 /* gpio3_b5_sel */
878 .num = 3,
879 .pin = 13,
880 .reg = 0x44,
881 .bit = 10,
882 .mask = 0x3
883 }, {
884 /* gpio3_b6_sel */
885 .num = 3,
886 .pin = 14,
887 .reg = 0x44,
888 .bit = 12,
889 .mask = 0x3
890 }, {
891 /* gpio3_b7_sel */
892 .num = 3,
893 .pin = 15,
894 .reg = 0x44,
895 .bit = 14,
896 .mask = 0x3
897 },
898 };
899
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)900 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
901 int *reg, u8 *bit, int *mask)
902 {
903 struct rockchip_pinctrl *info = bank->drvdata;
904 struct rockchip_pin_ctrl *ctrl = info->ctrl;
905 const struct rockchip_mux_recalced_data *data;
906 int i;
907
908 for (i = 0; i < ctrl->niomux_recalced; i++) {
909 data = &ctrl->iomux_recalced[i];
910 if (data->num == bank->bank_num &&
911 data->pin == pin)
912 break;
913 }
914
915 if (i >= ctrl->niomux_recalced)
916 return;
917
918 *reg = data->reg;
919 *mask = data->mask;
920 *bit = data->bit;
921 }
922
923 static const struct rockchip_mux_route_data px30_mux_route_data[] = {
924 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
925 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
926 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
927 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
928 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
929 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
930 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
931 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
932 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
933 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
934 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
935 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
936 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
937 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
938 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
939 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
940 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
941 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
942 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
943 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
944 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
945 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
946 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
947 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
948 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
949 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
950 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
951 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
952 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
953 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
954 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
955 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
956 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
957 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
958 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
959 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
960 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
961 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
962 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
963 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
964 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
965 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
966 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
967 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
968 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
969 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
970 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
971 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
972 };
973
974 static const struct rockchip_mux_route_data rv1126_mux_route_data[] = {
975 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
976 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
977
978 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
979 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
980 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
981
982 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
983 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
984
985 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
986 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
987
988 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
989 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
990
991 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
992 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
993 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
994
995 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
996 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
997
998 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
999 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
1000 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
1001
1002 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
1003 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
1004 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
1005
1006 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
1007 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
1008
1009 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
1010 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
1011
1012 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
1013 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
1014
1015 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
1016 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
1017
1018 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
1019 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
1020
1021 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
1022 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
1023
1024 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
1025 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
1026
1027 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
1028 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
1029 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
1030
1031 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
1032 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
1033 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
1034
1035 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
1036 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
1037 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
1038
1039 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
1040 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
1041
1042 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
1043 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
1044
1045 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
1046 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
1047
1048 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
1049 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
1050
1051 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
1052 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
1053
1054 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
1055 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
1056
1057 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
1058 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
1059
1060 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
1061 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
1062
1063 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
1064 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
1065 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
1066
1067 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
1068 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
1069 };
1070
1071 static const struct rockchip_mux_route_data rk3128_mux_route_data[] = {
1072 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
1073 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
1074 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
1075 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
1076 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
1077 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
1078 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
1079 };
1080
1081 static const struct rockchip_mux_route_data rk3188_mux_route_data[] = {
1082 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
1083 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
1084 };
1085
1086 static const struct rockchip_mux_route_data rk3228_mux_route_data[] = {
1087 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
1088 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
1089 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
1090 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
1091 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
1092 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
1093 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
1094 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
1095 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
1096 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
1097 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
1098 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
1099 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
1100 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
1101 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
1102 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
1103 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
1104 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
1105 };
1106
1107 static const struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1108 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
1109 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
1110 };
1111
1112 static const struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1113 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
1114 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
1115 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
1116 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
1117 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
1118 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
1119 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
1120 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
1121 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
1122 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
1123 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
1124 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
1125 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
1126 };
1127
1128 static const struct rockchip_mux_route_data rk3308b_mux_route_data[] = {
1129 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
1130 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
1131 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
1132 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
1133 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
1134 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
1135 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
1136 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
1137 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
1138 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
1139 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
1140 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
1141 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
1142 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
1143 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
1144 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
1145 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
1146 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
1147 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
1148 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
1149 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
1150 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
1151 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
1152 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
1153 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
1154 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
1155 };
1156
1157 static const struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1158 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
1159 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
1160 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
1161 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1162 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
1163 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
1164 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
1165 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
1166 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
1167 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
1168 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
1169 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
1170 };
1171
1172 static const struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1173 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
1174 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
1175 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
1176 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
1177 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
1178 };
1179
1180 static const struct rockchip_mux_route_data rk3568_mux_route_data[] = {
1181 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
1182 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
1183 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
1184 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
1185 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
1186 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
1187 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
1188 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
1189 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
1190 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
1191 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
1192 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
1193 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
1194 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
1195 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
1196 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
1197 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
1198 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
1199 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
1200 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
1201 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
1202 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
1203 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
1204 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
1205 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1206 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1207 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1208 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1209 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1210 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1211 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1212 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1213 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1214 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1215 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1216 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1217 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1218 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1219 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1220 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1221 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1222 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1223 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1224 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1225 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1226 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1227 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1228 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1229 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1230 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1231 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1232 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1233 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1234 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1235 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1236 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1237 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1238 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1239 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1240 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1241 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1242 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1243 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1244 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1245 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1246 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1247 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1248 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1249 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1250 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1251 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1252 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1253 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1254 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1255 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1256 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1257 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1258 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1259 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1260 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1261 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1262 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1263 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1264 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1265 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1266 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1267 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1268 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1269 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1270 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1271 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1272 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1273 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1274 };
1275
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)1276 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1277 int mux, u32 *loc, u32 *reg, u32 *value)
1278 {
1279 struct rockchip_pinctrl *info = bank->drvdata;
1280 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1281 const struct rockchip_mux_route_data *data;
1282 int i;
1283
1284 for (i = 0; i < ctrl->niomux_routes; i++) {
1285 data = &ctrl->iomux_routes[i];
1286 if ((data->bank_num == bank->bank_num) &&
1287 (data->pin == pin) && (data->func == mux))
1288 break;
1289 }
1290
1291 if (i >= ctrl->niomux_routes)
1292 return false;
1293
1294 *loc = data->route_location;
1295 *reg = data->route_offset;
1296 *value = data->route_val;
1297
1298 return true;
1299 }
1300
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1301 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1302 {
1303 struct rockchip_pinctrl *info = bank->drvdata;
1304 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1305 int iomux_num = (pin / 8);
1306 struct regmap *regmap;
1307 unsigned int val;
1308 int reg, ret, mask, mux_type;
1309 u8 bit;
1310
1311 if (iomux_num > 3)
1312 return -EINVAL;
1313
1314 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1315 dev_err(info->dev, "pin %d is unrouted\n", pin);
1316 return -EINVAL;
1317 }
1318
1319 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1320 return RK_FUNC_GPIO;
1321
1322 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1323 regmap = info->regmap_pmu;
1324 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1325 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1326 else
1327 regmap = info->regmap_base;
1328
1329 /* Banks with their own IOC block use its regmap for the iomux */
1330 if (bank->regmap_ioc)
1331 regmap = bank->regmap_ioc;
1332 else if (ctrl->type == RV1106)
1333 return -EINVAL;
1334
1335 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1336 return 0;
1337
1338 if (ctrl->type == RK3506) {
1339 if (bank->bank_num == 1)
1340 regmap = info->regmap_ioc1;
1341 else if (bank->bank_num == 4)
1342 return 0;
1343 }
1344
1345 /* get basic quadrupel of mux registers and the correct reg inside */
1346 mux_type = bank->iomux[iomux_num].type;
1347 reg = bank->iomux[iomux_num].offset;
1348 if (mux_type & IOMUX_WIDTH_4BIT) {
1349 if ((pin % 8) >= 4)
1350 reg += 0x4;
1351 bit = (pin % 4) * 4;
1352 mask = 0xf;
1353 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1354 if ((pin % 8) >= 5)
1355 reg += 0x4;
1356 bit = (pin % 8 % 5) * 3;
1357 mask = 0x7;
1358 } else {
1359 bit = (pin % 8) * 2;
1360 mask = 0x3;
1361 }
1362
1363 if (bank->recalced_mask & BIT(pin))
1364 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1365
1366 if (ctrl->type == RK3576) {
1367 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1368 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1369 }
1370
1371 if (ctrl->type == RK3588) {
1372 if (bank->bank_num == 0) {
1373 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1374 u32 reg0 = 0;
1375
1376 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1377 ret = regmap_read(regmap, reg0, &val);
1378 if (ret)
1379 return ret;
1380
1381 if (!(val & BIT(8)))
1382 return ((val >> bit) & mask);
1383
1384 reg = reg + 0x8000; /* BUS_IOC_BASE */
1385 regmap = info->regmap_base;
1386 }
1387 } else if (bank->bank_num > 0) {
1388 reg += 0x8000; /* BUS_IOC_BASE */
1389 }
1390 }
1391
1392 ret = regmap_read(regmap, reg, &val);
1393 if (ret)
1394 return ret;
1395
1396 return ((val >> bit) & mask);
1397 }
1398
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1399 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1400 int pin, int mux)
1401 {
1402 struct rockchip_pinctrl *info = bank->drvdata;
1403 struct device *dev = info->dev;
1404 int iomux_num = (pin / 8);
1405
1406 if (iomux_num > 3)
1407 return -EINVAL;
1408
1409 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1410 dev_err(dev, "pin %d is unrouted\n", pin);
1411 return -EINVAL;
1412 }
1413
1414 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1415 if (mux != RK_FUNC_GPIO) {
1416 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1417 return -ENOTSUPP;
1418 }
1419 }
1420
1421 return 0;
1422 }
1423
1424 /*
1425 * Set a new mux function for a pin.
1426 *
1427 * The register is divided into the upper and lower 16 bit. When changing
1428 * a value, the previous register value is not read and changed. Instead
1429 * it seems the changed bits are marked in the upper 16 bit, while the
1430 * changed value gets set in the same offset in the lower 16 bit.
1431 * All pin settings seem to be 2 bit wide in both the upper and lower
1432 * parts.
1433 * @bank: pin bank to change
1434 * @pin: pin to change
1435 * @mux: new mux function to set
1436 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1437 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1438 {
1439 struct rockchip_pinctrl *info = bank->drvdata;
1440 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1441 struct device *dev = info->dev;
1442 int iomux_num = (pin / 8);
1443 struct regmap *regmap;
1444 int reg, ret, mask, mux_type;
1445 u8 bit;
1446 u32 data, rmask, route_location, route_reg, route_val;
1447
1448 ret = rockchip_verify_mux(bank, pin, mux);
1449 if (ret < 0)
1450 return ret;
1451
1452 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1453 return 0;
1454
1455 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1456
1457 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1458 regmap = info->regmap_pmu;
1459 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1460 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1461 else
1462 regmap = info->regmap_base;
1463
1464 /* Banks with their own IOC block use its regmap for the iomux */
1465 if (bank->regmap_ioc)
1466 regmap = bank->regmap_ioc;
1467 else if (ctrl->type == RV1106)
1468 return -EINVAL;
1469
1470 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1471 return 0;
1472
1473 if (ctrl->type == RK3506) {
1474 if (bank->bank_num == 1)
1475 regmap = info->regmap_ioc1;
1476 else if (bank->bank_num == 4)
1477 return 0;
1478 }
1479
1480 /* get basic quadrupel of mux registers and the correct reg inside */
1481 mux_type = bank->iomux[iomux_num].type;
1482 reg = bank->iomux[iomux_num].offset;
1483 if (mux_type & IOMUX_WIDTH_4BIT) {
1484 if ((pin % 8) >= 4)
1485 reg += 0x4;
1486 bit = (pin % 4) * 4;
1487 mask = 0xf;
1488 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1489 if ((pin % 8) >= 5)
1490 reg += 0x4;
1491 bit = (pin % 8 % 5) * 3;
1492 mask = 0x7;
1493 } else {
1494 bit = (pin % 8) * 2;
1495 mask = 0x3;
1496 }
1497
1498 if (bank->recalced_mask & BIT(pin))
1499 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1500
1501 if (ctrl->type == RK3576) {
1502 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1503 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1504 }
1505
1506 if (ctrl->type == RK3588) {
1507 if (bank->bank_num == 0) {
1508 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1509 if (mux < 8) {
1510 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1511 data = (mask << (bit + 16));
1512 rmask = data | (data >> 16);
1513 data |= (mux & mask) << bit;
1514 ret = regmap_update_bits(regmap, reg, rmask, data);
1515 } else {
1516 u32 reg0 = 0;
1517
1518 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1519 data = (mask << (bit + 16));
1520 rmask = data | (data >> 16);
1521 data |= 8 << bit;
1522 ret = regmap_update_bits(regmap, reg0, rmask, data);
1523
1524 reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1525 data = (mask << (bit + 16));
1526 rmask = data | (data >> 16);
1527 data |= mux << bit;
1528 regmap = info->regmap_base;
1529 ret |= regmap_update_bits(regmap, reg0, rmask, data);
1530 }
1531 } else {
1532 data = (mask << (bit + 16));
1533 rmask = data | (data >> 16);
1534 data |= (mux & mask) << bit;
1535 ret = regmap_update_bits(regmap, reg, rmask, data);
1536 }
1537 return ret;
1538 } else if (bank->bank_num > 0) {
1539 reg += 0x8000; /* BUS_IOC_BASE */
1540 }
1541 }
1542
1543 if (mux > mask)
1544 return -EINVAL;
1545
1546 if (bank->route_mask & BIT(pin)) {
1547 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1548 &route_reg, &route_val)) {
1549 struct regmap *route_regmap = regmap;
1550
1551 /* handle special locations */
1552 switch (route_location) {
1553 case ROCKCHIP_ROUTE_PMU:
1554 route_regmap = info->regmap_pmu;
1555 break;
1556 case ROCKCHIP_ROUTE_GRF:
1557 route_regmap = info->regmap_base;
1558 break;
1559 }
1560
1561 ret = regmap_write(route_regmap, route_reg, route_val);
1562 if (ret)
1563 return ret;
1564 }
1565 }
1566
1567 data = (mask << (bit + 16));
1568 rmask = data | (data >> 16);
1569 data |= (mux & mask) << bit;
1570 ret = regmap_update_bits(regmap, reg, rmask, data);
1571
1572 return ret;
1573 }
1574
1575 #define PX30_PULL_PMU_OFFSET 0x10
1576 #define PX30_PULL_GRF_OFFSET 0x60
1577 #define PX30_PULL_BITS_PER_PIN 2
1578 #define PX30_PULL_PINS_PER_REG 8
1579 #define PX30_PULL_BANK_STRIDE 16
1580
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1581 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1582 int pin_num, struct regmap **regmap,
1583 int *reg, u8 *bit)
1584 {
1585 struct rockchip_pinctrl *info = bank->drvdata;
1586
1587 /* The first 32 pins of the first bank are located in PMU */
1588 if (bank->bank_num == 0) {
1589 *regmap = info->regmap_pmu;
1590 *reg = PX30_PULL_PMU_OFFSET;
1591 } else {
1592 *regmap = info->regmap_base;
1593 *reg = PX30_PULL_GRF_OFFSET;
1594
1595 /* correct the offset, as we're starting with the 2nd bank */
1596 *reg -= 0x10;
1597 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1598 }
1599
1600 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1601 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1602 *bit *= PX30_PULL_BITS_PER_PIN;
1603
1604 return 0;
1605 }
1606
1607 #define PX30_DRV_PMU_OFFSET 0x20
1608 #define PX30_DRV_GRF_OFFSET 0xf0
1609 #define PX30_DRV_BITS_PER_PIN 2
1610 #define PX30_DRV_PINS_PER_REG 8
1611 #define PX30_DRV_BANK_STRIDE 16
1612
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1613 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1614 int pin_num, struct regmap **regmap,
1615 int *reg, u8 *bit)
1616 {
1617 struct rockchip_pinctrl *info = bank->drvdata;
1618
1619 /* The first 32 pins of the first bank are located in PMU */
1620 if (bank->bank_num == 0) {
1621 *regmap = info->regmap_pmu;
1622 *reg = PX30_DRV_PMU_OFFSET;
1623 } else {
1624 *regmap = info->regmap_base;
1625 *reg = PX30_DRV_GRF_OFFSET;
1626
1627 /* correct the offset, as we're starting with the 2nd bank */
1628 *reg -= 0x10;
1629 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1630 }
1631
1632 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1633 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1634 *bit *= PX30_DRV_BITS_PER_PIN;
1635
1636 return 0;
1637 }
1638
1639 #define PX30_SCHMITT_PMU_OFFSET 0x38
1640 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1641 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1642 #define PX30_SCHMITT_BANK_STRIDE 16
1643 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1644
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1645 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1646 int pin_num,
1647 struct regmap **regmap,
1648 int *reg, u8 *bit)
1649 {
1650 struct rockchip_pinctrl *info = bank->drvdata;
1651 int pins_per_reg;
1652
1653 if (bank->bank_num == 0) {
1654 *regmap = info->regmap_pmu;
1655 *reg = PX30_SCHMITT_PMU_OFFSET;
1656 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1657 } else {
1658 *regmap = info->regmap_base;
1659 *reg = PX30_SCHMITT_GRF_OFFSET;
1660 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1661 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1662 }
1663
1664 *reg += ((pin_num / pins_per_reg) * 4);
1665 *bit = pin_num % pins_per_reg;
1666
1667 return 0;
1668 }
1669
1670 #define RV1103B_DRV_BITS_PER_PIN 8
1671 #define RV1103B_DRV_PINS_PER_REG 2
1672 #define RV1103B_DRV_GPIO0_A_OFFSET 0x40100
1673 #define RV1103B_DRV_GPIO0_B_OFFSET 0x50110
1674 #define RV1103B_DRV_GPIO1_A01_OFFSET 0x140
1675 #define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C
1676 #define RV1103B_DRV_GPIO2_OFFSET 0x30180
1677 #define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C
1678
rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1679 static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1680 int pin_num, struct regmap **regmap,
1681 int *reg, u8 *bit)
1682 {
1683 struct rockchip_pinctrl *info = bank->drvdata;
1684 int ret = 0;
1685
1686 *regmap = info->regmap_base;
1687 switch (bank->bank_num) {
1688 case 0:
1689 if (pin_num < 7)
1690 *reg = RV1103B_DRV_GPIO0_A_OFFSET;
1691 else if (pin_num > 7 && pin_num < 14)
1692 *reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
1693 else
1694 ret = -EINVAL;
1695 break;
1696
1697 case 1:
1698 if (pin_num < 6)
1699 *reg = RV1103B_DRV_GPIO1_A01_OFFSET;
1700 else if (pin_num >= 6 && pin_num < 23)
1701 *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1702 else if (pin_num >= 24 && pin_num < 30)
1703 *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1704 else
1705 ret = -EINVAL;
1706 break;
1707
1708 case 2:
1709 if (pin_num < 12) {
1710 *reg = RV1103B_DRV_GPIO2_OFFSET;
1711 } else if (pin_num >= 16) {
1712 ret = -EINVAL;
1713 } else {
1714 *reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
1715 *bit = 10;
1716
1717 return 0;
1718 }
1719 break;
1720
1721 default:
1722 ret = -EINVAL;
1723 break;
1724 }
1725
1726 if (ret) {
1727 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1728
1729 return ret;
1730 }
1731
1732 *reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
1733 *bit = pin_num % RV1103B_DRV_PINS_PER_REG;
1734 *bit *= RV1103B_DRV_BITS_PER_PIN;
1735
1736 return 0;
1737 }
1738
1739 #define RV1103B_PULL_BITS_PER_PIN 2
1740 #define RV1103B_PULL_PINS_PER_REG 8
1741 #define RV1103B_PULL_GPIO0_A_OFFSET 0x40200
1742 #define RV1103B_PULL_GPIO0_B_OFFSET 0x50204
1743 #define RV1103B_PULL_GPIO1_A01_OFFSET 0x210
1744 #define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210
1745 #define RV1103B_PULL_GPIO2_OFFSET 0x30220
1746 #define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C
1747
rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1748 static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1749 int pin_num, struct regmap **regmap,
1750 int *reg, u8 *bit)
1751 {
1752 struct rockchip_pinctrl *info = bank->drvdata;
1753 int ret = 0;
1754
1755 *regmap = info->regmap_base;
1756 switch (bank->bank_num) {
1757 case 0:
1758 if (pin_num < 7)
1759 *reg = RV1103B_PULL_GPIO0_A_OFFSET;
1760 else if (pin_num > 7 && pin_num < 14)
1761 *reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
1762 else
1763 ret = -EINVAL;
1764 break;
1765
1766 case 1:
1767 if (pin_num < 6)
1768 *reg = RV1103B_PULL_GPIO1_A01_OFFSET;
1769 else if (pin_num >= 6 && pin_num < 23)
1770 *reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1771 else if (pin_num >= 24 && pin_num < 30)
1772 *reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1773 else
1774 ret = -EINVAL;
1775 break;
1776
1777 case 2:
1778 if (pin_num < 12) {
1779 *reg = RV1103B_PULL_GPIO2_OFFSET;
1780 } else if (pin_num >= 16) {
1781 ret = -EINVAL;
1782 } else {
1783 *reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
1784 *bit = 13;
1785
1786 return 0;
1787 }
1788 break;
1789
1790 default:
1791 ret = -EINVAL;
1792 break;
1793 }
1794
1795 if (ret) {
1796 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1797
1798 return ret;
1799 }
1800
1801 *reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
1802 *bit = pin_num % RV1103B_PULL_PINS_PER_REG;
1803 *bit *= RV1103B_PULL_BITS_PER_PIN;
1804
1805 return 0;
1806 }
1807
1808 #define RV1103B_SMT_BITS_PER_PIN 1
1809 #define RV1103B_SMT_PINS_PER_REG 8
1810 #define RV1103B_SMT_GPIO0_A_OFFSET 0x40400
1811 #define RV1103B_SMT_GPIO0_B_OFFSET 0x50404
1812 #define RV1103B_SMT_GPIO1_A01_OFFSET 0x410
1813 #define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410
1814 #define RV1103B_SMT_GPIO2_OFFSET 0x30420
1815 #define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C
1816
rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1817 static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1818 int pin_num,
1819 struct regmap **regmap,
1820 int *reg, u8 *bit)
1821 {
1822 struct rockchip_pinctrl *info = bank->drvdata;
1823 int ret = 0;
1824
1825 *regmap = info->regmap_base;
1826 switch (bank->bank_num) {
1827 case 0:
1828 if (pin_num < 7)
1829 *reg = RV1103B_SMT_GPIO0_A_OFFSET;
1830 else if (pin_num > 7 && pin_num < 14)
1831 *reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
1832 else
1833 ret = -EINVAL;
1834 break;
1835
1836 case 1:
1837 if (pin_num < 6)
1838 *reg = RV1103B_SMT_GPIO1_A01_OFFSET;
1839 else if (pin_num >= 6 && pin_num < 23)
1840 *reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1841 else if (pin_num >= 24 && pin_num < 30)
1842 *reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1843 else
1844 ret = -EINVAL;
1845 break;
1846
1847 case 2:
1848 if (pin_num < 12) {
1849 *reg = RV1103B_SMT_GPIO2_OFFSET;
1850 } else if (pin_num >= 16) {
1851 ret = -EINVAL;
1852 } else {
1853 *reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
1854 *bit = 8;
1855
1856 return 0;
1857 }
1858 break;
1859
1860 default:
1861 ret = -EINVAL;
1862 break;
1863 }
1864
1865 if (ret) {
1866 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1867
1868 return ret;
1869 }
1870
1871 *reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
1872 *bit = pin_num % RV1103B_SMT_PINS_PER_REG;
1873 *bit *= RV1103B_SMT_BITS_PER_PIN;
1874
1875 return 0;
1876 }
1877
1878 #define RV1106_DRV_BITS_PER_PIN 8
1879 #define RV1106_DRV_PINS_PER_REG 2
1880 #define RV1106_PULL_BITS_PER_PIN 2
1881 #define RV1106_PULL_PINS_PER_REG 8
1882 #define RV1106_SMT_BITS_PER_PIN 1
1883 #define RV1106_SMT_PINS_PER_REG 8
1884
1885 /*
1886 * Each bank has its own IOC block, referenced by the rockchip,grf
1887 * phandle of the bank node. The offsets below are relative to the
1888 * bank's own block.
1889 */
1890 static const int rv1106_drv_offsets[] = { 0x10, 0x80, 0xc0, 0x100, 0x20 };
1891 static const int rv1106_pull_offsets[] = { 0x38, 0x1c0, 0x1d0, 0x1e0, 0x70 };
1892 static const int rv1106_smt_offsets[] = { 0x40, 0x280, 0x290, 0x2a0, 0xa0 };
1893
rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1894 static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1895 int pin_num, struct regmap **regmap,
1896 int *reg, u8 *bit)
1897 {
1898 if (bank->bank_num >= ARRAY_SIZE(rv1106_drv_offsets) ||
1899 !bank->regmap_ioc)
1900 return -EINVAL;
1901
1902 /* Only pins 0-6 of GPIO0 have drive-strength registers */
1903 if (bank->bank_num == 0 && pin_num > 6)
1904 return -ENOTSUPP;
1905
1906 *regmap = bank->regmap_ioc;
1907 *reg = rv1106_drv_offsets[bank->bank_num];
1908 *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4);
1909 *bit = pin_num % RV1106_DRV_PINS_PER_REG;
1910 *bit *= RV1106_DRV_BITS_PER_PIN;
1911
1912 return 0;
1913 }
1914
rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1915 static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1916 int pin_num, struct regmap **regmap,
1917 int *reg, u8 *bit)
1918 {
1919 if (bank->bank_num >= ARRAY_SIZE(rv1106_pull_offsets) ||
1920 !bank->regmap_ioc)
1921 return -EINVAL;
1922
1923 *regmap = bank->regmap_ioc;
1924 *reg = rv1106_pull_offsets[bank->bank_num];
1925 *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4);
1926 *bit = pin_num % RV1106_PULL_PINS_PER_REG;
1927 *bit *= RV1106_PULL_BITS_PER_PIN;
1928
1929 return 0;
1930 }
1931
rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1932 static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1933 int pin_num,
1934 struct regmap **regmap,
1935 int *reg, u8 *bit)
1936 {
1937 if (bank->bank_num >= ARRAY_SIZE(rv1106_smt_offsets) ||
1938 !bank->regmap_ioc)
1939 return -EINVAL;
1940
1941 *regmap = bank->regmap_ioc;
1942 *reg = rv1106_smt_offsets[bank->bank_num];
1943 *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4);
1944 *bit = pin_num % RV1106_SMT_PINS_PER_REG;
1945 *bit *= RV1106_SMT_BITS_PER_PIN;
1946
1947 return 0;
1948 }
1949
1950 #define RV1108_PULL_PMU_OFFSET 0x10
1951 #define RV1108_PULL_OFFSET 0x110
1952 #define RV1108_PULL_PINS_PER_REG 8
1953 #define RV1108_PULL_BITS_PER_PIN 2
1954 #define RV1108_PULL_BANK_STRIDE 16
1955
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1956 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1957 int pin_num, struct regmap **regmap,
1958 int *reg, u8 *bit)
1959 {
1960 struct rockchip_pinctrl *info = bank->drvdata;
1961
1962 /* The first 24 pins of the first bank are located in PMU */
1963 if (bank->bank_num == 0) {
1964 *regmap = info->regmap_pmu;
1965 *reg = RV1108_PULL_PMU_OFFSET;
1966 } else {
1967 *reg = RV1108_PULL_OFFSET;
1968 *regmap = info->regmap_base;
1969 /* correct the offset, as we're starting with the 2nd bank */
1970 *reg -= 0x10;
1971 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1972 }
1973
1974 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1975 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1976 *bit *= RV1108_PULL_BITS_PER_PIN;
1977
1978 return 0;
1979 }
1980
1981 #define RV1108_DRV_PMU_OFFSET 0x20
1982 #define RV1108_DRV_GRF_OFFSET 0x210
1983 #define RV1108_DRV_BITS_PER_PIN 2
1984 #define RV1108_DRV_PINS_PER_REG 8
1985 #define RV1108_DRV_BANK_STRIDE 16
1986
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1987 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1988 int pin_num, struct regmap **regmap,
1989 int *reg, u8 *bit)
1990 {
1991 struct rockchip_pinctrl *info = bank->drvdata;
1992
1993 /* The first 24 pins of the first bank are located in PMU */
1994 if (bank->bank_num == 0) {
1995 *regmap = info->regmap_pmu;
1996 *reg = RV1108_DRV_PMU_OFFSET;
1997 } else {
1998 *regmap = info->regmap_base;
1999 *reg = RV1108_DRV_GRF_OFFSET;
2000
2001 /* correct the offset, as we're starting with the 2nd bank */
2002 *reg -= 0x10;
2003 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
2004 }
2005
2006 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
2007 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
2008 *bit *= RV1108_DRV_BITS_PER_PIN;
2009
2010 return 0;
2011 }
2012
2013 #define RV1108_SCHMITT_PMU_OFFSET 0x30
2014 #define RV1108_SCHMITT_GRF_OFFSET 0x388
2015 #define RV1108_SCHMITT_BANK_STRIDE 8
2016 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
2017 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
2018
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2019 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2020 int pin_num,
2021 struct regmap **regmap,
2022 int *reg, u8 *bit)
2023 {
2024 struct rockchip_pinctrl *info = bank->drvdata;
2025 int pins_per_reg;
2026
2027 if (bank->bank_num == 0) {
2028 *regmap = info->regmap_pmu;
2029 *reg = RV1108_SCHMITT_PMU_OFFSET;
2030 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
2031 } else {
2032 *regmap = info->regmap_base;
2033 *reg = RV1108_SCHMITT_GRF_OFFSET;
2034 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
2035 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
2036 }
2037 *reg += ((pin_num / pins_per_reg) * 4);
2038 *bit = pin_num % pins_per_reg;
2039
2040 return 0;
2041 }
2042
2043 #define RV1126_PULL_PMU_OFFSET 0x40
2044 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
2045 #define RV1126_PULL_PINS_PER_REG 8
2046 #define RV1126_PULL_BITS_PER_PIN 2
2047 #define RV1126_PULL_BANK_STRIDE 16
2048 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
2049
rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2050 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2051 int pin_num, struct regmap **regmap,
2052 int *reg, u8 *bit)
2053 {
2054 struct rockchip_pinctrl *info = bank->drvdata;
2055
2056 /* The first 24 pins of the first bank are located in PMU */
2057 if (bank->bank_num == 0) {
2058 if (RV1126_GPIO_C4_D7(pin_num)) {
2059 *regmap = info->regmap_base;
2060 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
2061 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
2062 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
2063 *bit *= RV1126_PULL_BITS_PER_PIN;
2064 return 0;
2065 }
2066 *regmap = info->regmap_pmu;
2067 *reg = RV1126_PULL_PMU_OFFSET;
2068 } else {
2069 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
2070 *regmap = info->regmap_base;
2071 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
2072 }
2073
2074 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
2075 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
2076 *bit *= RV1126_PULL_BITS_PER_PIN;
2077
2078 return 0;
2079 }
2080
2081 #define RV1126_DRV_PMU_OFFSET 0x20
2082 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
2083 #define RV1126_DRV_BITS_PER_PIN 4
2084 #define RV1126_DRV_PINS_PER_REG 4
2085 #define RV1126_DRV_BANK_STRIDE 32
2086
rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2087 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2088 int pin_num, struct regmap **regmap,
2089 int *reg, u8 *bit)
2090 {
2091 struct rockchip_pinctrl *info = bank->drvdata;
2092
2093 /* The first 24 pins of the first bank are located in PMU */
2094 if (bank->bank_num == 0) {
2095 if (RV1126_GPIO_C4_D7(pin_num)) {
2096 *regmap = info->regmap_base;
2097 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
2098 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
2099 *reg -= 0x4;
2100 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
2101 *bit *= RV1126_DRV_BITS_PER_PIN;
2102 return 0;
2103 }
2104 *regmap = info->regmap_pmu;
2105 *reg = RV1126_DRV_PMU_OFFSET;
2106 } else {
2107 *regmap = info->regmap_base;
2108 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
2109 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
2110 }
2111
2112 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
2113 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
2114 *bit *= RV1126_DRV_BITS_PER_PIN;
2115
2116 return 0;
2117 }
2118
2119 #define RV1126_SCHMITT_PMU_OFFSET 0x60
2120 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
2121 #define RV1126_SCHMITT_BANK_STRIDE 16
2122 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
2123 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
2124
rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2125 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2126 int pin_num,
2127 struct regmap **regmap,
2128 int *reg, u8 *bit)
2129 {
2130 struct rockchip_pinctrl *info = bank->drvdata;
2131 int pins_per_reg;
2132
2133 if (bank->bank_num == 0) {
2134 if (RV1126_GPIO_C4_D7(pin_num)) {
2135 *regmap = info->regmap_base;
2136 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
2137 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
2138 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
2139 return 0;
2140 }
2141 *regmap = info->regmap_pmu;
2142 *reg = RV1126_SCHMITT_PMU_OFFSET;
2143 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
2144 } else {
2145 *regmap = info->regmap_base;
2146 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
2147 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
2148 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
2149 }
2150 *reg += ((pin_num / pins_per_reg) * 4);
2151 *bit = pin_num % pins_per_reg;
2152
2153 return 0;
2154 }
2155
2156 #define RK3308_SCHMITT_PINS_PER_REG 8
2157 #define RK3308_SCHMITT_BANK_STRIDE 16
2158 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
2159
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2160 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2161 int pin_num, struct regmap **regmap,
2162 int *reg, u8 *bit)
2163 {
2164 struct rockchip_pinctrl *info = bank->drvdata;
2165
2166 *regmap = info->regmap_base;
2167 *reg = RK3308_SCHMITT_GRF_OFFSET;
2168
2169 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
2170 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
2171 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
2172
2173 return 0;
2174 }
2175
2176 #define RK2928_PULL_OFFSET 0x118
2177 #define RK2928_PULL_PINS_PER_REG 16
2178 #define RK2928_PULL_BANK_STRIDE 8
2179
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2180 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2181 int pin_num, struct regmap **regmap,
2182 int *reg, u8 *bit)
2183 {
2184 struct rockchip_pinctrl *info = bank->drvdata;
2185
2186 *regmap = info->regmap_base;
2187 *reg = RK2928_PULL_OFFSET;
2188 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
2189 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
2190
2191 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
2192
2193 return 0;
2194 };
2195
2196 #define RK3128_PULL_OFFSET 0x118
2197
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2198 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2199 int pin_num, struct regmap **regmap,
2200 int *reg, u8 *bit)
2201 {
2202 struct rockchip_pinctrl *info = bank->drvdata;
2203
2204 *regmap = info->regmap_base;
2205 *reg = RK3128_PULL_OFFSET;
2206 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
2207 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
2208
2209 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
2210
2211 return 0;
2212 }
2213
2214 #define RK3188_PULL_OFFSET 0x164
2215 #define RK3188_PULL_BITS_PER_PIN 2
2216 #define RK3188_PULL_PINS_PER_REG 8
2217 #define RK3188_PULL_BANK_STRIDE 16
2218 #define RK3188_PULL_PMU_OFFSET 0x64
2219
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2220 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2221 int pin_num, struct regmap **regmap,
2222 int *reg, u8 *bit)
2223 {
2224 struct rockchip_pinctrl *info = bank->drvdata;
2225
2226 /* The first 12 pins of the first bank are located elsewhere */
2227 if (bank->bank_num == 0 && pin_num < 12) {
2228 *regmap = info->regmap_pmu ? info->regmap_pmu
2229 : bank->regmap_pull;
2230 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
2231 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2232 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2233 *bit *= RK3188_PULL_BITS_PER_PIN;
2234 } else {
2235 *regmap = info->regmap_pull ? info->regmap_pull
2236 : info->regmap_base;
2237 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
2238
2239 /* correct the offset, as it is the 2nd pull register */
2240 *reg -= 4;
2241 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2242 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2243
2244 /*
2245 * The bits in these registers have an inverse ordering
2246 * with the lowest pin being in bits 15:14 and the highest
2247 * pin in bits 1:0
2248 */
2249 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
2250 *bit *= RK3188_PULL_BITS_PER_PIN;
2251 }
2252
2253 return 0;
2254 }
2255
2256 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2257 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2258 int pin_num, struct regmap **regmap,
2259 int *reg, u8 *bit)
2260 {
2261 struct rockchip_pinctrl *info = bank->drvdata;
2262
2263 /* The first 24 pins of the first bank are located in PMU */
2264 if (bank->bank_num == 0) {
2265 *regmap = info->regmap_pmu;
2266 *reg = RK3188_PULL_PMU_OFFSET;
2267
2268 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2269 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2270 *bit *= RK3188_PULL_BITS_PER_PIN;
2271 } else {
2272 *regmap = info->regmap_base;
2273 *reg = RK3288_PULL_OFFSET;
2274
2275 /* correct the offset, as we're starting with the 2nd bank */
2276 *reg -= 0x10;
2277 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2278 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2279
2280 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2281 *bit *= RK3188_PULL_BITS_PER_PIN;
2282 }
2283
2284 return 0;
2285 }
2286
2287 #define RK3288_DRV_PMU_OFFSET 0x70
2288 #define RK3288_DRV_GRF_OFFSET 0x1c0
2289 #define RK3288_DRV_BITS_PER_PIN 2
2290 #define RK3288_DRV_PINS_PER_REG 8
2291 #define RK3288_DRV_BANK_STRIDE 16
2292
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2293 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2294 int pin_num, struct regmap **regmap,
2295 int *reg, u8 *bit)
2296 {
2297 struct rockchip_pinctrl *info = bank->drvdata;
2298
2299 /* The first 24 pins of the first bank are located in PMU */
2300 if (bank->bank_num == 0) {
2301 *regmap = info->regmap_pmu;
2302 *reg = RK3288_DRV_PMU_OFFSET;
2303
2304 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2305 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2306 *bit *= RK3288_DRV_BITS_PER_PIN;
2307 } else {
2308 *regmap = info->regmap_base;
2309 *reg = RK3288_DRV_GRF_OFFSET;
2310
2311 /* correct the offset, as we're starting with the 2nd bank */
2312 *reg -= 0x10;
2313 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2314 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2315
2316 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2317 *bit *= RK3288_DRV_BITS_PER_PIN;
2318 }
2319
2320 return 0;
2321 }
2322
2323 #define RK3228_PULL_OFFSET 0x100
2324
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2325 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2326 int pin_num, struct regmap **regmap,
2327 int *reg, u8 *bit)
2328 {
2329 struct rockchip_pinctrl *info = bank->drvdata;
2330
2331 *regmap = info->regmap_base;
2332 *reg = RK3228_PULL_OFFSET;
2333 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2334 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2335
2336 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2337 *bit *= RK3188_PULL_BITS_PER_PIN;
2338
2339 return 0;
2340 }
2341
2342 #define RK3228_DRV_GRF_OFFSET 0x200
2343
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2344 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2345 int pin_num, struct regmap **regmap,
2346 int *reg, u8 *bit)
2347 {
2348 struct rockchip_pinctrl *info = bank->drvdata;
2349
2350 *regmap = info->regmap_base;
2351 *reg = RK3228_DRV_GRF_OFFSET;
2352 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2353 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2354
2355 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2356 *bit *= RK3288_DRV_BITS_PER_PIN;
2357
2358 return 0;
2359 }
2360
2361 #define RK3308_PULL_OFFSET 0xa0
2362
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2363 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2364 int pin_num, struct regmap **regmap,
2365 int *reg, u8 *bit)
2366 {
2367 struct rockchip_pinctrl *info = bank->drvdata;
2368
2369 *regmap = info->regmap_base;
2370 *reg = RK3308_PULL_OFFSET;
2371 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2372 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2373
2374 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2375 *bit *= RK3188_PULL_BITS_PER_PIN;
2376
2377 return 0;
2378 }
2379
2380 #define RK3308_DRV_GRF_OFFSET 0x100
2381
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2382 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2383 int pin_num, struct regmap **regmap,
2384 int *reg, u8 *bit)
2385 {
2386 struct rockchip_pinctrl *info = bank->drvdata;
2387
2388 *regmap = info->regmap_base;
2389 *reg = RK3308_DRV_GRF_OFFSET;
2390 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2391 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2392
2393 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2394 *bit *= RK3288_DRV_BITS_PER_PIN;
2395
2396 return 0;
2397 }
2398
2399 #define RK3368_PULL_GRF_OFFSET 0x100
2400 #define RK3368_PULL_PMU_OFFSET 0x10
2401
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2402 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2403 int pin_num, struct regmap **regmap,
2404 int *reg, u8 *bit)
2405 {
2406 struct rockchip_pinctrl *info = bank->drvdata;
2407
2408 /* The first 32 pins of the first bank are located in PMU */
2409 if (bank->bank_num == 0) {
2410 *regmap = info->regmap_pmu;
2411 *reg = RK3368_PULL_PMU_OFFSET;
2412
2413 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2414 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2415 *bit *= RK3188_PULL_BITS_PER_PIN;
2416 } else {
2417 *regmap = info->regmap_base;
2418 *reg = RK3368_PULL_GRF_OFFSET;
2419
2420 /* correct the offset, as we're starting with the 2nd bank */
2421 *reg -= 0x10;
2422 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2423 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2424
2425 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2426 *bit *= RK3188_PULL_BITS_PER_PIN;
2427 }
2428
2429 return 0;
2430 }
2431
2432 #define RK3368_DRV_PMU_OFFSET 0x20
2433 #define RK3368_DRV_GRF_OFFSET 0x200
2434
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2435 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2436 int pin_num, struct regmap **regmap,
2437 int *reg, u8 *bit)
2438 {
2439 struct rockchip_pinctrl *info = bank->drvdata;
2440
2441 /* The first 32 pins of the first bank are located in PMU */
2442 if (bank->bank_num == 0) {
2443 *regmap = info->regmap_pmu;
2444 *reg = RK3368_DRV_PMU_OFFSET;
2445
2446 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2447 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2448 *bit *= RK3288_DRV_BITS_PER_PIN;
2449 } else {
2450 *regmap = info->regmap_base;
2451 *reg = RK3368_DRV_GRF_OFFSET;
2452
2453 /* correct the offset, as we're starting with the 2nd bank */
2454 *reg -= 0x10;
2455 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2456 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2457
2458 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2459 *bit *= RK3288_DRV_BITS_PER_PIN;
2460 }
2461
2462 return 0;
2463 }
2464
2465 #define RK3399_PULL_GRF_OFFSET 0xe040
2466 #define RK3399_PULL_PMU_OFFSET 0x40
2467 #define RK3399_DRV_3BITS_PER_PIN 3
2468
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2469 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2470 int pin_num, struct regmap **regmap,
2471 int *reg, u8 *bit)
2472 {
2473 struct rockchip_pinctrl *info = bank->drvdata;
2474
2475 /* The bank0:16 and bank1:32 pins are located in PMU */
2476 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2477 *regmap = info->regmap_pmu;
2478 *reg = RK3399_PULL_PMU_OFFSET;
2479
2480 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2481
2482 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2483 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2484 *bit *= RK3188_PULL_BITS_PER_PIN;
2485 } else {
2486 *regmap = info->regmap_base;
2487 *reg = RK3399_PULL_GRF_OFFSET;
2488
2489 /* correct the offset, as we're starting with the 3rd bank */
2490 *reg -= 0x20;
2491 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2492 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2493
2494 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2495 *bit *= RK3188_PULL_BITS_PER_PIN;
2496 }
2497
2498 return 0;
2499 }
2500
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2501 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2502 int pin_num, struct regmap **regmap,
2503 int *reg, u8 *bit)
2504 {
2505 struct rockchip_pinctrl *info = bank->drvdata;
2506 int drv_num = (pin_num / 8);
2507
2508 /* The bank0:16 and bank1:32 pins are located in PMU */
2509 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2510 *regmap = info->regmap_pmu;
2511 else
2512 *regmap = info->regmap_base;
2513
2514 *reg = bank->drv[drv_num].offset;
2515 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2516 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2517 *bit = (pin_num % 8) * 3;
2518 else
2519 *bit = (pin_num % 8) * 2;
2520
2521 return 0;
2522 }
2523
2524 #define RK3506_DRV_BITS_PER_PIN 8
2525 #define RK3506_DRV_PINS_PER_REG 2
2526 #define RK3506_DRV_GPIO0_A_OFFSET 0x100
2527 #define RK3506_DRV_GPIO0_D_OFFSET 0x830
2528 #define RK3506_DRV_GPIO1_OFFSET 0x140
2529 #define RK3506_DRV_GPIO2_OFFSET 0x180
2530 #define RK3506_DRV_GPIO3_OFFSET 0x1c0
2531 #define RK3506_DRV_GPIO4_OFFSET 0x840
2532
rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2533 static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2534 int pin_num, struct regmap **regmap,
2535 int *reg, u8 *bit)
2536 {
2537 struct rockchip_pinctrl *info = bank->drvdata;
2538 int ret = 0;
2539
2540 switch (bank->bank_num) {
2541 case 0:
2542 *regmap = info->regmap_pmu;
2543 if (pin_num > 24) {
2544 ret = -EINVAL;
2545 } else if (pin_num < 24) {
2546 *reg = RK3506_DRV_GPIO0_A_OFFSET;
2547 } else {
2548 *reg = RK3506_DRV_GPIO0_D_OFFSET;
2549 *bit = 3;
2550
2551 return 0;
2552 }
2553 break;
2554
2555 case 1:
2556 *regmap = info->regmap_ioc1;
2557 if (pin_num < 28)
2558 *reg = RK3506_DRV_GPIO1_OFFSET;
2559 else
2560 ret = -EINVAL;
2561 break;
2562
2563 case 2:
2564 *regmap = info->regmap_base;
2565 if (pin_num < 17)
2566 *reg = RK3506_DRV_GPIO2_OFFSET;
2567 else
2568 ret = -EINVAL;
2569 break;
2570
2571 case 3:
2572 *regmap = info->regmap_base;
2573 if (pin_num < 15)
2574 *reg = RK3506_DRV_GPIO3_OFFSET;
2575 else
2576 ret = -EINVAL;
2577 break;
2578
2579 case 4:
2580 *regmap = info->regmap_base;
2581 if (pin_num < 8 || pin_num > 11) {
2582 ret = -EINVAL;
2583 } else {
2584 *reg = RK3506_DRV_GPIO4_OFFSET;
2585 *bit = 10;
2586
2587 return 0;
2588 }
2589 break;
2590
2591 default:
2592 ret = -EINVAL;
2593 break;
2594 }
2595
2596 if (ret) {
2597 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2598
2599 return ret;
2600 }
2601
2602 *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
2603 *bit = pin_num % RK3506_DRV_PINS_PER_REG;
2604 *bit *= RK3506_DRV_BITS_PER_PIN;
2605
2606 return 0;
2607 }
2608
2609 #define RK3506_PULL_BITS_PER_PIN 2
2610 #define RK3506_PULL_PINS_PER_REG 8
2611 #define RK3506_PULL_GPIO0_A_OFFSET 0x200
2612 #define RK3506_PULL_GPIO0_D_OFFSET 0x830
2613 #define RK3506_PULL_GPIO1_OFFSET 0x210
2614 #define RK3506_PULL_GPIO2_OFFSET 0x220
2615 #define RK3506_PULL_GPIO3_OFFSET 0x230
2616 #define RK3506_PULL_GPIO4_OFFSET 0x840
2617
rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2618 static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2619 int pin_num, struct regmap **regmap,
2620 int *reg, u8 *bit)
2621 {
2622 struct rockchip_pinctrl *info = bank->drvdata;
2623 int ret = 0;
2624
2625 switch (bank->bank_num) {
2626 case 0:
2627 *regmap = info->regmap_pmu;
2628 if (pin_num > 24) {
2629 ret = -EINVAL;
2630 } else if (pin_num < 24) {
2631 *reg = RK3506_PULL_GPIO0_A_OFFSET;
2632 } else {
2633 *reg = RK3506_PULL_GPIO0_D_OFFSET;
2634 *bit = 5;
2635
2636 return 0;
2637 }
2638 break;
2639
2640 case 1:
2641 *regmap = info->regmap_ioc1;
2642 if (pin_num < 28)
2643 *reg = RK3506_PULL_GPIO1_OFFSET;
2644 else
2645 ret = -EINVAL;
2646 break;
2647
2648 case 2:
2649 *regmap = info->regmap_base;
2650 if (pin_num < 17)
2651 *reg = RK3506_PULL_GPIO2_OFFSET;
2652 else
2653 ret = -EINVAL;
2654 break;
2655
2656 case 3:
2657 *regmap = info->regmap_base;
2658 if (pin_num < 15)
2659 *reg = RK3506_PULL_GPIO3_OFFSET;
2660 else
2661 ret = -EINVAL;
2662 break;
2663
2664 case 4:
2665 *regmap = info->regmap_base;
2666 if (pin_num < 8 || pin_num > 11) {
2667 ret = -EINVAL;
2668 } else {
2669 *reg = RK3506_PULL_GPIO4_OFFSET;
2670 *bit = 13;
2671
2672 return 0;
2673 }
2674 break;
2675
2676 default:
2677 ret = -EINVAL;
2678 break;
2679 }
2680
2681 if (ret) {
2682 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2683
2684 return ret;
2685 }
2686
2687 *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
2688 *bit = pin_num % RK3506_PULL_PINS_PER_REG;
2689 *bit *= RK3506_PULL_BITS_PER_PIN;
2690
2691 return 0;
2692 }
2693
2694 #define RK3506_SMT_BITS_PER_PIN 1
2695 #define RK3506_SMT_PINS_PER_REG 8
2696 #define RK3506_SMT_GPIO0_A_OFFSET 0x400
2697 #define RK3506_SMT_GPIO0_D_OFFSET 0x830
2698 #define RK3506_SMT_GPIO1_OFFSET 0x410
2699 #define RK3506_SMT_GPIO2_OFFSET 0x420
2700 #define RK3506_SMT_GPIO3_OFFSET 0x430
2701 #define RK3506_SMT_GPIO4_OFFSET 0x840
2702
rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2703 static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2704 int pin_num,
2705 struct regmap **regmap,
2706 int *reg, u8 *bit)
2707 {
2708 struct rockchip_pinctrl *info = bank->drvdata;
2709 int ret = 0;
2710
2711 switch (bank->bank_num) {
2712 case 0:
2713 *regmap = info->regmap_pmu;
2714 if (pin_num > 24) {
2715 ret = -EINVAL;
2716 } else if (pin_num < 24) {
2717 *reg = RK3506_SMT_GPIO0_A_OFFSET;
2718 } else {
2719 *reg = RK3506_SMT_GPIO0_D_OFFSET;
2720 *bit = 9;
2721
2722 return 0;
2723 }
2724 break;
2725
2726 case 1:
2727 *regmap = info->regmap_ioc1;
2728 if (pin_num < 28)
2729 *reg = RK3506_SMT_GPIO1_OFFSET;
2730 else
2731 ret = -EINVAL;
2732 break;
2733
2734 case 2:
2735 *regmap = info->regmap_base;
2736 if (pin_num < 17)
2737 *reg = RK3506_SMT_GPIO2_OFFSET;
2738 else
2739 ret = -EINVAL;
2740 break;
2741
2742 case 3:
2743 *regmap = info->regmap_base;
2744 if (pin_num < 15)
2745 *reg = RK3506_SMT_GPIO3_OFFSET;
2746 else
2747 ret = -EINVAL;
2748 break;
2749
2750 case 4:
2751 *regmap = info->regmap_base;
2752 if (pin_num < 8 || pin_num > 11) {
2753 ret = -EINVAL;
2754 } else {
2755 *reg = RK3506_SMT_GPIO4_OFFSET;
2756 *bit = 8;
2757
2758 return 0;
2759 }
2760 break;
2761
2762 default:
2763 ret = -EINVAL;
2764 break;
2765 }
2766
2767 if (ret) {
2768 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2769
2770 return ret;
2771 }
2772
2773 *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
2774 *bit = pin_num % RK3506_SMT_PINS_PER_REG;
2775 *bit *= RK3506_SMT_BITS_PER_PIN;
2776
2777 return 0;
2778 }
2779
2780 #define RK3528_DRV_BITS_PER_PIN 8
2781 #define RK3528_DRV_PINS_PER_REG 2
2782 #define RK3528_DRV_GPIO0_OFFSET 0x100
2783 #define RK3528_DRV_GPIO1_OFFSET 0x20120
2784 #define RK3528_DRV_GPIO2_OFFSET 0x30160
2785 #define RK3528_DRV_GPIO3_OFFSET 0x20190
2786 #define RK3528_DRV_GPIO4_OFFSET 0x101C0
2787
rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2788 static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2789 int pin_num, struct regmap **regmap,
2790 int *reg, u8 *bit)
2791 {
2792 struct rockchip_pinctrl *info = bank->drvdata;
2793
2794 *regmap = info->regmap_base;
2795
2796 if (bank->bank_num == 0)
2797 *reg = RK3528_DRV_GPIO0_OFFSET;
2798 else if (bank->bank_num == 1)
2799 *reg = RK3528_DRV_GPIO1_OFFSET;
2800 else if (bank->bank_num == 2)
2801 *reg = RK3528_DRV_GPIO2_OFFSET;
2802 else if (bank->bank_num == 3)
2803 *reg = RK3528_DRV_GPIO3_OFFSET;
2804 else if (bank->bank_num == 4)
2805 *reg = RK3528_DRV_GPIO4_OFFSET;
2806 else
2807 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2808
2809 *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
2810 *bit = pin_num % RK3528_DRV_PINS_PER_REG;
2811 *bit *= RK3528_DRV_BITS_PER_PIN;
2812
2813 return 0;
2814 }
2815
2816 #define RK3528_PULL_BITS_PER_PIN 2
2817 #define RK3528_PULL_PINS_PER_REG 8
2818 #define RK3528_PULL_GPIO0_OFFSET 0x200
2819 #define RK3528_PULL_GPIO1_OFFSET 0x20210
2820 #define RK3528_PULL_GPIO2_OFFSET 0x30220
2821 #define RK3528_PULL_GPIO3_OFFSET 0x20230
2822 #define RK3528_PULL_GPIO4_OFFSET 0x10240
2823
rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2824 static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2825 int pin_num, struct regmap **regmap,
2826 int *reg, u8 *bit)
2827 {
2828 struct rockchip_pinctrl *info = bank->drvdata;
2829
2830 *regmap = info->regmap_base;
2831
2832 if (bank->bank_num == 0)
2833 *reg = RK3528_PULL_GPIO0_OFFSET;
2834 else if (bank->bank_num == 1)
2835 *reg = RK3528_PULL_GPIO1_OFFSET;
2836 else if (bank->bank_num == 2)
2837 *reg = RK3528_PULL_GPIO2_OFFSET;
2838 else if (bank->bank_num == 3)
2839 *reg = RK3528_PULL_GPIO3_OFFSET;
2840 else if (bank->bank_num == 4)
2841 *reg = RK3528_PULL_GPIO4_OFFSET;
2842 else
2843 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2844
2845 *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
2846 *bit = pin_num % RK3528_PULL_PINS_PER_REG;
2847 *bit *= RK3528_PULL_BITS_PER_PIN;
2848
2849 return 0;
2850 }
2851
2852 #define RK3528_SMT_BITS_PER_PIN 1
2853 #define RK3528_SMT_PINS_PER_REG 8
2854 #define RK3528_SMT_GPIO0_OFFSET 0x400
2855 #define RK3528_SMT_GPIO1_OFFSET 0x20410
2856 #define RK3528_SMT_GPIO2_OFFSET 0x30420
2857 #define RK3528_SMT_GPIO3_OFFSET 0x20430
2858 #define RK3528_SMT_GPIO4_OFFSET 0x10440
2859
rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2860 static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2861 int pin_num,
2862 struct regmap **regmap,
2863 int *reg, u8 *bit)
2864 {
2865 struct rockchip_pinctrl *info = bank->drvdata;
2866
2867 *regmap = info->regmap_base;
2868
2869 if (bank->bank_num == 0)
2870 *reg = RK3528_SMT_GPIO0_OFFSET;
2871 else if (bank->bank_num == 1)
2872 *reg = RK3528_SMT_GPIO1_OFFSET;
2873 else if (bank->bank_num == 2)
2874 *reg = RK3528_SMT_GPIO2_OFFSET;
2875 else if (bank->bank_num == 3)
2876 *reg = RK3528_SMT_GPIO3_OFFSET;
2877 else if (bank->bank_num == 4)
2878 *reg = RK3528_SMT_GPIO4_OFFSET;
2879 else
2880 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2881
2882 *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
2883 *bit = pin_num % RK3528_SMT_PINS_PER_REG;
2884 *bit *= RK3528_SMT_BITS_PER_PIN;
2885
2886 return 0;
2887 }
2888
2889 #define RK3562_DRV_BITS_PER_PIN 8
2890 #define RK3562_DRV_PINS_PER_REG 2
2891 #define RK3562_DRV_GPIO0_OFFSET 0x20070
2892 #define RK3562_DRV_GPIO1_OFFSET 0x200
2893 #define RK3562_DRV_GPIO2_OFFSET 0x240
2894 #define RK3562_DRV_GPIO3_OFFSET 0x10280
2895 #define RK3562_DRV_GPIO4_OFFSET 0x102C0
2896
rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2897 static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2898 int pin_num, struct regmap **regmap,
2899 int *reg, u8 *bit)
2900 {
2901 struct rockchip_pinctrl *info = bank->drvdata;
2902
2903 *regmap = info->regmap_base;
2904 switch (bank->bank_num) {
2905 case 0:
2906 *reg = RK3562_DRV_GPIO0_OFFSET;
2907 break;
2908
2909 case 1:
2910 *reg = RK3562_DRV_GPIO1_OFFSET;
2911 break;
2912
2913 case 2:
2914 *reg = RK3562_DRV_GPIO2_OFFSET;
2915 break;
2916
2917 case 3:
2918 *reg = RK3562_DRV_GPIO3_OFFSET;
2919 break;
2920
2921 case 4:
2922 *reg = RK3562_DRV_GPIO4_OFFSET;
2923 break;
2924
2925 default:
2926 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2927 break;
2928 }
2929
2930 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
2931 *bit = pin_num % RK3562_DRV_PINS_PER_REG;
2932 *bit *= RK3562_DRV_BITS_PER_PIN;
2933
2934 return 0;
2935 }
2936
2937 #define RK3562_PULL_BITS_PER_PIN 2
2938 #define RK3562_PULL_PINS_PER_REG 8
2939 #define RK3562_PULL_GPIO0_OFFSET 0x20020
2940 #define RK3562_PULL_GPIO1_OFFSET 0x80
2941 #define RK3562_PULL_GPIO2_OFFSET 0x90
2942 #define RK3562_PULL_GPIO3_OFFSET 0x100A0
2943 #define RK3562_PULL_GPIO4_OFFSET 0x100B0
2944
rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2945 static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2946 int pin_num, struct regmap **regmap,
2947 int *reg, u8 *bit)
2948 {
2949 struct rockchip_pinctrl *info = bank->drvdata;
2950
2951 *regmap = info->regmap_base;
2952 switch (bank->bank_num) {
2953 case 0:
2954 *reg = RK3562_PULL_GPIO0_OFFSET;
2955 break;
2956
2957 case 1:
2958 *reg = RK3562_PULL_GPIO1_OFFSET;
2959 break;
2960
2961 case 2:
2962 *reg = RK3562_PULL_GPIO2_OFFSET;
2963 break;
2964
2965 case 3:
2966 *reg = RK3562_PULL_GPIO3_OFFSET;
2967 break;
2968
2969 case 4:
2970 *reg = RK3562_PULL_GPIO4_OFFSET;
2971 break;
2972
2973 default:
2974 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2975 break;
2976 }
2977
2978 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
2979 *bit = pin_num % RK3562_PULL_PINS_PER_REG;
2980 *bit *= RK3562_PULL_BITS_PER_PIN;
2981
2982 return 0;
2983 }
2984
2985 #define RK3562_SMT_BITS_PER_PIN 2
2986 #define RK3562_SMT_PINS_PER_REG 8
2987 #define RK3562_SMT_GPIO0_OFFSET 0x20030
2988 #define RK3562_SMT_GPIO1_OFFSET 0xC0
2989 #define RK3562_SMT_GPIO2_OFFSET 0xD0
2990 #define RK3562_SMT_GPIO3_OFFSET 0x100E0
2991 #define RK3562_SMT_GPIO4_OFFSET 0x100F0
2992
rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2993 static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2994 int pin_num,
2995 struct regmap **regmap,
2996 int *reg, u8 *bit)
2997 {
2998 struct rockchip_pinctrl *info = bank->drvdata;
2999
3000 *regmap = info->regmap_base;
3001 switch (bank->bank_num) {
3002 case 0:
3003 *reg = RK3562_SMT_GPIO0_OFFSET;
3004 break;
3005
3006 case 1:
3007 *reg = RK3562_SMT_GPIO1_OFFSET;
3008 break;
3009
3010 case 2:
3011 *reg = RK3562_SMT_GPIO2_OFFSET;
3012 break;
3013
3014 case 3:
3015 *reg = RK3562_SMT_GPIO3_OFFSET;
3016 break;
3017
3018 case 4:
3019 *reg = RK3562_SMT_GPIO4_OFFSET;
3020 break;
3021
3022 default:
3023 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
3024 break;
3025 }
3026
3027 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
3028 *bit = pin_num % RK3562_SMT_PINS_PER_REG;
3029 *bit *= RK3562_SMT_BITS_PER_PIN;
3030
3031 return 0;
3032 }
3033
3034 #define RK3568_PULL_PMU_OFFSET 0x20
3035 #define RK3568_PULL_GRF_OFFSET 0x80
3036 #define RK3568_PULL_BITS_PER_PIN 2
3037 #define RK3568_PULL_PINS_PER_REG 8
3038 #define RK3568_PULL_BANK_STRIDE 0x10
3039
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3040 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
3041 int pin_num, struct regmap **regmap,
3042 int *reg, u8 *bit)
3043 {
3044 struct rockchip_pinctrl *info = bank->drvdata;
3045
3046 if (bank->bank_num == 0) {
3047 *regmap = info->regmap_pmu;
3048 *reg = RK3568_PULL_PMU_OFFSET;
3049 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
3050 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
3051
3052 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
3053 *bit *= RK3568_PULL_BITS_PER_PIN;
3054 } else {
3055 *regmap = info->regmap_base;
3056 *reg = RK3568_PULL_GRF_OFFSET;
3057 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
3058 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
3059
3060 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
3061 *bit *= RK3568_PULL_BITS_PER_PIN;
3062 }
3063
3064 return 0;
3065 }
3066
3067 #define RK3568_DRV_PMU_OFFSET 0x70
3068 #define RK3568_DRV_GRF_OFFSET 0x200
3069 #define RK3568_DRV_BITS_PER_PIN 8
3070 #define RK3568_DRV_PINS_PER_REG 2
3071 #define RK3568_DRV_BANK_STRIDE 0x40
3072
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3073 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
3074 int pin_num, struct regmap **regmap,
3075 int *reg, u8 *bit)
3076 {
3077 struct rockchip_pinctrl *info = bank->drvdata;
3078
3079 /* The first 32 pins of the first bank are located in PMU */
3080 if (bank->bank_num == 0) {
3081 *regmap = info->regmap_pmu;
3082 *reg = RK3568_DRV_PMU_OFFSET;
3083 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
3084
3085 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
3086 *bit *= RK3568_DRV_BITS_PER_PIN;
3087 } else {
3088 *regmap = info->regmap_base;
3089 *reg = RK3568_DRV_GRF_OFFSET;
3090 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
3091 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
3092
3093 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
3094 *bit *= RK3568_DRV_BITS_PER_PIN;
3095 }
3096
3097 return 0;
3098 }
3099
3100 #define RK3576_DRV_BITS_PER_PIN 4
3101 #define RK3576_DRV_PINS_PER_REG 4
3102 #define RK3576_DRV_GPIO0_AL_OFFSET 0x10
3103 #define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
3104 #define RK3576_DRV_GPIO1_OFFSET 0x6020
3105 #define RK3576_DRV_GPIO2_OFFSET 0x6040
3106 #define RK3576_DRV_GPIO3_OFFSET 0x6060
3107 #define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
3108 #define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
3109 #define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
3110
rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3111 static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
3112 int pin_num, struct regmap **regmap,
3113 int *reg, u8 *bit)
3114 {
3115 struct rockchip_pinctrl *info = bank->drvdata;
3116
3117 *regmap = info->regmap_base;
3118
3119 if (bank->bank_num == 0 && pin_num < 12)
3120 *reg = RK3576_DRV_GPIO0_AL_OFFSET;
3121 else if (bank->bank_num == 0)
3122 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
3123 else if (bank->bank_num == 1)
3124 *reg = RK3576_DRV_GPIO1_OFFSET;
3125 else if (bank->bank_num == 2)
3126 *reg = RK3576_DRV_GPIO2_OFFSET;
3127 else if (bank->bank_num == 3)
3128 *reg = RK3576_DRV_GPIO3_OFFSET;
3129 else if (bank->bank_num == 4 && pin_num < 16)
3130 *reg = RK3576_DRV_GPIO4_AL_OFFSET;
3131 else if (bank->bank_num == 4 && pin_num < 24)
3132 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
3133 else if (bank->bank_num == 4)
3134 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
3135 else
3136 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
3137
3138 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
3139 *bit = pin_num % RK3576_DRV_PINS_PER_REG;
3140 *bit *= RK3576_DRV_BITS_PER_PIN;
3141
3142 return 0;
3143 }
3144
3145 #define RK3576_PULL_BITS_PER_PIN 2
3146 #define RK3576_PULL_PINS_PER_REG 8
3147 #define RK3576_PULL_GPIO0_AL_OFFSET 0x20
3148 #define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
3149 #define RK3576_PULL_GPIO1_OFFSET 0x6110
3150 #define RK3576_PULL_GPIO2_OFFSET 0x6120
3151 #define RK3576_PULL_GPIO3_OFFSET 0x6130
3152 #define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
3153 #define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
3154 #define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
3155
rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3156 static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
3157 int pin_num, struct regmap **regmap,
3158 int *reg, u8 *bit)
3159 {
3160 struct rockchip_pinctrl *info = bank->drvdata;
3161
3162 *regmap = info->regmap_base;
3163
3164 if (bank->bank_num == 0 && pin_num < 12)
3165 *reg = RK3576_PULL_GPIO0_AL_OFFSET;
3166 else if (bank->bank_num == 0)
3167 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
3168 else if (bank->bank_num == 1)
3169 *reg = RK3576_PULL_GPIO1_OFFSET;
3170 else if (bank->bank_num == 2)
3171 *reg = RK3576_PULL_GPIO2_OFFSET;
3172 else if (bank->bank_num == 3)
3173 *reg = RK3576_PULL_GPIO3_OFFSET;
3174 else if (bank->bank_num == 4 && pin_num < 16)
3175 *reg = RK3576_PULL_GPIO4_AL_OFFSET;
3176 else if (bank->bank_num == 4 && pin_num < 24)
3177 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
3178 else if (bank->bank_num == 4)
3179 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
3180 else
3181 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
3182
3183 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
3184 *bit = pin_num % RK3576_PULL_PINS_PER_REG;
3185 *bit *= RK3576_PULL_BITS_PER_PIN;
3186
3187 return 0;
3188 }
3189
3190 #define RK3576_SMT_BITS_PER_PIN 1
3191 #define RK3576_SMT_PINS_PER_REG 8
3192 #define RK3576_SMT_GPIO0_AL_OFFSET 0x30
3193 #define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
3194 #define RK3576_SMT_GPIO1_OFFSET 0x6210
3195 #define RK3576_SMT_GPIO2_OFFSET 0x6220
3196 #define RK3576_SMT_GPIO3_OFFSET 0x6230
3197 #define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
3198 #define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
3199 #define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
3200
rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3201 static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3202 int pin_num,
3203 struct regmap **regmap,
3204 int *reg, u8 *bit)
3205 {
3206 struct rockchip_pinctrl *info = bank->drvdata;
3207
3208 *regmap = info->regmap_base;
3209
3210 if (bank->bank_num == 0 && pin_num < 12)
3211 *reg = RK3576_SMT_GPIO0_AL_OFFSET;
3212 else if (bank->bank_num == 0)
3213 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
3214 else if (bank->bank_num == 1)
3215 *reg = RK3576_SMT_GPIO1_OFFSET;
3216 else if (bank->bank_num == 2)
3217 *reg = RK3576_SMT_GPIO2_OFFSET;
3218 else if (bank->bank_num == 3)
3219 *reg = RK3576_SMT_GPIO3_OFFSET;
3220 else if (bank->bank_num == 4 && pin_num < 16)
3221 *reg = RK3576_SMT_GPIO4_AL_OFFSET;
3222 else if (bank->bank_num == 4 && pin_num < 24)
3223 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
3224 else if (bank->bank_num == 4)
3225 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
3226 else
3227 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
3228
3229 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
3230 *bit = pin_num % RK3576_SMT_PINS_PER_REG;
3231 *bit *= RK3576_SMT_BITS_PER_PIN;
3232
3233 return 0;
3234 }
3235
3236 #define RK3588_PMU1_IOC_REG (0x0000)
3237 #define RK3588_PMU2_IOC_REG (0x4000)
3238 #define RK3588_BUS_IOC_REG (0x8000)
3239 #define RK3588_VCCIO1_4_IOC_REG (0x9000)
3240 #define RK3588_VCCIO3_5_IOC_REG (0xA000)
3241 #define RK3588_VCCIO2_IOC_REG (0xB000)
3242 #define RK3588_VCCIO6_IOC_REG (0xC000)
3243 #define RK3588_EMMC_IOC_REG (0xD000)
3244
3245 static const u32 rk3588_ds_regs[][2] = {
3246 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
3247 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
3248 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
3249 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
3250 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
3251 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
3252 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
3253 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
3254 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
3255 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
3256 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
3257 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
3258 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
3259 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
3260 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
3261 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
3262 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
3263 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
3264 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
3265 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
3266 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
3267 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
3268 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
3269 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
3270 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
3271 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
3272 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
3273 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
3274 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
3275 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
3276 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
3277 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
3278 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
3279 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
3280 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
3281 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
3282 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
3283 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
3284 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
3285 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
3286 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
3287 };
3288
3289 static const u32 rk3588_p_regs[][2] = {
3290 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
3291 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
3292 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
3293 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
3294 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
3295 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
3296 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
3297 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
3298 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
3299 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
3300 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
3301 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
3302 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
3303 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
3304 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
3305 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
3306 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
3307 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
3308 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
3309 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
3310 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
3311 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
3312 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
3313 };
3314
3315 static const u32 rk3588_smt_regs[][2] = {
3316 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
3317 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
3318 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
3319 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
3320 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
3321 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
3322 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
3323 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
3324 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
3325 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
3326 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
3327 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
3328 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
3329 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
3330 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
3331 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
3332 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
3333 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
3334 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
3335 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
3336 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
3337 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
3338 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
3339 };
3340
3341 #define RK3588_PULL_BITS_PER_PIN 2
3342 #define RK3588_PULL_PINS_PER_REG 8
3343
rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3344 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
3345 int pin_num, struct regmap **regmap,
3346 int *reg, u8 *bit)
3347 {
3348 struct rockchip_pinctrl *info = bank->drvdata;
3349 u8 bank_num = bank->bank_num;
3350 u32 pin = bank_num * 32 + pin_num;
3351 int i;
3352
3353 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
3354 if (pin >= rk3588_p_regs[i][0]) {
3355 *reg = rk3588_p_regs[i][1];
3356 *regmap = info->regmap_base;
3357 *bit = pin_num % RK3588_PULL_PINS_PER_REG;
3358 *bit *= RK3588_PULL_BITS_PER_PIN;
3359 return 0;
3360 }
3361 }
3362
3363 return -EINVAL;
3364 }
3365
3366 #define RK3588_DRV_BITS_PER_PIN 4
3367 #define RK3588_DRV_PINS_PER_REG 4
3368
rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3369 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
3370 int pin_num, struct regmap **regmap,
3371 int *reg, u8 *bit)
3372 {
3373 struct rockchip_pinctrl *info = bank->drvdata;
3374 u8 bank_num = bank->bank_num;
3375 u32 pin = bank_num * 32 + pin_num;
3376 int i;
3377
3378 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
3379 if (pin >= rk3588_ds_regs[i][0]) {
3380 *reg = rk3588_ds_regs[i][1];
3381 *regmap = info->regmap_base;
3382 *bit = pin_num % RK3588_DRV_PINS_PER_REG;
3383 *bit *= RK3588_DRV_BITS_PER_PIN;
3384 return 0;
3385 }
3386 }
3387
3388 return -EINVAL;
3389 }
3390
3391 #define RK3588_SMT_BITS_PER_PIN 1
3392 #define RK3588_SMT_PINS_PER_REG 8
3393
rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3394 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3395 int pin_num,
3396 struct regmap **regmap,
3397 int *reg, u8 *bit)
3398 {
3399 struct rockchip_pinctrl *info = bank->drvdata;
3400 u8 bank_num = bank->bank_num;
3401 u32 pin = bank_num * 32 + pin_num;
3402 int i;
3403
3404 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
3405 if (pin >= rk3588_smt_regs[i][0]) {
3406 *reg = rk3588_smt_regs[i][1];
3407 *regmap = info->regmap_base;
3408 *bit = pin_num % RK3588_SMT_PINS_PER_REG;
3409 *bit *= RK3588_SMT_BITS_PER_PIN;
3410 return 0;
3411 }
3412 }
3413
3414 return -EINVAL;
3415 }
3416
3417 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
3418 { 2, 4, 8, 12, -1, -1, -1, -1 },
3419 { 3, 6, 9, 12, -1, -1, -1, -1 },
3420 { 5, 10, 15, 20, -1, -1, -1, -1 },
3421 { 4, 6, 8, 10, 12, 14, 16, 18 },
3422 { 4, 7, 10, 13, 16, 19, 22, 26 }
3423 };
3424
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)3425 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
3426 int pin_num)
3427 {
3428 struct rockchip_pinctrl *info = bank->drvdata;
3429 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3430 struct device *dev = info->dev;
3431 struct regmap *regmap;
3432 int reg, ret;
3433 u32 data, temp, rmask_bits;
3434 u8 bit;
3435 int drv_type = bank->drv[pin_num / 8].drv_type;
3436
3437 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3438 drv_type = DRV_TYPE_IO_LEVEL_2_BIT;
3439
3440 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
3441 if (ret)
3442 return ret;
3443
3444 switch (drv_type) {
3445 case DRV_TYPE_IO_1V8_3V0_AUTO:
3446 case DRV_TYPE_IO_3V3_ONLY:
3447 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
3448 switch (bit) {
3449 case 0 ... 12:
3450 /* regular case, nothing to do */
3451 break;
3452 case 15:
3453 /*
3454 * drive-strength offset is special, as it is
3455 * spread over 2 registers
3456 */
3457 ret = regmap_read(regmap, reg, &data);
3458 if (ret)
3459 return ret;
3460
3461 ret = regmap_read(regmap, reg + 0x4, &temp);
3462 if (ret)
3463 return ret;
3464
3465 /*
3466 * the bit data[15] contains bit 0 of the value
3467 * while temp[1:0] contains bits 2 and 1
3468 */
3469 data >>= 15;
3470 temp &= 0x3;
3471 temp <<= 1;
3472 data |= temp;
3473
3474 return rockchip_perpin_drv_list[drv_type][data];
3475 case 18 ... 21:
3476 /* setting fully enclosed in the second register */
3477 reg += 4;
3478 bit -= 16;
3479 break;
3480 default:
3481 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
3482 bit, drv_type);
3483 return -EINVAL;
3484 }
3485
3486 break;
3487 case DRV_TYPE_IO_DEFAULT:
3488 case DRV_TYPE_IO_1V8_OR_3V0:
3489 case DRV_TYPE_IO_1V8_ONLY:
3490 rmask_bits = RK3288_DRV_BITS_PER_PIN;
3491 break;
3492 case DRV_TYPE_IO_LEVEL_2_BIT:
3493 ret = regmap_read(regmap, reg, &data);
3494 if (ret)
3495 return ret;
3496 data >>= bit;
3497
3498 return data & 0x3;
3499 case DRV_TYPE_IO_LEVEL_8_BIT:
3500 ret = regmap_read(regmap, reg, &data);
3501 if (ret)
3502 return ret;
3503 data >>= bit;
3504 data &= (1 << 8) - 1;
3505
3506 ret = hweight8(data);
3507 if (ret > 0)
3508 return ret - 1;
3509 else
3510 return -EINVAL;
3511 default:
3512 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
3513 return -EINVAL;
3514 }
3515
3516 ret = regmap_read(regmap, reg, &data);
3517 if (ret)
3518 return ret;
3519
3520 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3521 data = data >> 10;
3522 return data & 0x3;
3523 }
3524
3525 data >>= bit;
3526 data &= (1 << rmask_bits) - 1;
3527
3528 return rockchip_perpin_drv_list[drv_type][data];
3529 }
3530
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)3531 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
3532 int pin_num, int strength)
3533 {
3534 struct rockchip_pinctrl *info = bank->drvdata;
3535 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3536 struct device *dev = info->dev;
3537 struct regmap *regmap;
3538 int reg, ret, i;
3539 u32 data, rmask, rmask_bits, temp;
3540 u8 bit;
3541 int drv_type = bank->drv[pin_num / 8].drv_type;
3542
3543 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
3544 bank->bank_num, pin_num, strength);
3545
3546 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
3547 if (ret)
3548 return ret;
3549 if (ctrl->type == RK3588) {
3550 rmask_bits = RK3588_DRV_BITS_PER_PIN;
3551 ret = strength;
3552 goto config;
3553 } else if (ctrl->type == RV1103B ||
3554 ctrl->type == RV1106 ||
3555 ctrl->type == RK3506 ||
3556 ctrl->type == RK3528 ||
3557 ctrl->type == RK3562 ||
3558 ctrl->type == RK3568) {
3559 rmask_bits = RK3568_DRV_BITS_PER_PIN;
3560 ret = (1 << (strength + 1)) - 1;
3561 goto config;
3562 } else if (ctrl->type == RK3576) {
3563 rmask_bits = RK3576_DRV_BITS_PER_PIN;
3564 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
3565 goto config;
3566 }
3567
3568 if (ctrl->type == RV1126) {
3569 rmask_bits = RV1126_DRV_BITS_PER_PIN;
3570 ret = strength;
3571 goto config;
3572 }
3573
3574 ret = -EINVAL;
3575 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
3576 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
3577 ret = i;
3578 break;
3579 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
3580 ret = rockchip_perpin_drv_list[drv_type][i];
3581 break;
3582 }
3583 }
3584
3585 if (ret < 0) {
3586 dev_err(dev, "unsupported driver strength %d\n", strength);
3587 return ret;
3588 }
3589
3590 switch (drv_type) {
3591 case DRV_TYPE_IO_1V8_3V0_AUTO:
3592 case DRV_TYPE_IO_3V3_ONLY:
3593 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
3594 switch (bit) {
3595 case 0 ... 12:
3596 /* regular case, nothing to do */
3597 break;
3598 case 15:
3599 /*
3600 * drive-strength offset is special, as it is spread
3601 * over 2 registers, the bit data[15] contains bit 0
3602 * of the value while temp[1:0] contains bits 2 and 1
3603 */
3604 data = (ret & 0x1) << 15;
3605 temp = (ret >> 0x1) & 0x3;
3606
3607 rmask = BIT(15) | BIT(31);
3608 data |= BIT(31);
3609 ret = regmap_update_bits(regmap, reg, rmask, data);
3610 if (ret)
3611 return ret;
3612
3613 rmask = 0x3 | (0x3 << 16);
3614 temp |= (0x3 << 16);
3615 reg += 0x4;
3616 ret = regmap_update_bits(regmap, reg, rmask, temp);
3617
3618 return ret;
3619 case 18 ... 21:
3620 /* setting fully enclosed in the second register */
3621 reg += 4;
3622 bit -= 16;
3623 break;
3624 default:
3625 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
3626 bit, drv_type);
3627 return -EINVAL;
3628 }
3629 break;
3630 case DRV_TYPE_IO_DEFAULT:
3631 case DRV_TYPE_IO_1V8_OR_3V0:
3632 case DRV_TYPE_IO_1V8_ONLY:
3633 rmask_bits = RK3288_DRV_BITS_PER_PIN;
3634 break;
3635 default:
3636 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
3637 return -EINVAL;
3638 }
3639
3640 config:
3641 if (ctrl->type == RK3506) {
3642 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
3643 rmask_bits = 2;
3644 ret = strength;
3645 }
3646 }
3647
3648 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3649 rmask_bits = 2;
3650 ret = strength;
3651 }
3652
3653 /* enable the write to the equivalent lower bits */
3654 data = ((1 << rmask_bits) - 1) << (bit + 16);
3655 rmask = data | (data >> 16);
3656 data |= (ret << bit);
3657
3658 ret = regmap_update_bits(regmap, reg, rmask, data);
3659
3660 return ret;
3661 }
3662
3663 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
3664 {
3665 PIN_CONFIG_BIAS_DISABLE,
3666 PIN_CONFIG_BIAS_PULL_UP,
3667 PIN_CONFIG_BIAS_PULL_DOWN,
3668 PIN_CONFIG_BIAS_BUS_HOLD
3669 },
3670 {
3671 PIN_CONFIG_BIAS_DISABLE,
3672 PIN_CONFIG_BIAS_PULL_DOWN,
3673 PIN_CONFIG_BIAS_DISABLE,
3674 PIN_CONFIG_BIAS_PULL_UP
3675 },
3676 };
3677
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)3678 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
3679 {
3680 struct rockchip_pinctrl *info = bank->drvdata;
3681 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3682 struct device *dev = info->dev;
3683 struct regmap *regmap;
3684 int reg, ret, pull_type;
3685 u8 bit;
3686 u32 data;
3687
3688 /* rk3066b does support any pulls */
3689 if (ctrl->type == RK3066B)
3690 return PIN_CONFIG_BIAS_DISABLE;
3691
3692 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3693 if (ret)
3694 return ret;
3695
3696 ret = regmap_read(regmap, reg, &data);
3697 if (ret)
3698 return ret;
3699
3700 switch (ctrl->type) {
3701 case RK2928:
3702 case RK3128:
3703 return !(data & BIT(bit))
3704 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
3705 : PIN_CONFIG_BIAS_DISABLE;
3706 case PX30:
3707 case RV1103B:
3708 case RV1106:
3709 case RV1108:
3710 case RK3188:
3711 case RK3288:
3712 case RK3308:
3713 case RK3308B:
3714 case RK3328:
3715 case RK3368:
3716 case RK3399:
3717 case RK3528:
3718 case RK3562:
3719 case RK3568:
3720 case RK3576:
3721 case RK3588:
3722 pull_type = bank->pull_type[pin_num / 8];
3723 data >>= bit;
3724 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
3725
3726 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3727 pull_type = 1;
3728 /*
3729 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3730 * where that pull up value becomes 3.
3731 */
3732 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
3733 if (data == 3)
3734 data = 1;
3735 }
3736
3737 return rockchip_pull_list[pull_type][data];
3738 default:
3739 dev_err(dev, "unsupported pinctrl type\n");
3740 return -EINVAL;
3741 };
3742 }
3743
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)3744 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
3745 int pin_num, int pull)
3746 {
3747 struct rockchip_pinctrl *info = bank->drvdata;
3748 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3749 struct device *dev = info->dev;
3750 struct regmap *regmap;
3751 int reg, ret, i, pull_type;
3752 u8 bit;
3753 u32 data, rmask;
3754
3755 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
3756
3757 /* rk3066b does support any pulls */
3758 if (ctrl->type == RK3066B)
3759 return pull ? -EINVAL : 0;
3760
3761 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3762 if (ret)
3763 return ret;
3764
3765 switch (ctrl->type) {
3766 case RK2928:
3767 case RK3128:
3768 data = BIT(bit + 16);
3769 if (pull == PIN_CONFIG_BIAS_DISABLE)
3770 data |= BIT(bit);
3771 ret = regmap_write(regmap, reg, data);
3772 break;
3773 case PX30:
3774 case RV1103B:
3775 case RV1106:
3776 case RV1108:
3777 case RV1126:
3778 case RK3188:
3779 case RK3288:
3780 case RK3308:
3781 case RK3308B:
3782 case RK3328:
3783 case RK3368:
3784 case RK3399:
3785 case RK3506:
3786 case RK3528:
3787 case RK3562:
3788 case RK3568:
3789 case RK3576:
3790 case RK3588:
3791 pull_type = bank->pull_type[pin_num / 8];
3792 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3793 pull_type = 1;
3794 ret = -EINVAL;
3795 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
3796 i++) {
3797 if (rockchip_pull_list[pull_type][i] == pull) {
3798 ret = i;
3799 break;
3800 }
3801 }
3802 /*
3803 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3804 * where that pull up value becomes 3.
3805 */
3806 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
3807 if (ret == 1)
3808 ret = 3;
3809 }
3810
3811 if (ret < 0) {
3812 dev_err(dev, "unsupported pull setting %d\n", pull);
3813 return ret;
3814 }
3815
3816 /* enable the write to the equivalent lower bits */
3817 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
3818 rmask = data | (data >> 16);
3819 data |= (ret << bit);
3820
3821 ret = regmap_update_bits(regmap, reg, rmask, data);
3822 break;
3823 default:
3824 dev_err(dev, "unsupported pinctrl type\n");
3825 return -EINVAL;
3826 }
3827
3828 return ret;
3829 }
3830
3831 #define RK3328_SCHMITT_BITS_PER_PIN 1
3832 #define RK3328_SCHMITT_PINS_PER_REG 16
3833 #define RK3328_SCHMITT_BANK_STRIDE 8
3834 #define RK3328_SCHMITT_GRF_OFFSET 0x380
3835
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3836 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3837 int pin_num,
3838 struct regmap **regmap,
3839 int *reg, u8 *bit)
3840 {
3841 struct rockchip_pinctrl *info = bank->drvdata;
3842
3843 *regmap = info->regmap_base;
3844 *reg = RK3328_SCHMITT_GRF_OFFSET;
3845
3846 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
3847 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
3848 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
3849
3850 return 0;
3851 }
3852
3853 #define RK3568_SCHMITT_BITS_PER_PIN 2
3854 #define RK3568_SCHMITT_PINS_PER_REG 8
3855 #define RK3568_SCHMITT_BANK_STRIDE 0x10
3856 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
3857 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
3858
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3859 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3860 int pin_num,
3861 struct regmap **regmap,
3862 int *reg, u8 *bit)
3863 {
3864 struct rockchip_pinctrl *info = bank->drvdata;
3865
3866 if (bank->bank_num == 0) {
3867 *regmap = info->regmap_pmu;
3868 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
3869 } else {
3870 *regmap = info->regmap_base;
3871 *reg = RK3568_SCHMITT_GRF_OFFSET;
3872 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
3873 }
3874
3875 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
3876 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
3877 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
3878
3879 return 0;
3880 }
3881
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)3882 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
3883 {
3884 struct rockchip_pinctrl *info = bank->drvdata;
3885 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3886 struct regmap *regmap;
3887 int reg, ret;
3888 u8 bit;
3889 u32 data;
3890
3891 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3892 if (ret)
3893 return ret;
3894
3895 ret = regmap_read(regmap, reg, &data);
3896 if (ret)
3897 return ret;
3898
3899 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3900 data >>= 8;
3901 return data & 0x3;
3902 }
3903
3904 data >>= bit;
3905 switch (ctrl->type) {
3906 case RK3562:
3907 case RK3568:
3908 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
3909 default:
3910 break;
3911 }
3912
3913 if (ctrl->type == RK3506)
3914 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
3915 return data & 0x3;
3916
3917 return data & 0x1;
3918 }
3919
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)3920 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
3921 int pin_num, int enable)
3922 {
3923 struct rockchip_pinctrl *info = bank->drvdata;
3924 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3925 struct device *dev = info->dev;
3926 struct regmap *regmap;
3927 int reg, ret;
3928 u8 bit;
3929 u32 data, rmask;
3930
3931 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
3932 bank->bank_num, pin_num, enable);
3933
3934 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3935 if (ret)
3936 return ret;
3937
3938 /* enable the write to the equivalent lower bits */
3939 switch (ctrl->type) {
3940 case RK3562:
3941 case RK3568:
3942 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
3943 rmask = data | (data >> 16);
3944 data |= ((enable ? 0x2 : 0x1) << bit);
3945 break;
3946 default:
3947 data = BIT(bit + 16) | (enable << bit);
3948 rmask = BIT(bit + 16) | BIT(bit);
3949 break;
3950 }
3951
3952 if (ctrl->type == RK3506) {
3953 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
3954 data = 0x3 << (bit + 16);
3955 rmask = data | (data >> 16);
3956 data |= ((enable ? 0x3 : 0) << bit);
3957 }
3958 }
3959
3960 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3961 data = 0x3 << (bit + 16);
3962 rmask = data | (data >> 16);
3963 data |= ((enable ? 0x3 : 0) << bit);
3964 }
3965
3966 return regmap_update_bits(regmap, reg, rmask, data);
3967 }
3968
3969 /*
3970 * Pinmux_ops handling
3971 */
3972
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)3973 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3974 {
3975 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3976
3977 return info->nfunctions;
3978 }
3979
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)3980 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
3981 unsigned selector)
3982 {
3983 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3984
3985 return info->functions[selector].name;
3986 }
3987
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)3988 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
3989 unsigned selector, const char * const **groups,
3990 unsigned * const num_groups)
3991 {
3992 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3993
3994 *groups = info->functions[selector].groups;
3995 *num_groups = info->functions[selector].ngroups;
3996
3997 return 0;
3998 }
3999
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)4000 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
4001 unsigned group)
4002 {
4003 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
4004 const unsigned int *pins = info->groups[group].pins;
4005 const struct rockchip_pin_config *data = info->groups[group].data;
4006 struct device *dev = info->dev;
4007 struct rockchip_pin_bank *bank;
4008 int cnt, ret = 0;
4009
4010 dev_dbg(dev, "enable function %s group %s\n",
4011 info->functions[selector].name, info->groups[group].name);
4012
4013 /*
4014 * for each pin in the pin group selected, program the corresponding
4015 * pin function number in the config register.
4016 */
4017 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
4018 bank = pin_to_bank(info, pins[cnt]);
4019 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
4020 data[cnt].func);
4021 if (ret)
4022 break;
4023 }
4024
4025 if (ret) {
4026 /* revert the already done pin settings */
4027 for (cnt--; cnt >= 0; cnt--) {
4028 bank = pin_to_bank(info, pins[cnt]);
4029 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
4030 }
4031
4032 return ret;
4033 }
4034
4035 return 0;
4036 }
4037
rockchip_pmx_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)4038 static int rockchip_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
4039 struct pinctrl_gpio_range *range,
4040 unsigned int offset)
4041 {
4042 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
4043 struct rockchip_pin_bank *bank;
4044
4045 bank = pin_to_bank(info, offset);
4046 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
4047 }
4048
4049 static const struct pinmux_ops rockchip_pmx_ops = {
4050 .get_functions_count = rockchip_pmx_get_funcs_count,
4051 .get_function_name = rockchip_pmx_get_func_name,
4052 .get_function_groups = rockchip_pmx_get_groups,
4053 .set_mux = rockchip_pmx_set,
4054 .gpio_request_enable = rockchip_pmx_gpio_request_enable,
4055 };
4056
4057 /*
4058 * Pinconf_ops handling
4059 */
4060
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)4061 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
4062 enum pin_config_param pull)
4063 {
4064 switch (ctrl->type) {
4065 case RK2928:
4066 case RK3128:
4067 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
4068 pull == PIN_CONFIG_BIAS_DISABLE);
4069 case RK3066B:
4070 return pull ? false : true;
4071 case PX30:
4072 case RV1103B:
4073 case RV1106:
4074 case RV1108:
4075 case RV1126:
4076 case RK3188:
4077 case RK3288:
4078 case RK3308:
4079 case RK3308B:
4080 case RK3328:
4081 case RK3368:
4082 case RK3399:
4083 case RK3506:
4084 case RK3528:
4085 case RK3562:
4086 case RK3568:
4087 case RK3576:
4088 case RK3588:
4089 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
4090 }
4091
4092 return false;
4093 }
4094
rockchip_pinconf_defer_pin(struct rockchip_pin_bank * bank,unsigned int pin,u32 param,u32 arg)4095 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
4096 unsigned int pin, u32 param, u32 arg)
4097 {
4098 struct rockchip_pin_deferred *cfg;
4099
4100 cfg = kzalloc_obj(*cfg);
4101 if (!cfg)
4102 return -ENOMEM;
4103
4104 cfg->pin = pin;
4105 cfg->param = param;
4106 cfg->arg = arg;
4107
4108 list_add_tail(&cfg->head, &bank->deferred_pins);
4109
4110 return 0;
4111 }
4112
4113 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)4114 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
4115 unsigned long *configs, unsigned num_configs)
4116 {
4117 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
4118 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
4119 struct gpio_chip *gpio = &bank->gpio_chip;
4120 enum pin_config_param param;
4121 u32 arg;
4122 int i;
4123 int rc;
4124
4125 for (i = 0; i < num_configs; i++) {
4126 param = pinconf_to_config_param(configs[i]);
4127 arg = pinconf_to_config_argument(configs[i]);
4128
4129 if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) {
4130 /*
4131 * Check for gpio driver not being probed yet.
4132 * The lock makes sure that either gpio-probe has completed
4133 * or the gpio driver hasn't probed yet.
4134 */
4135 scoped_guard(mutex, &bank->deferred_lock) {
4136 if (!gpio || !gpio->direction_output)
4137 return rockchip_pinconf_defer_pin(bank,
4138 pin - bank->pin_base,
4139 param, arg);
4140 }
4141 }
4142
4143 switch (param) {
4144 case PIN_CONFIG_BIAS_DISABLE:
4145 rc = rockchip_set_pull(bank, pin - bank->pin_base,
4146 param);
4147 if (rc)
4148 return rc;
4149 break;
4150 case PIN_CONFIG_BIAS_PULL_UP:
4151 case PIN_CONFIG_BIAS_PULL_DOWN:
4152 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
4153 case PIN_CONFIG_BIAS_BUS_HOLD:
4154 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
4155 return -ENOTSUPP;
4156
4157 if (!arg)
4158 return -EINVAL;
4159
4160 rc = rockchip_set_pull(bank, pin - bank->pin_base,
4161 param);
4162 if (rc)
4163 return rc;
4164 break;
4165 case PIN_CONFIG_LEVEL:
4166 rc = rockchip_set_mux(bank, pin - bank->pin_base,
4167 RK_FUNC_GPIO);
4168 if (rc != RK_FUNC_GPIO)
4169 return -EINVAL;
4170
4171 rc = gpio->direction_output(gpio, pin - bank->pin_base,
4172 arg);
4173 if (rc)
4174 return rc;
4175 break;
4176 case PIN_CONFIG_INPUT_ENABLE:
4177 rc = rockchip_set_mux(bank, pin - bank->pin_base,
4178 RK_FUNC_GPIO);
4179 if (rc != RK_FUNC_GPIO)
4180 return -EINVAL;
4181
4182 rc = gpio->direction_input(gpio, pin - bank->pin_base);
4183 if (rc)
4184 return rc;
4185 break;
4186 case PIN_CONFIG_DRIVE_STRENGTH:
4187 /* rk3288 is the first with per-pin drive-strength */
4188 if (!info->ctrl->drv_calc_reg)
4189 return -ENOTSUPP;
4190
4191 rc = rockchip_set_drive_perpin(bank,
4192 pin - bank->pin_base, arg);
4193 if (rc < 0)
4194 return rc;
4195 break;
4196 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4197 if (!info->ctrl->schmitt_calc_reg)
4198 return -ENOTSUPP;
4199
4200 rc = rockchip_set_schmitt(bank,
4201 pin - bank->pin_base, arg);
4202 if (rc < 0)
4203 return rc;
4204 break;
4205 default:
4206 return -ENOTSUPP;
4207 break;
4208 }
4209 } /* for each config */
4210
4211 return 0;
4212 }
4213
4214 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)4215 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
4216 unsigned long *config)
4217 {
4218 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
4219 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
4220 struct gpio_chip *gpio = &bank->gpio_chip;
4221 enum pin_config_param param = pinconf_to_config_param(*config);
4222 u16 arg;
4223 int rc;
4224
4225 switch (param) {
4226 case PIN_CONFIG_BIAS_DISABLE:
4227 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
4228 return -EINVAL;
4229
4230 arg = 0;
4231 break;
4232 case PIN_CONFIG_BIAS_PULL_UP:
4233 case PIN_CONFIG_BIAS_PULL_DOWN:
4234 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
4235 case PIN_CONFIG_BIAS_BUS_HOLD:
4236 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
4237 return -ENOTSUPP;
4238
4239 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
4240 return -EINVAL;
4241
4242 arg = 1;
4243 break;
4244 case PIN_CONFIG_LEVEL:
4245 rc = rockchip_get_mux(bank, pin - bank->pin_base);
4246 if (rc != RK_FUNC_GPIO)
4247 return -EINVAL;
4248
4249 if (!gpio || !gpio->get) {
4250 arg = 0;
4251 break;
4252 }
4253
4254 rc = gpio->get(gpio, pin - bank->pin_base);
4255 if (rc < 0)
4256 return rc;
4257
4258 arg = rc ? 1 : 0;
4259 break;
4260 case PIN_CONFIG_DRIVE_STRENGTH:
4261 /* rk3288 is the first with per-pin drive-strength */
4262 if (!info->ctrl->drv_calc_reg)
4263 return -ENOTSUPP;
4264
4265 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
4266 if (rc < 0)
4267 return rc;
4268
4269 arg = rc;
4270 break;
4271 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4272 if (!info->ctrl->schmitt_calc_reg)
4273 return -ENOTSUPP;
4274
4275 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
4276 if (rc < 0)
4277 return rc;
4278
4279 arg = rc;
4280 break;
4281 default:
4282 return -ENOTSUPP;
4283 break;
4284 }
4285
4286 *config = pinconf_to_config_packed(param, arg);
4287
4288 return 0;
4289 }
4290
4291 static const struct pinconf_ops rockchip_pinconf_ops = {
4292 .pin_config_get = rockchip_pinconf_get,
4293 .pin_config_set = rockchip_pinconf_set,
4294 .is_generic = true,
4295 };
4296
4297 static const struct of_device_id rockchip_bank_match[] = {
4298 { .compatible = "rockchip,gpio-bank" },
4299 { .compatible = "rockchip,rk3188-gpio-bank0" },
4300 {},
4301 };
4302
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)4303 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
4304 struct device_node *np)
4305 {
4306 struct device_node *child;
4307
4308 for_each_child_of_node(np, child) {
4309 if (of_match_node(rockchip_bank_match, child))
4310 continue;
4311
4312 info->nfunctions++;
4313 info->ngroups += of_get_child_count(child);
4314 }
4315 }
4316
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)4317 static int rockchip_pinctrl_parse_groups(struct device_node *np,
4318 struct rockchip_pin_group *grp,
4319 struct rockchip_pinctrl *info,
4320 u32 index)
4321 {
4322 struct device *dev = info->dev;
4323 struct rockchip_pin_bank *bank;
4324 int size;
4325 const __be32 *list;
4326 int num;
4327 int i, j;
4328 int ret;
4329
4330 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
4331
4332 /* Initialise group */
4333 grp->name = np->name;
4334
4335 /*
4336 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
4337 * do sanity check and calculate pins number
4338 */
4339 list = of_get_property(np, "rockchip,pins", &size);
4340 /* we do not check return since it's safe node passed down */
4341 size /= sizeof(*list);
4342 if (!size || size % 4)
4343 return dev_err_probe(dev, -EINVAL,
4344 "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n",
4345 np, size);
4346
4347 grp->npins = size / 4;
4348
4349 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
4350 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
4351 if (!grp->pins || !grp->data)
4352 return -ENOMEM;
4353
4354 for (i = 0, j = 0; i < size; i += 4, j++) {
4355 const __be32 *phandle;
4356 struct device_node *np_config;
4357
4358 num = be32_to_cpu(*list++);
4359 bank = bank_num_to_bank(info, num);
4360 if (IS_ERR(bank))
4361 return PTR_ERR(bank);
4362
4363 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
4364 grp->data[j].func = be32_to_cpu(*list++);
4365
4366 phandle = list++;
4367 if (!phandle)
4368 return -EINVAL;
4369
4370 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
4371 ret = pinconf_generic_parse_dt_config(np_config, NULL,
4372 &grp->data[j].configs, &grp->data[j].nconfigs);
4373 of_node_put(np_config);
4374 if (ret)
4375 return ret;
4376 }
4377
4378 return 0;
4379 }
4380
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)4381 static int rockchip_pinctrl_parse_functions(struct device_node *np,
4382 struct rockchip_pinctrl *info,
4383 u32 index)
4384 {
4385 struct device *dev = info->dev;
4386 struct rockchip_pmx_func *func;
4387 struct rockchip_pin_group *grp;
4388 int ret;
4389 static u32 grp_index;
4390 u32 i = 0;
4391
4392 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
4393
4394 func = &info->functions[index];
4395
4396 /* Initialise function */
4397 func->name = np->name;
4398 func->ngroups = of_get_child_count(np);
4399 if (func->ngroups <= 0)
4400 return 0;
4401
4402 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
4403 if (!func->groups)
4404 return -ENOMEM;
4405
4406 for_each_child_of_node_scoped(np, child) {
4407 func->groups[i] = child->name;
4408 grp = &info->groups[grp_index++];
4409 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
4410 if (ret)
4411 return ret;
4412 }
4413
4414 return 0;
4415 }
4416
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)4417 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
4418 struct rockchip_pinctrl *info)
4419 {
4420 struct device *dev = &pdev->dev;
4421 struct device_node *np = dev->of_node;
4422 int ret;
4423 int i;
4424
4425 rockchip_pinctrl_child_count(info, np);
4426
4427 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
4428 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
4429
4430 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
4431 if (!info->functions)
4432 return -ENOMEM;
4433
4434 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
4435 if (!info->groups)
4436 return -ENOMEM;
4437
4438 i = 0;
4439
4440 for_each_child_of_node_scoped(np, child) {
4441 if (of_match_node(rockchip_bank_match, child))
4442 continue;
4443
4444 ret = rockchip_pinctrl_parse_functions(child, info, i++);
4445 if (ret) {
4446 dev_err(dev, "failed to parse function\n");
4447 return ret;
4448 }
4449 }
4450
4451 return 0;
4452 }
4453
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)4454 static int rockchip_pinctrl_register(struct platform_device *pdev,
4455 struct rockchip_pinctrl *info)
4456 {
4457 struct pinctrl_desc *ctrldesc = &info->pctl;
4458 struct pinctrl_pin_desc *pindesc, *pdesc;
4459 struct rockchip_pin_bank *pin_bank;
4460 struct device *dev = &pdev->dev;
4461 char **pin_names;
4462 int pin, bank, ret;
4463 int k;
4464
4465 ctrldesc->name = "rockchip-pinctrl";
4466 ctrldesc->owner = THIS_MODULE;
4467 ctrldesc->pctlops = &rockchip_pctrl_ops;
4468 ctrldesc->pmxops = &rockchip_pmx_ops;
4469 ctrldesc->confops = &rockchip_pinconf_ops;
4470
4471 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
4472 if (!pindesc)
4473 return -ENOMEM;
4474
4475 ctrldesc->pins = pindesc;
4476 ctrldesc->npins = info->ctrl->nr_pins;
4477
4478 pdesc = pindesc;
4479 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
4480 pin_bank = &info->ctrl->pin_banks[bank];
4481
4482 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
4483 if (IS_ERR(pin_names))
4484 return PTR_ERR(pin_names);
4485
4486 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
4487 pdesc->number = k;
4488 pdesc->name = pin_names[pin];
4489 pdesc++;
4490 }
4491
4492 INIT_LIST_HEAD(&pin_bank->deferred_pins);
4493 mutex_init(&pin_bank->deferred_lock);
4494 }
4495
4496 ret = rockchip_pinctrl_parse_dt(pdev, info);
4497 if (ret)
4498 return ret;
4499
4500 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
4501 if (IS_ERR(info->pctl_dev))
4502 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
4503
4504 return 0;
4505 }
4506
4507 static const struct of_device_id rockchip_pinctrl_dt_match[];
4508
4509 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)4510 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
4511 struct rockchip_pinctrl *d,
4512 struct platform_device *pdev)
4513 {
4514 struct device *dev = &pdev->dev;
4515 struct device_node *node = dev->of_node;
4516 const struct of_device_id *match;
4517 struct rockchip_pin_ctrl *ctrl;
4518 struct rockchip_pin_bank *bank;
4519 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
4520
4521 match = of_match_node(rockchip_pinctrl_dt_match, node);
4522 ctrl = (struct rockchip_pin_ctrl *)match->data;
4523
4524 grf_offs = ctrl->grf_mux_offset;
4525 pmu_offs = ctrl->pmu_mux_offset;
4526 drv_pmu_offs = ctrl->pmu_drv_offset;
4527 drv_grf_offs = ctrl->grf_drv_offset;
4528
4529 /*
4530 * This function mutates the static per-SoC data. Most of it is
4531 * idempotent: recalculated iomux and drv offsets anchor at the
4532 * values calculated by a previous run. The pin count is not, so
4533 * reset it here; otherwise it accumulates when the probe runs
4534 * again after a probe deferral, shifting every bank's pin_base.
4535 */
4536 ctrl->nr_pins = 0;
4537
4538 bank = ctrl->pin_banks;
4539 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
4540 int bank_pins = 0;
4541
4542 raw_spin_lock_init(&bank->slock);
4543 bank->drvdata = d;
4544 bank->pin_base = ctrl->nr_pins;
4545 ctrl->nr_pins += bank->nr_pins;
4546
4547 /* calculate iomux and drv offsets */
4548 for (j = 0; j < 4; j++) {
4549 struct rockchip_iomux *iom = &bank->iomux[j];
4550 struct rockchip_drv *drv = &bank->drv[j];
4551 int inc;
4552
4553 if (bank_pins >= bank->nr_pins)
4554 break;
4555
4556 /* preset iomux offset value, set new start value */
4557 if (iom->offset >= 0) {
4558 if ((iom->type & IOMUX_SOURCE_PMU) ||
4559 (iom->type & IOMUX_L_SOURCE_PMU))
4560 pmu_offs = iom->offset;
4561 else
4562 grf_offs = iom->offset;
4563 } else { /* set current iomux offset */
4564 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
4565 (iom->type & IOMUX_L_SOURCE_PMU)) ?
4566 pmu_offs : grf_offs;
4567 }
4568
4569 /* preset drv offset value, set new start value */
4570 if (drv->offset >= 0) {
4571 if (iom->type & IOMUX_SOURCE_PMU)
4572 drv_pmu_offs = drv->offset;
4573 else
4574 drv_grf_offs = drv->offset;
4575 } else { /* set current drv offset */
4576 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
4577 drv_pmu_offs : drv_grf_offs;
4578 }
4579
4580 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
4581 i, j, iom->offset, drv->offset);
4582
4583 /*
4584 * Increase offset according to iomux width.
4585 * 4bit iomux'es are spread over two registers.
4586 */
4587 inc = (iom->type & (IOMUX_WIDTH_4BIT |
4588 IOMUX_WIDTH_3BIT |
4589 IOMUX_WIDTH_2BIT)) ? 8 : 4;
4590 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
4591 pmu_offs += inc;
4592 else
4593 grf_offs += inc;
4594
4595 /*
4596 * Increase offset according to drv width.
4597 * 3bit drive-strenth'es are spread over two registers.
4598 */
4599 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
4600 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
4601 inc = 8;
4602 else
4603 inc = 4;
4604
4605 if (iom->type & IOMUX_SOURCE_PMU)
4606 drv_pmu_offs += inc;
4607 else
4608 drv_grf_offs += inc;
4609
4610 bank_pins += 8;
4611 }
4612 }
4613
4614 return ctrl;
4615 }
4616
iomux_recalced_routes_init(struct rockchip_pinctrl * info)4617 static void iomux_recalced_routes_init(struct rockchip_pinctrl *info)
4618 {
4619 struct rockchip_pin_ctrl *ctrl = info->ctrl;
4620 struct rockchip_pin_bank *bank = ctrl->pin_banks;
4621 int i, j;
4622
4623 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
4624 /* calculate the per-bank recalced_mask */
4625 for (j = 0; j < ctrl->niomux_recalced; j++) {
4626 int pin = 0;
4627
4628 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
4629 pin = ctrl->iomux_recalced[j].pin;
4630 bank->recalced_mask |= BIT(pin);
4631 }
4632 }
4633
4634 /* calculate the per-bank route_mask */
4635 for (j = 0; j < ctrl->niomux_routes; j++) {
4636 int pin = 0;
4637
4638 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
4639 pin = ctrl->iomux_routes[j].pin;
4640 bank->route_mask |= BIT(pin);
4641 }
4642 }
4643 }
4644 }
4645
4646 #define RK3288_GRF_GPIO6C_IOMUX 0x64
4647 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
4648
4649 static u32 rk3288_grf_gpio6c_iomux;
4650
rockchip_pinctrl_suspend(struct device * dev)4651 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
4652 {
4653 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4654 int ret = pinctrl_force_sleep(info->pctl_dev);
4655
4656 if (ret)
4657 return ret;
4658
4659 /*
4660 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
4661 * the setting here, and restore it at resume.
4662 */
4663 if (info->ctrl->type == RK3288) {
4664 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4665 &rk3288_grf_gpio6c_iomux);
4666 if (ret) {
4667 pinctrl_force_default(info->pctl_dev);
4668 return ret;
4669 }
4670 }
4671
4672 return 0;
4673 }
4674
rockchip_pinctrl_resume(struct device * dev)4675 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
4676 {
4677 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4678 int ret;
4679
4680 if (info->ctrl->type == RK3288) {
4681 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4682 rk3288_grf_gpio6c_iomux |
4683 GPIO6C6_SEL_WRITE_ENABLE);
4684 if (ret)
4685 return ret;
4686 }
4687
4688 return pinctrl_force_default(info->pctl_dev);
4689 }
4690
4691 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
4692 rockchip_pinctrl_resume);
4693
4694 #define RK3308B_GRF_SOC_CON13 0x608
4695 #define RK3308B_GRF_SOC_CON15 0x610
4696
4697 /* RK3308B_GRF_SOC_CON13 */
4698 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
4699 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
4700 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
4701
4702 /* RK3308B_GRF_SOC_CON15 */
4703 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
4704 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
4705 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
4706
4707 /*
4708 * RK3308B has 3-bit gpio##_sel_plus iomuxes over some 2-bit old ones.
4709 * Enable them by setting the gpio##_sel_src_ctrl registers.
4710 */
rk3308b_soc_sel_src_init(struct rockchip_pinctrl * info)4711 static int rk3308b_soc_sel_src_init(struct rockchip_pinctrl *info)
4712 {
4713 int ret;
4714
4715 ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13,
4716 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL |
4717 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL |
4718 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL);
4719 if (ret)
4720 return ret;
4721
4722 return regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15,
4723 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL |
4724 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL |
4725 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL);
4726 }
4727
4728 #define RK3308_GRF_CHIP_ID 0x800
4729
rk3308_soc_data_init(struct rockchip_pinctrl * info)4730 static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
4731 {
4732 struct rockchip_pin_ctrl *ctrl = info->ctrl;
4733 unsigned int chip_id;
4734 int ret;
4735
4736 ret = regmap_read(info->regmap_base, RK3308_GRF_CHIP_ID, &chip_id);
4737 if (ret)
4738 return ret;
4739
4740 switch (chip_id) {
4741 case 0xcea:
4742 /* Original RK3308, no changes needed */
4743 break;
4744 case 0x3308:
4745 case 0x3308c:
4746 ctrl->type = RK3308B;
4747 ctrl->iomux_recalced = rk3308b_mux_recalced_data;
4748 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data);
4749 ctrl->iomux_routes = rk3308b_mux_route_data;
4750 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data);
4751
4752 ret = rk3308b_soc_sel_src_init(info);
4753 if (ret)
4754 return ret;
4755 break;
4756 default:
4757 return dev_err_probe(info->dev, -EINVAL,
4758 "Unknown RK3308 chip_id: 0x%x\n", chip_id);
4759 }
4760
4761 return 0;
4762 }
4763
rockchip_pinctrl_probe(struct platform_device * pdev)4764 static int rockchip_pinctrl_probe(struct platform_device *pdev)
4765 {
4766 struct rockchip_pinctrl *info;
4767 struct device *dev = &pdev->dev;
4768 struct device_node *np = dev->of_node, *node;
4769 struct rockchip_pin_ctrl *ctrl;
4770 struct resource *res;
4771 void __iomem *base;
4772 int ret;
4773 int i;
4774
4775 if (!dev->of_node)
4776 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
4777
4778 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
4779 if (!info)
4780 return -ENOMEM;
4781
4782 info->dev = dev;
4783
4784 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
4785 if (!ctrl)
4786 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
4787 info->ctrl = ctrl;
4788
4789 node = of_parse_phandle(np, "rockchip,grf", 0);
4790 if (node) {
4791 info->regmap_base = syscon_node_to_regmap(node);
4792 of_node_put(node);
4793 if (IS_ERR(info->regmap_base))
4794 return PTR_ERR(info->regmap_base);
4795 } else {
4796 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
4797 if (IS_ERR(base))
4798 return PTR_ERR(base);
4799
4800 rockchip_regmap_config.max_register = resource_size(res) - 4;
4801 rockchip_regmap_config.name = "rockchip,pinctrl";
4802 info->regmap_base =
4803 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4804
4805 /* to check for the old dt-bindings */
4806 info->reg_size = resource_size(res);
4807
4808 /* Honor the old binding, with pull registers as 2nd resource */
4809 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
4810 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
4811 if (IS_ERR(base))
4812 return PTR_ERR(base);
4813
4814 rockchip_regmap_config.max_register = resource_size(res) - 4;
4815 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
4816 info->regmap_pull =
4817 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4818 }
4819 }
4820
4821 /* try to find the optional reference to the pmu syscon */
4822 info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu");
4823
4824 /* try to find the optional reference to the ioc1 syscon */
4825 info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1");
4826
4827 if (ctrl->type == RK3308) {
4828 ret = rk3308_soc_data_init(info);
4829 if (ret)
4830 return ret;
4831 }
4832
4833 iomux_recalced_routes_init(info);
4834
4835 /*
4836 * On SoCs where each GPIO bank has its own IOC block, the bank nodes
4837 * carry a rockchip,grf phandle pointing at it. The bank number comes
4838 * from the gpio alias, as used by the gpio driver, falling back to
4839 * the node position for devicetrees without aliases. The fallback is
4840 * wrong when an SoC variant omits a bank, so aliases are needed
4841 * there.
4842 */
4843 i = 0;
4844 for_each_child_of_node_scoped(np, child) {
4845 struct rockchip_pin_bank *bank = NULL;
4846 int id, j;
4847
4848 if (!of_match_node(rockchip_bank_match, child))
4849 continue;
4850
4851 id = of_alias_get_id(child, "gpio");
4852 if (id < 0)
4853 id = i;
4854 i++;
4855
4856 for (j = 0; j < ctrl->nr_banks; j++) {
4857 if (ctrl->pin_banks[j].bank_num == id) {
4858 bank = &ctrl->pin_banks[j];
4859 break;
4860 }
4861 }
4862 if (!bank)
4863 continue;
4864
4865 bank->regmap_ioc = syscon_regmap_lookup_by_phandle_optional(
4866 child, "rockchip,grf");
4867 if (IS_ERR(bank->regmap_ioc))
4868 return dev_err_probe(dev, PTR_ERR(bank->regmap_ioc),
4869 "%pOFn: failed to look up bank ioc\n",
4870 child);
4871 }
4872
4873 ret = rockchip_pinctrl_register(pdev, info);
4874 if (ret)
4875 return ret;
4876
4877 platform_set_drvdata(pdev, info);
4878
4879 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
4880 if (ret)
4881 return dev_err_probe(dev, ret, "failed to register gpio device\n");
4882
4883 return 0;
4884 }
4885
rockchip_pinctrl_remove(struct platform_device * pdev)4886 static void rockchip_pinctrl_remove(struct platform_device *pdev)
4887 {
4888 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
4889 struct rockchip_pin_bank *bank;
4890 struct rockchip_pin_deferred *cfg;
4891 int i;
4892
4893 of_platform_depopulate(&pdev->dev);
4894
4895 for (i = 0; i < info->ctrl->nr_banks; i++) {
4896 bank = &info->ctrl->pin_banks[i];
4897
4898 mutex_lock(&bank->deferred_lock);
4899 while (!list_empty(&bank->deferred_pins)) {
4900 cfg = list_first_entry(&bank->deferred_pins,
4901 struct rockchip_pin_deferred, head);
4902 list_del(&cfg->head);
4903 kfree(cfg);
4904 }
4905 mutex_unlock(&bank->deferred_lock);
4906 }
4907 }
4908
4909 static struct rockchip_pin_bank px30_pin_banks[] = {
4910 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4911 IOMUX_SOURCE_PMU,
4912 IOMUX_SOURCE_PMU,
4913 IOMUX_SOURCE_PMU
4914 ),
4915 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4916 IOMUX_WIDTH_4BIT,
4917 IOMUX_WIDTH_4BIT,
4918 IOMUX_WIDTH_4BIT
4919 ),
4920 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4921 IOMUX_WIDTH_4BIT,
4922 IOMUX_WIDTH_4BIT,
4923 IOMUX_WIDTH_4BIT
4924 ),
4925 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4926 IOMUX_WIDTH_4BIT,
4927 IOMUX_WIDTH_4BIT,
4928 IOMUX_WIDTH_4BIT
4929 ),
4930 };
4931
4932 static struct rockchip_pin_ctrl px30_pin_ctrl = {
4933 .pin_banks = px30_pin_banks,
4934 .nr_banks = ARRAY_SIZE(px30_pin_banks),
4935 .label = "PX30-GPIO",
4936 .type = PX30,
4937 .grf_mux_offset = 0x0,
4938 .pmu_mux_offset = 0x0,
4939 .iomux_routes = px30_mux_route_data,
4940 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
4941 .pull_calc_reg = px30_calc_pull_reg_and_bit,
4942 .drv_calc_reg = px30_calc_drv_reg_and_bit,
4943 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
4944 };
4945
4946 static struct rockchip_pin_bank rv1103b_pin_banks[] = {
4947 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
4948 IOMUX_WIDTH_4BIT,
4949 IOMUX_WIDTH_4BIT,
4950 IOMUX_WIDTH_4BIT,
4951 IOMUX_WIDTH_4BIT,
4952 0x40000, 0x50008, 0x50010, 0x50018,
4953 DRV_TYPE_IO_LEVEL_8_BIT,
4954 DRV_TYPE_IO_LEVEL_8_BIT,
4955 DRV_TYPE_IO_LEVEL_8_BIT,
4956 DRV_TYPE_IO_LEVEL_8_BIT),
4957 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
4958 IOMUX_WIDTH_4BIT,
4959 IOMUX_WIDTH_4BIT,
4960 IOMUX_WIDTH_4BIT,
4961 IOMUX_WIDTH_4BIT,
4962 0x20, 0x10028, 0x10030, 0x10038,
4963 DRV_TYPE_IO_LEVEL_8_BIT,
4964 DRV_TYPE_IO_LEVEL_8_BIT,
4965 DRV_TYPE_IO_LEVEL_8_BIT,
4966 DRV_TYPE_IO_LEVEL_8_BIT),
4967 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
4968 IOMUX_WIDTH_4BIT,
4969 IOMUX_WIDTH_4BIT,
4970 IOMUX_WIDTH_4BIT,
4971 IOMUX_WIDTH_4BIT,
4972 0x30040, 0x30048, 0x30050, 0x30058,
4973 DRV_TYPE_IO_LEVEL_8_BIT,
4974 DRV_TYPE_IO_LEVEL_8_BIT,
4975 DRV_TYPE_IO_LEVEL_8_BIT,
4976 DRV_TYPE_IO_LEVEL_8_BIT),
4977 };
4978
4979 static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
4980 .pin_banks = rv1103b_pin_banks,
4981 .nr_banks = ARRAY_SIZE(rv1103b_pin_banks),
4982 .label = "RV1103B-GPIO",
4983 .type = RV1103B,
4984 .iomux_recalced = rv1103b_mux_recalced_data,
4985 .niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data),
4986 .pull_calc_reg = rv1103b_calc_pull_reg_and_bit,
4987 .drv_calc_reg = rv1103b_calc_drv_reg_and_bit,
4988 .schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit,
4989 };
4990
4991 static struct rockchip_pin_bank rv1106_pin_banks[] = {
4992 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
4993 IOMUX_WIDTH_4BIT,
4994 IOMUX_WIDTH_4BIT,
4995 IOMUX_WIDTH_4BIT,
4996 IOMUX_WIDTH_4BIT,
4997 0, -1, -1, -1,
4998 DRV_TYPE_IO_LEVEL_8_BIT,
4999 DRV_TYPE_IO_LEVEL_8_BIT,
5000 DRV_TYPE_IO_LEVEL_8_BIT,
5001 DRV_TYPE_IO_LEVEL_8_BIT),
5002 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
5003 IOMUX_WIDTH_4BIT,
5004 IOMUX_WIDTH_4BIT,
5005 IOMUX_WIDTH_4BIT,
5006 IOMUX_WIDTH_4BIT,
5007 0, -1, -1, -1,
5008 DRV_TYPE_IO_LEVEL_8_BIT,
5009 DRV_TYPE_IO_LEVEL_8_BIT,
5010 DRV_TYPE_IO_LEVEL_8_BIT,
5011 DRV_TYPE_IO_LEVEL_8_BIT),
5012 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
5013 IOMUX_WIDTH_4BIT,
5014 IOMUX_WIDTH_4BIT,
5015 IOMUX_WIDTH_4BIT,
5016 IOMUX_WIDTH_4BIT,
5017 0x20, -1, -1, -1,
5018 DRV_TYPE_IO_LEVEL_8_BIT,
5019 DRV_TYPE_IO_LEVEL_8_BIT,
5020 DRV_TYPE_IO_LEVEL_8_BIT,
5021 DRV_TYPE_IO_LEVEL_8_BIT),
5022 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3",
5023 IOMUX_WIDTH_4BIT,
5024 IOMUX_WIDTH_4BIT,
5025 IOMUX_WIDTH_4BIT,
5026 IOMUX_WIDTH_4BIT,
5027 0x40, -1, -1, -1,
5028 DRV_TYPE_IO_LEVEL_8_BIT,
5029 DRV_TYPE_IO_LEVEL_8_BIT,
5030 DRV_TYPE_IO_LEVEL_8_BIT,
5031 DRV_TYPE_IO_LEVEL_8_BIT),
5032 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(4, 24, "gpio4",
5033 IOMUX_WIDTH_4BIT,
5034 IOMUX_WIDTH_4BIT,
5035 IOMUX_WIDTH_4BIT,
5036 0,
5037 0, -1, -1, -1,
5038 DRV_TYPE_IO_LEVEL_8_BIT,
5039 DRV_TYPE_IO_LEVEL_8_BIT,
5040 DRV_TYPE_IO_LEVEL_8_BIT,
5041 DRV_TYPE_IO_LEVEL_8_BIT),
5042 };
5043
5044 static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
5045 .pin_banks = rv1106_pin_banks,
5046 .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
5047 .label = "RV1106-GPIO",
5048 .type = RV1106,
5049 .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
5050 .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
5051 .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
5052 };
5053
5054 static struct rockchip_pin_bank rv1108_pin_banks[] = {
5055 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
5056 IOMUX_SOURCE_PMU,
5057 IOMUX_SOURCE_PMU,
5058 IOMUX_SOURCE_PMU),
5059 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
5060 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
5061 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
5062 };
5063
5064 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
5065 .pin_banks = rv1108_pin_banks,
5066 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
5067 .label = "RV1108-GPIO",
5068 .type = RV1108,
5069 .grf_mux_offset = 0x10,
5070 .pmu_mux_offset = 0x0,
5071 .iomux_recalced = rv1108_mux_recalced_data,
5072 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
5073 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
5074 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
5075 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
5076 };
5077
5078 static struct rockchip_pin_bank rv1126_pin_banks[] = {
5079 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
5080 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5081 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5082 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
5083 IOMUX_WIDTH_4BIT),
5084 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
5085 IOMUX_WIDTH_4BIT,
5086 IOMUX_WIDTH_4BIT,
5087 IOMUX_WIDTH_4BIT,
5088 IOMUX_WIDTH_4BIT,
5089 0x10010, 0x10018, 0x10020, 0x10028),
5090 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
5091 IOMUX_WIDTH_4BIT,
5092 IOMUX_WIDTH_4BIT,
5093 IOMUX_WIDTH_4BIT,
5094 IOMUX_WIDTH_4BIT),
5095 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
5096 IOMUX_WIDTH_4BIT,
5097 IOMUX_WIDTH_4BIT,
5098 IOMUX_WIDTH_4BIT,
5099 IOMUX_WIDTH_4BIT),
5100 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
5101 IOMUX_WIDTH_4BIT, 0, 0, 0),
5102 };
5103
5104 static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
5105 .pin_banks = rv1126_pin_banks,
5106 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
5107 .label = "RV1126-GPIO",
5108 .type = RV1126,
5109 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
5110 .pmu_mux_offset = 0x0,
5111 .iomux_routes = rv1126_mux_route_data,
5112 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
5113 .iomux_recalced = rv1126_mux_recalced_data,
5114 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
5115 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
5116 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
5117 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
5118 };
5119
5120 static struct rockchip_pin_bank rk2928_pin_banks[] = {
5121 PIN_BANK(0, 32, "gpio0"),
5122 PIN_BANK(1, 32, "gpio1"),
5123 PIN_BANK(2, 32, "gpio2"),
5124 PIN_BANK(3, 32, "gpio3"),
5125 };
5126
5127 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
5128 .pin_banks = rk2928_pin_banks,
5129 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
5130 .label = "RK2928-GPIO",
5131 .type = RK2928,
5132 .grf_mux_offset = 0xa8,
5133 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
5134 };
5135
5136 static struct rockchip_pin_bank rk3036_pin_banks[] = {
5137 PIN_BANK(0, 32, "gpio0"),
5138 PIN_BANK(1, 32, "gpio1"),
5139 PIN_BANK(2, 32, "gpio2"),
5140 };
5141
5142 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
5143 .pin_banks = rk3036_pin_banks,
5144 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
5145 .label = "RK3036-GPIO",
5146 .type = RK2928,
5147 .grf_mux_offset = 0xa8,
5148 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
5149 };
5150
5151 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
5152 PIN_BANK(0, 32, "gpio0"),
5153 PIN_BANK(1, 32, "gpio1"),
5154 PIN_BANK(2, 32, "gpio2"),
5155 PIN_BANK(3, 32, "gpio3"),
5156 PIN_BANK(4, 32, "gpio4"),
5157 PIN_BANK(6, 16, "gpio6"),
5158 };
5159
5160 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
5161 .pin_banks = rk3066a_pin_banks,
5162 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
5163 .label = "RK3066a-GPIO",
5164 .type = RK2928,
5165 .grf_mux_offset = 0xa8,
5166 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
5167 };
5168
5169 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
5170 PIN_BANK(0, 32, "gpio0"),
5171 PIN_BANK(1, 32, "gpio1"),
5172 PIN_BANK(2, 32, "gpio2"),
5173 PIN_BANK(3, 32, "gpio3"),
5174 };
5175
5176 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
5177 .pin_banks = rk3066b_pin_banks,
5178 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
5179 .label = "RK3066b-GPIO",
5180 .type = RK3066B,
5181 .grf_mux_offset = 0x60,
5182 };
5183
5184 static struct rockchip_pin_bank rk3128_pin_banks[] = {
5185 PIN_BANK(0, 32, "gpio0"),
5186 PIN_BANK(1, 32, "gpio1"),
5187 PIN_BANK(2, 32, "gpio2"),
5188 PIN_BANK(3, 32, "gpio3"),
5189 };
5190
5191 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
5192 .pin_banks = rk3128_pin_banks,
5193 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
5194 .label = "RK3128-GPIO",
5195 .type = RK3128,
5196 .grf_mux_offset = 0xa8,
5197 .iomux_recalced = rk3128_mux_recalced_data,
5198 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
5199 .iomux_routes = rk3128_mux_route_data,
5200 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
5201 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
5202 };
5203
5204 static struct rockchip_pin_bank rk3188_pin_banks[] = {
5205 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
5206 PIN_BANK(1, 32, "gpio1"),
5207 PIN_BANK(2, 32, "gpio2"),
5208 PIN_BANK(3, 32, "gpio3"),
5209 };
5210
5211 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
5212 .pin_banks = rk3188_pin_banks,
5213 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
5214 .label = "RK3188-GPIO",
5215 .type = RK3188,
5216 .grf_mux_offset = 0x60,
5217 .iomux_routes = rk3188_mux_route_data,
5218 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
5219 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
5220 };
5221
5222 static struct rockchip_pin_bank rk3228_pin_banks[] = {
5223 PIN_BANK(0, 32, "gpio0"),
5224 PIN_BANK(1, 32, "gpio1"),
5225 PIN_BANK(2, 32, "gpio2"),
5226 PIN_BANK(3, 32, "gpio3"),
5227 };
5228
5229 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
5230 .pin_banks = rk3228_pin_banks,
5231 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
5232 .label = "RK3228-GPIO",
5233 .type = RK3288,
5234 .grf_mux_offset = 0x0,
5235 .iomux_routes = rk3228_mux_route_data,
5236 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
5237 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
5238 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
5239 };
5240
5241 static struct rockchip_pin_bank rk3288_pin_banks[] = {
5242 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
5243 IOMUX_SOURCE_PMU,
5244 IOMUX_SOURCE_PMU,
5245 IOMUX_UNROUTED
5246 ),
5247 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
5248 IOMUX_UNROUTED,
5249 IOMUX_UNROUTED,
5250 0
5251 ),
5252 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
5253 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
5254 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
5255 IOMUX_WIDTH_4BIT,
5256 0,
5257 0
5258 ),
5259 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
5260 0,
5261 0,
5262 IOMUX_UNROUTED
5263 ),
5264 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
5265 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
5266 0,
5267 IOMUX_WIDTH_4BIT,
5268 IOMUX_UNROUTED
5269 ),
5270 PIN_BANK(8, 16, "gpio8"),
5271 };
5272
5273 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
5274 .pin_banks = rk3288_pin_banks,
5275 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
5276 .label = "RK3288-GPIO",
5277 .type = RK3288,
5278 .grf_mux_offset = 0x0,
5279 .pmu_mux_offset = 0x84,
5280 .iomux_routes = rk3288_mux_route_data,
5281 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
5282 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
5283 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
5284 };
5285
5286 static struct rockchip_pin_bank rk3308_pin_banks[] = {
5287 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
5288 IOMUX_WIDTH_2BIT,
5289 IOMUX_WIDTH_2BIT,
5290 IOMUX_WIDTH_2BIT),
5291 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
5292 IOMUX_WIDTH_2BIT,
5293 IOMUX_WIDTH_2BIT,
5294 IOMUX_WIDTH_2BIT),
5295 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
5296 IOMUX_WIDTH_2BIT,
5297 IOMUX_WIDTH_2BIT,
5298 IOMUX_WIDTH_2BIT),
5299 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
5300 IOMUX_WIDTH_2BIT,
5301 IOMUX_WIDTH_2BIT,
5302 IOMUX_WIDTH_2BIT),
5303 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
5304 IOMUX_WIDTH_2BIT,
5305 IOMUX_WIDTH_2BIT,
5306 IOMUX_WIDTH_2BIT),
5307 };
5308
5309 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
5310 .pin_banks = rk3308_pin_banks,
5311 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
5312 .label = "RK3308-GPIO",
5313 .type = RK3308,
5314 .grf_mux_offset = 0x0,
5315 .iomux_recalced = rk3308_mux_recalced_data,
5316 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
5317 .iomux_routes = rk3308_mux_route_data,
5318 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
5319 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
5320 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
5321 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
5322 };
5323
5324 static struct rockchip_pin_bank rk3328_pin_banks[] = {
5325 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
5326 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
5327 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
5328 IOMUX_WIDTH_2BIT,
5329 IOMUX_WIDTH_3BIT,
5330 0),
5331 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
5332 IOMUX_WIDTH_3BIT,
5333 IOMUX_WIDTH_3BIT,
5334 0,
5335 0),
5336 };
5337
5338 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
5339 .pin_banks = rk3328_pin_banks,
5340 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
5341 .label = "RK3328-GPIO",
5342 .type = RK3328,
5343 .grf_mux_offset = 0x0,
5344 .iomux_recalced = rk3328_mux_recalced_data,
5345 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
5346 .iomux_routes = rk3328_mux_route_data,
5347 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
5348 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
5349 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
5350 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
5351 };
5352
5353 static struct rockchip_pin_bank rk3368_pin_banks[] = {
5354 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
5355 IOMUX_SOURCE_PMU,
5356 IOMUX_SOURCE_PMU,
5357 IOMUX_SOURCE_PMU
5358 ),
5359 PIN_BANK(1, 32, "gpio1"),
5360 PIN_BANK(2, 32, "gpio2"),
5361 PIN_BANK(3, 32, "gpio3"),
5362 };
5363
5364 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
5365 .pin_banks = rk3368_pin_banks,
5366 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
5367 .label = "RK3368-GPIO",
5368 .type = RK3368,
5369 .grf_mux_offset = 0x0,
5370 .pmu_mux_offset = 0x0,
5371 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
5372 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
5373 };
5374
5375 static struct rockchip_pin_bank rk3399_pin_banks[] = {
5376 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
5377 IOMUX_SOURCE_PMU,
5378 IOMUX_SOURCE_PMU,
5379 IOMUX_SOURCE_PMU,
5380 IOMUX_SOURCE_PMU,
5381 DRV_TYPE_IO_1V8_ONLY,
5382 DRV_TYPE_IO_1V8_ONLY,
5383 DRV_TYPE_IO_DEFAULT,
5384 DRV_TYPE_IO_DEFAULT,
5385 0x80,
5386 0x88,
5387 -1,
5388 -1,
5389 PULL_TYPE_IO_1V8_ONLY,
5390 PULL_TYPE_IO_1V8_ONLY,
5391 PULL_TYPE_IO_DEFAULT,
5392 PULL_TYPE_IO_DEFAULT
5393 ),
5394 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
5395 IOMUX_SOURCE_PMU,
5396 IOMUX_SOURCE_PMU,
5397 IOMUX_SOURCE_PMU,
5398 DRV_TYPE_IO_1V8_OR_3V0,
5399 DRV_TYPE_IO_1V8_OR_3V0,
5400 DRV_TYPE_IO_1V8_OR_3V0,
5401 DRV_TYPE_IO_1V8_OR_3V0,
5402 0xa0,
5403 0xa8,
5404 0xb0,
5405 0xb8
5406 ),
5407 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
5408 DRV_TYPE_IO_1V8_OR_3V0,
5409 DRV_TYPE_IO_1V8_ONLY,
5410 DRV_TYPE_IO_1V8_ONLY,
5411 PULL_TYPE_IO_DEFAULT,
5412 PULL_TYPE_IO_DEFAULT,
5413 PULL_TYPE_IO_1V8_ONLY,
5414 PULL_TYPE_IO_1V8_ONLY
5415 ),
5416 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
5417 DRV_TYPE_IO_3V3_ONLY,
5418 DRV_TYPE_IO_3V3_ONLY,
5419 DRV_TYPE_IO_1V8_OR_3V0
5420 ),
5421 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
5422 DRV_TYPE_IO_1V8_3V0_AUTO,
5423 DRV_TYPE_IO_1V8_OR_3V0,
5424 DRV_TYPE_IO_1V8_OR_3V0
5425 ),
5426 };
5427
5428 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
5429 .pin_banks = rk3399_pin_banks,
5430 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
5431 .label = "RK3399-GPIO",
5432 .type = RK3399,
5433 .grf_mux_offset = 0xe000,
5434 .pmu_mux_offset = 0x0,
5435 .grf_drv_offset = 0xe100,
5436 .pmu_drv_offset = 0x80,
5437 .iomux_routes = rk3399_mux_route_data,
5438 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
5439 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
5440 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
5441 };
5442
5443 static struct rockchip_pin_bank rk3506_pin_banks[] = {
5444 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0",
5445 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5446 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5447 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5448 IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU,
5449 0x0, 0x8, 0x10, 0x830,
5450 DRV_TYPE_IO_LEVEL_8_BIT,
5451 DRV_TYPE_IO_LEVEL_8_BIT,
5452 DRV_TYPE_IO_LEVEL_8_BIT,
5453 DRV_TYPE_IO_LEVEL_2_BIT,
5454 0, 0, 0, 1),
5455 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
5456 IOMUX_WIDTH_4BIT,
5457 IOMUX_WIDTH_4BIT,
5458 IOMUX_WIDTH_4BIT,
5459 IOMUX_WIDTH_4BIT,
5460 0x20, 0x28, 0x30, 0x38,
5461 DRV_TYPE_IO_LEVEL_8_BIT,
5462 DRV_TYPE_IO_LEVEL_8_BIT,
5463 DRV_TYPE_IO_LEVEL_8_BIT,
5464 DRV_TYPE_IO_LEVEL_8_BIT),
5465 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
5466 IOMUX_WIDTH_4BIT,
5467 IOMUX_WIDTH_4BIT,
5468 IOMUX_WIDTH_4BIT,
5469 IOMUX_WIDTH_4BIT,
5470 0x40, 0x48, 0x50, 0x58,
5471 DRV_TYPE_IO_LEVEL_8_BIT,
5472 DRV_TYPE_IO_LEVEL_8_BIT,
5473 DRV_TYPE_IO_LEVEL_8_BIT,
5474 DRV_TYPE_IO_LEVEL_8_BIT),
5475 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3",
5476 IOMUX_WIDTH_4BIT,
5477 IOMUX_WIDTH_4BIT,
5478 IOMUX_WIDTH_4BIT,
5479 IOMUX_WIDTH_4BIT,
5480 0x60, 0x68, 0x70, 0x78,
5481 DRV_TYPE_IO_LEVEL_8_BIT,
5482 DRV_TYPE_IO_LEVEL_8_BIT,
5483 DRV_TYPE_IO_LEVEL_8_BIT,
5484 DRV_TYPE_IO_LEVEL_8_BIT),
5485 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4",
5486 IOMUX_WIDTH_4BIT,
5487 IOMUX_WIDTH_4BIT,
5488 IOMUX_WIDTH_4BIT,
5489 IOMUX_WIDTH_4BIT,
5490 0x80, 0x88, 0x90, 0x98,
5491 DRV_TYPE_IO_LEVEL_2_BIT,
5492 DRV_TYPE_IO_LEVEL_2_BIT,
5493 DRV_TYPE_IO_LEVEL_2_BIT,
5494 DRV_TYPE_IO_LEVEL_2_BIT,
5495 1, 1, 1, 1),
5496 };
5497
5498 static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = {
5499 .pin_banks = rk3506_pin_banks,
5500 .nr_banks = ARRAY_SIZE(rk3506_pin_banks),
5501 .label = "RK3506-GPIO",
5502 .type = RK3506,
5503 .pull_calc_reg = rk3506_calc_pull_reg_and_bit,
5504 .drv_calc_reg = rk3506_calc_drv_reg_and_bit,
5505 .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit,
5506 };
5507
5508 static struct rockchip_pin_bank rk3528_pin_banks[] = {
5509 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
5510 IOMUX_WIDTH_4BIT,
5511 IOMUX_WIDTH_4BIT,
5512 IOMUX_WIDTH_4BIT,
5513 IOMUX_WIDTH_4BIT,
5514 0, 0, 0, 0),
5515 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
5516 IOMUX_WIDTH_4BIT,
5517 IOMUX_WIDTH_4BIT,
5518 IOMUX_WIDTH_4BIT,
5519 IOMUX_WIDTH_4BIT,
5520 0x20020, 0x20028, 0x20030, 0x20038),
5521 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
5522 IOMUX_WIDTH_4BIT,
5523 IOMUX_WIDTH_4BIT,
5524 IOMUX_WIDTH_4BIT,
5525 IOMUX_WIDTH_4BIT,
5526 0x30040, 0, 0, 0),
5527 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
5528 IOMUX_WIDTH_4BIT,
5529 IOMUX_WIDTH_4BIT,
5530 IOMUX_WIDTH_4BIT,
5531 IOMUX_WIDTH_4BIT,
5532 0x20060, 0x20068, 0x20070, 0),
5533 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
5534 IOMUX_WIDTH_4BIT,
5535 IOMUX_WIDTH_4BIT,
5536 IOMUX_WIDTH_4BIT,
5537 IOMUX_WIDTH_4BIT,
5538 0x10080, 0x10088, 0x10090, 0x10098),
5539 };
5540
5541 static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
5542 .pin_banks = rk3528_pin_banks,
5543 .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
5544 .label = "RK3528-GPIO",
5545 .type = RK3528,
5546 .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
5547 .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
5548 .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
5549 };
5550
5551 static struct rockchip_pin_bank rk3562_pin_banks[] = {
5552 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
5553 IOMUX_WIDTH_4BIT,
5554 IOMUX_WIDTH_4BIT,
5555 IOMUX_WIDTH_4BIT,
5556 IOMUX_WIDTH_4BIT,
5557 0x20000, 0x20008, 0x20010, 0x20018),
5558 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
5559 IOMUX_WIDTH_4BIT,
5560 IOMUX_WIDTH_4BIT,
5561 IOMUX_WIDTH_4BIT,
5562 IOMUX_WIDTH_4BIT,
5563 0, 0x08, 0x10, 0x18),
5564 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
5565 IOMUX_WIDTH_4BIT,
5566 IOMUX_WIDTH_4BIT,
5567 IOMUX_WIDTH_4BIT,
5568 IOMUX_WIDTH_4BIT,
5569 0x20, 0, 0, 0),
5570 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
5571 IOMUX_WIDTH_4BIT,
5572 IOMUX_WIDTH_4BIT,
5573 IOMUX_WIDTH_4BIT,
5574 IOMUX_WIDTH_4BIT,
5575 0x10040, 0x10048, 0x10050, 0x10058),
5576 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
5577 IOMUX_WIDTH_4BIT,
5578 IOMUX_WIDTH_4BIT,
5579 0,
5580 0,
5581 0x10060, 0x10068, 0, 0),
5582 };
5583
5584 static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
5585 .pin_banks = rk3562_pin_banks,
5586 .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
5587 .label = "RK3562-GPIO",
5588 .type = RK3562,
5589 .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
5590 .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
5591 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
5592 };
5593
5594 static struct rockchip_pin_bank rk3568_pin_banks[] = {
5595 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5596 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5597 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5598 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
5599 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
5600 IOMUX_WIDTH_4BIT,
5601 IOMUX_WIDTH_4BIT,
5602 IOMUX_WIDTH_4BIT),
5603 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
5604 IOMUX_WIDTH_4BIT,
5605 IOMUX_WIDTH_4BIT,
5606 IOMUX_WIDTH_4BIT),
5607 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
5608 IOMUX_WIDTH_4BIT,
5609 IOMUX_WIDTH_4BIT,
5610 IOMUX_WIDTH_4BIT),
5611 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
5612 IOMUX_WIDTH_4BIT,
5613 IOMUX_WIDTH_4BIT,
5614 IOMUX_WIDTH_4BIT),
5615 };
5616
5617 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
5618 .pin_banks = rk3568_pin_banks,
5619 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
5620 .label = "RK3568-GPIO",
5621 .type = RK3568,
5622 .grf_mux_offset = 0x0,
5623 .pmu_mux_offset = 0x0,
5624 .grf_drv_offset = 0x0200,
5625 .pmu_drv_offset = 0x0070,
5626 .iomux_routes = rk3568_mux_route_data,
5627 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
5628 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
5629 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
5630 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
5631 };
5632
5633 #define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
5634 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
5635 IOMUX_WIDTH_4BIT, \
5636 IOMUX_WIDTH_4BIT, \
5637 IOMUX_WIDTH_4BIT, \
5638 IOMUX_WIDTH_4BIT, \
5639 OFFSET0, OFFSET1, \
5640 OFFSET2, OFFSET3, \
5641 PULL_TYPE_IO_1V8_ONLY, \
5642 PULL_TYPE_IO_1V8_ONLY, \
5643 PULL_TYPE_IO_1V8_ONLY, \
5644 PULL_TYPE_IO_1V8_ONLY)
5645
5646 static struct rockchip_pin_bank rk3576_pin_banks[] = {
5647 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
5648 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
5649 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
5650 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
5651 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
5652 };
5653
5654 static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
5655 .pin_banks = rk3576_pin_banks,
5656 .nr_banks = ARRAY_SIZE(rk3576_pin_banks),
5657 .label = "RK3576-GPIO",
5658 .type = RK3576,
5659 .pull_calc_reg = rk3576_calc_pull_reg_and_bit,
5660 .drv_calc_reg = rk3576_calc_drv_reg_and_bit,
5661 .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
5662 };
5663
5664 static struct rockchip_pin_bank rk3588_pin_banks[] = {
5665 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
5666 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5667 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
5668 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5669 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
5670 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5671 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
5672 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5673 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
5674 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5675 };
5676
5677 static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
5678 .pin_banks = rk3588_pin_banks,
5679 .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
5680 .label = "RK3588-GPIO",
5681 .type = RK3588,
5682 .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
5683 .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
5684 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
5685 };
5686
5687 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
5688 { .compatible = "rockchip,px30-pinctrl",
5689 .data = &px30_pin_ctrl },
5690 { .compatible = "rockchip,rv1103b-pinctrl",
5691 .data = &rv1103b_pin_ctrl },
5692 { .compatible = "rockchip,rv1106-pinctrl",
5693 .data = &rv1106_pin_ctrl },
5694 { .compatible = "rockchip,rv1108-pinctrl",
5695 .data = &rv1108_pin_ctrl },
5696 { .compatible = "rockchip,rv1126-pinctrl",
5697 .data = &rv1126_pin_ctrl },
5698 { .compatible = "rockchip,rk2928-pinctrl",
5699 .data = &rk2928_pin_ctrl },
5700 { .compatible = "rockchip,rk3036-pinctrl",
5701 .data = &rk3036_pin_ctrl },
5702 { .compatible = "rockchip,rk3066a-pinctrl",
5703 .data = &rk3066a_pin_ctrl },
5704 { .compatible = "rockchip,rk3066b-pinctrl",
5705 .data = &rk3066b_pin_ctrl },
5706 { .compatible = "rockchip,rk3128-pinctrl",
5707 .data = (void *)&rk3128_pin_ctrl },
5708 { .compatible = "rockchip,rk3188-pinctrl",
5709 .data = &rk3188_pin_ctrl },
5710 { .compatible = "rockchip,rk3228-pinctrl",
5711 .data = &rk3228_pin_ctrl },
5712 { .compatible = "rockchip,rk3288-pinctrl",
5713 .data = &rk3288_pin_ctrl },
5714 { .compatible = "rockchip,rk3308-pinctrl",
5715 .data = &rk3308_pin_ctrl },
5716 { .compatible = "rockchip,rk3328-pinctrl",
5717 .data = &rk3328_pin_ctrl },
5718 { .compatible = "rockchip,rk3368-pinctrl",
5719 .data = &rk3368_pin_ctrl },
5720 { .compatible = "rockchip,rk3399-pinctrl",
5721 .data = &rk3399_pin_ctrl },
5722 { .compatible = "rockchip,rk3506-pinctrl",
5723 .data = &rk3506_pin_ctrl },
5724 { .compatible = "rockchip,rk3528-pinctrl",
5725 .data = &rk3528_pin_ctrl },
5726 { .compatible = "rockchip,rk3562-pinctrl",
5727 .data = &rk3562_pin_ctrl },
5728 { .compatible = "rockchip,rk3568-pinctrl",
5729 .data = &rk3568_pin_ctrl },
5730 { .compatible = "rockchip,rk3576-pinctrl",
5731 .data = &rk3576_pin_ctrl },
5732 { .compatible = "rockchip,rk3588-pinctrl",
5733 .data = &rk3588_pin_ctrl },
5734 {},
5735 };
5736 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
5737
5738 static struct platform_driver rockchip_pinctrl_driver = {
5739 .probe = rockchip_pinctrl_probe,
5740 .remove = rockchip_pinctrl_remove,
5741 .driver = {
5742 .name = "rockchip-pinctrl",
5743 .pm = &rockchip_pinctrl_dev_pm_ops,
5744 .of_match_table = rockchip_pinctrl_dt_match,
5745 },
5746 };
5747
rockchip_pinctrl_drv_register(void)5748 static int __init rockchip_pinctrl_drv_register(void)
5749 {
5750 return platform_driver_register(&rockchip_pinctrl_driver);
5751 }
5752 postcore_initcall(rockchip_pinctrl_drv_register);
5753
rockchip_pinctrl_drv_unregister(void)5754 static void __exit rockchip_pinctrl_drv_unregister(void)
5755 {
5756 platform_driver_unregister(&rockchip_pinctrl_driver);
5757 }
5758 module_exit(rockchip_pinctrl_drv_unregister);
5759
5760 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
5761 MODULE_LICENSE("GPL");
5762 MODULE_ALIAS("platform:pinctrl-rockchip");
5763