xref: /linux/drivers/net/ethernet/renesas/rtsn.c (revision 91ec2035134982b98fab0609a9fd8480e8217dc1)
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Renesas Ethernet-TSN device driver
4  *
5  * Copyright (C) 2022 Renesas Electronics Corporation
6  * Copyright (C) 2023 Niklas Söderlund <niklas.soderlund@ragnatech.se>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/module.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/of.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/spinlock.h>
23 
24 #include "rtsn.h"
25 #include "rcar_gen4_ptp.h"
26 
27 struct rtsn_private {
28 	struct net_device *ndev;
29 	struct platform_device *pdev;
30 	void __iomem *base;
31 	struct rcar_gen4_ptp_private *ptp_priv;
32 	struct clk *clk;
33 	struct reset_control *reset;
34 
35 	u32 num_tx_ring;
36 	u32 num_rx_ring;
37 	u32 tx_desc_bat_size;
38 	dma_addr_t tx_desc_bat_dma;
39 	struct rtsn_desc *tx_desc_bat;
40 	u32 rx_desc_bat_size;
41 	dma_addr_t rx_desc_bat_dma;
42 	struct rtsn_desc *rx_desc_bat;
43 	dma_addr_t tx_desc_dma;
44 	dma_addr_t rx_desc_dma;
45 	struct rtsn_ext_desc *tx_ring;
46 	struct rtsn_ext_ts_desc *rx_ring;
47 	struct sk_buff **tx_skb;
48 	struct sk_buff **rx_skb;
49 	spinlock_t lock;	/* Register access lock */
50 	u32 cur_tx;
51 	u32 dirty_tx;
52 	u32 cur_rx;
53 	u32 dirty_rx;
54 	u8 ts_tag;
55 	struct napi_struct napi;
56 	struct rtnl_link_stats64 stats;
57 
58 	struct mii_bus *mii;
59 	phy_interface_t iface;
60 	int link;
61 	int speed;
62 
63 	int tx_data_irq;
64 	int rx_data_irq;
65 
66 	u32 tstamp_tx_ctrl;
67 	u32 tstamp_rx_ctrl;
68 };
69 
rtsn_read(struct rtsn_private * priv,enum rtsn_reg reg)70 static u32 rtsn_read(struct rtsn_private *priv, enum rtsn_reg reg)
71 {
72 	return ioread32(priv->base + reg);
73 }
74 
rtsn_write(struct rtsn_private * priv,enum rtsn_reg reg,u32 data)75 static void rtsn_write(struct rtsn_private *priv, enum rtsn_reg reg, u32 data)
76 {
77 	iowrite32(data, priv->base + reg);
78 }
79 
rtsn_modify(struct rtsn_private * priv,enum rtsn_reg reg,u32 clear,u32 set)80 static void rtsn_modify(struct rtsn_private *priv, enum rtsn_reg reg,
81 			u32 clear, u32 set)
82 {
83 	rtsn_write(priv, reg, (rtsn_read(priv, reg) & ~clear) | set);
84 }
85 
rtsn_reg_wait(struct rtsn_private * priv,enum rtsn_reg reg,u32 mask,u32 expected)86 static int rtsn_reg_wait(struct rtsn_private *priv, enum rtsn_reg reg,
87 			 u32 mask, u32 expected)
88 {
89 	u32 val;
90 
91 	return readl_poll_timeout(priv->base + reg, val,
92 				  (val & mask) == expected,
93 				  RTSN_INTERVAL_US, RTSN_TIMEOUT_US);
94 }
95 
rtsn_ctrl_data_irq(struct rtsn_private * priv,bool enable)96 static void rtsn_ctrl_data_irq(struct rtsn_private *priv, bool enable)
97 {
98 	if (enable) {
99 		rtsn_write(priv, TDIE0, TDIE_TDID_TDX(TX_CHAIN_IDX));
100 		rtsn_write(priv, RDIE0, RDIE_RDID_RDX(RX_CHAIN_IDX));
101 	} else {
102 		rtsn_write(priv, TDID0, TDIE_TDID_TDX(TX_CHAIN_IDX));
103 		rtsn_write(priv, RDID0, RDIE_RDID_RDX(RX_CHAIN_IDX));
104 	}
105 }
106 
rtsn_tx_free(struct net_device * ndev,bool free_txed_only)107 static int rtsn_tx_free(struct net_device *ndev, bool free_txed_only)
108 {
109 	struct rtsn_private *priv = netdev_priv(ndev);
110 	struct rtsn_ext_desc *desc;
111 	struct sk_buff *skb;
112 	int free_num = 0;
113 	int entry, size;
114 
115 	for (; priv->cur_tx - priv->dirty_tx > 0; priv->dirty_tx++) {
116 		entry = priv->dirty_tx % priv->num_tx_ring;
117 		desc = &priv->tx_ring[entry];
118 		if (free_txed_only && (desc->die_dt & DT_MASK) != DT_FEMPTY)
119 			break;
120 
121 		dma_rmb();
122 		size = le16_to_cpu(desc->info_ds) & TX_DS;
123 		skb = priv->tx_skb[entry];
124 		if (skb) {
125 			if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
126 				struct skb_shared_hwtstamps shhwtstamps;
127 				struct timespec64 ts;
128 
129 				rcar_gen4_ptp_gettime64(priv->ptp_priv, &ts);
130 				memset(&shhwtstamps, 0, sizeof(shhwtstamps));
131 				shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
132 				skb_tstamp_tx(skb, &shhwtstamps);
133 			}
134 			dma_unmap_single(ndev->dev.parent,
135 					 le32_to_cpu(desc->dptr),
136 					 size, DMA_TO_DEVICE);
137 			dev_kfree_skb_any(priv->tx_skb[entry]);
138 			free_num++;
139 
140 			priv->stats.tx_packets++;
141 			priv->stats.tx_bytes += size;
142 		}
143 
144 		desc->die_dt = DT_EEMPTY;
145 	}
146 
147 	desc = &priv->tx_ring[priv->num_tx_ring];
148 	desc->die_dt = DT_LINK;
149 
150 	return free_num;
151 }
152 
rtsn_rx(struct net_device * ndev,int budget)153 static int rtsn_rx(struct net_device *ndev, int budget)
154 {
155 	struct rtsn_private *priv = netdev_priv(ndev);
156 	unsigned int ndescriptors;
157 	unsigned int rx_packets;
158 	unsigned int i;
159 	bool get_ts;
160 
161 	get_ts = priv->tstamp_rx_ctrl != HWTSTAMP_FILTER_NONE;
162 
163 	ndescriptors = priv->dirty_rx + priv->num_rx_ring - priv->cur_rx;
164 	rx_packets = 0;
165 	for (i = 0; i < ndescriptors; i++) {
166 		const unsigned int entry = priv->cur_rx % priv->num_rx_ring;
167 		struct rtsn_ext_ts_desc *desc = &priv->rx_ring[entry];
168 		struct sk_buff *skb;
169 		dma_addr_t dma_addr;
170 		u16 pkt_len;
171 
172 		/* Stop processing descriptors if budget is consumed. */
173 		if (rx_packets >= budget)
174 			break;
175 
176 		/* Stop processing descriptors on first empty. */
177 		if ((desc->die_dt & DT_MASK) == DT_FEMPTY)
178 			break;
179 
180 		dma_rmb();
181 		pkt_len = le16_to_cpu(desc->info_ds) & RX_DS;
182 
183 		skb = priv->rx_skb[entry];
184 		priv->rx_skb[entry] = NULL;
185 		dma_addr = le32_to_cpu(desc->dptr);
186 		dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ,
187 				 DMA_FROM_DEVICE);
188 
189 		/* Get timestamp if enabled. */
190 		if (get_ts) {
191 			struct skb_shared_hwtstamps *shhwtstamps;
192 			struct timespec64 ts;
193 
194 			shhwtstamps = skb_hwtstamps(skb);
195 			memset(shhwtstamps, 0, sizeof(*shhwtstamps));
196 
197 			ts.tv_sec = (u64)le32_to_cpu(desc->ts_sec);
198 			ts.tv_nsec = le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff));
199 
200 			shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
201 		}
202 
203 		skb_put(skb, pkt_len);
204 		skb->protocol = eth_type_trans(skb, ndev);
205 		napi_gro_receive(&priv->napi, skb);
206 
207 		/* Update statistics. */
208 		priv->stats.rx_packets++;
209 		priv->stats.rx_bytes += pkt_len;
210 
211 		/* Update counters. */
212 		priv->cur_rx++;
213 		rx_packets++;
214 	}
215 
216 	/* Refill the RX ring buffers */
217 	for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
218 		const unsigned int entry = priv->dirty_rx % priv->num_rx_ring;
219 		struct rtsn_ext_ts_desc *desc = &priv->rx_ring[entry];
220 		struct sk_buff *skb;
221 		dma_addr_t dma_addr;
222 
223 		desc->info_ds = cpu_to_le16(PKT_BUF_SZ);
224 
225 		if (!priv->rx_skb[entry]) {
226 			skb = napi_alloc_skb(&priv->napi,
227 					     PKT_BUF_SZ + RTSN_ALIGN - 1);
228 			if (!skb)
229 				break;
230 			skb_reserve(skb, NET_IP_ALIGN);
231 			dma_addr = dma_map_single(ndev->dev.parent, skb->data,
232 						  le16_to_cpu(desc->info_ds),
233 						  DMA_FROM_DEVICE);
234 			if (dma_mapping_error(ndev->dev.parent, dma_addr))
235 				desc->info_ds = cpu_to_le16(0);
236 			desc->dptr = cpu_to_le32(dma_addr);
237 			skb_checksum_none_assert(skb);
238 			priv->rx_skb[entry] = skb;
239 		}
240 
241 		dma_wmb();
242 		desc->die_dt = DT_FEMPTY | D_DIE;
243 	}
244 
245 	priv->rx_ring[priv->num_rx_ring].die_dt = DT_LINK;
246 
247 	return rx_packets;
248 }
249 
rtsn_poll(struct napi_struct * napi,int budget)250 static int rtsn_poll(struct napi_struct *napi, int budget)
251 {
252 	struct rtsn_private *priv;
253 	struct net_device *ndev;
254 	unsigned long flags;
255 	int work_done;
256 
257 	ndev = napi->dev;
258 	priv = netdev_priv(ndev);
259 
260 	/* Processing RX Descriptor Ring */
261 	work_done = rtsn_rx(ndev, budget);
262 
263 	/* Processing TX Descriptor Ring */
264 	spin_lock_irqsave(&priv->lock, flags);
265 	rtsn_tx_free(ndev, true);
266 	netif_wake_subqueue(ndev, 0);
267 	spin_unlock_irqrestore(&priv->lock, flags);
268 
269 	/* Re-enable TX/RX interrupts */
270 	if (work_done < budget && napi_complete_done(napi, work_done)) {
271 		spin_lock_irqsave(&priv->lock, flags);
272 		rtsn_ctrl_data_irq(priv, true);
273 		spin_unlock_irqrestore(&priv->lock, flags);
274 	}
275 
276 	return work_done;
277 }
278 
rtsn_desc_alloc(struct rtsn_private * priv)279 static int rtsn_desc_alloc(struct rtsn_private *priv)
280 {
281 	struct device *dev = &priv->pdev->dev;
282 	unsigned int i;
283 
284 	priv->tx_desc_bat_size = sizeof(struct rtsn_desc) * TX_NUM_CHAINS;
285 	priv->tx_desc_bat = dma_alloc_coherent(dev, priv->tx_desc_bat_size,
286 					       &priv->tx_desc_bat_dma,
287 					       GFP_KERNEL);
288 
289 	if (!priv->tx_desc_bat)
290 		return -ENOMEM;
291 
292 	for (i = 0; i < TX_NUM_CHAINS; i++)
293 		priv->tx_desc_bat[i].die_dt = DT_EOS;
294 
295 	priv->rx_desc_bat_size = sizeof(struct rtsn_desc) * RX_NUM_CHAINS;
296 	priv->rx_desc_bat = dma_alloc_coherent(dev, priv->rx_desc_bat_size,
297 					       &priv->rx_desc_bat_dma,
298 					       GFP_KERNEL);
299 
300 	if (!priv->rx_desc_bat)
301 		return -ENOMEM;
302 
303 	for (i = 0; i < RX_NUM_CHAINS; i++)
304 		priv->rx_desc_bat[i].die_dt = DT_EOS;
305 
306 	return 0;
307 }
308 
rtsn_desc_free(struct rtsn_private * priv)309 static void rtsn_desc_free(struct rtsn_private *priv)
310 {
311 	if (priv->tx_desc_bat)
312 		dma_free_coherent(&priv->pdev->dev, priv->tx_desc_bat_size,
313 				  priv->tx_desc_bat, priv->tx_desc_bat_dma);
314 	priv->tx_desc_bat = NULL;
315 
316 	if (priv->rx_desc_bat)
317 		dma_free_coherent(&priv->pdev->dev, priv->rx_desc_bat_size,
318 				  priv->rx_desc_bat, priv->rx_desc_bat_dma);
319 	priv->rx_desc_bat = NULL;
320 }
321 
rtsn_chain_free(struct rtsn_private * priv)322 static void rtsn_chain_free(struct rtsn_private *priv)
323 {
324 	struct device *dev = &priv->pdev->dev;
325 
326 	dma_free_coherent(dev,
327 			  sizeof(struct rtsn_ext_desc) * (priv->num_tx_ring + 1),
328 			  priv->tx_ring, priv->tx_desc_dma);
329 	priv->tx_ring = NULL;
330 
331 	dma_free_coherent(dev,
332 			  sizeof(struct rtsn_ext_ts_desc) * (priv->num_rx_ring + 1),
333 			  priv->rx_ring, priv->rx_desc_dma);
334 	priv->rx_ring = NULL;
335 
336 	kfree(priv->tx_skb);
337 	priv->tx_skb = NULL;
338 
339 	kfree(priv->rx_skb);
340 	priv->rx_skb = NULL;
341 }
342 
rtsn_chain_init(struct rtsn_private * priv,int tx_size,int rx_size)343 static int rtsn_chain_init(struct rtsn_private *priv, int tx_size, int rx_size)
344 {
345 	struct net_device *ndev = priv->ndev;
346 	struct sk_buff *skb;
347 	int i;
348 
349 	priv->num_tx_ring = tx_size;
350 	priv->num_rx_ring = rx_size;
351 
352 	priv->tx_skb = kzalloc_objs(*priv->tx_skb, tx_size);
353 	priv->rx_skb = kzalloc_objs(*priv->rx_skb, rx_size);
354 
355 	if (!priv->rx_skb || !priv->tx_skb)
356 		goto error;
357 
358 	for (i = 0; i < rx_size; i++) {
359 		skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RTSN_ALIGN - 1);
360 		if (!skb)
361 			goto error;
362 		skb_reserve(skb, NET_IP_ALIGN);
363 		priv->rx_skb[i] = skb;
364 	}
365 
366 	/* Allocate TX, RX descriptors */
367 	priv->tx_ring = dma_alloc_coherent(ndev->dev.parent,
368 					   sizeof(struct rtsn_ext_desc) * (tx_size + 1),
369 					   &priv->tx_desc_dma, GFP_KERNEL);
370 	priv->rx_ring = dma_alloc_coherent(ndev->dev.parent,
371 					   sizeof(struct rtsn_ext_ts_desc) * (rx_size + 1),
372 					   &priv->rx_desc_dma, GFP_KERNEL);
373 
374 	if (!priv->tx_ring || !priv->rx_ring)
375 		goto error;
376 
377 	return 0;
378 error:
379 	rtsn_chain_free(priv);
380 
381 	return -ENOMEM;
382 }
383 
rtsn_chain_format(struct rtsn_private * priv)384 static void rtsn_chain_format(struct rtsn_private *priv)
385 {
386 	struct net_device *ndev = priv->ndev;
387 	struct rtsn_ext_ts_desc *rx_desc;
388 	struct rtsn_ext_desc *tx_desc;
389 	struct rtsn_desc *bat_desc;
390 	dma_addr_t dma_addr;
391 	unsigned int i;
392 
393 	priv->cur_tx = 0;
394 	priv->cur_rx = 0;
395 	priv->dirty_rx = 0;
396 	priv->dirty_tx = 0;
397 
398 	/* TX */
399 	memset(priv->tx_ring, 0, sizeof(*tx_desc) * priv->num_tx_ring);
400 	for (i = 0, tx_desc = priv->tx_ring; i < priv->num_tx_ring; i++, tx_desc++)
401 		tx_desc->die_dt = DT_EEMPTY | D_DIE;
402 
403 	tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma);
404 	tx_desc->die_dt = DT_LINK;
405 
406 	bat_desc = &priv->tx_desc_bat[TX_CHAIN_IDX];
407 	bat_desc->die_dt = DT_LINK;
408 	bat_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma);
409 
410 	/* RX */
411 	memset(priv->rx_ring, 0, sizeof(*rx_desc) * priv->num_rx_ring);
412 	for (i = 0, rx_desc = priv->rx_ring; i < priv->num_rx_ring; i++, rx_desc++) {
413 		dma_addr = dma_map_single(ndev->dev.parent,
414 					  priv->rx_skb[i]->data, PKT_BUF_SZ,
415 					  DMA_FROM_DEVICE);
416 		if (!dma_mapping_error(ndev->dev.parent, dma_addr))
417 			rx_desc->info_ds = cpu_to_le16(PKT_BUF_SZ);
418 		rx_desc->dptr = cpu_to_le32((u32)dma_addr);
419 		rx_desc->die_dt = DT_FEMPTY | D_DIE;
420 	}
421 	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma);
422 	rx_desc->die_dt = DT_LINK;
423 
424 	bat_desc = &priv->rx_desc_bat[RX_CHAIN_IDX];
425 	bat_desc->die_dt = DT_LINK;
426 	bat_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma);
427 }
428 
rtsn_dmac_init(struct rtsn_private * priv)429 static int rtsn_dmac_init(struct rtsn_private *priv)
430 {
431 	int ret;
432 
433 	ret = rtsn_chain_init(priv, TX_CHAIN_SIZE, RX_CHAIN_SIZE);
434 	if (ret)
435 		return ret;
436 
437 	rtsn_chain_format(priv);
438 
439 	return 0;
440 }
441 
rtsn_read_mode(struct rtsn_private * priv)442 static enum rtsn_mode rtsn_read_mode(struct rtsn_private *priv)
443 {
444 	return (rtsn_read(priv, OSR) & OSR_OPS) >> 1;
445 }
446 
rtsn_wait_mode(struct rtsn_private * priv,enum rtsn_mode mode)447 static int rtsn_wait_mode(struct rtsn_private *priv, enum rtsn_mode mode)
448 {
449 	unsigned int i;
450 
451 	/* Need to busy loop as mode changes can happen in atomic context. */
452 	for (i = 0; i < RTSN_TIMEOUT_US / RTSN_INTERVAL_US; i++) {
453 		if (rtsn_read_mode(priv) == mode)
454 			return 0;
455 
456 		udelay(RTSN_INTERVAL_US);
457 	}
458 
459 	return -ETIMEDOUT;
460 }
461 
rtsn_change_mode(struct rtsn_private * priv,enum rtsn_mode mode)462 static int rtsn_change_mode(struct rtsn_private *priv, enum rtsn_mode mode)
463 {
464 	int ret;
465 
466 	rtsn_write(priv, OCR, mode);
467 	ret = rtsn_wait_mode(priv, mode);
468 	if (ret)
469 		netdev_err(priv->ndev, "Failed to switch operation mode\n");
470 	return ret;
471 }
472 
rtsn_get_data_irq_status(struct rtsn_private * priv)473 static int rtsn_get_data_irq_status(struct rtsn_private *priv)
474 {
475 	u32 val;
476 
477 	val = rtsn_read(priv, TDIS0) | TDIS_TDS(TX_CHAIN_IDX);
478 	val |= rtsn_read(priv, RDIS0) | RDIS_RDS(RX_CHAIN_IDX);
479 
480 	return val;
481 }
482 
rtsn_irq(int irq,void * dev_id)483 static irqreturn_t rtsn_irq(int irq, void *dev_id)
484 {
485 	struct rtsn_private *priv = dev_id;
486 	int ret = IRQ_NONE;
487 
488 	spin_lock(&priv->lock);
489 
490 	if (rtsn_get_data_irq_status(priv)) {
491 		/* Clear TX/RX irq status */
492 		rtsn_write(priv, TDIS0, TDIS_TDS(TX_CHAIN_IDX));
493 		rtsn_write(priv, RDIS0, RDIS_RDS(RX_CHAIN_IDX));
494 
495 		if (napi_schedule_prep(&priv->napi)) {
496 			/* Disable TX/RX interrupts */
497 			rtsn_ctrl_data_irq(priv, false);
498 
499 			__napi_schedule(&priv->napi);
500 		}
501 
502 		ret = IRQ_HANDLED;
503 	}
504 
505 	spin_unlock(&priv->lock);
506 
507 	return ret;
508 }
509 
rtsn_request_irq(unsigned int irq,irq_handler_t handler,unsigned long flags,struct rtsn_private * priv,const char * ch)510 static int rtsn_request_irq(unsigned int irq, irq_handler_t handler,
511 			    unsigned long flags, struct rtsn_private *priv,
512 			    const char *ch)
513 {
514 	char *name;
515 	int ret;
516 
517 	name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, "%s:%s",
518 			      priv->ndev->name, ch);
519 	if (!name)
520 		return -ENOMEM;
521 
522 	ret = request_irq(irq, handler, flags, name, priv);
523 	if (ret)
524 		netdev_err(priv->ndev, "Cannot request IRQ %s\n", name);
525 
526 	return ret;
527 }
528 
rtsn_free_irqs(struct rtsn_private * priv)529 static void rtsn_free_irqs(struct rtsn_private *priv)
530 {
531 	free_irq(priv->tx_data_irq, priv);
532 	free_irq(priv->rx_data_irq, priv);
533 }
534 
rtsn_request_irqs(struct rtsn_private * priv)535 static int rtsn_request_irqs(struct rtsn_private *priv)
536 {
537 	int ret;
538 
539 	priv->rx_data_irq = platform_get_irq_byname(priv->pdev, "rx");
540 	if (priv->rx_data_irq < 0)
541 		return priv->rx_data_irq;
542 
543 	priv->tx_data_irq = platform_get_irq_byname(priv->pdev, "tx");
544 	if (priv->tx_data_irq < 0)
545 		return priv->tx_data_irq;
546 
547 	ret = rtsn_request_irq(priv->tx_data_irq, rtsn_irq, 0, priv, "tx");
548 	if (ret)
549 		return ret;
550 
551 	ret = rtsn_request_irq(priv->rx_data_irq, rtsn_irq, 0, priv, "rx");
552 	if (ret) {
553 		free_irq(priv->tx_data_irq, priv);
554 		return ret;
555 	}
556 
557 	return 0;
558 }
559 
rtsn_reset(struct rtsn_private * priv)560 static int rtsn_reset(struct rtsn_private *priv)
561 {
562 	reset_control_reset(priv->reset);
563 	mdelay(1);
564 
565 	return rtsn_wait_mode(priv, OCR_OPC_DISABLE);
566 }
567 
rtsn_axibmi_init(struct rtsn_private * priv)568 static int rtsn_axibmi_init(struct rtsn_private *priv)
569 {
570 	int ret;
571 
572 	ret = rtsn_reg_wait(priv, RR, RR_RST, RR_RST_COMPLETE);
573 	if (ret)
574 		return ret;
575 
576 	/* Set AXIWC */
577 	rtsn_write(priv, AXIWC, AXIWC_DEFAULT);
578 
579 	/* Set AXIRC */
580 	rtsn_write(priv, AXIRC, AXIRC_DEFAULT);
581 
582 	/* TX Descriptor chain setting */
583 	rtsn_write(priv, TATLS0, TATLS0_TEDE | TATLS0_TATEN(TX_CHAIN_IDX));
584 	rtsn_write(priv, TATLS1, priv->tx_desc_bat_dma + TX_CHAIN_ADDR_OFFSET);
585 	rtsn_write(priv, TATLR, TATLR_TATL);
586 
587 	ret = rtsn_reg_wait(priv, TATLR, TATLR_TATL, 0);
588 	if (ret)
589 		return ret;
590 
591 	/* RX Descriptor chain setting */
592 	rtsn_write(priv, RATLS0,
593 		   RATLS0_RETS | RATLS0_REDE | RATLS0_RATEN(RX_CHAIN_IDX));
594 	rtsn_write(priv, RATLS1, priv->rx_desc_bat_dma + RX_CHAIN_ADDR_OFFSET);
595 	rtsn_write(priv, RATLR, RATLR_RATL);
596 
597 	ret = rtsn_reg_wait(priv, RATLR, RATLR_RATL, 0);
598 	if (ret)
599 		return ret;
600 
601 	/* Enable TX/RX interrupts */
602 	rtsn_ctrl_data_irq(priv, true);
603 
604 	return 0;
605 }
606 
rtsn_mhd_init(struct rtsn_private * priv)607 static void rtsn_mhd_init(struct rtsn_private *priv)
608 {
609 	/* TX General setting */
610 	rtsn_write(priv, TGC1, TGC1_STTV_DEFAULT | TGC1_TQTM_SFM);
611 	rtsn_write(priv, TMS0, TMS_MFS_MAX);
612 
613 	/* RX Filter IP */
614 	rtsn_write(priv, CFCR0, CFCR_SDID(RX_CHAIN_IDX));
615 	rtsn_write(priv, FMSCR, FMSCR_FMSIE(RX_CHAIN_IDX));
616 }
617 
rtsn_get_phy_params(struct rtsn_private * priv)618 static int rtsn_get_phy_params(struct rtsn_private *priv)
619 {
620 	int ret;
621 
622 	ret = of_get_phy_mode(priv->pdev->dev.of_node, &priv->iface);
623 	if (ret)
624 		return ret;
625 
626 	switch (priv->iface) {
627 	case PHY_INTERFACE_MODE_MII:
628 		priv->speed = 100;
629 		break;
630 	case PHY_INTERFACE_MODE_RGMII:
631 	case PHY_INTERFACE_MODE_RGMII_ID:
632 	case PHY_INTERFACE_MODE_RGMII_RXID:
633 	case PHY_INTERFACE_MODE_RGMII_TXID:
634 		priv->speed = 1000;
635 		break;
636 	default:
637 		return -EOPNOTSUPP;
638 	}
639 
640 	return 0;
641 }
642 
rtsn_set_phy_interface(struct rtsn_private * priv)643 static void rtsn_set_phy_interface(struct rtsn_private *priv)
644 {
645 	u32 val;
646 
647 	switch (priv->iface) {
648 	case PHY_INTERFACE_MODE_MII:
649 		val = MPIC_PIS_MII;
650 		break;
651 	case PHY_INTERFACE_MODE_RGMII:
652 	case PHY_INTERFACE_MODE_RGMII_ID:
653 	case PHY_INTERFACE_MODE_RGMII_RXID:
654 	case PHY_INTERFACE_MODE_RGMII_TXID:
655 		val = MPIC_PIS_GMII;
656 		break;
657 	default:
658 		return;
659 	}
660 
661 	rtsn_modify(priv, MPIC, MPIC_PIS_MASK, val);
662 }
663 
rtsn_set_rate(struct rtsn_private * priv)664 static void rtsn_set_rate(struct rtsn_private *priv)
665 {
666 	u32 val;
667 
668 	switch (priv->speed) {
669 	case 10:
670 		val = MPIC_LSC_10M;
671 		break;
672 	case 100:
673 		val = MPIC_LSC_100M;
674 		break;
675 	case 1000:
676 		val = MPIC_LSC_1G;
677 		break;
678 	default:
679 		return;
680 	}
681 
682 	rtsn_modify(priv, MPIC, MPIC_LSC_MASK, val);
683 }
684 
rtsn_rmac_init(struct rtsn_private * priv)685 static int rtsn_rmac_init(struct rtsn_private *priv)
686 {
687 	const u8 *mac_addr = priv->ndev->dev_addr;
688 
689 	/* Set MAC address */
690 	rtsn_write(priv, MRMAC0, (mac_addr[0] << 8) | mac_addr[1]);
691 	rtsn_write(priv, MRMAC1, (mac_addr[2] << 24) | (mac_addr[3] << 16) |
692 		   (mac_addr[4] << 8) | mac_addr[5]);
693 
694 	/* Set xMII type */
695 	rtsn_set_phy_interface(priv);
696 	rtsn_set_rate(priv);
697 
698 	/* Enable MII */
699 	rtsn_modify(priv, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
700 		    MPIC_PSMCS_DEFAULT | MPIC_PSMHT_DEFAULT);
701 
702 	/* Link verification */
703 	rtsn_modify(priv, MLVC, MLVC_PLV, MLVC_PLV);
704 	return rtsn_reg_wait(priv, MLVC, MLVC_PLV, 0);
705 }
706 
rtsn_hw_init(struct rtsn_private * priv)707 static int rtsn_hw_init(struct rtsn_private *priv)
708 {
709 	int ret;
710 
711 	ret = rtsn_reset(priv);
712 	if (ret)
713 		return ret;
714 
715 	/* Change to CONFIG mode */
716 	ret = rtsn_change_mode(priv, OCR_OPC_CONFIG);
717 	if (ret)
718 		return ret;
719 
720 	ret = rtsn_axibmi_init(priv);
721 	if (ret)
722 		return ret;
723 
724 	rtsn_mhd_init(priv);
725 
726 	ret = rtsn_rmac_init(priv);
727 	if (ret)
728 		return ret;
729 
730 	ret = rtsn_change_mode(priv, OCR_OPC_DISABLE);
731 	if (ret)
732 		return ret;
733 
734 	/* Change to OPERATION mode */
735 	ret = rtsn_change_mode(priv, OCR_OPC_OPERATION);
736 
737 	return ret;
738 }
739 
rtsn_mii_access(struct mii_bus * bus,bool read,int phyad,int regad,u16 data)740 static int rtsn_mii_access(struct mii_bus *bus, bool read, int phyad,
741 			   int regad, u16 data)
742 {
743 	struct rtsn_private *priv = bus->priv;
744 	u32 val;
745 	int ret;
746 
747 	val = MPSM_PDA(phyad) | MPSM_PRA(regad) | MPSM_PSME;
748 
749 	if (!read)
750 		val |= MPSM_PSMAD | MPSM_PRD_SET(data);
751 
752 	rtsn_write(priv, MPSM, val);
753 
754 	ret = rtsn_reg_wait(priv, MPSM, MPSM_PSME, 0);
755 	if (ret)
756 		return ret;
757 
758 	if (read)
759 		ret = MPSM_PRD_GET(rtsn_read(priv, MPSM));
760 
761 	return ret;
762 }
763 
rtsn_mii_read(struct mii_bus * bus,int addr,int regnum)764 static int rtsn_mii_read(struct mii_bus *bus, int addr, int regnum)
765 {
766 	return rtsn_mii_access(bus, true, addr, regnum, 0);
767 }
768 
rtsn_mii_write(struct mii_bus * bus,int addr,int regnum,u16 val)769 static int rtsn_mii_write(struct mii_bus *bus, int addr, int regnum, u16 val)
770 {
771 	return rtsn_mii_access(bus, false, addr, regnum, val);
772 }
773 
rtsn_mdio_alloc(struct rtsn_private * priv)774 static int rtsn_mdio_alloc(struct rtsn_private *priv)
775 {
776 	struct platform_device *pdev = priv->pdev;
777 	struct device *dev = &pdev->dev;
778 	struct device_node *mdio_node;
779 	struct mii_bus *mii;
780 	int ret;
781 
782 	mii = mdiobus_alloc();
783 	if (!mii)
784 		return -ENOMEM;
785 
786 	mdio_node = of_get_child_by_name(dev->of_node, "mdio");
787 	if (!mdio_node) {
788 		ret = -ENODEV;
789 		goto out_free_bus;
790 	}
791 
792 	/* Enter config mode before registering the MDIO bus */
793 	ret = rtsn_reset(priv);
794 	if (ret)
795 		goto out_put_node;
796 
797 	ret = rtsn_change_mode(priv, OCR_OPC_CONFIG);
798 	if (ret)
799 		goto out_put_node;
800 
801 	rtsn_modify(priv, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
802 		    MPIC_PSMCS_DEFAULT | MPIC_PSMHT_DEFAULT);
803 
804 	/* Register the MDIO bus */
805 	mii->name = "rtsn_mii";
806 	snprintf(mii->id, MII_BUS_ID_SIZE, "%s-%x",
807 		 pdev->name, pdev->id);
808 	mii->priv = priv;
809 	mii->read = rtsn_mii_read;
810 	mii->write = rtsn_mii_write;
811 	mii->parent = dev;
812 
813 	ret = of_mdiobus_register(mii, mdio_node);
814 	of_node_put(mdio_node);
815 	if (ret)
816 		goto out_free_bus;
817 
818 	priv->mii = mii;
819 
820 	return 0;
821 
822 out_put_node:
823 	of_node_put(mdio_node);
824 out_free_bus:
825 	mdiobus_free(mii);
826 	return ret;
827 }
828 
rtsn_mdio_free(struct rtsn_private * priv)829 static void rtsn_mdio_free(struct rtsn_private *priv)
830 {
831 	mdiobus_unregister(priv->mii);
832 	mdiobus_free(priv->mii);
833 	priv->mii = NULL;
834 }
835 
rtsn_adjust_link(struct net_device * ndev)836 static void rtsn_adjust_link(struct net_device *ndev)
837 {
838 	struct rtsn_private *priv = netdev_priv(ndev);
839 	struct phy_device *phydev = ndev->phydev;
840 	bool new_state = false;
841 	unsigned long flags;
842 
843 	spin_lock_irqsave(&priv->lock, flags);
844 
845 	if (phydev->link) {
846 		if (phydev->speed != priv->speed) {
847 			new_state = true;
848 			priv->speed = phydev->speed;
849 		}
850 
851 		if (!priv->link) {
852 			new_state = true;
853 			priv->link = phydev->link;
854 		}
855 	} else if (priv->link) {
856 		new_state = true;
857 		priv->link = 0;
858 		priv->speed = 0;
859 	}
860 
861 	if (new_state) {
862 		/* Need to transition to CONFIG mode before reconfiguring and
863 		 * then back to the original mode. Any state change to/from
864 		 * CONFIG or OPERATION must go over DISABLED to stop Rx/Tx.
865 		 */
866 		enum rtsn_mode orgmode = rtsn_read_mode(priv);
867 
868 		/* Transit to CONFIG */
869 		if (orgmode != OCR_OPC_CONFIG) {
870 			if (orgmode != OCR_OPC_DISABLE &&
871 			    rtsn_change_mode(priv, OCR_OPC_DISABLE))
872 				goto out;
873 			if (rtsn_change_mode(priv, OCR_OPC_CONFIG))
874 				goto out;
875 		}
876 
877 		rtsn_set_rate(priv);
878 
879 		/* Transition to original mode */
880 		if (orgmode != OCR_OPC_CONFIG) {
881 			if (rtsn_change_mode(priv, OCR_OPC_DISABLE))
882 				goto out;
883 			if (orgmode != OCR_OPC_DISABLE &&
884 			    rtsn_change_mode(priv, orgmode))
885 				goto out;
886 		}
887 	}
888 out:
889 	spin_unlock_irqrestore(&priv->lock, flags);
890 
891 	if (new_state)
892 		phy_print_status(phydev);
893 }
894 
rtsn_phy_init(struct rtsn_private * priv)895 static int rtsn_phy_init(struct rtsn_private *priv)
896 {
897 	struct device_node *np = priv->ndev->dev.parent->of_node;
898 	struct phy_device *phydev;
899 	struct device_node *phy;
900 
901 	priv->link = 0;
902 
903 	phy = of_parse_phandle(np, "phy-handle", 0);
904 	if (!phy)
905 		return -ENOENT;
906 
907 	phydev = of_phy_connect(priv->ndev, phy, rtsn_adjust_link, 0,
908 				priv->iface);
909 	of_node_put(phy);
910 	if (!phydev)
911 		return -ENOENT;
912 
913 	/* Only support full-duplex mode */
914 	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
915 	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
916 	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
917 
918 	phy_attached_info(phydev);
919 
920 	return 0;
921 }
922 
rtsn_phy_deinit(struct rtsn_private * priv)923 static void rtsn_phy_deinit(struct rtsn_private *priv)
924 {
925 	phy_disconnect(priv->ndev->phydev);
926 	priv->ndev->phydev = NULL;
927 }
928 
rtsn_init(struct rtsn_private * priv)929 static int rtsn_init(struct rtsn_private *priv)
930 {
931 	int ret;
932 
933 	ret = rtsn_desc_alloc(priv);
934 	if (ret)
935 		return ret;
936 
937 	ret = rtsn_dmac_init(priv);
938 	if (ret)
939 		goto error_free_desc;
940 
941 	ret = rtsn_hw_init(priv);
942 	if (ret)
943 		goto error_free_chain;
944 
945 	ret = rtsn_phy_init(priv);
946 	if (ret)
947 		goto error_free_chain;
948 
949 	ret = rtsn_request_irqs(priv);
950 	if (ret)
951 		goto error_free_phy;
952 
953 	return 0;
954 error_free_phy:
955 	rtsn_phy_deinit(priv);
956 error_free_chain:
957 	rtsn_chain_free(priv);
958 error_free_desc:
959 	rtsn_desc_free(priv);
960 	return ret;
961 }
962 
rtsn_deinit(struct rtsn_private * priv)963 static void rtsn_deinit(struct rtsn_private *priv)
964 {
965 	rtsn_free_irqs(priv);
966 	rtsn_phy_deinit(priv);
967 	rtsn_chain_free(priv);
968 	rtsn_desc_free(priv);
969 }
970 
rtsn_parse_mac_address(struct device_node * np,struct net_device * ndev)971 static void rtsn_parse_mac_address(struct device_node *np,
972 				   struct net_device *ndev)
973 {
974 	struct rtsn_private *priv = netdev_priv(ndev);
975 	u8 addr[ETH_ALEN];
976 	u32 mrmac0;
977 	u32 mrmac1;
978 
979 	/* Try to read address from Device Tree. */
980 	if (!of_get_mac_address(np, addr)) {
981 		eth_hw_addr_set(ndev, addr);
982 		return;
983 	}
984 
985 	/* Try to read address from device. */
986 	mrmac0 = rtsn_read(priv, MRMAC0);
987 	mrmac1 = rtsn_read(priv, MRMAC1);
988 
989 	addr[0] = (mrmac0 >>  8) & 0xff;
990 	addr[1] = (mrmac0 >>  0) & 0xff;
991 	addr[2] = (mrmac1 >> 24) & 0xff;
992 	addr[3] = (mrmac1 >> 16) & 0xff;
993 	addr[4] = (mrmac1 >>  8) & 0xff;
994 	addr[5] = (mrmac1 >>  0) & 0xff;
995 
996 	if (is_valid_ether_addr(addr)) {
997 		eth_hw_addr_set(ndev, addr);
998 		return;
999 	}
1000 
1001 	/* Fallback to a random address */
1002 	eth_hw_addr_random(ndev);
1003 }
1004 
rtsn_open(struct net_device * ndev)1005 static int rtsn_open(struct net_device *ndev)
1006 {
1007 	struct rtsn_private *priv = netdev_priv(ndev);
1008 	int ret;
1009 
1010 	napi_enable(&priv->napi);
1011 
1012 	ret = rtsn_init(priv);
1013 	if (ret) {
1014 		napi_disable(&priv->napi);
1015 		return ret;
1016 	}
1017 
1018 	phy_start(ndev->phydev);
1019 
1020 	netif_start_queue(ndev);
1021 
1022 	return 0;
1023 }
1024 
rtsn_stop(struct net_device * ndev)1025 static int rtsn_stop(struct net_device *ndev)
1026 {
1027 	struct rtsn_private *priv = netdev_priv(ndev);
1028 
1029 	phy_stop(priv->ndev->phydev);
1030 	napi_disable(&priv->napi);
1031 	rtsn_change_mode(priv, OCR_OPC_DISABLE);
1032 	rtsn_deinit(priv);
1033 
1034 	return 0;
1035 }
1036 
rtsn_start_xmit(struct sk_buff * skb,struct net_device * ndev)1037 static netdev_tx_t rtsn_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1038 {
1039 	struct rtsn_private *priv = netdev_priv(ndev);
1040 	struct rtsn_ext_desc *desc;
1041 	int ret = NETDEV_TX_OK;
1042 	unsigned long flags;
1043 	dma_addr_t dma_addr;
1044 	int entry;
1045 
1046 	spin_lock_irqsave(&priv->lock, flags);
1047 
1048 	/* Drop packet if it won't fit in a single descriptor. */
1049 	if (skb->len >= TX_DS) {
1050 		priv->stats.tx_dropped++;
1051 		priv->stats.tx_errors++;
1052 		dev_kfree_skb_any(skb);
1053 		goto out;
1054 	}
1055 
1056 	if (priv->cur_tx - priv->dirty_tx > priv->num_tx_ring) {
1057 		netif_stop_subqueue(ndev, 0);
1058 		ret = NETDEV_TX_BUSY;
1059 		goto out;
1060 	}
1061 
1062 	if (skb_put_padto(skb, ETH_ZLEN))
1063 		goto out;
1064 
1065 	dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1066 				  DMA_TO_DEVICE);
1067 	if (dma_mapping_error(ndev->dev.parent, dma_addr)) {
1068 		dev_kfree_skb_any(skb);
1069 		goto out;
1070 	}
1071 
1072 	entry = priv->cur_tx % priv->num_tx_ring;
1073 	priv->tx_skb[entry] = skb;
1074 	desc = &priv->tx_ring[entry];
1075 	desc->dptr = cpu_to_le32(dma_addr);
1076 	desc->info_ds = cpu_to_le16(skb->len);
1077 	desc->info1 = cpu_to_le64(skb->len);
1078 
1079 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1080 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1081 		priv->ts_tag++;
1082 		desc->info_ds |= cpu_to_le16(TXC);
1083 		desc->info = priv->ts_tag;
1084 	}
1085 
1086 	skb_tx_timestamp(skb);
1087 	dma_wmb();
1088 
1089 	desc->die_dt = DT_FSINGLE | D_DIE;
1090 	priv->cur_tx++;
1091 
1092 	/* Start xmit */
1093 	rtsn_write(priv, TRCR0, BIT(TX_CHAIN_IDX));
1094 out:
1095 	spin_unlock_irqrestore(&priv->lock, flags);
1096 	return ret;
1097 }
1098 
rtsn_get_stats64(struct net_device * ndev,struct rtnl_link_stats64 * storage)1099 static void rtsn_get_stats64(struct net_device *ndev,
1100 			     struct rtnl_link_stats64 *storage)
1101 {
1102 	struct rtsn_private *priv = netdev_priv(ndev);
1103 	*storage = priv->stats;
1104 }
1105 
rtsn_do_ioctl(struct net_device * ndev,struct ifreq * ifr,int cmd)1106 static int rtsn_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
1107 {
1108 	if (!netif_running(ndev))
1109 		return -ENODEV;
1110 
1111 	return phy_do_ioctl_running(ndev, ifr, cmd);
1112 }
1113 
rtsn_hwtstamp_get(struct net_device * ndev,struct kernel_hwtstamp_config * config)1114 static int rtsn_hwtstamp_get(struct net_device *ndev,
1115 			     struct kernel_hwtstamp_config *config)
1116 {
1117 	struct rtsn_private *priv;
1118 
1119 	if (!netif_running(ndev))
1120 		return -ENODEV;
1121 
1122 	priv = netdev_priv(ndev);
1123 
1124 	config->flags = 0;
1125 	config->tx_type = priv->tstamp_tx_ctrl;
1126 	config->rx_filter = priv->tstamp_rx_ctrl;
1127 
1128 	return 0;
1129 }
1130 
rtsn_hwtstamp_set(struct net_device * ndev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)1131 static int rtsn_hwtstamp_set(struct net_device *ndev,
1132 			     struct kernel_hwtstamp_config *config,
1133 			     struct netlink_ext_ack *extack)
1134 {
1135 	enum hwtstamp_rx_filters tstamp_rx_ctrl;
1136 	enum hwtstamp_tx_types tstamp_tx_ctrl;
1137 	struct rtsn_private *priv;
1138 
1139 	if (!netif_running(ndev))
1140 		return -ENODEV;
1141 
1142 	priv = netdev_priv(ndev);
1143 
1144 	if (config->flags)
1145 		return -EINVAL;
1146 
1147 	switch (config->tx_type) {
1148 	case HWTSTAMP_TX_OFF:
1149 	case HWTSTAMP_TX_ON:
1150 		tstamp_tx_ctrl = config->tx_type;
1151 		break;
1152 	default:
1153 		return -ERANGE;
1154 	}
1155 
1156 	switch (config->rx_filter) {
1157 	case HWTSTAMP_FILTER_NONE:
1158 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1159 		tstamp_rx_ctrl = config->rx_filter;
1160 		break;
1161 	default:
1162 		config->rx_filter = HWTSTAMP_FILTER_ALL;
1163 		tstamp_rx_ctrl = HWTSTAMP_FILTER_ALL;
1164 		break;
1165 	}
1166 
1167 	priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1168 	priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1169 
1170 	return 0;
1171 }
1172 
1173 static const struct net_device_ops rtsn_netdev_ops = {
1174 	.ndo_open		= rtsn_open,
1175 	.ndo_stop		= rtsn_stop,
1176 	.ndo_start_xmit		= rtsn_start_xmit,
1177 	.ndo_get_stats64	= rtsn_get_stats64,
1178 	.ndo_eth_ioctl		= rtsn_do_ioctl,
1179 	.ndo_validate_addr	= eth_validate_addr,
1180 	.ndo_set_mac_address	= eth_mac_addr,
1181 	.ndo_hwtstamp_set	= rtsn_hwtstamp_set,
1182 	.ndo_hwtstamp_get	= rtsn_hwtstamp_get,
1183 };
1184 
rtsn_get_ts_info(struct net_device * ndev,struct kernel_ethtool_ts_info * info)1185 static int rtsn_get_ts_info(struct net_device *ndev,
1186 			    struct kernel_ethtool_ts_info *info)
1187 {
1188 	struct rtsn_private *priv = netdev_priv(ndev);
1189 
1190 	info->phc_index = rcar_gen4_ptp_clock_index(priv->ptp_priv);
1191 	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1192 		SOF_TIMESTAMPING_TX_HARDWARE |
1193 		SOF_TIMESTAMPING_RX_HARDWARE |
1194 		SOF_TIMESTAMPING_RAW_HARDWARE;
1195 	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
1196 	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1197 
1198 	return 0;
1199 }
1200 
1201 static const struct ethtool_ops rtsn_ethtool_ops = {
1202 	.nway_reset		= phy_ethtool_nway_reset,
1203 	.get_link		= ethtool_op_get_link,
1204 	.get_ts_info		= rtsn_get_ts_info,
1205 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1206 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1207 };
1208 
1209 static const struct of_device_id rtsn_match_table[] = {
1210 	{ .compatible = "renesas,r8a779g0-ethertsn", },
1211 	{ /* Sentinel */ }
1212 };
1213 
1214 MODULE_DEVICE_TABLE(of, rtsn_match_table);
1215 
rtsn_probe(struct platform_device * pdev)1216 static int rtsn_probe(struct platform_device *pdev)
1217 {
1218 	struct rtsn_private *priv;
1219 	struct net_device *ndev;
1220 	void __iomem *ptpaddr;
1221 	struct resource *res;
1222 	int ret;
1223 
1224 	ndev = alloc_etherdev_mqs(sizeof(struct rtsn_private), TX_NUM_CHAINS,
1225 				  RX_NUM_CHAINS);
1226 	if (!ndev)
1227 		return -ENOMEM;
1228 
1229 	priv = netdev_priv(ndev);
1230 	priv->pdev = pdev;
1231 	priv->ndev = ndev;
1232 
1233 	spin_lock_init(&priv->lock);
1234 	platform_set_drvdata(pdev, priv);
1235 
1236 	priv->clk = devm_clk_get(&pdev->dev, NULL);
1237 	if (IS_ERR(priv->clk)) {
1238 		ret = PTR_ERR(priv->clk);
1239 		goto error_free;
1240 	}
1241 
1242 	priv->reset = devm_reset_control_get(&pdev->dev, NULL);
1243 	if (IS_ERR(priv->reset)) {
1244 		ret = PTR_ERR(priv->reset);
1245 		goto error_free;
1246 	}
1247 
1248 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tsnes");
1249 	if (!res) {
1250 		dev_err(&pdev->dev, "Can't find tsnes resource\n");
1251 		ret = -EINVAL;
1252 		goto error_free;
1253 	}
1254 
1255 	priv->base = devm_ioremap_resource(&pdev->dev, res);
1256 	if (IS_ERR(priv->base)) {
1257 		ret = PTR_ERR(priv->base);
1258 		goto error_free;
1259 	}
1260 
1261 	SET_NETDEV_DEV(ndev, &pdev->dev);
1262 
1263 	ndev->features = NETIF_F_RXCSUM;
1264 	ndev->hw_features = NETIF_F_RXCSUM;
1265 	ndev->base_addr = res->start;
1266 	ndev->netdev_ops = &rtsn_netdev_ops;
1267 	ndev->ethtool_ops = &rtsn_ethtool_ops;
1268 
1269 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gptp");
1270 	if (!res) {
1271 		dev_err(&pdev->dev, "Can't find gptp resource\n");
1272 		ret = -EINVAL;
1273 		goto error_free;
1274 	}
1275 
1276 	ptpaddr = devm_ioremap_resource(&pdev->dev, res);
1277 	if (IS_ERR(ptpaddr)) {
1278 		ret = PTR_ERR(ptpaddr);
1279 		goto error_free;
1280 	}
1281 
1282 	priv->ptp_priv = rcar_gen4_ptp_alloc(pdev, ptpaddr);
1283 	if (!priv->ptp_priv) {
1284 		ret = -ENOMEM;
1285 		goto error_free;
1286 	}
1287 
1288 	ret = rtsn_get_phy_params(priv);
1289 	if (ret)
1290 		goto error_free;
1291 
1292 	pm_runtime_enable(&pdev->dev);
1293 	pm_runtime_get_sync(&pdev->dev);
1294 
1295 	netif_napi_add(ndev, &priv->napi, rtsn_poll);
1296 
1297 	rtsn_parse_mac_address(pdev->dev.of_node, ndev);
1298 
1299 	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1300 
1301 	device_set_wakeup_capable(&pdev->dev, 1);
1302 
1303 	ret = rcar_gen4_ptp_register(priv->ptp_priv, clk_get_rate(priv->clk));
1304 	if (ret)
1305 		goto error_pm;
1306 
1307 	ret = rtsn_mdio_alloc(priv);
1308 	if (ret)
1309 		goto error_ptp;
1310 
1311 	ret = register_netdev(ndev);
1312 	if (ret)
1313 		goto error_mdio;
1314 
1315 	netdev_info(ndev, "MAC address %pM\n", ndev->dev_addr);
1316 
1317 	return 0;
1318 
1319 error_mdio:
1320 	rtsn_mdio_free(priv);
1321 error_ptp:
1322 	rcar_gen4_ptp_unregister(priv->ptp_priv);
1323 error_pm:
1324 	netif_napi_del(&priv->napi);
1325 	rtsn_change_mode(priv, OCR_OPC_DISABLE);
1326 	pm_runtime_put_sync(&pdev->dev);
1327 	pm_runtime_disable(&pdev->dev);
1328 error_free:
1329 	free_netdev(ndev);
1330 
1331 	return ret;
1332 }
1333 
rtsn_remove(struct platform_device * pdev)1334 static void rtsn_remove(struct platform_device *pdev)
1335 {
1336 	struct rtsn_private *priv = platform_get_drvdata(pdev);
1337 
1338 	unregister_netdev(priv->ndev);
1339 	rtsn_mdio_free(priv);
1340 	rcar_gen4_ptp_unregister(priv->ptp_priv);
1341 	rtsn_change_mode(priv, OCR_OPC_DISABLE);
1342 	netif_napi_del(&priv->napi);
1343 
1344 	pm_runtime_put_sync(&pdev->dev);
1345 	pm_runtime_disable(&pdev->dev);
1346 
1347 	free_netdev(priv->ndev);
1348 }
1349 
1350 static struct platform_driver rtsn_driver = {
1351 	.probe		= rtsn_probe,
1352 	.remove		= rtsn_remove,
1353 	.driver	= {
1354 		.name	= "rtsn",
1355 		.of_match_table	= rtsn_match_table,
1356 	}
1357 };
1358 module_platform_driver(rtsn_driver);
1359 
1360 MODULE_AUTHOR("Phong Hoang, Niklas Söderlund");
1361 MODULE_DESCRIPTION("Renesas Ethernet-TSN device driver");
1362 MODULE_LICENSE("GPL");
1363