1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Ricky Wu <ricky_wu@realtek.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/rtsx_pci.h>
13
14 #include "rts5264.h"
15 #include "rtsx_pcr.h"
16
rts5264_get_ic_version(struct rtsx_pcr * pcr)17 static u8 rts5264_get_ic_version(struct rtsx_pcr *pcr)
18 {
19 u8 val;
20
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
22 return val & 0x0F;
23 }
24
rts5264_fill_driving(struct rtsx_pcr * pcr,u8 voltage)25 static void rts5264_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
26 {
27 u8 driving_3v3[4][3] = {
28 {0x88, 0x88, 0x88},
29 {0x77, 0x77, 0x77},
30 {0x99, 0x99, 0x99},
31 {0x66, 0x66, 0x66},
32 };
33 u8 driving_1v8[4][3] = {
34 {0x99, 0x99, 0x99},
35 {0x77, 0x77, 0x77},
36 {0xBB, 0xBB, 0xBB},
37 {0x65, 0x65, 0x65},
38 };
39 u8 (*driving)[3], drive_sel;
40
41 if (voltage == OUTPUT_3V3) {
42 driving = driving_3v3;
43 drive_sel = pcr->sd30_drive_sel_3v3;
44 } else {
45 driving = driving_1v8;
46 drive_sel = pcr->sd30_drive_sel_1v8;
47 }
48
49 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
50 0xFF, driving[drive_sel][0]);
51 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
52 0xFF, driving[drive_sel][1]);
53 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
54 0xFF, driving[drive_sel][2]);
55 }
56
rts5264_force_power_down(struct rtsx_pcr * pcr,u8 pm_state,bool runtime)57 static void rts5264_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
58 {
59 /* Set relink_time to 0 */
60 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
61 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
62 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
63 RELINK_TIME_MASK, 0);
64
65 if (pm_state == HOST_ENTER_S3)
66 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
67 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
68
69 if (!runtime) {
70 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,
71 CD_RESUME_EN_MASK, 0);
72 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
73 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
74 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
75 } else {
76 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
77 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
78 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
79 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
80 D3_DELINK_MODE_EN, 0);
81 rtsx_pci_write_register(pcr, RTS5264_FW_CTL,
82 RTS5264_INFORM_RTD3_COLD, RTS5264_INFORM_RTD3_COLD);
83 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
84 RTS5264_FORCE_PRSNT_LOW, RTS5264_FORCE_PRSNT_LOW);
85 }
86
87 rtsx_pci_write_register(pcr, RTS5264_REG_FPDCTL,
88 SSC_POWER_DOWN, SSC_POWER_DOWN);
89 }
90
rts5264_enable_auto_blink(struct rtsx_pcr * pcr)91 static int rts5264_enable_auto_blink(struct rtsx_pcr *pcr)
92 {
93 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
94 LED_SHINE_MASK, LED_SHINE_EN);
95 }
96
rts5264_disable_auto_blink(struct rtsx_pcr * pcr)97 static int rts5264_disable_auto_blink(struct rtsx_pcr *pcr)
98 {
99 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
100 LED_SHINE_MASK, LED_SHINE_DISABLE);
101 }
102
rts5264_turn_on_led(struct rtsx_pcr * pcr)103 static int rts5264_turn_on_led(struct rtsx_pcr *pcr)
104 {
105 return rtsx_pci_write_register(pcr, GPIO_CTL,
106 0x02, 0x02);
107 }
108
rts5264_turn_off_led(struct rtsx_pcr * pcr)109 static int rts5264_turn_off_led(struct rtsx_pcr *pcr)
110 {
111 return rtsx_pci_write_register(pcr, GPIO_CTL,
112 0x02, 0x00);
113 }
114
115 /* SD Pull Control Enable:
116 * SD_DAT[3:0] ==> pull up
117 * SD_CD ==> pull up
118 * SD_WP ==> pull up
119 * SD_CMD ==> pull up
120 * SD_CLK ==> pull down
121 */
122 static const u32 rts5264_sd_pull_ctl_enable_tbl[] = {
123 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
124 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
125 0,
126 };
127
128 /* SD Pull Control Disable:
129 * SD_DAT[3:0] ==> pull down
130 * SD_CD ==> pull up
131 * SD_WP ==> pull down
132 * SD_CMD ==> pull down
133 * SD_CLK ==> pull down
134 */
135 static const u32 rts5264_sd_pull_ctl_disable_tbl[] = {
136 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
137 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
138 0,
139 };
140
rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr * pcr)141 static int rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
142 {
143 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
144 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
145 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
146 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
147 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
149
150 return 0;
151 }
152
rts5264_card_power_on(struct rtsx_pcr * pcr,int card)153 static int rts5264_card_power_on(struct rtsx_pcr *pcr, int card)
154 {
155 struct rtsx_cr_option *option = &pcr->option;
156
157 if (option->ocp_en)
158 rtsx_pci_enable_ocp(pcr);
159
160 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
161 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
162
163 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG1,
164 RTS5264_LDO1_TUNE_MASK, RTS5264_LDO1_33);
165 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
166 RTS5264_LDO1_POWERON, RTS5264_LDO1_POWERON);
167 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
168 RTS5264_LDO3318_POWERON, RTS5264_LDO3318_POWERON);
169
170 msleep(20);
171
172 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
173
174 /* Initialize SD_CFG1 register */
175 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
176 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
177 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
178 0xFF, SD20_RX_POS_EDGE);
179 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
180 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
181 SD_STOP | SD_CLR_ERR);
182
183 /* Reset SD_CFG3 register */
184 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
185 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
186 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
187 SD30_CLK_STOP_CFG0, 0);
188
189 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
190 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
191 rts5264_sd_set_sample_push_timing_sd30(pcr);
192
193 return 0;
194 }
195
rts5264_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)196 static int rts5264_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
197 {
198 rtsx_pci_write_register(pcr, RTS5264_CARD_PWR_CTL,
199 RTS5264_PUPDC, RTS5264_PUPDC);
200
201 switch (voltage) {
202 case OUTPUT_3V3:
203 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
204 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318);
205 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,
206 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_33);
207 rtsx_pci_write_register(pcr, SD_PAD_CTL,
208 SD_IO_USING_1V8, 0);
209 break;
210 case OUTPUT_1V8:
211 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
212 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318_DFT);
213 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,
214 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_18);
215 rtsx_pci_write_register(pcr, SD_PAD_CTL,
216 SD_IO_USING_1V8, SD_IO_USING_1V8);
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 /* set pad drive */
223 rts5264_fill_driving(pcr, voltage);
224
225 return 0;
226 }
227
rts5264_stop_cmd(struct rtsx_pcr * pcr)228 static void rts5264_stop_cmd(struct rtsx_pcr *pcr)
229 {
230 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
231 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
232 rtsx_pci_write_register(pcr, DMACTL, DMA_RST, DMA_RST);
233 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
234 }
235
rts5264_card_before_power_off(struct rtsx_pcr * pcr)236 static void rts5264_card_before_power_off(struct rtsx_pcr *pcr)
237 {
238 rts5264_stop_cmd(pcr);
239 rts5264_switch_output_voltage(pcr, OUTPUT_3V3);
240 }
241
rts5264_card_power_off(struct rtsx_pcr * pcr,int card)242 static int rts5264_card_power_off(struct rtsx_pcr *pcr, int card)
243 {
244 int err = 0;
245
246 rts5264_card_before_power_off(pcr);
247 err = rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
248 RTS5264_LDO_POWERON_MASK, 0);
249
250 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
251 CFG_SD_POW_AUTO_PD, 0);
252 if (pcr->option.ocp_en)
253 rtsx_pci_disable_ocp(pcr);
254
255 return err;
256 }
257
rts5264_enable_ocp(struct rtsx_pcr * pcr)258 static void rts5264_enable_ocp(struct rtsx_pcr *pcr)
259 {
260 u8 mask = 0;
261 u8 val = 0;
262
263 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
264 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN,
265 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN);
266 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
267 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN,
268 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN);
269 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
270 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN,
271 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN);
272 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
273 RTS5264_POW_VDET, RTS5264_POW_VDET);
274
275 mask = SD_OCP_INT_EN | SD_DETECT_EN;
276 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
277 val = mask;
278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
279
280 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;
281 val = mask;
282 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, val);
283
284 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;
285 val = mask;
286 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, val);
287 }
288
rts5264_disable_ocp(struct rtsx_pcr * pcr)289 static void rts5264_disable_ocp(struct rtsx_pcr *pcr)
290 {
291 u8 mask = 0;
292
293 mask = SD_OCP_INT_EN | SD_DETECT_EN;
294 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
295 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
296
297 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;
298 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, 0);
299
300 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;
301 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, 0);
302
303 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
304 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);
305 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
306 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);
307 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
308 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);
309 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, RTS5264_POW_VDET, 0);
310 }
311
rts5264_init_ocp(struct rtsx_pcr * pcr)312 static void rts5264_init_ocp(struct rtsx_pcr *pcr)
313 {
314 struct rtsx_cr_option *option = &pcr->option;
315
316 if (option->ocp_en) {
317 u8 mask, val;
318
319 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
320 RTS5264_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
321 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
322 RTS5264_LDO1_OCP_LMT_THD_MASK,
323 RTS5264_LDO1_LMT_THD_2000);
324
325 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
326 RTS5264_LDO2_OCP_THD_MASK, RTS5264_LDO2_OCP_THD_950);
327 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
328 RTS5264_LDO2_OCP_LMT_THD_MASK,
329 RTS5264_LDO2_LMT_THD_2000);
330
331 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
332 RTS5264_LDO3_OCP_THD_MASK, RTS5264_LDO3_OCP_THD_710);
333 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
334 RTS5264_LDO3_OCP_LMT_THD_MASK,
335 RTS5264_LDO3_LMT_THD_1500);
336
337 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
338 RTS5264_TUNE_VROV_MASK, RTS5264_TUNE_VROV_1V6);
339
340 mask = SD_OCP_GLITCH_MASK | SDVIO_OCP_GLITCH_MASK;
341 val = pcr->hw_param.ocp_glitch;
342 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
343
344 } else {
345 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
346 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);
347 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
348 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);
349 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
350 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);
351 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
352 RTS5264_POW_VDET, 0);
353 }
354 }
355
rts5264_get_ocpstat2(struct rtsx_pcr * pcr,u8 * val)356 static int rts5264_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
357 {
358 return rtsx_pci_read_register(pcr, RTS5264_OCP_VDD3_STS, val);
359 }
360
rts5264_get_ovpstat(struct rtsx_pcr * pcr,u8 * val)361 static int rts5264_get_ovpstat(struct rtsx_pcr *pcr, u8 *val)
362 {
363 return rtsx_pci_read_register(pcr, RTS5264_OVP_STS, val);
364 }
365
rts5264_clear_ocpstat(struct rtsx_pcr * pcr)366 static void rts5264_clear_ocpstat(struct rtsx_pcr *pcr)
367 {
368 u8 mask = 0;
369 u8 val = 0;
370
371 mask = SD_OCP_INT_CLR | SD_OC_CLR;
372 mask |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR;
373 val = mask;
374 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
375 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,
376 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR,
377 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR);
378 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,
379 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR,
380 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR);
381
382 udelay(1000);
383
384 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
385 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,
386 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR, 0);
387 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,
388 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR, 0);
389 }
390
rts5264_process_ocp(struct rtsx_pcr * pcr)391 static void rts5264_process_ocp(struct rtsx_pcr *pcr)
392 {
393 if (!pcr->option.ocp_en)
394 return;
395
396 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
397 rts5264_get_ocpstat2(pcr, &pcr->ocp_stat2);
398 rts5264_get_ovpstat(pcr, &pcr->ovp_stat);
399
400 if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) ||
401 (pcr->ocp_stat2 & (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) ||
402 (pcr->ovp_stat & (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) {
403 rts5264_clear_ocpstat(pcr);
404 rts5264_card_power_off(pcr, RTSX_SD_CARD);
405 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
406 pcr->ocp_stat = 0;
407 pcr->ocp_stat2 = 0;
408 pcr->ovp_stat = 0;
409 }
410 }
411
rts5264_init_from_hw(struct rtsx_pcr * pcr)412 static void rts5264_init_from_hw(struct rtsx_pcr *pcr)
413 {
414 struct pci_dev *pdev = pcr->pci;
415 u32 lval1, lval2, i;
416 u16 setting_reg1, setting_reg2, phy_val;
417 u8 valid, efuse_valid, tmp, efuse_len;
418
419 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
420 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
421 REG_EFUSE_POR | REG_EFUSE_POWERON);
422 udelay(1);
423 rtsx_pci_write_register(pcr, RTS5264_EFUSE_ADDR,
424 RTS5264_EFUSE_ADDR_MASK, 0x00);
425 rtsx_pci_write_register(pcr, RTS5264_EFUSE_CTL,
426 RTS5264_EFUSE_ENABLE | RTS5264_EFUSE_MODE_MASK,
427 RTS5264_EFUSE_ENABLE);
428
429 /* Wait transfer end */
430 for (i = 0; i < MAX_RW_REG_CNT; i++) {
431 rtsx_pci_read_register(pcr, RTS5264_EFUSE_CTL, &tmp);
432 if ((tmp & 0x80) == 0)
433 break;
434 }
435 rtsx_pci_read_register(pcr, RTS5264_EFUSE_READ_DATA, &tmp);
436 efuse_len = ((tmp & 0x70) >> 4);
437 pcr_dbg(pcr, "Load efuse len: 0x%x\n", efuse_len);
438 efuse_valid = ((tmp & 0x0C) >> 2);
439 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
440
441 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
442 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
443 /* 0x816 */
444 valid = (u8)((lval2 >> 16) & 0x03);
445
446 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
447 REG_EFUSE_POR, 0);
448 pcr_dbg(pcr, "Disable efuse por!\n");
449
450 if (is_version(pcr, PID_5264, RTS5264_IC_VER_B)) {
451 pci_write_config_dword(pdev, 0x718, 0x0007C000);
452 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE, 0xFF, 0x88);
453 rtsx_pci_read_phy_register(pcr, _PHY_REV0, &phy_val);
454 phy_val &= 0xFFFD;
455
456 if (efuse_len == 0) {
457 rtsx_pci_write_register(pcr, RTS5264_FW_CFG_INFO2, 0x0F, 0x0F);
458 rtsx_pci_write_register(pcr, 0xFF14, 0xFF, 0x79);
459 rtsx_pci_write_register(pcr, 0xFF15, 0xFF, 0xFF);
460 rtsx_pci_write_register(pcr, 0xFF16, 0xFF, 0x3D);
461 rtsx_pci_write_register(pcr, 0xFF17, 0xFF, 0xFE);
462
463 rtsx_pci_write_register(pcr, 0xFF18, 0xFF, 0x5B);
464 rtsx_pci_write_register(pcr, 0xFF19, 0xFF, 0xFF);
465 rtsx_pci_write_register(pcr, 0xFF1A, 0xFF, 0x3E);
466 rtsx_pci_write_register(pcr, 0xFF1B, 0xFF, 0xFE);
467
468 rtsx_pci_write_register(pcr, 0xFF1C, 0xFF, 0x00);
469 rtsx_pci_write_register(pcr, 0xFF1D, 0xFF, 0xFF);
470 rtsx_pci_write_register(pcr, 0xFF1E, 0xFF, 0x3F);
471 rtsx_pci_write_register(pcr, 0xFF1F, 0xFF, 0xFE);
472
473 rtsx_pci_write_register(pcr, 0xFF20, 0xFF, 0x81);
474 rtsx_pci_write_register(pcr, 0xFF21, 0xFF, 0xFF);
475 rtsx_pci_write_register(pcr, 0xFF22, 0xFF, 0x3C);
476 rtsx_pci_write_register(pcr, 0xFF23, 0xFF, 0xFE);
477 }
478
479 rtsx_pci_write_register(pcr, 0xFF24, 0xFF, 0x79);
480 rtsx_pci_write_register(pcr, 0xFF25, 0xFF, 0x5B);
481 rtsx_pci_write_register(pcr, 0xFF26, 0xFF, 0x00);
482 rtsx_pci_write_register(pcr, 0xFF27, 0xFF, 0x40);
483
484 rtsx_pci_write_register(pcr, 0xFF28, 0xFF, (u8)phy_val);
485 rtsx_pci_write_register(pcr, 0xFF29, 0xFF, (u8)(phy_val >> 8));
486 rtsx_pci_write_register(pcr, 0xFF2A, 0xFF, 0x19);
487 rtsx_pci_write_register(pcr, 0xFF2B, 0xFF, 0x40);
488
489 rtsx_pci_write_register(pcr, 0xFF2C, 0xFF, 0x20);
490 rtsx_pci_write_register(pcr, 0xFF2D, 0xFF, 0xDA);
491 rtsx_pci_write_register(pcr, 0xFF2E, 0xFF, 0x0A);
492 rtsx_pci_write_register(pcr, 0xFF2F, 0xFF, 0x40);
493
494 rtsx_pci_write_register(pcr, 0xFF30, 0xFF, 0x20);
495 rtsx_pci_write_register(pcr, 0xFF31, 0xFF, 0xD2);
496 rtsx_pci_write_register(pcr, 0xFF32, 0xFF, 0x0A);
497 rtsx_pci_write_register(pcr, 0xFF33, 0xFF, 0x40);
498 } else {
499 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE, 0x80, 0x80);
500 }
501
502 if (efuse_valid == 2 || efuse_valid == 3) {
503 if (valid == 3) {
504 /* Bypass efuse */
505 setting_reg1 = PCR_SETTING_REG1;
506 setting_reg2 = PCR_SETTING_REG2;
507 } else {
508 /* Use efuse data */
509 setting_reg1 = PCR_SETTING_REG4;
510 setting_reg2 = PCR_SETTING_REG5;
511 }
512 } else if (efuse_valid == 0) {
513 // default
514 setting_reg1 = PCR_SETTING_REG1;
515 setting_reg2 = PCR_SETTING_REG2;
516 } else {
517 return;
518 }
519
520 pci_read_config_dword(pdev, setting_reg2, &lval2);
521 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
522
523 if (!rts5264_vendor_setting_valid(lval2)) {
524 pcr_dbg(pcr, "skip fetch vendor setting\n");
525 return;
526 }
527
528 pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);
529
530 if (rts5264_reg_check_reverse_socket(lval2))
531 pcr->flags |= PCR_REVERSE_SOCKET;
532
533 pci_read_config_dword(pdev, setting_reg1, &lval1);
534 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
535
536 pcr->aspm_en = rts5264_reg_to_aspm(lval1);
537 pcr->sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1);
538 pcr->sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1);
539
540 if (setting_reg1 == PCR_SETTING_REG1) {
541 /* store setting */
542 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
543 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
544 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
545 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
546 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
547 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
548 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
549
550 pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
551 lval2 = lval2 & 0x00FFFFFF;
552 pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
553 }
554 }
555
rts5264_init_from_cfg(struct rtsx_pcr * pcr)556 static void rts5264_init_from_cfg(struct rtsx_pcr *pcr)
557 {
558 struct rtsx_cr_option *option = &pcr->option;
559
560 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
561 | PM_L1_1_EN | PM_L1_2_EN))
562 rtsx_pci_disable_oobs_polling(pcr);
563 else
564 rtsx_pci_enable_oobs_polling(pcr);
565
566 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
567
568 if (option->ltr_en) {
569 if (option->ltr_enabled)
570 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
571 }
572 }
573
rts5264_extra_init_hw(struct rtsx_pcr * pcr)574 static int rts5264_extra_init_hw(struct rtsx_pcr *pcr)
575 {
576 struct rtsx_cr_option *option = &pcr->option;
577
578 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,
579 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
580 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
581
582 rts5264_init_from_cfg(pcr);
583 rts5264_init_from_hw(pcr);
584
585 /* power off efuse */
586 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
587 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
588 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,
589 RTS5264_CHIP_RST_N_SEL, 0);
590 rtsx_pci_write_register(pcr, RTS5264_REG_LDO12_CFG,
591 RTS5264_LDO12_SR_MASK, RTS5264_LDO12_SR_0_0_MS);
592 rtsx_pci_write_register(pcr, CDGW, 0xFF, 0x01);
593 rtsx_pci_write_register(pcr, RTS5264_CKMUX_MBIAS_PWR,
594 RTS5264_POW_CKMUX, RTS5264_POW_CKMUX);
595 rtsx_pci_write_register(pcr, RTS5264_CMD_OE_START_EARLY,
596 RTS5264_CMD_OE_EARLY_EN | RTS5264_CMD_OE_EARLY_CYCLE_MASK,
597 RTS5264_CMD_OE_EARLY_EN);
598 rtsx_pci_write_register(pcr, RTS5264_DAT_OE_START_EARLY,
599 RTS5264_DAT_OE_EARLY_EN | RTS5264_DAT_OE_EARLY_CYCLE_MASK,
600 RTS5264_DAT_OE_EARLY_EN);
601 rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
602
603 rtsx_pci_write_register(pcr, RTS5264_PWR_CUT,
604 RTS5264_CFG_MEM_PD, RTS5264_CFG_MEM_PD);
605 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
606 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
607 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
608 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
609 RTS5264_AUX_CLK_16M_EN, 0);
610
611 /* Release PRSNT# */
612 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
613 RTS5264_FORCE_PRSNT_LOW, 0);
614 rtsx_pci_write_register(pcr, PCLK_CTL,
615 PCLK_MODE_SEL, PCLK_MODE_SEL);
616
617 /* LED shine disabled, set initial shine cycle period */
618 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
619
620 /* Configure driving */
621 rts5264_fill_driving(pcr, OUTPUT_3V3);
622
623 if (pcr->flags & PCR_REVERSE_SOCKET)
624 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
625 else
626 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
627
628 /*
629 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
630 * to drive low, and we forcibly request clock.
631 */
632 if (option->force_clkreq_0)
633 rtsx_pci_write_register(pcr, PETXCFG,
634 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
635 else
636 rtsx_pci_write_register(pcr, PETXCFG,
637 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
638
639 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFF);
640 rtsx_pci_write_register(pcr, RBCTL, U_AUTO_DMA_EN_MASK, 0);
641 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
642 RTS5264_F_HIGH_RC_MASK, RTS5264_F_HIGH_RC_400K);
643
644 if (pcr->rtd3_en) {
645 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
646 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
647 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
648 } else {
649 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
650 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
651 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
652 }
653 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
654
655 /* Clear Enter RTD3_cold Information*/
656 rtsx_pci_write_register(pcr, RTS5264_FW_CTL,
657 RTS5264_INFORM_RTD3_COLD, 0);
658
659 return 0;
660 }
661
rts5264_optimize_phy(struct rtsx_pcr * pcr)662 static int rts5264_optimize_phy(struct rtsx_pcr *pcr)
663 {
664 u16 subvendor, subdevice, val;
665
666 subvendor = pcr->pci->subsystem_vendor;
667 subdevice = pcr->pci->subsystem_device;
668
669 if ((subvendor == 0x1028) && (subdevice == 0x0CE1)) {
670 rtsx_pci_read_phy_register(pcr, _PHY_REV0, &val);
671 if ((val & 0xFE00) > 0x3800)
672 rtsx_pci_update_phy(pcr, _PHY_REV0, 0x1FF, 0x3800);
673 }
674
675 if (is_version(pcr, PID_5264, RTS5264_IC_VER_B))
676 rtsx_pci_write_phy_register(pcr, 0x00, 0x5B79);
677
678 return 0;
679 }
680
rts5264_enable_aspm(struct rtsx_pcr * pcr,bool enable)681 static void rts5264_enable_aspm(struct rtsx_pcr *pcr, bool enable)
682 {
683 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
684 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
685
686 if (pcr->aspm_enabled == enable)
687 return;
688
689 val |= (pcr->aspm_en & 0x02);
690 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
691 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
692 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
693 pcr->aspm_enabled = enable;
694 }
695
rts5264_disable_aspm(struct rtsx_pcr * pcr,bool enable)696 static void rts5264_disable_aspm(struct rtsx_pcr *pcr, bool enable)
697 {
698 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
699 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
700
701 if (pcr->aspm_enabled == enable)
702 return;
703
704 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
705 PCI_EXP_LNKCTL_ASPMC, 0);
706 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
707 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
708 udelay(10);
709 pcr->aspm_enabled = enable;
710 }
711
rts5264_set_aspm(struct rtsx_pcr * pcr,bool enable)712 static void rts5264_set_aspm(struct rtsx_pcr *pcr, bool enable)
713 {
714 if (enable)
715 rts5264_enable_aspm(pcr, true);
716 else
717 rts5264_disable_aspm(pcr, false);
718 }
719
rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr * pcr,int active)720 static void rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
721 {
722 struct rtsx_cr_option *option = &(pcr->option);
723
724 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
725 int card_exist = (interrupt & SD_EXIST);
726 int aspm_L1_1, aspm_L1_2;
727 u8 val = 0;
728
729 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
730 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
731
732 if (active) {
733 /* Run, latency: 60us */
734 if (aspm_L1_1)
735 val = option->ltr_l1off_snooze_sspwrgate;
736 } else {
737 /* L1off, latency: 300us */
738 if (aspm_L1_2)
739 val = option->ltr_l1off_sspwrgate;
740 }
741
742 if (aspm_L1_1 || aspm_L1_2) {
743 if (rtsx_check_dev_flag(pcr,
744 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
745 if (card_exist)
746 val &= ~L1OFF_MBIAS2_EN_5250;
747 else
748 val |= L1OFF_MBIAS2_EN_5250;
749 }
750 }
751 rtsx_set_l1off_sub(pcr, val);
752 }
753
754 static const struct pcr_ops rts5264_pcr_ops = {
755 .turn_on_led = rts5264_turn_on_led,
756 .turn_off_led = rts5264_turn_off_led,
757 .extra_init_hw = rts5264_extra_init_hw,
758 .optimize_phy = rts5264_optimize_phy,
759 .enable_auto_blink = rts5264_enable_auto_blink,
760 .disable_auto_blink = rts5264_disable_auto_blink,
761 .card_power_on = rts5264_card_power_on,
762 .card_power_off = rts5264_card_power_off,
763 .switch_output_voltage = rts5264_switch_output_voltage,
764 .force_power_down = rts5264_force_power_down,
765 .stop_cmd = rts5264_stop_cmd,
766 .set_aspm = rts5264_set_aspm,
767 .set_l1off_cfg_sub_d0 = rts5264_set_l1off_cfg_sub_d0,
768 .enable_ocp = rts5264_enable_ocp,
769 .disable_ocp = rts5264_disable_ocp,
770 .init_ocp = rts5264_init_ocp,
771 .process_ocp = rts5264_process_ocp,
772 .clear_ocpstat = rts5264_clear_ocpstat,
773 };
774
double_ssc_depth(u8 depth)775 static inline u8 double_ssc_depth(u8 depth)
776 {
777 return ((depth > 1) ? (depth - 1) : depth);
778 }
779
rts5264_pci_switch_clock(struct rtsx_pcr * pcr,unsigned int card_clock,u8 ssc_depth,bool initial_mode,bool double_clk,bool vpclk)780 int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
781 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
782 {
783 int err, clk;
784 u16 n;
785 u8 clk_divider, mcu_cnt, div;
786 static const u8 depth[] = {
787 [RTSX_SSC_DEPTH_4M] = RTS5264_SSC_DEPTH_4M,
788 [RTSX_SSC_DEPTH_2M] = RTS5264_SSC_DEPTH_2M,
789 [RTSX_SSC_DEPTH_1M] = RTS5264_SSC_DEPTH_1M,
790 [RTSX_SSC_DEPTH_500K] = RTS5264_SSC_DEPTH_512K,
791 };
792
793 if (initial_mode) {
794 /* We use 250k(around) here, in initial stage */
795 clk_divider = SD_CLK_DIVIDE_128;
796 card_clock = 30000000;
797 } else {
798 clk_divider = SD_CLK_DIVIDE_0;
799 }
800 err = rtsx_pci_write_register(pcr, SD_CFG1,
801 SD_CLK_DIVIDE_MASK, clk_divider);
802 if (err < 0)
803 return err;
804
805 card_clock /= 1000000;
806 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
807
808 clk = card_clock;
809 if (!initial_mode && double_clk)
810 clk = card_clock * 2;
811 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
812 clk, pcr->cur_clock);
813
814 if (clk == pcr->cur_clock)
815 return 0;
816
817 if (pcr->ops->conv_clk_and_div_n)
818 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
819 else
820 n = clk - 4;
821 if ((clk <= 4) || (n > 396))
822 return -EINVAL;
823
824 mcu_cnt = 125/clk + 3;
825 if (mcu_cnt > 15)
826 mcu_cnt = 15;
827
828 div = CLK_DIV_1;
829 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
830 if (pcr->ops->conv_clk_and_div_n) {
831 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
832 DIV_N_TO_CLK) * 2;
833 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
834 CLK_TO_DIV_N);
835 } else {
836 n = (n + 4) * 2 - 4;
837 }
838 div++;
839 }
840
841 n = (n / 2) - 1;
842 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
843
844 ssc_depth = depth[ssc_depth];
845 if (double_clk)
846 ssc_depth = double_ssc_depth(ssc_depth);
847
848 if (ssc_depth) {
849 if (div == CLK_DIV_2) {
850 if (ssc_depth > 1)
851 ssc_depth -= 1;
852 else
853 ssc_depth = RTS5264_SSC_DEPTH_8M;
854 } else if (div == CLK_DIV_4) {
855 if (ssc_depth > 2)
856 ssc_depth -= 2;
857 else
858 ssc_depth = RTS5264_SSC_DEPTH_8M;
859 } else if (div == CLK_DIV_8) {
860 if (ssc_depth > 3)
861 ssc_depth -= 3;
862 else
863 ssc_depth = RTS5264_SSC_DEPTH_8M;
864 }
865 } else {
866 ssc_depth = 0;
867 }
868 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
869
870 rtsx_pci_init_cmd(pcr);
871 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
872 CHANGE_CLK, CHANGE_CLK);
873 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
874 0xFF, (div << 4) | mcu_cnt);
875 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
876 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
877 SSC_DEPTH_MASK, ssc_depth);
878 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
879
880 if (is_version(pcr, PID_5264, RTS5264_IC_VER_A)) {
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
882 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_CARD_CLK_SRC2,
883 RTS5264_REG_BIG_KVCO_A, 0);
884 } else {
885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_SYS_DUMMY_1,
887 RTS5264_REG_BIG_KVCO, 0);
888 }
889
890 if (vpclk) {
891 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
892 PHASE_NOT_RESET, 0);
893 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
894 PHASE_NOT_RESET, 0);
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
896 PHASE_NOT_RESET, PHASE_NOT_RESET);
897 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
898 PHASE_NOT_RESET, PHASE_NOT_RESET);
899 }
900
901 err = rtsx_pci_send_cmd(pcr, 2000);
902 if (err < 0)
903 return err;
904
905 /* Wait SSC clock stable */
906 udelay(SSC_CLOCK_STABLE_WAIT);
907 err = rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
908 if (err < 0)
909 return err;
910
911 pcr->cur_clock = clk;
912 return 0;
913 }
914
rts5264_init_params(struct rtsx_pcr * pcr)915 void rts5264_init_params(struct rtsx_pcr *pcr)
916 {
917 struct rtsx_cr_option *option = &pcr->option;
918 struct rtsx_hw_param *hw_param = &pcr->hw_param;
919 u8 val;
920
921 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
922 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
923 rtsx_pci_read_register(pcr, RTS5264_FW_STATUS, &val);
924 if (!(val & RTS5264_EXPRESS_LINK_FAIL_MASK))
925 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
926 pcr->num_slots = 1;
927 pcr->ops = &rts5264_pcr_ops;
928
929 pcr->flags = 0;
930 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
931 pcr->sd30_drive_sel_1v8 = 0x00;
932 pcr->sd30_drive_sel_3v3 = 0x00;
933 pcr->aspm_en = ASPM_L1_EN;
934 pcr->aspm_mode = ASPM_MODE_REG;
935 pcr->tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11);
936 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
937
938 pcr->ic_version = rts5264_get_ic_version(pcr);
939 pcr->sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl;
940 pcr->sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl;
941
942 pcr->reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3;
943
944 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
945 | LTR_L1SS_PWR_GATE_EN);
946 option->ltr_en = true;
947
948 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
949 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
950 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
951 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
952 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
953 option->ltr_l1off_sspwrgate = 0x7F;
954 option->ltr_l1off_snooze_sspwrgate = 0x78;
955
956 option->ocp_en = 1;
957 hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);
958 hw_param->ocp_glitch = SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;
959 option->sd_800mA_ocp_thd = RTS5264_LDO1_OCP_THD_1150;
960 }
961