1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../cam.h"
8 #include "../ps.h"
9 #include "../usb.h"
10 #include "reg.h"
11 #include "def.h"
12 #include "phy.h"
13 #include "../rtl8192c/phy_common.h"
14 #include "mac.h"
15 #include "dm.h"
16 #include "../rtl8192c/dm_common.h"
17 #include "../rtl8192c/fw_common.h"
18 #include "hw.h"
19 #include "../rtl8192ce/hw.h"
20 #include "trx.h"
21 #include "led.h"
22 #include "table.h"
23
_rtl92cu_phy_param_tab_init(struct ieee80211_hw * hw)24 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
25 {
26 struct rtl_priv *rtlpriv = rtl_priv(hw);
27 struct rtl_phy *rtlphy = &(rtlpriv->phy);
28 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
29
30 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
31 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
32 if (IS_HIGHT_PA(rtlefuse->board_type)) {
33 rtlphy->hwparam_tables[PHY_REG_PG].length =
34 RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH;
35 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
36 RTL8192CUPHY_REG_ARRAY_PG_HP;
37 } else {
38 rtlphy->hwparam_tables[PHY_REG_PG].length =
39 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
40 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
41 RTL8192CUPHY_REG_ARRAY_PG;
42 }
43 /* 2T */
44 rtlphy->hwparam_tables[PHY_REG_2T].length =
45 RTL8192CUPHY_REG_2TARRAY_LENGTH;
46 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
47 RTL8192CUPHY_REG_2TARRAY;
48 rtlphy->hwparam_tables[RADIOA_2T].length =
49 RTL8192CURADIOA_2TARRAYLENGTH;
50 rtlphy->hwparam_tables[RADIOA_2T].pdata =
51 RTL8192CURADIOA_2TARRAY;
52 rtlphy->hwparam_tables[RADIOB_2T].length =
53 RTL8192CURADIOB_2TARRAYLENGTH;
54 rtlphy->hwparam_tables[RADIOB_2T].pdata =
55 RTL8192CU_RADIOB_2TARRAY;
56 rtlphy->hwparam_tables[AGCTAB_2T].length =
57 RTL8192CUAGCTAB_2TARRAYLENGTH;
58 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
59 RTL8192CUAGCTAB_2TARRAY;
60 /* 1T */
61 if (IS_HIGHT_PA(rtlefuse->board_type)) {
62 rtlphy->hwparam_tables[PHY_REG_1T].length =
63 RTL8192CUPHY_REG_1T_HPARRAYLENGTH;
64 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
65 RTL8192CUPHY_REG_1T_HPARRAY;
66 rtlphy->hwparam_tables[RADIOA_1T].length =
67 RTL8192CURADIOA_1T_HPARRAYLENGTH;
68 rtlphy->hwparam_tables[RADIOA_1T].pdata =
69 RTL8192CURADIOA_1T_HPARRAY;
70 rtlphy->hwparam_tables[RADIOB_1T].length =
71 RTL8192CURADIOB_1TARRAYLENGTH;
72 rtlphy->hwparam_tables[RADIOB_1T].pdata =
73 RTL8192CU_RADIOB_1TARRAY;
74 rtlphy->hwparam_tables[AGCTAB_1T].length =
75 RTL8192CUAGCTAB_1T_HPARRAYLENGTH;
76 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
77 RTL8192CUAGCTAB_1T_HPARRAY;
78 } else {
79 rtlphy->hwparam_tables[PHY_REG_1T].length =
80 RTL8192CUPHY_REG_1TARRAY_LENGTH;
81 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
82 RTL8192CUPHY_REG_1TARRAY;
83 rtlphy->hwparam_tables[RADIOA_1T].length =
84 RTL8192CURADIOA_1TARRAYLENGTH;
85 rtlphy->hwparam_tables[RADIOA_1T].pdata =
86 RTL8192CU_RADIOA_1TARRAY;
87 rtlphy->hwparam_tables[RADIOB_1T].length =
88 RTL8192CURADIOB_1TARRAYLENGTH;
89 rtlphy->hwparam_tables[RADIOB_1T].pdata =
90 RTL8192CU_RADIOB_1TARRAY;
91 rtlphy->hwparam_tables[AGCTAB_1T].length =
92 RTL8192CUAGCTAB_1TARRAYLENGTH;
93 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
94 RTL8192CUAGCTAB_1TARRAY;
95 }
96 }
97
98 static noinline_for_stack void
_rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)99 _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
100 bool autoload_fail, u8 *hwinfo)
101 {
102 struct rtl_priv *rtlpriv = rtl_priv(hw);
103 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
104 u8 rf_path, index, tempval;
105 u16 i;
106
107 for (rf_path = 0; rf_path < 2; rf_path++) {
108 for (i = 0; i < 3; i++) {
109 if (!autoload_fail) {
110 rtlefuse->
111 eeprom_chnlarea_txpwr_cck[rf_path][i] =
112 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
113 rtlefuse->
114 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
115 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
116 i];
117 } else {
118 rtlefuse->
119 eeprom_chnlarea_txpwr_cck[rf_path][i] =
120 EEPROM_DEFAULT_TXPOWERLEVEL;
121 rtlefuse->
122 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
123 EEPROM_DEFAULT_TXPOWERLEVEL;
124 }
125 }
126 }
127 for (i = 0; i < 3; i++) {
128 if (!autoload_fail)
129 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
130 else
131 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
132 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
133 (tempval & 0xf);
134 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
135 ((tempval & 0xf0) >> 4);
136 }
137 for (rf_path = 0; rf_path < 2; rf_path++)
138 for (i = 0; i < 3; i++)
139 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
141 rf_path, i,
142 rtlefuse->
143 eeprom_chnlarea_txpwr_cck[rf_path][i]);
144 for (rf_path = 0; rf_path < 2; rf_path++)
145 for (i = 0; i < 3; i++)
146 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
147 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
148 rf_path, i,
149 rtlefuse->
150 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
151 for (rf_path = 0; rf_path < 2; rf_path++)
152 for (i = 0; i < 3; i++)
153 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
154 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
155 rf_path, i,
156 rtlefuse->
157 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
158 for (rf_path = 0; rf_path < 2; rf_path++) {
159 for (i = 0; i < 14; i++) {
160 index = rtl92c_get_chnl_group((u8)i);
161 rtlefuse->txpwrlevel_cck[rf_path][i] =
162 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
163 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
164 rtlefuse->
165 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
166 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
167 max(rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
168 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][index], 0);
169 }
170 for (i = 0; i < 14; i++) {
171 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
172 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
173 rtlefuse->txpwrlevel_cck[rf_path][i],
174 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
175 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
176 }
177 }
178 for (i = 0; i < 3; i++) {
179 if (!autoload_fail) {
180 rtlefuse->eeprom_pwrlimit_ht40[i] =
181 hwinfo[EEPROM_TXPWR_GROUP + i];
182 rtlefuse->eeprom_pwrlimit_ht20[i] =
183 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
184 } else {
185 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
186 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
187 }
188 }
189 for (rf_path = 0; rf_path < 2; rf_path++) {
190 for (i = 0; i < 14; i++) {
191 index = rtl92c_get_chnl_group((u8)i);
192 if (rf_path == RF90_PATH_A) {
193 rtlefuse->pwrgroup_ht20[rf_path][i] =
194 (rtlefuse->eeprom_pwrlimit_ht20[index]
195 & 0xf);
196 rtlefuse->pwrgroup_ht40[rf_path][i] =
197 (rtlefuse->eeprom_pwrlimit_ht40[index]
198 & 0xf);
199 } else if (rf_path == RF90_PATH_B) {
200 rtlefuse->pwrgroup_ht20[rf_path][i] =
201 ((rtlefuse->eeprom_pwrlimit_ht20[index]
202 & 0xf0) >> 4);
203 rtlefuse->pwrgroup_ht40[rf_path][i] =
204 ((rtlefuse->eeprom_pwrlimit_ht40[index]
205 & 0xf0) >> 4);
206 }
207 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
208 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
209 rf_path, i,
210 rtlefuse->pwrgroup_ht20[rf_path][i]);
211 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
212 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
213 rf_path, i,
214 rtlefuse->pwrgroup_ht40[rf_path][i]);
215 }
216 }
217 for (i = 0; i < 14; i++) {
218 index = rtl92c_get_chnl_group((u8)i);
219 if (!autoload_fail)
220 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
221 else
222 tempval = EEPROM_DEFAULT_HT20_DIFF;
223 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
224 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
225 ((tempval >> 4) & 0xF);
226 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
227 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
228 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
229 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
230 index = rtl92c_get_chnl_group((u8)i);
231 if (!autoload_fail)
232 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
233 else
234 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
235 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
236 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
237 ((tempval >> 4) & 0xF);
238 }
239 rtlefuse->legacy_ht_txpowerdiff =
240 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
241 for (i = 0; i < 14; i++)
242 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
243 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
244 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
245 for (i = 0; i < 14; i++)
246 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
247 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
248 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
249 for (i = 0; i < 14; i++)
250 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
251 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
252 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
253 for (i = 0; i < 14; i++)
254 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
255 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
256 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
257 if (!autoload_fail)
258 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
259 else
260 rtlefuse->eeprom_regulatory = 0;
261 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
262 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
263 if (!autoload_fail) {
264 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
265 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
266 } else {
267 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
268 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
269 }
270 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
271 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
272 rtlefuse->eeprom_tssi[RF90_PATH_A],
273 rtlefuse->eeprom_tssi[RF90_PATH_B]);
274 if (!autoload_fail)
275 tempval = hwinfo[EEPROM_THERMAL_METER];
276 else
277 tempval = EEPROM_DEFAULT_THERMALMETER;
278 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
279 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
280 rtlefuse->eeprom_thermalmeter > 0x1c)
281 rtlefuse->eeprom_thermalmeter = 0x12;
282 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
283 rtlefuse->apk_thermalmeterignore = true;
284 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
285 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
286 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
287 }
288
_rtl92cu_read_board_type(struct ieee80211_hw * hw,u8 * contents)289 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
290 {
291 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
292 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
293 u8 boardtype;
294
295 if (IS_NORMAL_CHIP(rtlhal->version)) {
296 boardtype = ((contents[EEPROM_RF_OPT1]) &
297 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
298 } else {
299 boardtype = contents[EEPROM_RF_OPT4];
300 boardtype &= BOARD_TYPE_TEST_MASK;
301 }
302 rtlefuse->board_type = boardtype;
303 if (IS_HIGHT_PA(rtlefuse->board_type))
304 rtlefuse->external_pa = 1;
305 pr_info("Board Type %x\n", rtlefuse->board_type);
306 }
307
_rtl92cu_read_adapter_info(struct ieee80211_hw * hw)308 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
309 {
310 struct rtl_priv *rtlpriv = rtl_priv(hw);
311 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
312 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
313 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
314 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
315 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
316 0};
317 u8 *hwinfo;
318
319 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
320 if (!hwinfo)
321 return;
322
323 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
324 goto exit;
325
326 _rtl92cu_read_txpower_info_from_hwpg(hw,
327 rtlefuse->autoload_failflag, hwinfo);
328 _rtl92cu_read_board_type(hw, hwinfo);
329
330 rtlefuse->txpwr_fromeprom = true;
331 if (rtlhal->oem_id == RT_CID_DEFAULT) {
332 switch (rtlefuse->eeprom_oemid) {
333 case EEPROM_CID_DEFAULT:
334 if (rtlefuse->eeprom_did == 0x8176) {
335 if ((rtlefuse->eeprom_svid == 0x103C &&
336 rtlefuse->eeprom_smid == 0x1629))
337 rtlhal->oem_id = RT_CID_819X_HP;
338 else
339 rtlhal->oem_id = RT_CID_DEFAULT;
340 } else {
341 rtlhal->oem_id = RT_CID_DEFAULT;
342 }
343 break;
344 case EEPROM_CID_TOSHIBA:
345 rtlhal->oem_id = RT_CID_TOSHIBA;
346 break;
347 case EEPROM_CID_QMI:
348 rtlhal->oem_id = RT_CID_819X_QMI;
349 break;
350 case EEPROM_CID_WHQL:
351 default:
352 rtlhal->oem_id = RT_CID_DEFAULT;
353 break;
354 }
355 }
356 exit:
357 kfree(hwinfo);
358 }
359
_rtl92cu_hal_customized_behavior(struct ieee80211_hw * hw)360 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
361 {
362 struct rtl_priv *rtlpriv = rtl_priv(hw);
363 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
364
365 switch (rtlhal->oem_id) {
366 case RT_CID_819X_HP:
367 rtlpriv->ledctl.led_opendrain = true;
368 break;
369 case RT_CID_819X_LENOVO:
370 case RT_CID_DEFAULT:
371 case RT_CID_TOSHIBA:
372 case RT_CID_CCX:
373 case RT_CID_819X_ACER:
374 case RT_CID_WHQL:
375 default:
376 break;
377 }
378 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
379 rtlhal->oem_id);
380 }
381
rtl92cu_read_eeprom_info(struct ieee80211_hw * hw)382 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
383 {
384
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
387 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
388 u8 tmp_u1b;
389
390 if (!IS_NORMAL_CHIP(rtlhal->version))
391 return;
392 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
393 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
394 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
395 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
396 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
397 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
398 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
399 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
400 _rtl92cu_read_adapter_info(hw);
401 _rtl92cu_hal_customized_behavior(hw);
402 return;
403 }
404
_rtl92cu_init_power_on(struct ieee80211_hw * hw)405 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
406 {
407 struct rtl_priv *rtlpriv = rtl_priv(hw);
408 int status = 0;
409 u16 value16;
410 u8 value8;
411 /* polling autoload done. */
412 u32 pollingcount = 0;
413
414 do {
415 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
416 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
417 "Autoload Done!\n");
418 break;
419 }
420 if (pollingcount++ > 100) {
421 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
422 return -ENODEV;
423 }
424 } while (true);
425 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
426 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
427 /* Power on when re-enter from IPS/Radio off/card disable */
428 /* enable SPS into PWM mode */
429 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
430 udelay(100);
431 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
432 if (0 == (value8 & LDV12_EN)) {
433 value8 |= LDV12_EN;
434 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
435 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
436 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
437 value8);
438 udelay(100);
439 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
440 value8 &= ~ISO_MD2PP;
441 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
442 }
443 /* auto enable WLAN */
444 pollingcount = 0;
445 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
446 value16 |= APFM_ONMAC;
447 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
448 do {
449 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
450 pr_info("MAC auto ON okay!\n");
451 break;
452 }
453 if (pollingcount++ > 1000) {
454 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
455 return -ENODEV;
456 }
457 } while (true);
458 /* Enable Radio ,GPIO ,and LED function */
459 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
460 /* release RF digital isolation */
461 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
462 value16 &= ~ISO_DIOR;
463 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
464 /* Reconsider when to do this operation after asking HWSD. */
465 pollingcount = 0;
466 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
467 REG_APSD_CTRL) & ~BIT(6)));
468 do {
469 pollingcount++;
470 } while ((pollingcount < 200) &&
471 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
472 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
473 value16 = rtl_read_word(rtlpriv, REG_CR);
474 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
475 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
476 rtl_write_word(rtlpriv, REG_CR, value16);
477 return status;
478 }
479
_rtl92cu_init_queue_reserved_page(struct ieee80211_hw * hw,u8 out_ep_num,u8 queue_sel)480 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
481 u8 out_ep_num,
482 u8 queue_sel)
483 {
484 struct rtl_priv *rtlpriv = rtl_priv(hw);
485 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
486 bool ischipn = IS_NORMAL_CHIP(rtlhal->version);
487 u32 outepnum = (u32)out_ep_num;
488 u32 numhq = 0;
489 u32 numlq = 0;
490 u32 numnq = 0;
491 u32 numpubq;
492 u32 value32;
493 u8 value8;
494 u32 txqpagenum, txqpageunit, txqremaininpage;
495
496 numpubq = (ischipn) ? CHIP_B_PAGE_NUM_PUBQ :
497 CHIP_A_PAGE_NUM_PUBQ;
498 txqpagenum = TX_TOTAL_PAGE_NUMBER - numpubq;
499
500 txqpageunit = txqpagenum / outepnum;
501 txqremaininpage = txqpagenum % outepnum;
502 if (queue_sel & TX_SELE_HQ)
503 numhq = txqpageunit;
504 if (queue_sel & TX_SELE_LQ)
505 numlq = txqpageunit;
506 /* HIGH priority queue always present in the configuration of
507 * 2 out-ep. Remainder pages have assigned to High queue.
508 */
509 if (outepnum > 1 && txqremaininpage)
510 numhq += txqremaininpage;
511 /* NOTE: This step done before writing REG_RQPN. */
512 if (ischipn) {
513 if (queue_sel & TX_SELE_NQ)
514 numnq = txqpageunit;
515 value8 = (u8)_NPQ(numnq);
516 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
517 }
518 /* TX DMA */
519 value32 = _HPQ(numhq) | _LPQ(numlq) | _PUBQ(numpubq) | LD_RQPN;
520 rtl_write_dword(rtlpriv, REG_RQPN, value32);
521 }
522
_rtl92c_init_trx_buffer(struct ieee80211_hw * hw)523 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw)
524 {
525 struct rtl_priv *rtlpriv = rtl_priv(hw);
526 u8 txpktbuf_bndy = TX_PAGE_BOUNDARY;
527 u8 value8;
528
529 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
530 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
531 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
532 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
533 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
534 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
535 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
536 rtl_write_byte(rtlpriv, REG_PBP, value8);
537 }
538
_rtl92c_init_chipn_reg_priority(struct ieee80211_hw * hw,u16 beq,u16 bkq,u16 viq,u16 voq,u16 mgtq,u16 hiq)539 static void _rtl92c_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq,
540 u16 bkq, u16 viq, u16 voq,
541 u16 mgtq, u16 hiq)
542 {
543 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
545
546 value16 |= _TXDMA_BEQ_MAP(beq) | _TXDMA_BKQ_MAP(bkq) |
547 _TXDMA_VIQ_MAP(viq) | _TXDMA_VOQ_MAP(voq) |
548 _TXDMA_MGQ_MAP(mgtq) | _TXDMA_HIQ_MAP(hiq);
549 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
550 }
551
_rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw * hw,u8 queue_sel)552 static void _rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw,
553 u8 queue_sel)
554 {
555 u16 value;
556
557 switch (queue_sel) {
558 case TX_SELE_HQ:
559 value = QUEUE_HIGH;
560 break;
561 case TX_SELE_LQ:
562 value = QUEUE_LOW;
563 break;
564 case TX_SELE_NQ:
565 value = QUEUE_NORMAL;
566 break;
567 default:
568 WARN_ON(1); /* Shall not reach here! */
569 return;
570 }
571 _rtl92c_init_chipn_reg_priority(hw, value, value, value, value,
572 value, value);
573 pr_info("Tx queue select: 0x%02x\n", queue_sel);
574 }
575
_rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw * hw,u8 queue_sel)576 static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw,
577 u8 queue_sel)
578 {
579 u16 beq, bkq, viq, voq, mgtq, hiq;
580 u16 valuehi;
581 u16 valuelow;
582
583 switch (queue_sel) {
584 default:
585 WARN_ON(1);
586 fallthrough;
587 case (TX_SELE_HQ | TX_SELE_LQ):
588 valuehi = QUEUE_HIGH;
589 valuelow = QUEUE_LOW;
590 break;
591 case (TX_SELE_NQ | TX_SELE_LQ):
592 valuehi = QUEUE_NORMAL;
593 valuelow = QUEUE_LOW;
594 break;
595 case (TX_SELE_HQ | TX_SELE_NQ):
596 valuehi = QUEUE_HIGH;
597 valuelow = QUEUE_NORMAL;
598 break;
599 }
600
601 beq = valuelow;
602 bkq = valuelow;
603 viq = valuehi;
604 voq = valuehi;
605 mgtq = valuehi;
606 hiq = valuehi;
607
608 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);
609 pr_info("Tx queue select: 0x%02x\n", queue_sel);
610 }
611
_rtl92cu_init_chipn_three_out_ep_priority(struct ieee80211_hw * hw,u8 queue_sel)612 static void _rtl92cu_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw,
613 u8 queue_sel)
614 {
615 u16 beq, bkq, viq, voq, mgtq, hiq;
616
617 beq = QUEUE_LOW;
618 bkq = QUEUE_LOW;
619 viq = QUEUE_NORMAL;
620 voq = QUEUE_HIGH;
621 mgtq = QUEUE_HIGH;
622 hiq = QUEUE_HIGH;
623
624 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);
625 pr_info("Tx queue select :0x%02x..\n", queue_sel);
626 }
627
_rtl92cu_init_chipn_queue_priority(struct ieee80211_hw * hw,u8 out_ep_num,u8 queue_sel)628 static void _rtl92cu_init_chipn_queue_priority(struct ieee80211_hw *hw,
629 u8 out_ep_num,
630 u8 queue_sel)
631 {
632 switch (out_ep_num) {
633 case 1:
634 _rtl92cu_init_chipn_one_out_ep_priority(hw, queue_sel);
635 break;
636 case 2:
637 _rtl92cu_init_chipn_two_out_ep_priority(hw, queue_sel);
638 break;
639 case 3:
640 _rtl92cu_init_chipn_three_out_ep_priority(hw, queue_sel);
641 break;
642 default:
643 WARN_ON(1); /* Shall not reach here! */
644 break;
645 }
646 }
647
_rtl92cu_init_chipt_queue_priority(struct ieee80211_hw * hw,u8 out_ep_num,u8 queue_sel)648 static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw,
649 u8 out_ep_num,
650 u8 queue_sel)
651 {
652 u8 hq_sele = 0;
653 struct rtl_priv *rtlpriv = rtl_priv(hw);
654
655 switch (out_ep_num) {
656 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
657 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | HQSEL_HIQ;
658 break;
659 case 1:
660 if (TX_SELE_LQ == queue_sel) {
661 /* map all endpoint to Low queue */
662 hq_sele = 0;
663 } else if (TX_SELE_HQ == queue_sel) {
664 /* map all endpoint to High queue */
665 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
666 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
667 }
668 break;
669 default:
670 WARN_ON(1); /* Shall not reach here! */
671 break;
672 }
673 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
674 pr_info("Tx queue select :0x%02x..\n", hq_sele);
675 }
676
_rtl92cu_init_queue_priority(struct ieee80211_hw * hw,u8 out_ep_num,u8 queue_sel)677 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
678 u8 out_ep_num,
679 u8 queue_sel)
680 {
681 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
682
683 if (IS_NORMAL_CHIP(rtlhal->version))
684 _rtl92cu_init_chipn_queue_priority(hw, out_ep_num, queue_sel);
685 else
686 _rtl92cu_init_chipt_queue_priority(hw, out_ep_num, queue_sel);
687 }
688
_rtl92cu_init_wmac_setting(struct ieee80211_hw * hw)689 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
690 {
691 u16 value16;
692 u32 value32;
693 struct rtl_priv *rtlpriv = rtl_priv(hw);
694
695 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
696 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
697 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
698 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));
699 /* Accept all multicast address */
700 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
701 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
702 /* Accept all management frames */
703 value16 = 0xFFFF;
704 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
705 (u8 *)(&value16));
706 /* Reject all control frame - default value is 0 */
707 value16 = 0x0;
708 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
709 (u8 *)(&value16));
710 /* Accept all data frames */
711 value16 = 0xFFFF;
712 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,
713 (u8 *)(&value16));
714 }
715
_rtl92cu_init_beacon_parameters(struct ieee80211_hw * hw)716 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)
717 {
718 struct rtl_priv *rtlpriv = rtl_priv(hw);
719 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
720
721 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
722
723 /* TODO: Remove these magic number */
724 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
725 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
726 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
727 /* Change beacon AIFS to the largest number
728 * beacause test chip does not contension before sending beacon.
729 */
730 if (IS_NORMAL_CHIP(rtlhal->version))
731 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
732 else
733 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
734 }
735
_rtl92cu_init_mac(struct ieee80211_hw * hw)736 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
737 {
738 struct rtl_priv *rtlpriv = rtl_priv(hw);
739 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
740 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
741 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
742 int err = 0;
743 u32 boundary = TX_PAGE_BOUNDARY;
744 u8 out_ep_nums = rtlusb->out_ep_nums;
745 u8 queue_sel = rtlusb->out_queue_sel;
746
747 err = _rtl92cu_init_power_on(hw);
748
749 if (err) {
750 pr_err("Failed to init power on!\n");
751 return err;
752 }
753 if (!rtl92c_init_llt_table(hw, boundary)) {
754 pr_err("Failed to init LLT Table!\n");
755 return -EINVAL;
756 }
757 _rtl92cu_init_queue_reserved_page(hw, out_ep_nums, queue_sel);
758 _rtl92c_init_trx_buffer(hw);
759 _rtl92cu_init_queue_priority(hw, out_ep_nums, queue_sel);
760 /* Get Rx PHY status in order to report RSSI and others. */
761 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
762 rtl92c_init_interrupt(hw);
763 rtl92c_init_network_type(hw);
764 _rtl92cu_init_wmac_setting(hw);
765 rtl92c_init_adaptive_ctrl(hw);
766 rtl92c_init_edca(hw);
767 rtl92c_init_rate_fallback(hw);
768 rtl92c_init_retry_function(hw);
769 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
770 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
771 _rtl92cu_init_beacon_parameters(hw);
772 rtl92c_init_ampdu_aggregation(hw);
773 rtl92c_init_beacon_max_error(hw);
774 return err;
775 }
776
rtl92cu_enable_hw_security_config(struct ieee80211_hw * hw)777 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
778 {
779 struct rtl_priv *rtlpriv = rtl_priv(hw);
780 u8 sec_reg_value = 0x0;
781 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
782
783 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
784 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
785 rtlpriv->sec.pairwise_enc_algorithm,
786 rtlpriv->sec.group_enc_algorithm);
787 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
788 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
789 "not open sw encryption\n");
790 return;
791 }
792 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
793 if (rtlpriv->sec.use_defaultkey) {
794 sec_reg_value |= SCR_TXUSEDK;
795 sec_reg_value |= SCR_RXUSEDK;
796 }
797 if (IS_NORMAL_CHIP(rtlhal->version))
798 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
799 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
800 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
801 sec_reg_value);
802 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
803 }
804
_rtl92cu_hw_configure(struct ieee80211_hw * hw)805 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
806 {
807 struct rtl_priv *rtlpriv = rtl_priv(hw);
808 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
809
810 /* To Fix MAC loopback mode fail. */
811 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
812 rtl_write_byte(rtlpriv, 0x15, 0xe9);
813 /* HW SEQ CTRL */
814 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
815 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
816 /* fixed USB interface interference issue */
817 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
818 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
819 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
820 rtlusb->reg_bcn_ctrl_val = 0x18;
821 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
822 }
823
_initpabias(struct ieee80211_hw * hw)824 static void _initpabias(struct ieee80211_hw *hw)
825 {
826 struct rtl_priv *rtlpriv = rtl_priv(hw);
827 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
828 u8 pa_setting;
829
830 /* FIXED PA current issue */
831 pa_setting = efuse_read_1byte(hw, 0x1FA);
832 if (!(pa_setting & BIT(0))) {
833 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
834 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
835 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
836 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
837 }
838 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
839 IS_92C_SERIAL(rtlhal->version)) {
840 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
841 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
842 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
843 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
844 }
845 if (!(pa_setting & BIT(4))) {
846 pa_setting = rtl_read_byte(rtlpriv, 0x16);
847 pa_setting &= 0x0F;
848 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
849 }
850 }
851
rtl92cu_hw_init(struct ieee80211_hw * hw)852 int rtl92cu_hw_init(struct ieee80211_hw *hw)
853 {
854 struct rtl_priv *rtlpriv = rtl_priv(hw);
855 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
856 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
857 struct rtl_phy *rtlphy = &(rtlpriv->phy);
858 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
859 int err = 0;
860 unsigned long flags;
861
862 /* As this function can take a very long time (up to 350 ms)
863 * and can be called with irqs disabled, reenable the irqs
864 * to let the other devices continue being serviced.
865 *
866 * It is safe doing so since our own interrupts will only be enabled
867 * in a subsequent step.
868 */
869 local_save_flags(flags);
870 local_irq_enable();
871
872 rtlhal->fw_ready = false;
873 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
874 err = _rtl92cu_init_mac(hw);
875 if (err) {
876 pr_err("init mac failed!\n");
877 goto exit;
878 }
879 err = rtl92c_download_fw(hw);
880 if (err) {
881 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
882 "Failed to download FW. Init HW without FW now..\n");
883 err = 1;
884 goto exit;
885 }
886
887 rtlhal->fw_ready = true;
888 rtlhal->last_hmeboxnum = 0; /* h2c */
889 _rtl92cu_phy_param_tab_init(hw);
890 rtl92cu_phy_mac_config(hw);
891 rtl92cu_phy_bb_config(hw);
892 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
893 rtl92c_phy_rf_config(hw);
894 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
895 !IS_92C_SERIAL(rtlhal->version)) {
896 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
897 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
898 }
899 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
900 RF_CHNLBW, RFREG_OFFSET_MASK);
901 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
902 RF_CHNLBW, RFREG_OFFSET_MASK);
903 rtl92cu_bb_block_on(hw);
904 rtl_cam_reset_all_entry(hw);
905 rtl92cu_enable_hw_security_config(hw);
906 ppsc->rfpwr_state = ERFON;
907 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
908 if (ppsc->rfpwr_state == ERFON) {
909 rtl92c_phy_set_rfpath_switch(hw, 1);
910 if (rtlphy->iqk_initialized) {
911 rtl92c_phy_iq_calibrate(hw, true);
912 } else {
913 rtl92c_phy_iq_calibrate(hw, false);
914 rtlphy->iqk_initialized = true;
915 }
916 rtl92c_dm_check_txpower_tracking(hw);
917 rtl92c_phy_lc_calibrate(hw);
918 }
919 _rtl92cu_hw_configure(hw);
920 _initpabias(hw);
921 rtl92c_dm_init(hw);
922 exit:
923 local_irq_disable();
924 local_irq_restore(flags);
925 return err;
926 }
927
disable_rfafeandresetbb(struct ieee80211_hw * hw)928 static void disable_rfafeandresetbb(struct ieee80211_hw *hw)
929 {
930 struct rtl_priv *rtlpriv = rtl_priv(hw);
931 /**************************************
932 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
933 b. RF path 0 offset 0x00 = 0x00 disable RF
934 c. APSD_CTRL 0x600[7:0] = 0x40
935 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
936 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
937 ***************************************/
938 u8 erfpath = 0, value8 = 0;
939
940 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
941 rtl_set_rfreg(hw, (enum radio_path)erfpath, 0x0, MASKBYTE0, 0x0);
942
943 value8 |= APSDOFF;
944 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
945 value8 = 0;
946 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTN);
947 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
948 value8 &= (~FEN_BB_GLB_RSTN);
949 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
950 }
951
_resetdigitalprocedure1(struct ieee80211_hw * hw,bool withouthwsm)952 static void _resetdigitalprocedure1(struct ieee80211_hw *hw, bool withouthwsm)
953 {
954 struct rtl_priv *rtlpriv = rtl_priv(hw);
955 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
956
957 if (rtlhal->fw_version <= 0x20) {
958 /*****************************
959 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
960 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
961 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
962 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
963 ******************************/
964 u16 valu16 = 0;
965
966 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
967 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
968 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
969 (~FEN_CPUEN))); /* reset MCU ,8051 */
970 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
971 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
972 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
973 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
974 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
975 FEN_CPUEN)); /* enable MCU ,8051 */
976 } else {
977 u8 retry_cnts = 0;
978
979 /* IF fw in RAM code, do reset */
980 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
981 /* reset MCU ready status */
982 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
983 /* 8051 reset by self */
984 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
985 while ((retry_cnts++ < 100) &&
986 (FEN_CPUEN & rtl_read_word(rtlpriv,
987 REG_SYS_FUNC_EN))) {
988 udelay(50);
989 }
990 if (retry_cnts >= 100) {
991 pr_err("8051 reset failed!.........................\n");
992 /* if 8051 reset fail, reset MAC. */
993 rtl_write_byte(rtlpriv,
994 REG_SYS_FUNC_EN + 1,
995 0x50);
996 udelay(100);
997 }
998 }
999 /* Reset MAC and Enable 8051 */
1000 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1001 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1002 }
1003 if (withouthwsm) {
1004 /*****************************
1005 Without HW auto state machine
1006 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1007 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1008 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1009 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1010 ******************************/
1011 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1012 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1013 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1014 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1015 }
1016 }
1017
_resetdigitalprocedure2(struct ieee80211_hw * hw)1018 static void _resetdigitalprocedure2(struct ieee80211_hw *hw)
1019 {
1020 struct rtl_priv *rtlpriv = rtl_priv(hw);
1021 /*****************************
1022 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1023 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1024 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1025 ******************************/
1026 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1027 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1028 }
1029
_disablegpio(struct ieee80211_hw * hw)1030 static void _disablegpio(struct ieee80211_hw *hw)
1031 {
1032 struct rtl_priv *rtlpriv = rtl_priv(hw);
1033 /***************************************
1034 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1035 k. Value = GPIO_PIN_CTRL[7:0]
1036 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1037 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1038 n. LEDCFG 0x4C[15:0] = 0x8080
1039 ***************************************/
1040 u8 value8;
1041 u16 value16;
1042 u32 value32;
1043
1044 /* 1. Disable GPIO[7:0] */
1045 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1046 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1047 value8 = (u8)(value32&0x000000FF);
1048 value32 |= ((value8<<8) | 0x00FF0000);
1049 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1050 /* 2. Disable GPIO[10:8] */
1051 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1052 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1053 value8 = (u8)(value16&0x000F);
1054 value16 |= ((value8<<4) | 0x0780);
1055 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1056 /* 3. Disable LED0 & 1 */
1057 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1058 }
1059
disable_analog(struct ieee80211_hw * hw,bool withouthwsm)1060 static void disable_analog(struct ieee80211_hw *hw, bool withouthwsm)
1061 {
1062 struct rtl_priv *rtlpriv = rtl_priv(hw);
1063 u16 value16 = 0;
1064 u8 value8 = 0;
1065
1066 if (withouthwsm) {
1067 /*****************************
1068 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1069 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1070 r. When driver call disable, the ASIC will turn off remaining
1071 clock automatically
1072 ******************************/
1073 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1074 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1075 value8 &= (~LDV12_EN);
1076 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1077 }
1078
1079 /*****************************
1080 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1081 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1082 ******************************/
1083 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1084 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1085 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1086 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1087 }
1088
carddisable_hwsm(struct ieee80211_hw * hw)1089 static void carddisable_hwsm(struct ieee80211_hw *hw)
1090 {
1091 /* ==== RF Off Sequence ==== */
1092 disable_rfafeandresetbb(hw);
1093 /* ==== Reset digital sequence ====== */
1094 _resetdigitalprocedure1(hw, false);
1095 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1096 _disablegpio(hw);
1097 /* ==== Disable analog sequence === */
1098 disable_analog(hw, false);
1099 }
1100
carddisablewithout_hwsm(struct ieee80211_hw * hw)1101 static void carddisablewithout_hwsm(struct ieee80211_hw *hw)
1102 {
1103 /*==== RF Off Sequence ==== */
1104 disable_rfafeandresetbb(hw);
1105 /* ==== Reset digital sequence ====== */
1106 _resetdigitalprocedure1(hw, true);
1107 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1108 _disablegpio(hw);
1109 /* ==== Reset digital sequence ====== */
1110 _resetdigitalprocedure2(hw);
1111 /* ==== Disable analog sequence === */
1112 disable_analog(hw, true);
1113 }
1114
_rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)1115 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1116 u8 set_bits, u8 clear_bits)
1117 {
1118 struct rtl_priv *rtlpriv = rtl_priv(hw);
1119 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1120
1121 rtlusb->reg_bcn_ctrl_val |= set_bits;
1122 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1123 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1124 }
1125
_rtl92cu_stop_tx_beacon(struct ieee80211_hw * hw)1126 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1127 {
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1130 u8 tmp1byte = 0;
1131
1132 if (IS_NORMAL_CHIP(rtlhal->version)) {
1133 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1134 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1135 tmp1byte & (~BIT(6)));
1136 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1137 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1138 tmp1byte &= ~(BIT(0));
1139 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1140 } else {
1141 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1142 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1143 }
1144 }
1145
_rtl92cu_resume_tx_beacon(struct ieee80211_hw * hw)1146 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1147 {
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1150 u8 tmp1byte = 0;
1151
1152 if (IS_NORMAL_CHIP(rtlhal->version)) {
1153 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1154 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1155 tmp1byte | BIT(6));
1156 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1157 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1158 tmp1byte |= BIT(0);
1159 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1160 } else {
1161 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1162 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1163 }
1164 }
1165
_rtl92cu_enable_bcn_sub_func(struct ieee80211_hw * hw)1166 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1167 {
1168 struct rtl_priv *rtlpriv = rtl_priv(hw);
1169 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1170
1171 if (IS_NORMAL_CHIP(rtlhal->version))
1172 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1173 else
1174 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1175 }
1176
_rtl92cu_disable_bcn_sub_func(struct ieee80211_hw * hw)1177 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1178 {
1179 struct rtl_priv *rtlpriv = rtl_priv(hw);
1180 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1181
1182 if (IS_NORMAL_CHIP(rtlhal->version))
1183 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1184 else
1185 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1186 }
1187
_rtl92cu_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1188 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1189 enum nl80211_iftype type)
1190 {
1191 struct rtl_priv *rtlpriv = rtl_priv(hw);
1192 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1193 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1194
1195 bt_msr &= 0xfc;
1196 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1197 NL80211_IFTYPE_STATION) {
1198 _rtl92cu_stop_tx_beacon(hw);
1199 _rtl92cu_enable_bcn_sub_func(hw);
1200 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1201 _rtl92cu_resume_tx_beacon(hw);
1202 _rtl92cu_disable_bcn_sub_func(hw);
1203 } else {
1204 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1205 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1206 type);
1207 }
1208 switch (type) {
1209 case NL80211_IFTYPE_UNSPECIFIED:
1210 bt_msr |= MSR_NOLINK;
1211 ledaction = LED_CTL_LINK;
1212 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1213 "Set Network type to NO LINK!\n");
1214 break;
1215 case NL80211_IFTYPE_ADHOC:
1216 bt_msr |= MSR_ADHOC;
1217 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1218 "Set Network type to Ad Hoc!\n");
1219 break;
1220 case NL80211_IFTYPE_STATION:
1221 bt_msr |= MSR_INFRA;
1222 ledaction = LED_CTL_LINK;
1223 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1224 "Set Network type to STA!\n");
1225 break;
1226 case NL80211_IFTYPE_AP:
1227 bt_msr |= MSR_AP;
1228 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1229 "Set Network type to AP!\n");
1230 break;
1231 default:
1232 pr_err("Network type %d not supported!\n", type);
1233 goto error_out;
1234 }
1235 rtl_write_byte(rtlpriv, MSR, bt_msr);
1236 rtlpriv->cfg->ops->led_control(hw, ledaction);
1237 if ((bt_msr & MSR_MASK) == MSR_AP)
1238 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1239 else
1240 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1241 return 0;
1242 error_out:
1243 return 1;
1244 }
1245
rtl92cu_card_disable(struct ieee80211_hw * hw)1246 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1247 {
1248 struct rtl_priv *rtlpriv = rtl_priv(hw);
1249 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1250 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1251 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1252 enum nl80211_iftype opmode;
1253
1254 mac->link_state = MAC80211_NOLINK;
1255 opmode = NL80211_IFTYPE_UNSPECIFIED;
1256 _rtl92cu_set_media_status(hw, opmode);
1257 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1258 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1259 if (rtlusb->disablehwsm)
1260 carddisable_hwsm(hw);
1261 else
1262 carddisablewithout_hwsm(hw);
1263
1264 /* after power off we should do iqk again */
1265 rtlpriv->phy.iqk_initialized = false;
1266 }
1267
rtl92cu_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1268 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1269 {
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1272 u32 reg_rcr;
1273
1274 if (rtlpriv->psc.rfpwr_state != ERFON)
1275 return;
1276
1277 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1278
1279 if (check_bssid) {
1280 u8 tmp;
1281
1282 if (IS_NORMAL_CHIP(rtlhal->version)) {
1283 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1284 tmp = BIT(4);
1285 } else {
1286 reg_rcr |= RCR_CBSSID;
1287 tmp = BIT(4) | BIT(5);
1288 }
1289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1290 (u8 *) (®_rcr));
1291 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1292 } else {
1293 u8 tmp;
1294
1295 if (IS_NORMAL_CHIP(rtlhal->version)) {
1296 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1297 tmp = BIT(4);
1298 } else {
1299 reg_rcr &= ~RCR_CBSSID;
1300 tmp = BIT(4) | BIT(5);
1301 }
1302 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1303 rtlpriv->cfg->ops->set_hw_reg(hw,
1304 HW_VAR_RCR, (u8 *) (®_rcr));
1305 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1306 }
1307 }
1308
1309 /*========================================================================== */
1310
rtl92cu_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1311 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1312 {
1313 struct rtl_priv *rtlpriv = rtl_priv(hw);
1314
1315 if (_rtl92cu_set_media_status(hw, type))
1316 return -EOPNOTSUPP;
1317
1318 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1319 if (type != NL80211_IFTYPE_AP)
1320 rtl92cu_set_check_bssid(hw, true);
1321 } else {
1322 rtl92cu_set_check_bssid(hw, false);
1323 }
1324
1325 return 0;
1326 }
1327
_beacon_function_enable(struct ieee80211_hw * hw)1328 static void _beacon_function_enable(struct ieee80211_hw *hw)
1329 {
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331
1332 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1333 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1334 }
1335
rtl92cu_set_beacon_related_registers(struct ieee80211_hw * hw)1336 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1337 {
1338
1339 struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1341 u16 bcn_interval, atim_window;
1342 u32 value32;
1343
1344 bcn_interval = mac->beacon_interval;
1345 atim_window = 2; /*FIX MERGE */
1346 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1347 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1348 _rtl92cu_init_beacon_parameters(hw);
1349 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1350 /*
1351 * Force beacon frame transmission even after receiving beacon frame
1352 * from other ad hoc STA
1353 *
1354 *
1355 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1356 */
1357 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1358 value32 &= ~TSFRST;
1359 rtl_write_dword(rtlpriv, REG_TCR, value32);
1360 value32 |= TSFRST;
1361 rtl_write_dword(rtlpriv, REG_TCR, value32);
1362 rtl_dbg(rtlpriv, COMP_INIT | COMP_BEACON, DBG_LOUD,
1363 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1364 value32);
1365 /* TODO: Modify later (Find the right parameters)
1366 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1367 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1368 (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1369 (mac->opmode == NL80211_IFTYPE_AP)) {
1370 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1371 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1372 }
1373 _beacon_function_enable(hw);
1374 }
1375
rtl92cu_set_beacon_interval(struct ieee80211_hw * hw)1376 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1377 {
1378 struct rtl_priv *rtlpriv = rtl_priv(hw);
1379 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1380 u16 bcn_interval = mac->beacon_interval;
1381
1382 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1383 bcn_interval);
1384 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1385 }
1386
rtl92cu_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1387 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1388 u32 add_msr, u32 rm_msr)
1389 {
1390 }
1391
rtl92cu_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)1392 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1393 {
1394 struct rtl_priv *rtlpriv = rtl_priv(hw);
1395 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1397
1398 switch (variable) {
1399 case HW_VAR_RCR:
1400 *((u32 *)(val)) = mac->rx_conf;
1401 break;
1402 case HW_VAR_RF_STATE:
1403 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1404 break;
1405 case HW_VAR_FWLPS_RF_ON:{
1406 enum rf_pwrstate rfstate;
1407 u32 val_rcr;
1408
1409 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1410 (u8 *)(&rfstate));
1411 if (rfstate == ERFOFF) {
1412 *((bool *) (val)) = true;
1413 } else {
1414 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1415 val_rcr &= 0x00070000;
1416 if (val_rcr)
1417 *((bool *) (val)) = false;
1418 else
1419 *((bool *) (val)) = true;
1420 }
1421 break;
1422 }
1423 case HW_VAR_FW_PSMODE_STATUS:
1424 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1425 break;
1426 case HW_VAR_CORRECT_TSF:{
1427 u64 tsf;
1428 u32 *ptsf_low = (u32 *)&tsf;
1429 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1430
1431 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1432 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1433 *((u64 *)(val)) = tsf;
1434 break;
1435 }
1436 case HW_VAR_MGT_FILTER:
1437 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1438 break;
1439 case HW_VAR_CTRL_FILTER:
1440 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1441 break;
1442 case HW_VAR_DATA_FILTER:
1443 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1444 break;
1445 case HAL_DEF_WOWLAN:
1446 break;
1447 default:
1448 pr_err("switch case %#x not processed\n", variable);
1449 break;
1450 }
1451 }
1452
usb_cmd_send_packet(struct ieee80211_hw * hw,struct sk_buff * skb)1453 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1454 {
1455 /* Currently nothing happens here.
1456 * Traffic stops after some seconds in WPA2 802.11n mode.
1457 * Maybe because rtl8192cu chip should be set from here?
1458 * If I understand correctly, the realtek vendor driver sends some urbs
1459 * if its "here".
1460 *
1461 * This is maybe necessary:
1462 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, skb);
1463 */
1464 dev_kfree_skb(skb);
1465
1466 return true;
1467 }
1468
rtl92cu_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)1469 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1470 {
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1473 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1474 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1475 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1476 u8 idx = 0;
1477
1478 switch (variable) {
1479 case HW_VAR_ETHER_ADDR:{
1480 for (idx = 0; idx < ETH_ALEN; idx++) {
1481 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1482 val[idx]);
1483 }
1484 break;
1485 }
1486 case HW_VAR_BASIC_RATE:{
1487 u16 rate_cfg = ((u16 *) val)[0];
1488 u8 rate_index = 0;
1489
1490 rate_cfg &= 0x15f;
1491 /* TODO */
1492 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1493 * && ((rate_cfg & 0x150) == 0)) {
1494 * rate_cfg |= 0x010;
1495 * } */
1496 rate_cfg |= 0x01;
1497 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1498 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1499 (rate_cfg >> 8) & 0xff);
1500 while (rate_cfg > 0x1) {
1501 rate_cfg >>= 1;
1502 rate_index++;
1503 }
1504 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1505 rate_index);
1506 break;
1507 }
1508 case HW_VAR_BSSID:{
1509 for (idx = 0; idx < ETH_ALEN; idx++) {
1510 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1511 val[idx]);
1512 }
1513 break;
1514 }
1515 case HW_VAR_SIFS:{
1516 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1517 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1518 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1519 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1520 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1521 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1522 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1523 break;
1524 }
1525 case HW_VAR_SLOT_TIME:{
1526 u8 e_aci;
1527
1528 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1529 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
1530 "HW_VAR_SLOT_TIME %x\n", val[0]);
1531
1532 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1533 rtlpriv->cfg->ops->set_hw_reg(hw,
1534 HW_VAR_AC_PARAM,
1535 &e_aci);
1536 break;
1537 }
1538 case HW_VAR_ACK_PREAMBLE:{
1539 u8 reg_tmp;
1540 u8 short_preamble = (bool)*val;
1541
1542 reg_tmp = 0;
1543 if (short_preamble)
1544 reg_tmp |= 0x80;
1545 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1546 break;
1547 }
1548 case HW_VAR_AMPDU_MIN_SPACE:{
1549 u8 min_spacing_to_set;
1550 u8 sec_min_space;
1551
1552 min_spacing_to_set = *val;
1553 if (min_spacing_to_set <= 7) {
1554 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1555 case NO_ENCRYPTION:
1556 case AESCCMP_ENCRYPTION:
1557 sec_min_space = 0;
1558 break;
1559 case WEP40_ENCRYPTION:
1560 case WEP104_ENCRYPTION:
1561 case TKIP_ENCRYPTION:
1562 sec_min_space = 6;
1563 break;
1564 default:
1565 sec_min_space = 7;
1566 break;
1567 }
1568 if (min_spacing_to_set < sec_min_space)
1569 min_spacing_to_set = sec_min_space;
1570 mac->min_space_cfg = ((mac->min_space_cfg &
1571 0xf8) |
1572 min_spacing_to_set);
1573 *val = min_spacing_to_set;
1574 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
1575 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1576 mac->min_space_cfg);
1577 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1578 mac->min_space_cfg);
1579 }
1580 break;
1581 }
1582 case HW_VAR_SHORTGI_DENSITY:{
1583 u8 density_to_set;
1584
1585 density_to_set = *val;
1586 density_to_set &= 0x1f;
1587 mac->min_space_cfg &= 0x07;
1588 mac->min_space_cfg |= (density_to_set << 3);
1589 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
1590 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1591 mac->min_space_cfg);
1592 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1593 mac->min_space_cfg);
1594 break;
1595 }
1596 case HW_VAR_AMPDU_FACTOR:{
1597 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1598 u8 factor_toset;
1599 u8 *p_regtoset = NULL;
1600 u8 index = 0;
1601
1602 p_regtoset = regtoset_normal;
1603 factor_toset = *val;
1604 if (factor_toset <= 3) {
1605 factor_toset = (1 << (factor_toset + 2));
1606 if (factor_toset > 0xf)
1607 factor_toset = 0xf;
1608 for (index = 0; index < 4; index++) {
1609 if ((p_regtoset[index] & 0xf0) >
1610 (factor_toset << 4))
1611 p_regtoset[index] =
1612 (p_regtoset[index] & 0x0f)
1613 | (factor_toset << 4);
1614 if ((p_regtoset[index] & 0x0f) >
1615 factor_toset)
1616 p_regtoset[index] =
1617 (p_regtoset[index] & 0xf0)
1618 | (factor_toset);
1619 rtl_write_byte(rtlpriv,
1620 (REG_AGGLEN_LMT + index),
1621 p_regtoset[index]);
1622 }
1623 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
1624 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1625 factor_toset);
1626 }
1627 break;
1628 }
1629 case HW_VAR_AC_PARAM:{
1630 u8 e_aci = *val;
1631 u32 u4b_ac_param;
1632 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1633 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1634 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1635
1636 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1637 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1638 AC_PARAM_ECW_MIN_OFFSET);
1639 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1640 AC_PARAM_ECW_MAX_OFFSET);
1641 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1642 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
1643 "queue:%x, ac_param:%x\n",
1644 e_aci, u4b_ac_param);
1645 switch (e_aci) {
1646 case AC1_BK:
1647 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1648 u4b_ac_param);
1649 break;
1650 case AC0_BE:
1651 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1652 u4b_ac_param);
1653 break;
1654 case AC2_VI:
1655 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1656 u4b_ac_param);
1657 break;
1658 case AC3_VO:
1659 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1660 u4b_ac_param);
1661 break;
1662 default:
1663 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n",
1664 e_aci);
1665 break;
1666 }
1667 break;
1668 }
1669 case HW_VAR_RCR:{
1670 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1671 mac->rx_conf = ((u32 *) (val))[0];
1672 rtl_dbg(rtlpriv, COMP_RECV, DBG_DMESG,
1673 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1674 break;
1675 }
1676 case HW_VAR_RETRY_LIMIT:{
1677 u8 retry_limit = val[0];
1678
1679 rtl_write_word(rtlpriv, REG_RL,
1680 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1681 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1682 rtl_dbg(rtlpriv, COMP_MLME, DBG_DMESG,
1683 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1684 retry_limit);
1685 break;
1686 }
1687 case HW_VAR_DUAL_TSF_RST:
1688 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1689 break;
1690 case HW_VAR_EFUSE_BYTES:
1691 rtlefuse->efuse_usedbytes = *((u16 *) val);
1692 break;
1693 case HW_VAR_EFUSE_USAGE:
1694 rtlefuse->efuse_usedpercentage = *val;
1695 break;
1696 case HW_VAR_IO_CMD:
1697 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1698 break;
1699 case HW_VAR_WPA_CONFIG:
1700 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1701 break;
1702 case HW_VAR_SET_RPWM:{
1703 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1704
1705 if (rpwm_val & BIT(7))
1706 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1707 else
1708 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1709 *val | BIT(7));
1710 break;
1711 }
1712 case HW_VAR_H2C_FW_PWRMODE:{
1713 u8 psmode = *val;
1714
1715 if ((psmode != FW_PS_ACTIVE_MODE) &&
1716 (!IS_92C_SERIAL(rtlhal->version)))
1717 rtl92c_dm_rf_saving(hw, true);
1718 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1719 break;
1720 }
1721 case HW_VAR_FW_PSMODE_STATUS:
1722 ppsc->fw_current_inpsmode = *((bool *) val);
1723 break;
1724 case HW_VAR_H2C_FW_JOINBSSRPT:{
1725 u8 mstatus = *val;
1726 u8 tmp_reg422;
1727 bool recover = false;
1728
1729 if (mstatus == RT_MEDIA_CONNECT) {
1730 rtlpriv->cfg->ops->set_hw_reg(hw,
1731 HW_VAR_AID, NULL);
1732 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1733 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1734 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1735 tmp_reg422 = rtl_read_byte(rtlpriv,
1736 REG_FWHW_TXQ_CTRL + 2);
1737 if (tmp_reg422 & BIT(6))
1738 recover = true;
1739 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1740 tmp_reg422 & (~BIT(6)));
1741 rtl92c_set_fw_rsvdpagepkt(hw,
1742 &usb_cmd_send_packet);
1743 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1744 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1745 if (recover)
1746 rtl_write_byte(rtlpriv,
1747 REG_FWHW_TXQ_CTRL + 2,
1748 tmp_reg422 | BIT(6));
1749 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1750 }
1751 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1752 break;
1753 }
1754 case HW_VAR_AID:{
1755 u16 u2btmp;
1756
1757 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1758 u2btmp &= 0xC000;
1759 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1760 (u2btmp | mac->assoc_id));
1761 break;
1762 }
1763 case HW_VAR_CORRECT_TSF:{
1764 u8 btype_ibss = val[0];
1765
1766 if (btype_ibss)
1767 _rtl92cu_stop_tx_beacon(hw);
1768 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1769 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1770 0xffffffff));
1771 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1772 (u32)((mac->tsf >> 32) & 0xffffffff));
1773 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1774 if (btype_ibss)
1775 _rtl92cu_resume_tx_beacon(hw);
1776 break;
1777 }
1778 case HW_VAR_MGT_FILTER:
1779 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1780 mac->rx_mgt_filter = *(u16 *)val;
1781 break;
1782 case HW_VAR_CTRL_FILTER:
1783 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1784 mac->rx_ctrl_filter = *(u16 *)val;
1785 break;
1786 case HW_VAR_DATA_FILTER:
1787 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1788 mac->rx_data_filter = *(u16 *)val;
1789 break;
1790 case HW_VAR_KEEP_ALIVE:{
1791 u8 array[2];
1792
1793 array[0] = 0xff;
1794 array[1] = *((u8 *)val);
1795 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,
1796 array);
1797 break;
1798 }
1799 default:
1800 pr_err("switch case %#x not processed\n", variable);
1801 break;
1802 }
1803 }
1804
rtl92cu_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1805 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1806 struct ieee80211_sta *sta)
1807 {
1808 struct rtl_priv *rtlpriv = rtl_priv(hw);
1809 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1810 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1811 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1812 u32 ratr_value;
1813 u8 ratr_index = 0;
1814 u8 nmode = mac->ht_enable;
1815 u8 mimo_ps = IEEE80211_SMPS_OFF;
1816 u16 shortgi_rate;
1817 u32 tmp_ratr_value;
1818 u8 curtxbw_40mhz = mac->bw_40;
1819 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1820 1 : 0;
1821 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1822 1 : 0;
1823 enum wireless_mode wirelessmode = mac->mode;
1824
1825 if (rtlhal->current_bandtype == BAND_ON_5G)
1826 ratr_value = sta->deflink.supp_rates[1] << 4;
1827 else
1828 ratr_value = sta->deflink.supp_rates[0];
1829 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1830 ratr_value = 0xfff;
1831
1832 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1833 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1834 switch (wirelessmode) {
1835 case WIRELESS_MODE_B:
1836 if (ratr_value & 0x0000000c)
1837 ratr_value &= 0x0000000d;
1838 else
1839 ratr_value &= 0x0000000f;
1840 break;
1841 case WIRELESS_MODE_G:
1842 ratr_value &= 0x00000FF5;
1843 break;
1844 case WIRELESS_MODE_N_24G:
1845 case WIRELESS_MODE_N_5G:
1846 nmode = 1;
1847 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1848 ratr_value &= 0x0007F005;
1849 } else {
1850 u32 ratr_mask;
1851
1852 if (get_rf_type(rtlphy) == RF_1T2R ||
1853 get_rf_type(rtlphy) == RF_1T1R)
1854 ratr_mask = 0x000ff005;
1855 else
1856 ratr_mask = 0x0f0ff005;
1857
1858 ratr_value &= ratr_mask;
1859 }
1860 break;
1861 default:
1862 if (rtlphy->rf_type == RF_1T2R)
1863 ratr_value &= 0x000ff0ff;
1864 else
1865 ratr_value &= 0x0f0ff0ff;
1866
1867 break;
1868 }
1869
1870 ratr_value &= 0x0FFFFFFF;
1871
1872 if (nmode && ((curtxbw_40mhz &&
1873 curshortgi_40mhz) || (!curtxbw_40mhz &&
1874 curshortgi_20mhz))) {
1875 ratr_value |= 0x10000000;
1876 tmp_ratr_value = (ratr_value >> 12);
1877
1878 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1879 if ((1 << shortgi_rate) & tmp_ratr_value)
1880 break;
1881 }
1882
1883 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1884 (shortgi_rate << 4) | (shortgi_rate);
1885 }
1886
1887 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1888
1889 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1890 rtl_read_dword(rtlpriv, REG_ARFR0));
1891 }
1892
rtl92cu_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1893 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
1894 struct ieee80211_sta *sta,
1895 u8 rssi_level, bool update_bw)
1896 {
1897 struct rtl_priv *rtlpriv = rtl_priv(hw);
1898 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1899 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1901 struct rtl_sta_info *sta_entry = NULL;
1902 u32 ratr_bitmap;
1903 u8 ratr_index;
1904 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1905 u8 curshortgi_40mhz = curtxbw_40mhz &&
1906 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1907 1 : 0;
1908 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1909 1 : 0;
1910 enum wireless_mode wirelessmode = 0;
1911 bool shortgi = false;
1912 u8 rate_mask[5];
1913 u8 macid = 0;
1914 u8 mimo_ps = IEEE80211_SMPS_OFF;
1915
1916 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1917 wirelessmode = sta_entry->wireless_mode;
1918 if (mac->opmode == NL80211_IFTYPE_STATION ||
1919 mac->opmode == NL80211_IFTYPE_MESH_POINT)
1920 curtxbw_40mhz = mac->bw_40;
1921 else if (mac->opmode == NL80211_IFTYPE_AP ||
1922 mac->opmode == NL80211_IFTYPE_ADHOC)
1923 macid = sta->aid + 1;
1924
1925 if (rtlhal->current_bandtype == BAND_ON_5G)
1926 ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1927 else
1928 ratr_bitmap = sta->deflink.supp_rates[0];
1929 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1930 ratr_bitmap = 0xfff;
1931 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1932 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1933 switch (wirelessmode) {
1934 case WIRELESS_MODE_B:
1935 ratr_index = RATR_INX_WIRELESS_B;
1936 if (ratr_bitmap & 0x0000000c)
1937 ratr_bitmap &= 0x0000000d;
1938 else
1939 ratr_bitmap &= 0x0000000f;
1940 break;
1941 case WIRELESS_MODE_G:
1942 ratr_index = RATR_INX_WIRELESS_GB;
1943
1944 if (rssi_level == 1)
1945 ratr_bitmap &= 0x00000f00;
1946 else if (rssi_level == 2)
1947 ratr_bitmap &= 0x00000ff0;
1948 else
1949 ratr_bitmap &= 0x00000ff5;
1950 break;
1951 case WIRELESS_MODE_A:
1952 ratr_index = RATR_INX_WIRELESS_A;
1953 ratr_bitmap &= 0x00000ff0;
1954 break;
1955 case WIRELESS_MODE_N_24G:
1956 case WIRELESS_MODE_N_5G:
1957 ratr_index = RATR_INX_WIRELESS_NGB;
1958
1959 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1960 if (rssi_level == 1)
1961 ratr_bitmap &= 0x00070000;
1962 else if (rssi_level == 2)
1963 ratr_bitmap &= 0x0007f000;
1964 else
1965 ratr_bitmap &= 0x0007f005;
1966 } else {
1967 if (rtlphy->rf_type == RF_1T2R ||
1968 rtlphy->rf_type == RF_1T1R) {
1969 if (curtxbw_40mhz) {
1970 if (rssi_level == 1)
1971 ratr_bitmap &= 0x000f0000;
1972 else if (rssi_level == 2)
1973 ratr_bitmap &= 0x000ff000;
1974 else
1975 ratr_bitmap &= 0x000ff015;
1976 } else {
1977 if (rssi_level == 1)
1978 ratr_bitmap &= 0x000f0000;
1979 else if (rssi_level == 2)
1980 ratr_bitmap &= 0x000ff000;
1981 else
1982 ratr_bitmap &= 0x000ff005;
1983 }
1984 } else {
1985 if (curtxbw_40mhz) {
1986 if (rssi_level == 1)
1987 ratr_bitmap &= 0x0f0f0000;
1988 else if (rssi_level == 2)
1989 ratr_bitmap &= 0x0f0ff000;
1990 else
1991 ratr_bitmap &= 0x0f0ff015;
1992 } else {
1993 if (rssi_level == 1)
1994 ratr_bitmap &= 0x0f0f0000;
1995 else if (rssi_level == 2)
1996 ratr_bitmap &= 0x0f0ff000;
1997 else
1998 ratr_bitmap &= 0x0f0ff005;
1999 }
2000 }
2001 }
2002
2003 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2004 (!curtxbw_40mhz && curshortgi_20mhz)) {
2005
2006 if (macid == 0)
2007 shortgi = true;
2008 else if (macid == 1)
2009 shortgi = false;
2010 }
2011 break;
2012 default:
2013 ratr_index = RATR_INX_WIRELESS_NGB;
2014
2015 if (rtlphy->rf_type == RF_1T2R)
2016 ratr_bitmap &= 0x000ff0ff;
2017 else
2018 ratr_bitmap &= 0x0f0ff0ff;
2019 break;
2020 }
2021 sta_entry->ratr_index = ratr_index;
2022
2023 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2024 "ratr_bitmap :%x\n", ratr_bitmap);
2025 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2026 (ratr_index << 28);
2027 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2028 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2029 "Rate_index:%x, ratr_val:%x, %5phC\n",
2030 ratr_index, ratr_bitmap, rate_mask);
2031 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2032 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2033 * "scheduled while atomic" if called directly */
2034 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2035
2036 if (macid != 0)
2037 sta_entry->ratr_index = ratr_index;
2038 }
2039
rtl92cu_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2040 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2041 struct ieee80211_sta *sta,
2042 u8 rssi_level, bool update_bw)
2043 {
2044 struct rtl_priv *rtlpriv = rtl_priv(hw);
2045
2046 if (rtlpriv->dm.useramask)
2047 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2048 else
2049 rtl92cu_update_hal_rate_table(hw, sta);
2050 }
2051
rtl92cu_update_channel_access_setting(struct ieee80211_hw * hw)2052 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2053 {
2054 struct rtl_priv *rtlpriv = rtl_priv(hw);
2055 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2056 u16 sifs_timer;
2057
2058 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2059 &mac->slot_time);
2060 if (!mac->ht_enable)
2061 sifs_timer = 0x0a0a;
2062 else
2063 sifs_timer = 0x0e0e;
2064 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2065 }
2066
rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2067 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2068 {
2069 struct rtl_priv *rtlpriv = rtl_priv(hw);
2070 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2071 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2072 u8 u1tmp = 0;
2073 bool actuallyset = false;
2074 unsigned long flag = 0;
2075 /* to do - usb autosuspend */
2076 u8 usb_autosuspend = 0;
2077
2078 if (ppsc->swrf_processing)
2079 return false;
2080 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2081 if (ppsc->rfchange_inprogress) {
2082 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2083 return false;
2084 } else {
2085 ppsc->rfchange_inprogress = true;
2086 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2087 }
2088 cur_rfstate = ppsc->rfpwr_state;
2089 if (usb_autosuspend) {
2090 /* to do................... */
2091 } else {
2092 if (ppsc->pwrdown_mode) {
2093 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2094 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2095 ERFOFF : ERFON;
2096 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
2097 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2098 } else {
2099 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2100 rtl_read_byte(rtlpriv,
2101 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2102 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2103 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2104 ERFON : ERFOFF;
2105 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
2106 "GPIO_IN=%02x\n", u1tmp);
2107 }
2108 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2109 e_rfpowerstate_toset);
2110 }
2111 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2112 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2113 "GPIOChangeRF - HW Radio ON, RF ON\n");
2114 ppsc->hwradiooff = false;
2115 actuallyset = true;
2116 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2117 ERFOFF)) {
2118 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2119 "GPIOChangeRF - HW Radio OFF\n");
2120 ppsc->hwradiooff = true;
2121 actuallyset = true;
2122 } else {
2123 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2124 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2125 ppsc->hwradiooff, e_rfpowerstate_toset);
2126 }
2127 if (actuallyset) {
2128 ppsc->hwradiooff = true;
2129 if (e_rfpowerstate_toset == ERFON) {
2130 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2131 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2132 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2133 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2134 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2135 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2136 }
2137 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2138 ppsc->rfchange_inprogress = false;
2139 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2140 /* For power down module, we need to enable register block
2141 * contrl reg at 0x1c. Then enable power down control bit
2142 * of register 0x04 BIT4 and BIT15 as 1.
2143 */
2144 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2145 /* Enable register area 0x0-0xc. */
2146 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2147 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2148 }
2149 if (e_rfpowerstate_toset == ERFOFF) {
2150 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2151 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2152 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2153 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2154 }
2155 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2156 /* Enter D3 or ASPM after GPIO had been done. */
2157 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2158 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2159 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2160 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2161 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2162 ppsc->rfchange_inprogress = false;
2163 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2164 } else {
2165 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2166 ppsc->rfchange_inprogress = false;
2167 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2168 }
2169 *valid = 1;
2170 return !ppsc->hwradiooff;
2171 }
2172