1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver
4 //
5 // Copyright(c) 2023 Realtek Semiconductor Corp.
6 //
7 //
8
9 #include <linux/bitops.h>
10 #include <sound/core.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <sound/initval.h>
14 #include <sound/jack.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <sound/pcm.h>
19 #include <linux/pm_runtime.h>
20 #include <sound/pcm_params.h>
21 #include <linux/soundwire/sdw_registers.h>
22 #include <linux/slab.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/tlv.h>
25
26 #include "rt722-sdca.h"
27
28 #define RT722_NID_ADDR(nid, reg) ((nid) << 20 | (reg))
29
rt722_sdca_index_write(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int value)30 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
31 unsigned int nid, unsigned int reg, unsigned int value)
32 {
33 struct regmap *regmap = rt722->regmap;
34 unsigned int addr = RT722_NID_ADDR(nid, reg);
35 int ret;
36
37 ret = regmap_write(regmap, addr, value);
38 if (ret < 0)
39 dev_err(&rt722->slave->dev,
40 "%s: Failed to set private value: %06x <= %04x ret=%d\n",
41 __func__, addr, value, ret);
42
43 return ret;
44 }
45
rt722_sdca_index_read(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int * value)46 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
47 unsigned int nid, unsigned int reg, unsigned int *value)
48 {
49 int ret;
50 struct regmap *regmap = rt722->regmap;
51 unsigned int addr = RT722_NID_ADDR(nid, reg);
52
53 ret = regmap_read(regmap, addr, value);
54 if (ret < 0)
55 dev_err(&rt722->slave->dev,
56 "%s: Failed to get private value: %06x => %04x ret=%d\n",
57 __func__, addr, *value, ret);
58
59 return ret;
60 }
61
rt722_sdca_index_update_bits(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int mask,unsigned int val)62 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722,
63 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
64 {
65 unsigned int tmp;
66 int ret;
67
68 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp);
69 if (ret < 0)
70 return ret;
71
72 set_mask_bits(&tmp, mask, val);
73 return rt722_sdca_index_write(rt722, nid, reg, tmp);
74 }
75
rt722_sdca_btn_type(unsigned char * buffer)76 static int rt722_sdca_btn_type(unsigned char *buffer)
77 {
78 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) ||
79 (*(buffer + 1) == 0x10))
80 return SND_JACK_BTN_2;
81 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) ||
82 (*(buffer + 1) == 0x20))
83 return SND_JACK_BTN_3;
84 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) ||
85 (*(buffer + 1) == 0x40))
86 return SND_JACK_BTN_0;
87 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) ||
88 (*(buffer + 1) == 0x80))
89 return SND_JACK_BTN_1;
90
91 return 0;
92 }
93
rt722_sdca_button_detect(struct rt722_sdca_priv * rt722)94 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722)
95 {
96 unsigned int btn_type = 0, offset, idx, val, owner;
97 int ret;
98 unsigned char buf[3];
99
100 /* get current UMP message owner */
101 ret = regmap_read(rt722->regmap,
102 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
103 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
104 if (ret < 0)
105 return 0;
106
107 /* if owner is device then there is no button event from device */
108 if (owner == 1)
109 return 0;
110
111 /* read UMP message offset */
112 ret = regmap_read(rt722->regmap,
113 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
114 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
115 if (ret < 0)
116 goto _end_btn_det_;
117
118 for (idx = 0; idx < sizeof(buf); idx++) {
119 ret = regmap_read(rt722->regmap,
120 RT722_BUF_ADDR_HID1 + offset + idx, &val);
121 if (ret < 0)
122 goto _end_btn_det_;
123 buf[idx] = val & 0xff;
124 }
125
126 if (buf[0] == 0x11)
127 btn_type = rt722_sdca_btn_type(&buf[1]);
128
129 _end_btn_det_:
130 /* Host is owner, so set back to device */
131 if (owner == 0)
132 /* set owner to device */
133 regmap_write(rt722->regmap,
134 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
135 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
136
137 return btn_type;
138 }
139
rt722_sdca_headset_detect(struct rt722_sdca_priv * rt722)140 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722)
141 {
142 unsigned int det_mode;
143 int ret;
144
145 /* get detected_mode */
146 ret = regmap_read(rt722->regmap,
147 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
148 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
149 if (ret < 0)
150 goto io_error;
151
152 switch (det_mode) {
153 case 0x00:
154 rt722->jack_type = 0;
155 break;
156 case 0x03:
157 rt722->jack_type = SND_JACK_HEADPHONE;
158 break;
159 case 0x05:
160 rt722->jack_type = SND_JACK_HEADSET;
161 break;
162 }
163
164 /* write selected_mode */
165 if (det_mode) {
166 ret = regmap_write(rt722->regmap,
167 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
168 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode);
169 if (ret < 0)
170 goto io_error;
171 }
172
173 dev_dbg(&rt722->slave->dev,
174 "%s, detected_mode=0x%x\n", __func__, det_mode);
175
176 return 0;
177
178 io_error:
179 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
180 return ret;
181 }
182
rt722_sdca_jack_detect_handler(struct work_struct * work)183 static void rt722_sdca_jack_detect_handler(struct work_struct *work)
184 {
185 struct rt722_sdca_priv *rt722 =
186 container_of(work, struct rt722_sdca_priv, jack_detect_work.work);
187 int btn_type = 0, ret;
188
189 if (!rt722->hs_jack)
190 return;
191
192 if (!rt722->component->card || !rt722->component->card->instantiated)
193 return;
194
195 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */
196 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) {
197 ret = rt722_sdca_headset_detect(rt722);
198 if (ret < 0)
199 return;
200 }
201
202 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
203 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
204 btn_type = rt722_sdca_button_detect(rt722);
205
206 if (rt722->jack_type == 0)
207 btn_type = 0;
208
209 dev_dbg(&rt722->slave->dev,
210 "in %s, jack_type=%d\n", __func__, rt722->jack_type);
211 dev_dbg(&rt722->slave->dev,
212 "in %s, btn_type=0x%x\n", __func__, btn_type);
213 dev_dbg(&rt722->slave->dev,
214 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
215 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
216
217 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
218 SND_JACK_HEADSET |
219 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
220 SND_JACK_BTN_2 | SND_JACK_BTN_3);
221
222 if (btn_type) {
223 /* button released */
224 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
225 SND_JACK_HEADSET |
226 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
227 SND_JACK_BTN_2 | SND_JACK_BTN_3);
228
229 mod_delayed_work(system_power_efficient_wq,
230 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
231 }
232 }
233
rt722_sdca_btn_check_handler(struct work_struct * work)234 static void rt722_sdca_btn_check_handler(struct work_struct *work)
235 {
236 struct rt722_sdca_priv *rt722 =
237 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work);
238 int btn_type = 0, ret, idx;
239 unsigned int det_mode, offset, val;
240 unsigned char buf[3];
241
242 ret = regmap_read(rt722->regmap,
243 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
244 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
245 if (ret < 0)
246 goto io_error;
247
248 /* pin attached */
249 if (det_mode) {
250 /* read UMP message offset */
251 ret = regmap_read(rt722->regmap,
252 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
253 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
254 if (ret < 0)
255 goto io_error;
256
257 for (idx = 0; idx < sizeof(buf); idx++) {
258 ret = regmap_read(rt722->regmap,
259 RT722_BUF_ADDR_HID1 + offset + idx, &val);
260 if (ret < 0)
261 goto io_error;
262 buf[idx] = val & 0xff;
263 }
264
265 if (buf[0] == 0x11)
266 btn_type = rt722_sdca_btn_type(&buf[1]);
267 } else
268 rt722->jack_type = 0;
269
270 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
271 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
272 SND_JACK_HEADSET |
273 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
274 SND_JACK_BTN_2 | SND_JACK_BTN_3);
275
276 if (btn_type) {
277 /* button released */
278 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
279 SND_JACK_HEADSET |
280 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
281 SND_JACK_BTN_2 | SND_JACK_BTN_3);
282
283 mod_delayed_work(system_power_efficient_wq,
284 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
285 }
286
287 return;
288
289 io_error:
290 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
291 }
292
rt722_sdca_jack_init(struct rt722_sdca_priv * rt722)293 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722)
294 {
295 mutex_lock(&rt722->calibrate_mutex);
296 if (rt722->hs_jack) {
297 /* set SCP_SDCA_IntMask1[0]=1 */
298 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
299 SDW_SCP_SDCA_INTMASK_SDCA_0);
300 /* set SCP_SDCA_IntMask2[0]=1 */
301 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
302 SDW_SCP_SDCA_INTMASK_SDCA_8);
303 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__);
304 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
305 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E);
306 /* set XU(et03h) & XU(et0Dh) to Not bypassed */
307 regmap_write(rt722->regmap,
308 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03,
309 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
310 regmap_write(rt722->regmap,
311 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D,
312 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
313 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000);
314 /* trigger GE interrupt */
315 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
316 RT722_GE_RELATED_CTL2, 0x4000, 0x4000);
317 }
318 mutex_unlock(&rt722->calibrate_mutex);
319 }
320
rt722_sdca_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)321 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component,
322 struct snd_soc_jack *hs_jack, void *data)
323 {
324 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
325 int ret;
326
327 rt722->hs_jack = hs_jack;
328
329 ret = pm_runtime_resume_and_get(component->dev);
330 if (ret < 0) {
331 if (ret != -EACCES) {
332 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
333 return ret;
334 }
335 /* pm_runtime not enabled yet */
336 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
337 return 0;
338 }
339
340 rt722_sdca_jack_init(rt722);
341
342 pm_runtime_put_autosuspend(component->dev);
343
344 return 0;
345 }
346
347 /* For SDCA control DAC/ADC Gain */
rt722_sdca_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)348 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350 {
351 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
352 struct soc_mixer_control *mc =
353 (struct soc_mixer_control *)kcontrol->private_value;
354 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
355 unsigned int read_l, read_r, gain_l_val, gain_r_val;
356 unsigned int adc_vol_flag = 0, changed = 0;
357 unsigned int lvalue, rvalue;
358 const unsigned int interval_offset = 0xc0;
359 const unsigned int tendB = 0xa00;
360
361 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
362 strstr(ucontrol->id.name, "FU0F Capture Volume"))
363 adc_vol_flag = 1;
364
365 regmap_read(rt722->regmap, mc->reg, &lvalue);
366 regmap_read(rt722->regmap, mc->rreg, &rvalue);
367
368 /* L Channel */
369 gain_l_val = ucontrol->value.integer.value[0];
370 if (gain_l_val > mc->max)
371 gain_l_val = mc->max;
372
373 if (mc->shift == 8) /* boost gain */
374 gain_l_val = gain_l_val * tendB;
375 else {
376 /* ADC/DAC gain */
377 if (adc_vol_flag)
378 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
379 else
380 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
381 gain_l_val &= 0xffff;
382 }
383
384 /* R Channel */
385 gain_r_val = ucontrol->value.integer.value[1];
386 if (gain_r_val > mc->max)
387 gain_r_val = mc->max;
388
389 if (mc->shift == 8) /* boost gain */
390 gain_r_val = gain_r_val * tendB;
391 else {
392 /* ADC/DAC gain */
393 if (adc_vol_flag)
394 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
395 else
396 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
397 gain_r_val &= 0xffff;
398 }
399
400 if (lvalue != gain_l_val || rvalue != gain_r_val)
401 changed = 1;
402 else
403 return 0;
404
405 /* Lch*/
406 regmap_write(rt722->regmap, mc->reg, gain_l_val);
407
408 /* Rch */
409 regmap_write(rt722->regmap, mc->rreg, gain_r_val);
410
411 regmap_read(rt722->regmap, mc->reg, &read_l);
412 regmap_read(rt722->regmap, mc->rreg, &read_r);
413 if (read_r == gain_r_val && read_l == gain_l_val)
414 return changed;
415
416 return -EIO;
417 }
418
rt722_sdca_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)419 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
421 {
422 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
423 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
424 struct soc_mixer_control *mc =
425 (struct soc_mixer_control *)kcontrol->private_value;
426 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
427 unsigned int adc_vol_flag = 0;
428 const unsigned int interval_offset = 0xc0;
429 const unsigned int tendB = 0xa00;
430
431 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
432 strstr(ucontrol->id.name, "FU0F Capture Volume"))
433 adc_vol_flag = 1;
434
435 regmap_read(rt722->regmap, mc->reg, &read_l);
436 regmap_read(rt722->regmap, mc->rreg, &read_r);
437
438 if (mc->shift == 8) /* boost gain */
439 ctl_l = read_l / tendB;
440 else {
441 if (adc_vol_flag)
442 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
443 else
444 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
445 }
446
447 if (read_l != read_r) {
448 if (mc->shift == 8) /* boost gain */
449 ctl_r = read_r / tendB;
450 else { /* ADC/DAC gain */
451 if (adc_vol_flag)
452 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
453 else
454 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
455 }
456 } else {
457 ctl_r = ctl_l;
458 }
459
460 ucontrol->value.integer.value[0] = ctl_l;
461 ucontrol->value.integer.value[1] = ctl_r;
462
463 return 0;
464 }
465
rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv * rt722)466 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722)
467 {
468 int err, i;
469 unsigned int ch_mute;
470
471 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) {
472 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i];
473 err = regmap_write(rt722->regmap,
474 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
475 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
476 if (err < 0)
477 return err;
478 }
479
480 return 0;
481 }
482
rt722_sdca_fu1e_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)483 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol)
485 {
486 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
487 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
488 struct rt722_sdca_dmic_kctrl_priv *p =
489 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
490 unsigned int i;
491
492 for (i = 0; i < p->count; i++)
493 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i];
494
495 return 0;
496 }
497
rt722_sdca_fu1e_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)498 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
499 struct snd_ctl_elem_value *ucontrol)
500 {
501 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
502 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
503 struct rt722_sdca_dmic_kctrl_priv *p =
504 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
505 int err, changed = 0, i;
506
507 for (i = 0; i < p->count; i++) {
508 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
509 changed = 1;
510 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
511 }
512
513 err = rt722_sdca_set_fu1e_capture_ctl(rt722);
514 if (err < 0)
515 return err;
516
517 return changed;
518 }
519
rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv * rt722)520 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722)
521 {
522 int err;
523 unsigned int ch_l, ch_r;
524
525 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00;
526 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00;
527
528 err = regmap_write(rt722->regmap,
529 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
530 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l);
531 if (err < 0)
532 return err;
533
534 err = regmap_write(rt722->regmap,
535 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
536 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r);
537 if (err < 0)
538 return err;
539
540 return 0;
541 }
542
rt722_sdca_fu0f_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)543 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_value *ucontrol)
545 {
546 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
547 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
548
549 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute;
550 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute;
551 return 0;
552 }
553
rt722_sdca_fu0f_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)554 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
555 struct snd_ctl_elem_value *ucontrol)
556 {
557 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
558 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
559 int err, changed = 0;
560
561 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
562 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
563 changed = 1;
564
565 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
566 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
567 err = rt722_sdca_set_fu0f_capture_ctl(rt722);
568 if (err < 0)
569 return err;
570
571 return changed;
572 }
573
rt722_sdca_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)574 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol,
575 struct snd_ctl_elem_info *uinfo)
576 {
577 struct rt722_sdca_dmic_kctrl_priv *p =
578 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
579
580 if (p->max == 1)
581 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
582 else
583 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
584 uinfo->count = p->count;
585 uinfo->value.integer.min = 0;
586 uinfo->value.integer.max = p->max;
587 return 0;
588 }
589
rt722_sdca_dmic_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)590 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
591 struct snd_ctl_elem_value *ucontrol)
592 {
593 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
594 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
595 struct rt722_sdca_dmic_kctrl_priv *p =
596 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
597 unsigned int boost_step = 0x0a00;
598 unsigned int vol_max = 0x1e00;
599 unsigned int regvalue, ctl, i;
600 unsigned int adc_vol_flag = 0;
601 const unsigned int interval_offset = 0xc0;
602
603 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
604 adc_vol_flag = 1;
605
606 /* check all channels */
607 for (i = 0; i < p->count; i++) {
608 regmap_read(rt722->regmap, p->reg_base + i, ®value);
609
610 if (!adc_vol_flag) /* boost gain */
611 ctl = regvalue / boost_step;
612 else /* ADC gain */
613 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset);
614
615 ucontrol->value.integer.value[i] = ctl;
616 }
617
618 return 0;
619 }
620
rt722_sdca_dmic_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)621 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
622 struct snd_ctl_elem_value *ucontrol)
623 {
624 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
625 struct rt722_sdca_dmic_kctrl_priv *p =
626 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
627 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
628 unsigned int boost_step = 0x0a00;
629 unsigned int vol_max = 0x1e00;
630 unsigned int gain_val[4];
631 unsigned int i, adc_vol_flag = 0, changed = 0;
632 unsigned int regvalue[4];
633 const unsigned int interval_offset = 0xc0;
634 int err;
635
636 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
637 adc_vol_flag = 1;
638
639 /* check all channels */
640 for (i = 0; i < p->count; i++) {
641 regmap_read(rt722->regmap, p->reg_base + i, ®value[i]);
642
643 gain_val[i] = ucontrol->value.integer.value[i];
644 if (gain_val[i] > p->max)
645 gain_val[i] = p->max;
646
647 if (!adc_vol_flag) /* boost gain */
648 gain_val[i] = gain_val[i] * boost_step;
649 else { /* ADC gain */
650 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset);
651 gain_val[i] &= 0xffff;
652 }
653
654 if (regvalue[i] != gain_val[i])
655 changed = 1;
656 }
657
658 if (!changed)
659 return 0;
660
661 for (i = 0; i < p->count; i++) {
662 err = regmap_write(rt722->regmap, p->reg_base + i, gain_val[i]);
663 if (err < 0)
664 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n",
665 __func__, p->reg_base + i);
666 }
667
668 return changed;
669 }
670
671 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
672 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \
673 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
674 .invert = xinvert})
675
676 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
677 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
678 .info = rt722_sdca_fu_info, \
679 .get = rt722_sdca_fu1e_capture_get, \
680 .put = rt722_sdca_fu1e_capture_put, \
681 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
682
683 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
684 xhandler_put, xcount, xmax, tlv_array) \
685 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
686 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
687 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
688 .tlv.p = (tlv_array), \
689 .info = rt722_sdca_fu_info, \
690 .get = xhandler_get, .put = xhandler_put, \
691 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
692
693 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
694 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
695 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
696
697 static const struct snd_kcontrol_new rt722_sdca_controls[] = {
698 /* Headphone playback settings */
699 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
700 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
701 RT722_SDCA_CTL_FU_VOLUME, CH_L),
702 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
703 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
704 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
705 /* Headset mic capture settings */
706 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
707 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put),
708 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
709 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
710 RT722_SDCA_CTL_FU_VOLUME, CH_L),
711 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
712 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0,
713 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv),
714 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume",
715 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
716 RT722_SDCA_CTL_FU_CH_GAIN, CH_L),
717 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
718 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0,
719 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv),
720 /* AMP playback settings */
721 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
722 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
723 RT722_SDCA_CTL_FU_VOLUME, CH_L),
724 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
725 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
726 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
727 /* DMIC capture settings */
728 RT722_SDCA_FU_CTRL("FU1E Capture Switch",
729 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
730 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4),
731 RT722_SDCA_EXT_TLV("FU1E Capture Volume",
732 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
733 RT722_SDCA_CTL_FU_VOLUME, CH_01),
734 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
735 4, 0x3f, mic_vol_tlv),
736 RT722_SDCA_EXT_TLV("FU15 Boost Volume",
737 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15,
738 RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
739 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
740 4, 3, boost_vol_tlv),
741 };
742
743 static const char * const adc22_mux_text[] = {
744 "MIC2",
745 "LINE1",
746 "LINE2",
747 };
748
749 static const char * const adc07_10_mux_text[] = {
750 "DMIC1",
751 "DMIC2",
752 };
753
754 static SOC_ENUM_SINGLE_DECL(rt722_adc22_enum,
755 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
756 12, adc22_mux_text);
757
758 static SOC_ENUM_SINGLE_DECL(rt722_adc24_enum,
759 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
760 4, adc07_10_mux_text);
761
762 static SOC_ENUM_SINGLE_DECL(rt722_adc25_enum,
763 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
764 0, adc07_10_mux_text);
765
766 static const struct snd_kcontrol_new rt722_sdca_adc22_mux =
767 SOC_DAPM_ENUM("ADC 22 Mux", rt722_adc22_enum);
768
769 static const struct snd_kcontrol_new rt722_sdca_adc24_mux =
770 SOC_DAPM_ENUM("ADC 24 Mux", rt722_adc24_enum);
771
772 static const struct snd_kcontrol_new rt722_sdca_adc25_mux =
773 SOC_DAPM_ENUM("ADC 25 Mux", rt722_adc25_enum);
774
rt722_sdca_fu42_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)775 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w,
776 struct snd_kcontrol *kcontrol, int event)
777 {
778 struct snd_soc_component *component =
779 snd_soc_dapm_to_component(w->dapm);
780 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
781 unsigned char unmute = 0x0, mute = 0x1;
782
783 switch (event) {
784 case SND_SOC_DAPM_POST_PMU:
785 regmap_write(rt722->regmap,
786 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
787 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
788 regmap_write(rt722->regmap,
789 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
790 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
791 break;
792 case SND_SOC_DAPM_PRE_PMD:
793 regmap_write(rt722->regmap,
794 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
795 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
796 regmap_write(rt722->regmap,
797 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
798 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
799 break;
800 }
801 return 0;
802 }
803
rt722_sdca_fu21_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)804 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806 {
807 struct snd_soc_component *component =
808 snd_soc_dapm_to_component(w->dapm);
809 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
810 unsigned char unmute = 0x0, mute = 0x1;
811
812 switch (event) {
813 case SND_SOC_DAPM_POST_PMU:
814 regmap_write(rt722->regmap,
815 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
816 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
817 regmap_write(rt722->regmap,
818 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
819 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
820 break;
821 case SND_SOC_DAPM_PRE_PMD:
822 regmap_write(rt722->regmap,
823 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
824 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
825 regmap_write(rt722->regmap,
826 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
827 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
828 break;
829 }
830 return 0;
831 }
832
rt722_sdca_fu113_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)833 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w,
834 struct snd_kcontrol *kcontrol, int event)
835 {
836 struct snd_soc_component *component =
837 snd_soc_dapm_to_component(w->dapm);
838 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
839
840 switch (event) {
841 case SND_SOC_DAPM_POST_PMU:
842 rt722->fu1e_dapm_mute = false;
843 rt722_sdca_set_fu1e_capture_ctl(rt722);
844 usleep_range(150000, 160000);
845 break;
846 case SND_SOC_DAPM_PRE_PMD:
847 rt722->fu1e_dapm_mute = true;
848 rt722_sdca_set_fu1e_capture_ctl(rt722);
849 break;
850 }
851 return 0;
852 }
853
rt722_sdca_fu36_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)854 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w,
855 struct snd_kcontrol *kcontrol, int event)
856 {
857 struct snd_soc_component *component =
858 snd_soc_dapm_to_component(w->dapm);
859 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
860
861 switch (event) {
862 case SND_SOC_DAPM_POST_PMU:
863 rt722->fu0f_dapm_mute = false;
864 rt722_sdca_set_fu0f_capture_ctl(rt722);
865 break;
866 case SND_SOC_DAPM_PRE_PMD:
867 rt722->fu0f_dapm_mute = true;
868 rt722_sdca_set_fu0f_capture_ctl(rt722);
869 break;
870 }
871 return 0;
872 }
873
rt722_pde_transition_delay(struct rt722_sdca_priv * rt722,unsigned char func,unsigned char entity,unsigned char ps)874 static void rt722_pde_transition_delay(struct rt722_sdca_priv *rt722, unsigned char func,
875 unsigned char entity, unsigned char ps)
876 {
877 unsigned int delay = 1000, val;
878
879 pm_runtime_mark_last_busy(&rt722->slave->dev);
880
881 /* waiting for Actual PDE becomes to PS0/PS3 */
882 while (delay) {
883 regmap_read(rt722->regmap,
884 SDW_SDCA_CTL(func, entity, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
885 if (val == ps)
886 break;
887
888 usleep_range(1000, 1500);
889 delay--;
890 }
891 if (!delay) {
892 dev_warn(&rt722->slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
893 }
894 }
895
rt722_sdca_pde47_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)896 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w,
897 struct snd_kcontrol *kcontrol, int event)
898 {
899 struct snd_soc_component *component =
900 snd_soc_dapm_to_component(w->dapm);
901 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
902 unsigned char ps0 = 0x0, ps3 = 0x3;
903
904 switch (event) {
905 case SND_SOC_DAPM_POST_PMU:
906 regmap_write(rt722->regmap,
907 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
908 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
909 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps0);
910 break;
911 case SND_SOC_DAPM_PRE_PMD:
912 regmap_write(rt722->regmap,
913 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
914 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
915 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps3);
916 break;
917 }
918 return 0;
919 }
920
rt722_sdca_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)921 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w,
922 struct snd_kcontrol *kcontrol, int event)
923 {
924 struct snd_soc_component *component =
925 snd_soc_dapm_to_component(w->dapm);
926 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
927 unsigned char ps0 = 0x0, ps3 = 0x3;
928
929 switch (event) {
930 case SND_SOC_DAPM_POST_PMU:
931 regmap_write(rt722->regmap,
932 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
933 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
934 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps0);
935 break;
936 case SND_SOC_DAPM_PRE_PMD:
937 regmap_write(rt722->regmap,
938 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
939 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
940 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps3);
941 break;
942 }
943 return 0;
944 }
945
rt722_sdca_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)946 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w,
947 struct snd_kcontrol *kcontrol, int event)
948 {
949 struct snd_soc_component *component =
950 snd_soc_dapm_to_component(w->dapm);
951 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
952 unsigned char ps0 = 0x0, ps3 = 0x3;
953
954 switch (event) {
955 case SND_SOC_DAPM_POST_PMU:
956 regmap_write(rt722->regmap,
957 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
958 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
959 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps0);
960 break;
961 case SND_SOC_DAPM_PRE_PMD:
962 regmap_write(rt722->regmap,
963 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
964 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
965 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps3);
966 break;
967 }
968 return 0;
969 }
970
rt722_sdca_pde12_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)971 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w,
972 struct snd_kcontrol *kcontrol, int event)
973 {
974 struct snd_soc_component *component =
975 snd_soc_dapm_to_component(w->dapm);
976 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
977 unsigned char ps0 = 0x0, ps3 = 0x3;
978
979 switch (event) {
980 case SND_SOC_DAPM_POST_PMU:
981 regmap_write(rt722->regmap,
982 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
983 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
984 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps0);
985 break;
986 case SND_SOC_DAPM_PRE_PMD:
987 regmap_write(rt722->regmap,
988 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
989 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
990 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps3);
991 break;
992 }
993 return 0;
994 }
995
996 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = {
997 SND_SOC_DAPM_OUTPUT("HP"),
998 SND_SOC_DAPM_OUTPUT("SPK"),
999 SND_SOC_DAPM_INPUT("MIC2"),
1000 SND_SOC_DAPM_INPUT("LINE1"),
1001 SND_SOC_DAPM_INPUT("LINE2"),
1002 SND_SOC_DAPM_INPUT("DMIC1_2"),
1003 SND_SOC_DAPM_INPUT("DMIC3_4"),
1004
1005 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1006 rt722_sdca_pde23_event,
1007 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1008 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0,
1009 rt722_sdca_pde47_event,
1010 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1011 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1012 rt722_sdca_pde11_event,
1013 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1014 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
1015 rt722_sdca_pde12_event,
1016 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1017
1018 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0,
1019 rt722_sdca_fu21_event,
1020 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1021 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0,
1022 rt722_sdca_fu42_event,
1023 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1024 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0,
1025 rt722_sdca_fu36_event,
1026 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1027 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0,
1028 rt722_sdca_fu113_event,
1029 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1030 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
1031 &rt722_sdca_adc22_mux),
1032 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
1033 &rt722_sdca_adc24_mux),
1034 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
1035 &rt722_sdca_adc25_mux),
1036
1037 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0),
1038 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0),
1039 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0),
1040 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0),
1041 };
1042
1043 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = {
1044 {"FU 42", NULL, "DP1RX"},
1045 {"FU 21", NULL, "DP3RX"},
1046
1047 {"ADC 22 Mux", "MIC2", "MIC2"},
1048 {"ADC 22 Mux", "LINE1", "LINE1"},
1049 {"ADC 22 Mux", "LINE2", "LINE2"},
1050 {"ADC 24 Mux", "DMIC1", "DMIC1_2"},
1051 {"ADC 24 Mux", "DMIC2", "DMIC3_4"},
1052 {"ADC 25 Mux", "DMIC1", "DMIC1_2"},
1053 {"ADC 25 Mux", "DMIC2", "DMIC3_4"},
1054 {"FU 36", NULL, "PDE 12"},
1055 {"FU 36", NULL, "ADC 22 Mux"},
1056 {"FU 113", NULL, "PDE 11"},
1057 {"FU 113", NULL, "ADC 24 Mux"},
1058 {"FU 113", NULL, "ADC 25 Mux"},
1059 {"DP2TX", NULL, "FU 36"},
1060 {"DP6TX", NULL, "FU 113"},
1061
1062 {"HP", NULL, "PDE 47"},
1063 {"HP", NULL, "FU 42"},
1064 {"SPK", NULL, "PDE 23"},
1065 {"SPK", NULL, "FU 21"},
1066 };
1067
rt722_sdca_parse_dt(struct rt722_sdca_priv * rt722,struct device * dev)1068 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev)
1069 {
1070 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src);
1071
1072 return 0;
1073 }
1074
rt722_sdca_probe(struct snd_soc_component * component)1075 static int rt722_sdca_probe(struct snd_soc_component *component)
1076 {
1077 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1078 int ret;
1079
1080 rt722_sdca_parse_dt(rt722, &rt722->slave->dev);
1081 rt722->component = component;
1082
1083 ret = pm_runtime_resume(component->dev);
1084 if (ret < 0 && ret != -EACCES)
1085 return ret;
1086
1087 return 0;
1088 }
1089
1090 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = {
1091 .probe = rt722_sdca_probe,
1092 .controls = rt722_sdca_controls,
1093 .num_controls = ARRAY_SIZE(rt722_sdca_controls),
1094 .dapm_widgets = rt722_sdca_dapm_widgets,
1095 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets),
1096 .dapm_routes = rt722_sdca_audio_map,
1097 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map),
1098 .set_jack = rt722_sdca_set_jack_detect,
1099 .endianness = 1,
1100 };
1101
rt722_sdca_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)1102 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1103 int direction)
1104 {
1105 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1106
1107 return 0;
1108 }
1109
rt722_sdca_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1110 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream,
1111 struct snd_soc_dai *dai)
1112 {
1113 snd_soc_dai_set_dma_data(dai, substream, NULL);
1114 }
1115
rt722_sdca_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1116 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
1117 struct snd_pcm_hw_params *params,
1118 struct snd_soc_dai *dai)
1119 {
1120 struct snd_soc_component *component = dai->component;
1121 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1122 struct sdw_stream_config stream_config;
1123 struct sdw_port_config port_config;
1124 enum sdw_data_direction direction;
1125 struct sdw_stream_runtime *sdw_stream;
1126 int retval, port, num_channels;
1127 unsigned int sampling_rate;
1128
1129 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1130 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1131
1132 if (!sdw_stream)
1133 return -EINVAL;
1134
1135 if (!rt722->slave)
1136 return -EINVAL;
1137
1138 /*
1139 * RT722_AIF1 with port = 1 for headphone playback
1140 * RT722_AIF1 with port = 2 for headset-mic capture
1141 * RT722_AIF2 with port = 3 for speaker playback
1142 * RT722_AIF3 with port = 6 for digital-mic capture
1143 */
1144 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1145 direction = SDW_DATA_DIR_RX;
1146 if (dai->id == RT722_AIF1)
1147 port = 1;
1148 else if (dai->id == RT722_AIF2)
1149 port = 3;
1150 else
1151 return -EINVAL;
1152 } else {
1153 direction = SDW_DATA_DIR_TX;
1154 if (dai->id == RT722_AIF1)
1155 port = 2;
1156 else if (dai->id == RT722_AIF3)
1157 port = 6;
1158 else
1159 return -EINVAL;
1160 }
1161 stream_config.frame_rate = params_rate(params);
1162 stream_config.ch_count = params_channels(params);
1163 stream_config.bps = snd_pcm_format_width(params_format(params));
1164 stream_config.direction = direction;
1165
1166 num_channels = params_channels(params);
1167 port_config.ch_mask = GENMASK(num_channels - 1, 0);
1168 port_config.num = port;
1169
1170 retval = sdw_stream_add_slave(rt722->slave, &stream_config,
1171 &port_config, 1, sdw_stream);
1172 if (retval) {
1173 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1174 return retval;
1175 }
1176
1177 if (params_channels(params) > 16) {
1178 dev_err(component->dev, "%s: Unsupported channels %d\n",
1179 __func__, params_channels(params));
1180 return -EINVAL;
1181 }
1182
1183 /* sampling rate configuration */
1184 switch (params_rate(params)) {
1185 case 44100:
1186 sampling_rate = RT722_SDCA_RATE_44100HZ;
1187 break;
1188 case 48000:
1189 sampling_rate = RT722_SDCA_RATE_48000HZ;
1190 break;
1191 case 96000:
1192 sampling_rate = RT722_SDCA_RATE_96000HZ;
1193 break;
1194 case 192000:
1195 sampling_rate = RT722_SDCA_RATE_192000HZ;
1196 break;
1197 default:
1198 dev_err(component->dev, "%s: Rate %d is not supported\n",
1199 __func__, params_rate(params));
1200 return -EINVAL;
1201 }
1202
1203 /* set sampling frequency */
1204 if (dai->id == RT722_AIF1) {
1205 regmap_write(rt722->regmap,
1206 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01,
1207 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1208 regmap_write(rt722->regmap,
1209 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11,
1210 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1211 }
1212
1213 if (dai->id == RT722_AIF2)
1214 regmap_write(rt722->regmap,
1215 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
1216 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1217
1218 if (dai->id == RT722_AIF3)
1219 regmap_write(rt722->regmap,
1220 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F,
1221 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1222
1223 return 0;
1224 }
1225
rt722_sdca_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1226 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
1227 struct snd_soc_dai *dai)
1228 {
1229 struct snd_soc_component *component = dai->component;
1230 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1231 struct sdw_stream_runtime *sdw_stream =
1232 snd_soc_dai_get_dma_data(dai, substream);
1233
1234 if (!rt722->slave)
1235 return -EINVAL;
1236
1237 sdw_stream_remove_slave(rt722->slave, sdw_stream);
1238 return 0;
1239 }
1240
1241 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
1242 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
1243 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1244 SNDRV_PCM_FMTBIT_S24_LE)
1245
1246 static const struct snd_soc_dai_ops rt722_sdca_ops = {
1247 .hw_params = rt722_sdca_pcm_hw_params,
1248 .hw_free = rt722_sdca_pcm_hw_free,
1249 .set_stream = rt722_sdca_set_sdw_stream,
1250 .shutdown = rt722_sdca_shutdown,
1251 };
1252
1253 static struct snd_soc_dai_driver rt722_sdca_dai[] = {
1254 {
1255 .name = "rt722-sdca-aif1",
1256 .id = RT722_AIF1,
1257 .playback = {
1258 .stream_name = "DP1 Headphone Playback",
1259 .channels_min = 1,
1260 .channels_max = 2,
1261 .rates = RT722_STEREO_RATES,
1262 .formats = RT722_FORMATS,
1263 },
1264 .capture = {
1265 .stream_name = "DP2 Headset Capture",
1266 .channels_min = 1,
1267 .channels_max = 2,
1268 .rates = RT722_STEREO_RATES,
1269 .formats = RT722_FORMATS,
1270 },
1271 .ops = &rt722_sdca_ops,
1272 },
1273 {
1274 .name = "rt722-sdca-aif2",
1275 .id = RT722_AIF2,
1276 .playback = {
1277 .stream_name = "DP3 Speaker Playback",
1278 .channels_min = 1,
1279 .channels_max = 2,
1280 .rates = RT722_STEREO_RATES,
1281 .formats = RT722_FORMATS,
1282 },
1283 .ops = &rt722_sdca_ops,
1284 },
1285 {
1286 .name = "rt722-sdca-aif3",
1287 .id = RT722_AIF3,
1288 .capture = {
1289 .stream_name = "DP6 DMic Capture",
1290 .channels_min = 1,
1291 .channels_max = 4,
1292 .rates = RT722_STEREO_RATES,
1293 .formats = RT722_FORMATS,
1294 },
1295 .ops = &rt722_sdca_ops,
1296 }
1297 };
1298
rt722_sdca_init(struct device * dev,struct regmap * regmap,struct sdw_slave * slave)1299 int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct sdw_slave *slave)
1300 {
1301 struct rt722_sdca_priv *rt722;
1302
1303 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL);
1304 if (!rt722)
1305 return -ENOMEM;
1306
1307 dev_set_drvdata(dev, rt722);
1308 rt722->slave = slave;
1309 rt722->regmap = regmap;
1310
1311 regcache_cache_only(rt722->regmap, true);
1312
1313 mutex_init(&rt722->calibrate_mutex);
1314 mutex_init(&rt722->disable_irq_lock);
1315
1316 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler);
1317 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler);
1318
1319 /*
1320 * Mark hw_init to false
1321 * HW init will be performed when device reports present
1322 */
1323 rt722->hw_init = false;
1324 rt722->first_hw_init = false;
1325 rt722->fu1e_dapm_mute = true;
1326 rt722->fu0f_dapm_mute = true;
1327 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true;
1328 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] =
1329 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true;
1330
1331 return devm_snd_soc_register_component(dev,
1332 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai));
1333 }
1334
rt722_sdca_dmic_preset(struct rt722_sdca_priv * rt722)1335 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722)
1336 {
1337 unsigned int mic_func_status;
1338 struct device *dev = &rt722->slave->dev;
1339
1340 regmap_read(rt722->regmap,
1341 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &mic_func_status);
1342 dev_dbg(dev, "%s mic func_status=0x%x\n", __func__, mic_func_status);
1343
1344 if ((mic_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1345 /* Set AD07 power entity floating control */
1346 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1347 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29);
1348 /* Set AD10 power entity floating control */
1349 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1350 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00);
1351 /* Set DMIC1/DMIC2 power entity floating control */
1352 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1353 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a);
1354 /* Set DMIC2 IT entity floating control */
1355 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1356 RT722_DMIC_ENT_FLOAT_CTL, 0x2626);
1357 /* Set AD10 FU entity floating control */
1358 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1359 RT722_ADC_ENT_FLOAT_CTL, 0x1e00);
1360 /* Set DMIC2 FU entity floating control */
1361 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1362 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
1363 /* Set AD10 FU channel floating control */
1364 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1365 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304);
1366 /* Set DMIC2 FU channel floating control */
1367 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1368 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
1369 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */
1370 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1371 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000);
1372 /* Enable vf707_r12_05/vf707_r13_05 */
1373 regmap_write(rt722->regmap,
1374 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26,
1375 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01);
1376 /* Fine tune PDE2A latency */
1377 regmap_write(rt722->regmap, 0x2f5c, 0x25);
1378 /* PHYtiming TDZ/TZD control */
1379 regmap_write(rt722->regmap, 0x2f03, 0x06);
1380
1381 /* clear flag */
1382 regmap_write(rt722->regmap,
1383 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1384 FUNCTION_NEEDS_INITIALIZATION);
1385 }
1386 }
1387
rt722_sdca_amp_preset(struct rt722_sdca_priv * rt722)1388 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722)
1389 {
1390 unsigned int amp_func_status;
1391 struct device *dev = &rt722->slave->dev;
1392
1393 regmap_read(rt722->regmap,
1394 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
1395 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
1396
1397 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1398 /* Set DVQ=01 */
1399 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1400 0xc215);
1401 /* Reset dc_cal_top */
1402 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1403 0x702c);
1404 /* W1C Trigger Calibration */
1405 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1406 0xf02d);
1407 /* Set DAC02/ClassD power entity floating control */
1408 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL,
1409 0x2323);
1410 /* Set EAPD high */
1411 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL,
1412 0x0002);
1413 /* Enable vf707_r14 */
1414 regmap_write(rt722->regmap,
1415 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23,
1416 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04);
1417
1418 /* clear flag */
1419 regmap_write(rt722->regmap,
1420 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1421 FUNCTION_NEEDS_INITIALIZATION);
1422 }
1423 }
1424
rt722_sdca_jack_preset(struct rt722_sdca_priv * rt722)1425 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722)
1426 {
1427 int loop_check, chk_cnt = 100, ret;
1428 unsigned int calib_status = 0;
1429 unsigned int jack_func_status;
1430 struct device *dev = &rt722->slave->dev;
1431
1432 regmap_read(rt722->regmap,
1433 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &jack_func_status);
1434 dev_dbg(dev, "%s jack func_status=0x%x\n", __func__, jack_func_status);
1435
1436 if ((jack_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1437 /* Config analog bias */
1438 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3,
1439 0xa081);
1440 /* GE related settings */
1441 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2,
1442 0xa009);
1443 /* Button A, B, C, D bypass mode */
1444 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4,
1445 0xcf00);
1446 /* HID1 slot enable */
1447 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5,
1448 0x000f);
1449 /* Report ID for HID1 */
1450 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0,
1451 0x1100);
1452 /* OSC/OOC for slot 2, 3 */
1453 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7,
1454 0x0c12);
1455 /* Set JD de-bounce clock control */
1456 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1,
1457 0x7002);
1458 /* Set DVQ=01 */
1459 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1460 0xc215);
1461 /* FSM switch to calibration manual mode */
1462 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL,
1463 0x4100);
1464 /* W1C Trigger DC calibration (HP) */
1465 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3,
1466 0x008d);
1467 /* check HP calibration FSM status */
1468 for (loop_check = 0; loop_check < chk_cnt; loop_check++) {
1469 usleep_range(10000, 11000);
1470 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI,
1471 RT722_DAC_DC_CALI_CTL3, &calib_status);
1472 if (ret < 0)
1473 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret);
1474 if ((calib_status & 0x0040) == 0x0)
1475 break;
1476 }
1477
1478 if (loop_check == chk_cnt)
1479 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__);
1480
1481 /* Set ADC09 power entity floating control */
1482 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL,
1483 0x2a12);
1484 /* Set MIC2 and LINE1 power entity floating control */
1485 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL,
1486 0x3429);
1487 /* Set ET41h and LINE2 power entity floating control */
1488 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL,
1489 0x4112);
1490 /* Set DAC03 and HP power entity floating control */
1491 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL,
1492 0x4040);
1493 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1,
1494 0x4141);
1495 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1,
1496 0x0101);
1497 /* Fine tune PDE40 latency */
1498 regmap_write(rt722->regmap, 0x2f58, 0x07);
1499 regmap_write(rt722->regmap, 0x2f03, 0x06);
1500 /* MIC VRefo */
1501 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1502 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200);
1503 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1504 RT722_VREFO_GAT, 0x4000, 0x4000);
1505 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
1506 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4,
1507 0x0010);
1508
1509 /* clear flag */
1510 regmap_write(rt722->regmap,
1511 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1512 FUNCTION_NEEDS_INITIALIZATION);
1513 }
1514 }
1515
rt722_sdca_io_init(struct device * dev,struct sdw_slave * slave)1516 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
1517 {
1518 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
1519
1520 rt722->disable_irq = false;
1521
1522 if (rt722->hw_init)
1523 return 0;
1524
1525 regcache_cache_only(rt722->regmap, false);
1526 if (rt722->first_hw_init) {
1527 regcache_cache_bypass(rt722->regmap, true);
1528 } else {
1529 /*
1530 * PM runtime is only enabled when a Slave reports as Attached
1531 */
1532
1533 /* set autosuspend parameters */
1534 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1535 pm_runtime_use_autosuspend(&slave->dev);
1536
1537 /* update count of parent 'active' children */
1538 pm_runtime_set_active(&slave->dev);
1539
1540 /* make sure the device does not suspend immediately */
1541 pm_runtime_mark_last_busy(&slave->dev);
1542
1543 pm_runtime_enable(&slave->dev);
1544 }
1545
1546 pm_runtime_get_noresume(&slave->dev);
1547
1548 rt722_sdca_dmic_preset(rt722);
1549 rt722_sdca_amp_preset(rt722);
1550 rt722_sdca_jack_preset(rt722);
1551
1552 if (rt722->first_hw_init) {
1553 regcache_cache_bypass(rt722->regmap, false);
1554 regcache_mark_dirty(rt722->regmap);
1555 } else
1556 rt722->first_hw_init = true;
1557
1558 /* Mark Slave initialization complete */
1559 rt722->hw_init = true;
1560
1561 pm_runtime_put_autosuspend(&slave->dev);
1562
1563 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1564 return 0;
1565 }
1566
1567 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
1568 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1569 MODULE_LICENSE("GPL");
1570