1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/dmi.h> 12 #include <linux/firmware.h> 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/soundwire/sdw_registers.h> 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/tlv.h> 27 28 #include "rt722-sdca.h" 29 30 #define RT722_NID_ADDR(nid, reg) ((nid) << 20 | (reg)) 31 32 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, 33 unsigned int nid, unsigned int reg, unsigned int value) 34 { 35 struct regmap *regmap = rt722->regmap; 36 unsigned int addr = RT722_NID_ADDR(nid, reg); 37 int ret; 38 39 ret = regmap_write(regmap, addr, value); 40 if (ret < 0) 41 dev_err(&rt722->slave->dev, 42 "%s: Failed to set private value: %06x <= %04x ret=%d\n", 43 __func__, addr, value, ret); 44 45 return ret; 46 } 47 48 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, 49 unsigned int nid, unsigned int reg, unsigned int *value) 50 { 51 int ret; 52 struct regmap *regmap = rt722->regmap; 53 unsigned int addr = RT722_NID_ADDR(nid, reg); 54 55 ret = regmap_read(regmap, addr, value); 56 if (ret < 0) 57 dev_err(&rt722->slave->dev, 58 "%s: Failed to get private value: %06x => %04x ret=%d\n", 59 __func__, addr, *value, ret); 60 61 return ret; 62 } 63 64 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722, 65 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val) 66 { 67 unsigned int tmp; 68 int ret; 69 70 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp); 71 if (ret < 0) 72 return ret; 73 74 set_mask_bits(&tmp, mask, val); 75 return rt722_sdca_index_write(rt722, nid, reg, tmp); 76 } 77 78 static int rt722_sdca_btn_type(unsigned char *buffer) 79 { 80 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || 81 (*(buffer + 1) == 0x10)) 82 return SND_JACK_BTN_2; 83 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) || 84 (*(buffer + 1) == 0x20)) 85 return SND_JACK_BTN_3; 86 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) || 87 (*(buffer + 1) == 0x40)) 88 return SND_JACK_BTN_0; 89 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) || 90 (*(buffer + 1) == 0x80)) 91 return SND_JACK_BTN_1; 92 93 return 0; 94 } 95 96 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722) 97 { 98 unsigned int btn_type = 0, offset, idx, val, owner; 99 int ret; 100 unsigned char buf[3]; 101 102 /* get current UMP message owner */ 103 ret = regmap_read(rt722->regmap, 104 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 105 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 106 if (ret < 0) 107 return 0; 108 109 /* if owner is device then there is no button event from device */ 110 if (owner == 1) 111 return 0; 112 113 /* read UMP message offset */ 114 ret = regmap_read(rt722->regmap, 115 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 116 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 117 if (ret < 0) 118 goto _end_btn_det_; 119 120 for (idx = 0; idx < sizeof(buf); idx++) { 121 ret = regmap_read(rt722->regmap, 122 RT722_BUF_ADDR_HID1 + offset + idx, &val); 123 if (ret < 0) 124 goto _end_btn_det_; 125 buf[idx] = val & 0xff; 126 } 127 128 if (buf[0] == 0x11) 129 btn_type = rt722_sdca_btn_type(&buf[1]); 130 131 _end_btn_det_: 132 /* Host is owner, so set back to device */ 133 if (owner == 0) 134 /* set owner to device */ 135 regmap_write(rt722->regmap, 136 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 137 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 138 139 return btn_type; 140 } 141 142 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722) 143 { 144 unsigned int det_mode; 145 int ret; 146 147 /* get detected_mode */ 148 ret = regmap_read(rt722->regmap, 149 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 150 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 151 if (ret < 0) 152 goto io_error; 153 154 switch (det_mode) { 155 case 0x00: 156 rt722->jack_type = 0; 157 break; 158 case 0x03: 159 rt722->jack_type = SND_JACK_HEADPHONE; 160 break; 161 case 0x05: 162 rt722->jack_type = SND_JACK_HEADSET; 163 break; 164 } 165 166 /* write selected_mode */ 167 if (det_mode) { 168 ret = regmap_write(rt722->regmap, 169 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 170 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode); 171 if (ret < 0) 172 goto io_error; 173 } 174 175 dev_dbg(&rt722->slave->dev, 176 "%s, detected_mode=0x%x\n", __func__, det_mode); 177 178 return 0; 179 180 io_error: 181 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 182 return ret; 183 } 184 185 static void rt722_sdca_jack_detect_handler(struct work_struct *work) 186 { 187 struct rt722_sdca_priv *rt722 = 188 container_of(work, struct rt722_sdca_priv, jack_detect_work.work); 189 int btn_type = 0, ret; 190 191 if (!rt722->hs_jack) 192 return; 193 194 if (!rt722->component->card || !rt722->component->card->instantiated) 195 return; 196 197 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */ 198 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) { 199 ret = rt722_sdca_headset_detect(rt722); 200 if (ret < 0) 201 return; 202 } 203 204 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 205 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 206 btn_type = rt722_sdca_button_detect(rt722); 207 208 if (rt722->jack_type == 0) 209 btn_type = 0; 210 211 dev_dbg(&rt722->slave->dev, 212 "in %s, jack_type=%d\n", __func__, rt722->jack_type); 213 dev_dbg(&rt722->slave->dev, 214 "in %s, btn_type=0x%x\n", __func__, btn_type); 215 dev_dbg(&rt722->slave->dev, 216 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 217 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 218 219 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 220 SND_JACK_HEADSET | 221 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 222 SND_JACK_BTN_2 | SND_JACK_BTN_3); 223 224 if (btn_type) { 225 /* button released */ 226 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 227 SND_JACK_HEADSET | 228 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 229 SND_JACK_BTN_2 | SND_JACK_BTN_3); 230 231 mod_delayed_work(system_power_efficient_wq, 232 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 233 } 234 } 235 236 static void rt722_sdca_btn_check_handler(struct work_struct *work) 237 { 238 struct rt722_sdca_priv *rt722 = 239 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work); 240 int btn_type = 0, ret, idx; 241 unsigned int det_mode, offset, val; 242 unsigned char buf[3]; 243 244 ret = regmap_read(rt722->regmap, 245 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 246 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 247 if (ret < 0) 248 goto io_error; 249 250 /* pin attached */ 251 if (det_mode) { 252 /* read UMP message offset */ 253 ret = regmap_read(rt722->regmap, 254 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 255 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 256 if (ret < 0) 257 goto io_error; 258 259 for (idx = 0; idx < sizeof(buf); idx++) { 260 ret = regmap_read(rt722->regmap, 261 RT722_BUF_ADDR_HID1 + offset + idx, &val); 262 if (ret < 0) 263 goto io_error; 264 buf[idx] = val & 0xff; 265 } 266 267 if (buf[0] == 0x11) 268 btn_type = rt722_sdca_btn_type(&buf[1]); 269 } else 270 rt722->jack_type = 0; 271 272 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 273 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 274 SND_JACK_HEADSET | 275 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 276 SND_JACK_BTN_2 | SND_JACK_BTN_3); 277 278 if (btn_type) { 279 /* button released */ 280 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 281 SND_JACK_HEADSET | 282 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 283 SND_JACK_BTN_2 | SND_JACK_BTN_3); 284 285 mod_delayed_work(system_power_efficient_wq, 286 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 287 } 288 289 return; 290 291 io_error: 292 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 293 } 294 295 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722) 296 { 297 mutex_lock(&rt722->calibrate_mutex); 298 if (rt722->hs_jack) { 299 /* set SCP_SDCA_IntMask1[0]=1 */ 300 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 301 SDW_SCP_SDCA_INTMASK_SDCA_0); 302 /* set SCP_SDCA_IntMask2[0]=1 */ 303 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 304 SDW_SCP_SDCA_INTMASK_SDCA_8); 305 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__); 306 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 307 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E); 308 /* set XU(et03h) & XU(et0Dh) to Not bypassed */ 309 regmap_write(rt722->regmap, 310 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, 311 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 312 regmap_write(rt722->regmap, 313 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 314 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 315 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000); 316 /* trigger GE interrupt */ 317 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 318 RT722_GE_RELATED_CTL2, 0x4000, 0x4000); 319 } 320 mutex_unlock(&rt722->calibrate_mutex); 321 } 322 323 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component, 324 struct snd_soc_jack *hs_jack, void *data) 325 { 326 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 327 int ret; 328 329 rt722->hs_jack = hs_jack; 330 331 ret = pm_runtime_resume_and_get(component->dev); 332 if (ret < 0) { 333 if (ret != -EACCES) { 334 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 335 return ret; 336 } 337 /* pm_runtime not enabled yet */ 338 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 339 return 0; 340 } 341 342 rt722_sdca_jack_init(rt722); 343 344 pm_runtime_put_autosuspend(component->dev); 345 346 return 0; 347 } 348 349 static int rt722_cae_load(struct rt722_sdca_priv *rt722) 350 { 351 struct device *dev = &rt722->slave->dev; 352 static const char func_tag[] = "FUNC"; 353 static const char xu_tag[] = "XU"; 354 const char *dmi_vendor, *dmi_product, *dmi_sku; 355 char *cae_filename; 356 const struct firmware *cae_fw = NULL; 357 unsigned int cae_st_spk, cae_st_hp, cae_st_mic; 358 unsigned int func, value; 359 unsigned int combined_val; 360 unsigned int addr, size; 361 unsigned int fw_offset; 362 unsigned char mbq_high_val = 0; 363 unsigned char *param_data; 364 unsigned char *fw_data; 365 char tag[5]; 366 char *space; 367 int v_len, p_len, s_len; 368 int ret = 0, i; 369 int retry = 50; 370 371 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 372 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 373 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 374 375 if (!dmi_vendor || !dmi_product || !dmi_sku) { 376 dev_warn(dev, "%s: Incomplete DMI info\n", __func__); 377 return -EINVAL; 378 } 379 space = strchr(dmi_vendor, ' '); 380 v_len = space ? space - dmi_vendor : strlen(dmi_vendor); 381 382 space = strchr(dmi_product, ' '); 383 p_len = space ? space - dmi_product : strlen(dmi_product); 384 385 space = strchr(dmi_sku, ' '); 386 s_len = space ? space - dmi_sku : strlen(dmi_sku); 387 388 cae_filename = kasprintf(GFP_KERNEL, 389 "realtek/rt722/rt722_RAE_%.*s_%.*s_%.*s.dat", 390 v_len, dmi_vendor, 391 p_len, dmi_product, 392 s_len, dmi_sku); 393 if (!cae_filename) 394 return -ENOMEM; 395 dev_dbg(dev, "%s: try to load CAE file %s\n", __func__, cae_filename); 396 397 regmap_write(rt722->regmap, RT722_SPK_CAE_PARAM1, 0x5f); 398 regmap_write(rt722->regmap, RT722_HP_CAE_PARAM39, 0x5f); 399 regmap_write(rt722->regmap, RT722_MIC_CAE_PARAM39, 0x5f); 400 usleep_range(50000, 60000); 401 402 request_firmware(&cae_fw, cae_filename, dev); 403 kfree(cae_filename); 404 if (!cae_fw) { 405 dev_err(dev, "%s: Failed to load CAE firmware\n", __func__); 406 return -ENOENT; 407 } 408 409 regmap_read(rt722->regmap, RT722_SPK_CAE_PARAM38, &cae_st_spk); 410 regmap_read(rt722->regmap, RT722_HP_CAE_PARAM68, &cae_st_hp); 411 regmap_read(rt722->regmap, RT722_MIC_CAE_PARAM99, &cae_st_mic); 412 cae_st_spk &= 0x80; 413 cae_st_hp &= 0x80; 414 cae_st_mic &= 0x80; 415 416 dev_dbg(dev, "%s(%d) spk_crc:%x, hp_crc:%x, mic_crc:%x\n", 417 __func__, __LINE__, cae_st_spk, cae_st_hp, cae_st_mic); 418 419 if (cae_st_spk) 420 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 421 RT722_EQ_CTRL_SPK, 0x0008, 0x0008); 422 else if (cae_st_hp) 423 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 424 RT722_EQ_CTRL_HP, 0x0008, 0x0008); 425 else if (cae_st_mic) 426 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 427 RT722_EQ_CTRL_DMIC, 0x0008, 0x0008); 428 429 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 430 RT722_MISC_CTRL1, 0x8000, 0x8000); 431 432 regmap_update_bits(rt722->regmap, RT722_SPK_CAE_PARAM34, 0x1, 0x0); 433 regmap_update_bits(rt722->regmap, RT722_HP_CAE_PARAM64, 0x1, 0x0); 434 regmap_update_bits(rt722->regmap, RT722_MIC_CAE_PARAM95, 0x1, 0x0); 435 436 while (--retry) { 437 regmap_read(rt722->regmap, RT722_SPK_CAE_PARAM35, &cae_st_spk); 438 regmap_read(rt722->regmap, RT722_HP_CAE_PARAM65, &cae_st_hp); 439 regmap_read(rt722->regmap, RT722_MIC_CAE_PARAM96, &cae_st_mic); 440 dev_dbg(dev, "%s(%d) cae_st_spk:%x, cae_st_hp:%x, cae_st_mic:%x\n", 441 __func__, __LINE__, cae_st_spk, cae_st_hp, cae_st_mic); 442 if ((cae_st_spk & 0x40) && (cae_st_hp & 0x40) && (cae_st_mic & 0x40)) 443 break; 444 usleep_range(1000, 1100); 445 } 446 447 if (!retry && !((cae_st_spk & 0x40) && (cae_st_hp & 0x40) 448 && (cae_st_mic & 0x40))) { 449 dev_err(dev, "%s: CAE is not ready to be loaded.\n", __func__); 450 ret = -ETIMEDOUT; 451 goto out_release; 452 } 453 454 dev_dbg(dev, "%s, cae_fw size=0x%zx, start\n", __func__, cae_fw->size); 455 456 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 457 RT722_EQ_CTRL_AMIC, 0x8000); 458 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 459 RT722_EQ_CTRL_DMIC, 0x8004); 460 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 461 RT722_EQ_CTRL_HP, 0x8074); 462 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 463 RT722_EQ_CTRL_SPK, 0xa074); 464 465 regcache_cache_bypass(rt722->regmap, true); 466 for (fw_offset = 0; fw_offset < cae_fw->size;) { 467 468 if (fw_offset + 12 > cae_fw->size) { 469 dev_err(dev, "%s: Unexpected end of firmware\n", __func__); 470 ret = -EINVAL; 471 goto verify_abort; 472 } 473 474 fw_data = (unsigned char *)&cae_fw->data[fw_offset]; 475 memcpy(tag, fw_data, 4); 476 tag[4] = '\0'; 477 478 if (strcmp(tag, xu_tag) == 0) { 479 dev_dbg(dev, "%s: This is a XU tag", __func__); 480 memcpy(&addr, (fw_data + 4), 4); 481 memcpy(&size, (fw_data + 8), 4); 482 483 if (size == 0 || size > cae_fw->size - fw_offset - 12) { 484 dev_err(dev, "%s: Invalid payload size: %u\n", __func__, size); 485 ret = -EINVAL; 486 goto verify_abort; 487 } 488 489 param_data = (unsigned char *)(fw_data + 12); 490 491 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size); 492 493 if ((addr <= 0x05302300 && addr >= 0x05300000) || 494 (addr <= 0x020020b4 && addr >= 0x020000b1)) { 495 if (addr & BIT(13)) { 496 mbq_high_val = param_data[0]; 497 dev_dbg(dev, "MBQ: High Byte 0x%02x\n", mbq_high_val); 498 fw_offset += (size + 12); 499 500 continue; 501 } else { 502 regcache_cache_bypass(rt722->regmap, false); 503 combined_val = (mbq_high_val << 8) | param_data[0]; 504 if (addr == 0x20000b1 || addr == 0x20000b4) 505 combined_val |= (0x2 << 8); 506 ret = regmap_write(rt722->regmap, addr, combined_val); 507 if (ret) { 508 dev_err(dev, 509 "MBQ fail: addr=0x%x ret=%d\n", addr, ret); 510 regcache_cache_bypass(rt722->regmap, true); 511 goto verify_abort; 512 } 513 514 dev_dbg(dev, "MBQ-reg=0x%x, value=0x%x\n", 515 addr, combined_val); 516 517 fw_offset += (size + 12); 518 regcache_cache_bypass(rt722->regmap, true); 519 continue; 520 } 521 } 522 523 for (i = 0; i < size; i++) { 524 ret = regmap_write(rt722->regmap, addr + i, param_data[i]); 525 if (ret) { 526 dev_err(dev, 527 "CAE write fail: addr=0x%x ret=%d\n", 528 addr + i, ret); 529 goto verify_abort; 530 } 531 } 532 fw_offset += (size + 12); 533 } else if (strcmp(tag, func_tag) == 0) { 534 dev_dbg(dev, "%s: This is a FUNC tag", __func__); 535 536 memcpy(&func, (fw_data + 4), 4); 537 memcpy(&value, (fw_data + 8), 4); 538 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", 539 __func__, func, value); 540 541 if (func == 1) 542 msleep(value); 543 544 fw_offset += 12; 545 } else { 546 dev_err(dev, "%s: No XU/FUNC tag at fw_offset=0x%x\n", 547 __func__, fw_offset); 548 ret = -EINVAL; 549 goto verify_abort; 550 } 551 } 552 553 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 554 RT722_MISC_CTRL1, 0x8000, 0x0000); 555 regcache_cache_bypass(rt722->regmap, false); 556 rt722->cae_update_done = 1; 557 dev_dbg(dev, "%s: CAE FW update done.\n", __func__); 558 release_firmware(cae_fw); 559 return 0; 560 561 verify_abort: 562 regcache_cache_bypass(rt722->regmap, false); 563 if (!ret) 564 ret = -EIO; 565 out_release: 566 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 567 RT722_MISC_CTRL1, 0x8000, 0x0000); 568 release_firmware(cae_fw); 569 dev_err(dev, "%s: CAE FW update aborted (ret=%d).\n", __func__, ret); 570 return ret; 571 } 572 573 static int rt722_cae_update_put(struct snd_kcontrol *kcontrol, 574 struct snd_ctl_elem_value *ucontrol) 575 { 576 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 577 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 578 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 579 int ret, changed = 0; 580 581 if (!rt722->hw_init) 582 return 0; 583 584 ret = pm_runtime_resume_and_get(component->dev); 585 if (ret < 0 && ret != -EACCES) 586 return ret; 587 588 if (ucontrol->value.integer.value[0]) { 589 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 590 ret = rt722_cae_load(rt722); 591 if (ret) { 592 dev_err(component->dev, "CAE load failed: %d\n", ret); 593 goto out; 594 } else 595 changed = 1; 596 } 597 } else { 598 if (rt722->cae_update_done) { 599 rt722->cae_update_done = 0; 600 changed = 1; 601 } 602 } 603 604 out: 605 pm_runtime_mark_last_busy(component->dev); 606 pm_runtime_put_autosuspend(component->dev); 607 608 return ret < 0 ? ret : changed; 609 } 610 611 static int rt722_cae_update_get(struct snd_kcontrol *kcontrol, 612 struct snd_ctl_elem_value *ucontrol) 613 { 614 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 615 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 616 617 ucontrol->value.integer.value[0] = rt722->cae_update_done; 618 619 return 0; 620 } 621 622 623 /* For SDCA control DAC/ADC Gain */ 624 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 625 struct snd_ctl_elem_value *ucontrol) 626 { 627 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 628 struct soc_mixer_control *mc = 629 (struct soc_mixer_control *)kcontrol->private_value; 630 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 631 unsigned int read_l, read_r, gain_l_val, gain_r_val; 632 unsigned int adc_vol_flag = 0, changed = 0; 633 unsigned int lvalue, rvalue; 634 const unsigned int interval_offset = 0xc0; 635 const unsigned int tendB = 0xa00; 636 637 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 638 strstr(ucontrol->id.name, "FU0F Capture Volume")) 639 adc_vol_flag = 1; 640 641 regmap_read(rt722->regmap, mc->reg, &lvalue); 642 regmap_read(rt722->regmap, mc->rreg, &rvalue); 643 644 /* L Channel */ 645 gain_l_val = ucontrol->value.integer.value[0]; 646 if (gain_l_val > mc->max) 647 gain_l_val = mc->max; 648 649 if (mc->shift == 8) /* boost gain */ 650 gain_l_val = gain_l_val * tendB; 651 else { 652 /* ADC/DAC gain */ 653 if (adc_vol_flag) 654 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 655 else 656 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 657 gain_l_val &= 0xffff; 658 } 659 660 /* R Channel */ 661 gain_r_val = ucontrol->value.integer.value[1]; 662 if (gain_r_val > mc->max) 663 gain_r_val = mc->max; 664 665 if (mc->shift == 8) /* boost gain */ 666 gain_r_val = gain_r_val * tendB; 667 else { 668 /* ADC/DAC gain */ 669 if (adc_vol_flag) 670 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 671 else 672 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 673 gain_r_val &= 0xffff; 674 } 675 676 if (lvalue != gain_l_val || rvalue != gain_r_val) 677 changed = 1; 678 else 679 return 0; 680 681 /* Lch*/ 682 regmap_write(rt722->regmap, mc->reg, gain_l_val); 683 684 /* Rch */ 685 regmap_write(rt722->regmap, mc->rreg, gain_r_val); 686 687 regmap_read(rt722->regmap, mc->reg, &read_l); 688 regmap_read(rt722->regmap, mc->rreg, &read_r); 689 if (read_r == gain_r_val && read_l == gain_l_val) 690 return changed; 691 692 return -EIO; 693 } 694 695 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 696 struct snd_ctl_elem_value *ucontrol) 697 { 698 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 699 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 700 struct soc_mixer_control *mc = 701 (struct soc_mixer_control *)kcontrol->private_value; 702 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 703 unsigned int adc_vol_flag = 0; 704 const unsigned int interval_offset = 0xc0; 705 const unsigned int tendB = 0xa00; 706 707 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 708 strstr(ucontrol->id.name, "FU0F Capture Volume")) 709 adc_vol_flag = 1; 710 711 regmap_read(rt722->regmap, mc->reg, &read_l); 712 regmap_read(rt722->regmap, mc->rreg, &read_r); 713 714 if (mc->shift == 8) /* boost gain */ 715 ctl_l = read_l / tendB; 716 else { 717 if (adc_vol_flag) 718 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 719 else 720 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 721 } 722 723 if (read_l != read_r) { 724 if (mc->shift == 8) /* boost gain */ 725 ctl_r = read_r / tendB; 726 else { /* ADC/DAC gain */ 727 if (adc_vol_flag) 728 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 729 else 730 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 731 } 732 } else { 733 ctl_r = ctl_l; 734 } 735 736 ucontrol->value.integer.value[0] = ctl_l; 737 ucontrol->value.integer.value[1] = ctl_r; 738 739 return 0; 740 } 741 742 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722) 743 { 744 int err, i; 745 unsigned int ch_mute; 746 747 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) { 748 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i]; 749 err = regmap_write(rt722->regmap, 750 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 751 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 752 if (err < 0) 753 return err; 754 } 755 756 return 0; 757 } 758 759 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 760 struct snd_ctl_elem_value *ucontrol) 761 { 762 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 763 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 764 struct rt722_sdca_dmic_kctrl_priv *p = 765 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 766 unsigned int i; 767 768 for (i = 0; i < p->count; i++) 769 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i]; 770 771 return 0; 772 } 773 774 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 775 struct snd_ctl_elem_value *ucontrol) 776 { 777 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 778 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 779 struct rt722_sdca_dmic_kctrl_priv *p = 780 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 781 int err, changed = 0, i; 782 783 for (i = 0; i < p->count; i++) { 784 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 785 changed = 1; 786 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 787 } 788 789 err = rt722_sdca_set_fu1e_capture_ctl(rt722); 790 if (err < 0) 791 return err; 792 793 return changed; 794 } 795 796 static int rt722_sdca_set_fu06_playback_ctl(struct rt722_sdca_priv *rt722) 797 { 798 int err; 799 unsigned int ch_l, ch_r; 800 801 ch_l = (rt722->fu06_dapm_mute || rt722->fu06_mixer_l_mute) ? 0x01 : 0x00; 802 ch_r = (rt722->fu06_dapm_mute || rt722->fu06_mixer_r_mute) ? 0x01 : 0x00; 803 804 err = regmap_write(rt722->regmap, 805 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 806 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 807 if (err < 0) 808 return err; 809 810 err = regmap_write(rt722->regmap, 811 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 812 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 813 if (err < 0) 814 return err; 815 816 return 0; 817 } 818 819 static int rt722_sdca_fu06_playback_get(struct snd_kcontrol *kcontrol, 820 struct snd_ctl_elem_value *ucontrol) 821 { 822 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 823 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 824 825 ucontrol->value.integer.value[0] = !rt722->fu06_mixer_l_mute; 826 ucontrol->value.integer.value[1] = !rt722->fu06_mixer_r_mute; 827 return 0; 828 } 829 830 static int rt722_sdca_fu06_playback_put(struct snd_kcontrol *kcontrol, 831 struct snd_ctl_elem_value *ucontrol) 832 { 833 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 834 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 835 int err, changed = 0; 836 837 if (rt722->fu06_mixer_l_mute != !ucontrol->value.integer.value[0] || 838 rt722->fu06_mixer_r_mute != !ucontrol->value.integer.value[1]) 839 changed = 1; 840 841 rt722->fu06_mixer_l_mute = !ucontrol->value.integer.value[0]; 842 rt722->fu06_mixer_r_mute = !ucontrol->value.integer.value[1]; 843 844 err = rt722_sdca_set_fu06_playback_ctl(rt722); 845 if (err < 0) 846 return err; 847 848 return changed; 849 } 850 851 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722) 852 { 853 int err; 854 unsigned int ch_l, ch_r; 855 856 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00; 857 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00; 858 859 err = regmap_write(rt722->regmap, 860 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 861 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 862 if (err < 0) 863 return err; 864 865 err = regmap_write(rt722->regmap, 866 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 867 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 868 if (err < 0) 869 return err; 870 871 return 0; 872 } 873 874 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 875 struct snd_ctl_elem_value *ucontrol) 876 { 877 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 878 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 879 880 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute; 881 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute; 882 return 0; 883 } 884 885 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 886 struct snd_ctl_elem_value *ucontrol) 887 { 888 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 889 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 890 int err, changed = 0; 891 892 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 893 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 894 changed = 1; 895 896 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 897 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 898 err = rt722_sdca_set_fu0f_capture_ctl(rt722); 899 if (err < 0) 900 return err; 901 902 return changed; 903 } 904 905 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol, 906 struct snd_ctl_elem_info *uinfo) 907 { 908 struct rt722_sdca_dmic_kctrl_priv *p = 909 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 910 911 if (p->max == 1) 912 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 913 else 914 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 915 uinfo->count = p->count; 916 uinfo->value.integer.min = 0; 917 uinfo->value.integer.max = p->max; 918 return 0; 919 } 920 921 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 922 struct snd_ctl_elem_value *ucontrol) 923 { 924 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 925 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 926 struct rt722_sdca_dmic_kctrl_priv *p = 927 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 928 unsigned int boost_step = 0x0a00; 929 unsigned int vol_max = 0x1e00; 930 unsigned int regvalue, ctl, i; 931 unsigned int adc_vol_flag = 0; 932 const unsigned int interval_offset = 0xc0; 933 934 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 935 adc_vol_flag = 1; 936 937 /* check all channels */ 938 for (i = 0; i < p->count; i++) { 939 regmap_read(rt722->regmap, p->reg_base + i, ®value); 940 941 if (!adc_vol_flag) /* boost gain */ 942 ctl = regvalue / boost_step; 943 else /* ADC gain */ 944 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 945 946 ucontrol->value.integer.value[i] = ctl; 947 } 948 949 return 0; 950 } 951 952 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 953 struct snd_ctl_elem_value *ucontrol) 954 { 955 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 956 struct rt722_sdca_dmic_kctrl_priv *p = 957 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 958 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 959 unsigned int boost_step = 0x0a00; 960 unsigned int vol_max = 0x1e00; 961 unsigned int gain_val[4]; 962 unsigned int i, adc_vol_flag = 0, changed = 0; 963 unsigned int regvalue[4]; 964 const unsigned int interval_offset = 0xc0; 965 int err; 966 967 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 968 adc_vol_flag = 1; 969 970 /* check all channels */ 971 for (i = 0; i < p->count; i++) { 972 regmap_read(rt722->regmap, p->reg_base + i, ®value[i]); 973 974 gain_val[i] = ucontrol->value.integer.value[i]; 975 if (gain_val[i] > p->max) 976 gain_val[i] = p->max; 977 978 if (!adc_vol_flag) /* boost gain */ 979 gain_val[i] = gain_val[i] * boost_step; 980 else { /* ADC gain */ 981 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 982 gain_val[i] &= 0xffff; 983 } 984 985 if (regvalue[i] != gain_val[i]) 986 changed = 1; 987 } 988 989 if (!changed) 990 return 0; 991 992 for (i = 0; i < p->count; i++) { 993 err = regmap_write(rt722->regmap, p->reg_base + i, gain_val[i]); 994 if (err < 0) 995 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n", 996 __func__, p->reg_base + i); 997 } 998 999 return changed; 1000 } 1001 1002 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \ 1003 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \ 1004 {.reg_base = xreg_base, .count = xcount, .max = xmax, \ 1005 .invert = xinvert}) 1006 1007 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ 1008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 1009 .info = rt722_sdca_fu_info, \ 1010 .get = rt722_sdca_fu1e_capture_get, \ 1011 .put = rt722_sdca_fu1e_capture_put, \ 1012 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)} 1013 1014 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ 1015 xhandler_put, xcount, xmax, tlv_array) \ 1016 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 1017 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 1018 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 1019 .tlv.p = (tlv_array), \ 1020 .info = rt722_sdca_fu_info, \ 1021 .get = xhandler_get, .put = xhandler_put, \ 1022 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) } 1023 1024 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1025 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 1026 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 1027 1028 static const struct snd_kcontrol_new rt722_sdca_controls[] = { 1029 /* Headphone playback settings */ 1030 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 1031 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1032 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1033 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1034 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 1035 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 1036 /* Headset mic capture settings */ 1037 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 1038 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put), 1039 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 1040 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 1041 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1042 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 1043 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 1044 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv), 1045 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 1046 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 1047 RT722_SDCA_CTL_FU_CH_GAIN, CH_L), 1048 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 1049 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0, 1050 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv), 1051 /* AMP playback settings */ 1052 SOC_DOUBLE_EXT("FU06 Playback Switch", SND_SOC_NOPM, 0, 1, 1, 0, 1053 rt722_sdca_fu06_playback_get, rt722_sdca_fu06_playback_put), 1054 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 1055 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 1056 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1057 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 1058 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 1059 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 1060 /* DMIC capture settings */ 1061 RT722_SDCA_FU_CTRL("FU1E Capture Switch", 1062 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 1063 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4), 1064 RT722_SDCA_EXT_TLV("FU1E Capture Volume", 1065 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 1066 RT722_SDCA_CTL_FU_VOLUME, CH_01), 1067 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 1068 4, 0x3f, mic_vol_tlv), 1069 RT722_SDCA_EXT_TLV("FU15 Boost Volume", 1070 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, 1071 RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 1072 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 1073 4, 3, boost_vol_tlv), 1074 /* CAE firmware update */ 1075 SOC_SINGLE_EXT("CAE Update", SND_SOC_NOPM, 0, 1, 0, 1076 rt722_cae_update_get, rt722_cae_update_put), 1077 }; 1078 1079 static const char * const adc22_mux_text[] = { 1080 "MIC2", 1081 "LINE1", 1082 "LINE2", 1083 }; 1084 1085 static const char * const adc07_10_mux_text[] = { 1086 "DMIC1", 1087 "DMIC2", 1088 }; 1089 1090 static SOC_ENUM_SINGLE_DECL(rt722_adc22_enum, 1091 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1092 12, adc22_mux_text); 1093 1094 static SOC_ENUM_SINGLE_DECL(rt722_adc24_enum, 1095 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1096 4, adc07_10_mux_text); 1097 1098 static SOC_ENUM_SINGLE_DECL(rt722_adc25_enum, 1099 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1100 0, adc07_10_mux_text); 1101 1102 static const struct snd_kcontrol_new rt722_sdca_adc22_mux = 1103 SOC_DAPM_ENUM("ADC 22 Mux", rt722_adc22_enum); 1104 1105 static const struct snd_kcontrol_new rt722_sdca_adc24_mux = 1106 SOC_DAPM_ENUM("ADC 24 Mux", rt722_adc24_enum); 1107 1108 static const struct snd_kcontrol_new rt722_sdca_adc25_mux = 1109 SOC_DAPM_ENUM("ADC 25 Mux", rt722_adc25_enum); 1110 1111 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w, 1112 struct snd_kcontrol *kcontrol, int event) 1113 { 1114 struct snd_soc_component *component = 1115 snd_soc_dapm_to_component(w->dapm); 1116 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1117 unsigned char unmute = 0x0, mute = 0x1; 1118 1119 switch (event) { 1120 case SND_SOC_DAPM_POST_PMU: 1121 regmap_write(rt722->regmap, 1122 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1123 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 1124 regmap_write(rt722->regmap, 1125 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1126 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 1127 break; 1128 case SND_SOC_DAPM_PRE_PMD: 1129 regmap_write(rt722->regmap, 1130 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1131 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 1132 regmap_write(rt722->regmap, 1133 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1134 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 1135 break; 1136 } 1137 return 0; 1138 } 1139 1140 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w, 1141 struct snd_kcontrol *kcontrol, int event) 1142 { 1143 struct snd_soc_component *component = 1144 snd_soc_dapm_to_component(w->dapm); 1145 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1146 1147 switch (event) { 1148 case SND_SOC_DAPM_POST_PMU: 1149 rt722->fu06_dapm_mute = false; 1150 break; 1151 case SND_SOC_DAPM_PRE_PMD: 1152 rt722->fu06_dapm_mute = true; 1153 break; 1154 } 1155 1156 return rt722_sdca_set_fu06_playback_ctl(rt722); 1157 } 1158 1159 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w, 1160 struct snd_kcontrol *kcontrol, int event) 1161 { 1162 struct snd_soc_component *component = 1163 snd_soc_dapm_to_component(w->dapm); 1164 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1165 1166 switch (event) { 1167 case SND_SOC_DAPM_POST_PMU: 1168 rt722->fu1e_dapm_mute = false; 1169 rt722_sdca_set_fu1e_capture_ctl(rt722); 1170 usleep_range(150000, 160000); 1171 break; 1172 case SND_SOC_DAPM_PRE_PMD: 1173 rt722->fu1e_dapm_mute = true; 1174 rt722_sdca_set_fu1e_capture_ctl(rt722); 1175 break; 1176 } 1177 return 0; 1178 } 1179 1180 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w, 1181 struct snd_kcontrol *kcontrol, int event) 1182 { 1183 struct snd_soc_component *component = 1184 snd_soc_dapm_to_component(w->dapm); 1185 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1186 1187 switch (event) { 1188 case SND_SOC_DAPM_POST_PMU: 1189 rt722->fu0f_dapm_mute = false; 1190 rt722_sdca_set_fu0f_capture_ctl(rt722); 1191 break; 1192 case SND_SOC_DAPM_PRE_PMD: 1193 rt722->fu0f_dapm_mute = true; 1194 rt722_sdca_set_fu0f_capture_ctl(rt722); 1195 break; 1196 } 1197 return 0; 1198 } 1199 1200 static void rt722_pde_transition_delay(struct rt722_sdca_priv *rt722, unsigned char func, 1201 unsigned char entity, unsigned char ps) 1202 { 1203 unsigned int delay = 1000, val; 1204 1205 pm_runtime_mark_last_busy(&rt722->slave->dev); 1206 1207 /* waiting for Actual PDE becomes to PS0/PS3 */ 1208 while (delay) { 1209 regmap_read(rt722->regmap, 1210 SDW_SDCA_CTL(func, entity, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 1211 if (val == ps) 1212 break; 1213 1214 usleep_range(1000, 1500); 1215 delay--; 1216 } 1217 if (!delay) { 1218 dev_warn(&rt722->slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 1219 } 1220 } 1221 1222 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 1223 struct snd_kcontrol *kcontrol, int event) 1224 { 1225 struct snd_soc_component *component = 1226 snd_soc_dapm_to_component(w->dapm); 1227 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1228 unsigned char ps0 = 0x0, ps3 = 0x3; 1229 1230 switch (event) { 1231 case SND_SOC_DAPM_POST_PMU: 1232 regmap_write(rt722->regmap, 1233 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 1234 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1235 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps0); 1236 break; 1237 case SND_SOC_DAPM_PRE_PMD: 1238 regmap_write(rt722->regmap, 1239 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 1240 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1241 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps3); 1242 break; 1243 } 1244 return 0; 1245 } 1246 1247 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w, 1248 struct snd_kcontrol *kcontrol, int event) 1249 { 1250 struct snd_soc_component *component = 1251 snd_soc_dapm_to_component(w->dapm); 1252 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1253 unsigned char ps0 = 0x0, ps3 = 0x3; 1254 1255 switch (event) { 1256 case SND_SOC_DAPM_POST_PMU: 1257 regmap_write(rt722->regmap, 1258 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 1259 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1260 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps0); 1261 break; 1262 case SND_SOC_DAPM_PRE_PMD: 1263 regmap_write(rt722->regmap, 1264 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 1265 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1266 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps3); 1267 break; 1268 } 1269 return 0; 1270 } 1271 1272 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w, 1273 struct snd_kcontrol *kcontrol, int event) 1274 { 1275 struct snd_soc_component *component = 1276 snd_soc_dapm_to_component(w->dapm); 1277 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1278 unsigned char ps0 = 0x0, ps3 = 0x3; 1279 1280 switch (event) { 1281 case SND_SOC_DAPM_POST_PMU: 1282 regmap_write(rt722->regmap, 1283 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1284 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1285 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps0); 1286 break; 1287 case SND_SOC_DAPM_PRE_PMD: 1288 regmap_write(rt722->regmap, 1289 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1290 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1291 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps3); 1292 break; 1293 } 1294 return 0; 1295 } 1296 1297 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w, 1298 struct snd_kcontrol *kcontrol, int event) 1299 { 1300 struct snd_soc_component *component = 1301 snd_soc_dapm_to_component(w->dapm); 1302 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1303 unsigned char ps0 = 0x0, ps3 = 0x3; 1304 1305 switch (event) { 1306 case SND_SOC_DAPM_POST_PMU: 1307 regmap_write(rt722->regmap, 1308 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1309 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1310 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps0); 1311 break; 1312 case SND_SOC_DAPM_PRE_PMD: 1313 regmap_write(rt722->regmap, 1314 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1315 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1316 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps3); 1317 break; 1318 } 1319 return 0; 1320 } 1321 1322 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = { 1323 SND_SOC_DAPM_OUTPUT("HP"), 1324 SND_SOC_DAPM_OUTPUT("SPK"), 1325 SND_SOC_DAPM_INPUT("MIC2"), 1326 SND_SOC_DAPM_INPUT("LINE1"), 1327 SND_SOC_DAPM_INPUT("LINE2"), 1328 SND_SOC_DAPM_INPUT("DMIC1_2"), 1329 SND_SOC_DAPM_INPUT("DMIC3_4"), 1330 1331 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1332 rt722_sdca_pde23_event, 1333 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1334 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 1335 rt722_sdca_pde47_event, 1336 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1337 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1338 rt722_sdca_pde11_event, 1339 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1340 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0, 1341 rt722_sdca_pde12_event, 1342 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1343 1344 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 1345 rt722_sdca_fu21_event, 1346 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1347 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 1348 rt722_sdca_fu42_event, 1349 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1350 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 1351 rt722_sdca_fu36_event, 1352 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1353 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 1354 rt722_sdca_fu113_event, 1355 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1356 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 1357 &rt722_sdca_adc22_mux), 1358 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 1359 &rt722_sdca_adc24_mux), 1360 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 1361 &rt722_sdca_adc25_mux), 1362 1363 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1364 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1365 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1366 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1367 }; 1368 1369 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = { 1370 {"FU 42", NULL, "DP1RX"}, 1371 {"FU 21", NULL, "DP3RX"}, 1372 1373 {"ADC 22 Mux", "MIC2", "MIC2"}, 1374 {"ADC 22 Mux", "LINE1", "LINE1"}, 1375 {"ADC 22 Mux", "LINE2", "LINE2"}, 1376 {"ADC 24 Mux", "DMIC1", "DMIC1_2"}, 1377 {"ADC 24 Mux", "DMIC2", "DMIC3_4"}, 1378 {"ADC 25 Mux", "DMIC1", "DMIC1_2"}, 1379 {"ADC 25 Mux", "DMIC2", "DMIC3_4"}, 1380 {"FU 36", NULL, "PDE 12"}, 1381 {"FU 36", NULL, "ADC 22 Mux"}, 1382 {"FU 113", NULL, "PDE 11"}, 1383 {"FU 113", NULL, "ADC 24 Mux"}, 1384 {"FU 113", NULL, "ADC 25 Mux"}, 1385 {"DP2TX", NULL, "FU 36"}, 1386 {"DP6TX", NULL, "FU 113"}, 1387 1388 {"HP", NULL, "PDE 47"}, 1389 {"HP", NULL, "FU 42"}, 1390 {"SPK", NULL, "PDE 23"}, 1391 {"SPK", NULL, "FU 21"}, 1392 }; 1393 1394 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev) 1395 { 1396 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src); 1397 1398 return 0; 1399 } 1400 1401 static int rt722_sdca_probe(struct snd_soc_component *component) 1402 { 1403 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1404 int ret; 1405 1406 rt722_sdca_parse_dt(rt722, &rt722->slave->dev); 1407 rt722->component = component; 1408 1409 ret = pm_runtime_resume(component->dev); 1410 if (ret < 0 && ret != -EACCES) 1411 return ret; 1412 1413 return 0; 1414 } 1415 1416 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = { 1417 .probe = rt722_sdca_probe, 1418 .controls = rt722_sdca_controls, 1419 .num_controls = ARRAY_SIZE(rt722_sdca_controls), 1420 .dapm_widgets = rt722_sdca_dapm_widgets, 1421 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets), 1422 .dapm_routes = rt722_sdca_audio_map, 1423 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map), 1424 .set_jack = rt722_sdca_set_jack_detect, 1425 .endianness = 1, 1426 }; 1427 1428 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1429 int direction) 1430 { 1431 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1432 1433 return 0; 1434 } 1435 1436 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream, 1437 struct snd_soc_dai *dai) 1438 { 1439 snd_soc_dai_set_dma_data(dai, substream, NULL); 1440 } 1441 1442 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1443 struct snd_pcm_hw_params *params, 1444 struct snd_soc_dai *dai) 1445 { 1446 struct snd_soc_component *component = dai->component; 1447 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1448 struct sdw_stream_config stream_config; 1449 struct sdw_port_config port_config; 1450 enum sdw_data_direction direction; 1451 struct sdw_stream_runtime *sdw_stream; 1452 int retval, port, num_channels; 1453 unsigned int sampling_rate; 1454 1455 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1456 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1457 1458 if (!sdw_stream) 1459 return -EINVAL; 1460 1461 if (!rt722->slave) 1462 return -EINVAL; 1463 1464 /* 1465 * RT722_AIF1 with port = 1 for headphone playback 1466 * RT722_AIF1 with port = 2 for headset-mic capture 1467 * RT722_AIF2 with port = 3 for speaker playback 1468 * RT722_AIF3 with port = 6 for digital-mic capture 1469 */ 1470 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1471 direction = SDW_DATA_DIR_RX; 1472 if (dai->id == RT722_AIF1) 1473 port = 1; 1474 else if (dai->id == RT722_AIF2) 1475 port = 3; 1476 else 1477 return -EINVAL; 1478 } else { 1479 direction = SDW_DATA_DIR_TX; 1480 if (dai->id == RT722_AIF1) 1481 port = 2; 1482 else if (dai->id == RT722_AIF3) 1483 port = 6; 1484 else 1485 return -EINVAL; 1486 } 1487 stream_config.frame_rate = params_rate(params); 1488 stream_config.ch_count = params_channels(params); 1489 stream_config.bps = snd_pcm_format_width(params_format(params)); 1490 stream_config.direction = direction; 1491 1492 num_channels = params_channels(params); 1493 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1494 port_config.num = port; 1495 1496 retval = sdw_stream_add_slave(rt722->slave, &stream_config, 1497 &port_config, 1, sdw_stream); 1498 if (retval) { 1499 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1500 return retval; 1501 } 1502 1503 if (params_channels(params) > 16) { 1504 dev_err(component->dev, "%s: Unsupported channels %d\n", 1505 __func__, params_channels(params)); 1506 return -EINVAL; 1507 } 1508 1509 /* sampling rate configuration */ 1510 switch (params_rate(params)) { 1511 case 44100: 1512 sampling_rate = RT722_SDCA_RATE_44100HZ; 1513 break; 1514 case 48000: 1515 sampling_rate = RT722_SDCA_RATE_48000HZ; 1516 break; 1517 case 96000: 1518 sampling_rate = RT722_SDCA_RATE_96000HZ; 1519 break; 1520 case 192000: 1521 sampling_rate = RT722_SDCA_RATE_192000HZ; 1522 break; 1523 default: 1524 dev_err(component->dev, "%s: Rate %d is not supported\n", 1525 __func__, params_rate(params)); 1526 return -EINVAL; 1527 } 1528 1529 /* set sampling frequency */ 1530 if (dai->id == RT722_AIF1) { 1531 regmap_write(rt722->regmap, 1532 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 1533 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1534 regmap_write(rt722->regmap, 1535 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 1536 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1537 } 1538 1539 if (dai->id == RT722_AIF2) 1540 regmap_write(rt722->regmap, 1541 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 1542 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1543 1544 if (dai->id == RT722_AIF3) 1545 regmap_write(rt722->regmap, 1546 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 1547 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1548 1549 return 0; 1550 } 1551 1552 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1553 struct snd_soc_dai *dai) 1554 { 1555 struct snd_soc_component *component = dai->component; 1556 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1557 struct sdw_stream_runtime *sdw_stream = 1558 snd_soc_dai_get_dma_data(dai, substream); 1559 1560 if (!rt722->slave) 1561 return -EINVAL; 1562 1563 sdw_stream_remove_slave(rt722->slave, sdw_stream); 1564 return 0; 1565 } 1566 1567 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1568 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1569 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1570 SNDRV_PCM_FMTBIT_S24_LE) 1571 1572 static const struct snd_soc_dai_ops rt722_sdca_ops = { 1573 .hw_params = rt722_sdca_pcm_hw_params, 1574 .hw_free = rt722_sdca_pcm_hw_free, 1575 .set_stream = rt722_sdca_set_sdw_stream, 1576 .shutdown = rt722_sdca_shutdown, 1577 }; 1578 1579 static struct snd_soc_dai_driver rt722_sdca_dai[] = { 1580 { 1581 .name = "rt722-sdca-aif1", 1582 .id = RT722_AIF1, 1583 .playback = { 1584 .stream_name = "DP1 Headphone Playback", 1585 .channels_min = 1, 1586 .channels_max = 2, 1587 .rates = RT722_STEREO_RATES, 1588 .formats = RT722_FORMATS, 1589 }, 1590 .capture = { 1591 .stream_name = "DP2 Headset Capture", 1592 .channels_min = 1, 1593 .channels_max = 2, 1594 .rates = RT722_STEREO_RATES, 1595 .formats = RT722_FORMATS, 1596 }, 1597 .ops = &rt722_sdca_ops, 1598 }, 1599 { 1600 .name = "rt722-sdca-aif2", 1601 .id = RT722_AIF2, 1602 .playback = { 1603 .stream_name = "DP3 Speaker Playback", 1604 .channels_min = 1, 1605 .channels_max = 2, 1606 .rates = RT722_STEREO_RATES, 1607 .formats = RT722_FORMATS, 1608 }, 1609 .ops = &rt722_sdca_ops, 1610 }, 1611 { 1612 .name = "rt722-sdca-aif3", 1613 .id = RT722_AIF3, 1614 .capture = { 1615 .stream_name = "DP6 DMic Capture", 1616 .channels_min = 1, 1617 .channels_max = 4, 1618 .rates = RT722_STEREO_RATES, 1619 .formats = RT722_FORMATS, 1620 }, 1621 .ops = &rt722_sdca_ops, 1622 } 1623 }; 1624 1625 int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct sdw_slave *slave) 1626 { 1627 struct rt722_sdca_priv *rt722; 1628 1629 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL); 1630 if (!rt722) 1631 return -ENOMEM; 1632 1633 dev_set_drvdata(dev, rt722); 1634 rt722->slave = slave; 1635 rt722->regmap = regmap; 1636 1637 regcache_cache_only(rt722->regmap, true); 1638 1639 mutex_init(&rt722->calibrate_mutex); 1640 mutex_init(&rt722->disable_irq_lock); 1641 1642 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler); 1643 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler); 1644 1645 /* 1646 * Mark hw_init to false 1647 * HW init will be performed when device reports present 1648 */ 1649 rt722->hw_init = false; 1650 rt722->first_hw_init = false; 1651 rt722->fu1e_dapm_mute = true; 1652 rt722->fu0f_dapm_mute = true; 1653 rt722->fu06_dapm_mute = true; 1654 rt722->fu06_mixer_l_mute = rt722->fu06_mixer_r_mute = false; 1655 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true; 1656 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] = 1657 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true; 1658 rt722->cae_update_done = 0; 1659 1660 return devm_snd_soc_register_component(dev, 1661 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai)); 1662 } 1663 1664 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1665 { 1666 unsigned int mic_func_status; 1667 struct device *dev = &rt722->slave->dev; 1668 1669 regmap_read(rt722->regmap, 1670 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &mic_func_status); 1671 dev_dbg(dev, "%s mic func_status=0x%x\n", __func__, mic_func_status); 1672 1673 if ((mic_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1674 /* Set AD07 power entity floating control */ 1675 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1676 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1677 /* Set AD10 power entity floating control */ 1678 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1679 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1680 /* Set DMIC1/DMIC2 power entity floating control */ 1681 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1682 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1683 /* Set DMIC2 IT entity floating control */ 1684 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1685 RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1686 /* Set AD10 FU entity floating control */ 1687 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1688 RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1689 /* Set DMIC2 FU entity floating control */ 1690 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1691 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1692 /* Set AD10 FU channel floating control */ 1693 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1694 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1695 /* Set DMIC2 FU channel floating control */ 1696 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1697 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1698 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1699 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1700 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1701 /* Enable vf707_r12_05/vf707_r13_05 */ 1702 regmap_write(rt722->regmap, 1703 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1704 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1705 /* Fine tune PDE2A latency */ 1706 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1707 /* PHYtiming TDZ/TZD control */ 1708 regmap_write(rt722->regmap, 0x2f03, 0x06); 1709 1710 if (rt722->hw_vid == RT722_VB) 1711 regmap_write(rt722->regmap, 0x2f52, 0x00); 1712 1713 /* clear flag */ 1714 regmap_write(rt722->regmap, 1715 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1716 FUNCTION_NEEDS_INITIALIZATION); 1717 } 1718 } 1719 1720 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1721 { 1722 unsigned int amp_func_status; 1723 struct device *dev = &rt722->slave->dev; 1724 1725 regmap_read(rt722->regmap, 1726 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 1727 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 1728 1729 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1730 /* Set DVQ=01 */ 1731 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1732 0xc215); 1733 /* Reset dc_cal_top */ 1734 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1735 0x702c); 1736 /* W1C Trigger Calibration */ 1737 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1738 0xf02d); 1739 /* Set DAC02/ClassD power entity floating control */ 1740 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1741 0x2323); 1742 /* Set EAPD high */ 1743 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1744 0x0002); 1745 /* Enable vf707_r14 */ 1746 regmap_write(rt722->regmap, 1747 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1748 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1749 1750 if (rt722->hw_vid == RT722_VB) 1751 regmap_write(rt722->regmap, 0x2f54, 0x00); 1752 1753 /* clear flag */ 1754 regmap_write(rt722->regmap, 1755 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1756 FUNCTION_NEEDS_INITIALIZATION); 1757 } 1758 } 1759 1760 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1761 { 1762 int loop_check, chk_cnt = 100, ret; 1763 unsigned int calib_status = 0; 1764 unsigned int jack_func_status; 1765 struct device *dev = &rt722->slave->dev; 1766 1767 regmap_read(rt722->regmap, 1768 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &jack_func_status); 1769 dev_dbg(dev, "%s jack func_status=0x%x\n", __func__, jack_func_status); 1770 1771 if ((jack_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1772 /* Config analog bias */ 1773 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1774 0xa081); 1775 /* GE related settings */ 1776 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1777 0xa009); 1778 /* Button A, B, C, D bypass mode */ 1779 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1780 0xcf00); 1781 /* HID1 slot enable */ 1782 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1783 0x000f); 1784 /* Report ID for HID1 */ 1785 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1786 0x1100); 1787 /* OSC/OOC for slot 2, 3 */ 1788 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1789 0x0c12); 1790 /* Set JD de-bounce clock control */ 1791 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1792 0x7002); 1793 /* Set DVQ=01 */ 1794 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1795 0xc215); 1796 /* FSM switch to calibration manual mode */ 1797 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1798 0x4100); 1799 /* W1C Trigger DC calibration (HP) */ 1800 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1801 0x008d); 1802 /* check HP calibration FSM status */ 1803 for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1804 usleep_range(10000, 11000); 1805 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1806 RT722_DAC_DC_CALI_CTL3, &calib_status); 1807 if (ret < 0) 1808 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1809 if ((calib_status & 0x0040) == 0x0) 1810 break; 1811 } 1812 1813 if (loop_check == chk_cnt) 1814 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__); 1815 1816 /* Set ADC09 power entity floating control */ 1817 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1818 0x2a12); 1819 /* Set MIC2 and LINE1 power entity floating control */ 1820 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1821 0x3429); 1822 /* Set ET41h and LINE2 power entity floating control */ 1823 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1824 0x4112); 1825 /* Set DAC03 and HP power entity floating control */ 1826 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1827 0x4040); 1828 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1829 0x4141); 1830 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1831 0x0101); 1832 /* Fine tune PDE40 latency */ 1833 regmap_write(rt722->regmap, 0x2f58, 0x07); 1834 regmap_write(rt722->regmap, 0x2f03, 0x06); 1835 /* MIC VRefo */ 1836 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1837 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1838 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1839 RT722_VREFO_GAT, 0x4000, 0x4000); 1840 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1841 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1842 0x0010); 1843 1844 if (rt722->hw_vid == RT722_VB) 1845 regmap_write(rt722->regmap, 0x2f51, 0x00); 1846 1847 /* clear flag */ 1848 regmap_write(rt722->regmap, 1849 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1850 FUNCTION_NEEDS_INITIALIZATION); 1851 } 1852 } 1853 1854 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1855 { 1856 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 1857 unsigned int val; 1858 1859 rt722->disable_irq = false; 1860 1861 if (rt722->hw_init) 1862 return 0; 1863 1864 regcache_cache_only(rt722->regmap, false); 1865 if (rt722->first_hw_init) { 1866 regcache_cache_bypass(rt722->regmap, true); 1867 } else { 1868 /* 1869 * PM runtime is only enabled when a Slave reports as Attached 1870 */ 1871 1872 /* set autosuspend parameters */ 1873 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1874 pm_runtime_use_autosuspend(&slave->dev); 1875 1876 /* update count of parent 'active' children */ 1877 pm_runtime_set_active(&slave->dev); 1878 1879 /* make sure the device does not suspend immediately */ 1880 pm_runtime_mark_last_busy(&slave->dev); 1881 1882 pm_runtime_enable(&slave->dev); 1883 } 1884 1885 pm_runtime_get_noresume(&slave->dev); 1886 1887 rt722_sdca_index_read(rt722, RT722_VENDOR_REG, RT722_JD_PRODUCT_NUM, &val); 1888 rt722->hw_vid = (val & 0x0f00) >> 8; 1889 dev_dbg(&slave->dev, "%s hw_vid=0x%x\n", __func__, rt722->hw_vid); 1890 1891 rt722_sdca_dmic_preset(rt722); 1892 rt722_sdca_amp_preset(rt722); 1893 rt722_sdca_jack_preset(rt722); 1894 1895 if (rt722->first_hw_init) { 1896 regcache_cache_bypass(rt722->regmap, false); 1897 regcache_mark_dirty(rt722->regmap); 1898 } else 1899 rt722->first_hw_init = true; 1900 1901 /* Mark Slave initialization complete */ 1902 rt722->hw_init = true; 1903 1904 pm_runtime_put_autosuspend(&slave->dev); 1905 1906 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1907 return 0; 1908 } 1909 1910 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 1911 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1912 MODULE_LICENSE("GPL"); 1913