1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5645.c -- RT5645 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/acpi.h> 19 #include <linux/dmi.h> 20 #include <linux/regulator/consumer.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt5645.h" 32 33 #define QUIRK_INV_JD1_1(q) ((q) & 1) 34 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) 35 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) 36 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) 37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7) 38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) 39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) 40 41 static unsigned int quirk = -1; 42 module_param(quirk, uint, 0444); 43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override"); 44 45 static const struct acpi_gpio_mapping *cht_rt5645_gpios; 46 47 #define RT5645_DEVICE_ID 0x6308 48 #define RT5650_DEVICE_ID 0x6419 49 50 #define RT5645_PR_RANGE_BASE (0xff + 1) 51 #define RT5645_PR_SPACING 0x100 52 53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 54 55 #define RT5645_HWEQ_NUM 57 56 57 #define TIME_TO_POWER_MS 400 58 59 static const struct regmap_range_cfg rt5645_ranges[] = { 60 { 61 .name = "PR", 62 .range_min = RT5645_PR_BASE, 63 .range_max = RT5645_PR_BASE + 0xf8, 64 .selector_reg = RT5645_PRIV_INDEX, 65 .selector_mask = 0xff, 66 .selector_shift = 0x0, 67 .window_start = RT5645_PRIV_DATA, 68 .window_len = 0x1, 69 }, 70 }; 71 72 static const struct reg_sequence init_list[] = { 73 {RT5645_PR_BASE + 0x3d, 0x3600}, 74 {RT5645_PR_BASE + 0x1c, 0xfd70}, 75 {RT5645_PR_BASE + 0x20, 0x611f}, 76 {RT5645_PR_BASE + 0x21, 0x4040}, 77 {RT5645_PR_BASE + 0x23, 0x0004}, 78 {RT5645_ASRC_4, 0x0120}, 79 }; 80 81 static const struct reg_sequence rt5650_init_list[] = { 82 {0xf6, 0x0100}, 83 {RT5645_PWR_ANLG1, 0x02}, 84 {RT5645_IL_CMD3, 0x6728}, 85 {RT5645_PR_BASE + 0x3a, 0x0000}, 86 {RT5645_CLSD_OUT_CTRL1, 0x4059}, 87 {RT5645_GEN_CTRL3, 0x0200}, 88 }; 89 90 static const struct reg_default rt5645_reg[] = { 91 { 0x00, 0x0000 }, 92 { 0x01, 0xc8c8 }, 93 { 0x02, 0xc8c8 }, 94 { 0x03, 0xc8c8 }, 95 { 0x0a, 0x0002 }, 96 { 0x0b, 0x2827 }, 97 { 0x0c, 0xe000 }, 98 { 0x0d, 0x0000 }, 99 { 0x0e, 0x0000 }, 100 { 0x0f, 0x0808 }, 101 { 0x14, 0x3333 }, 102 { 0x16, 0x4b00 }, 103 { 0x18, 0x018b }, 104 { 0x19, 0xafaf }, 105 { 0x1a, 0xafaf }, 106 { 0x1b, 0x0001 }, 107 { 0x1c, 0x2f2f }, 108 { 0x1d, 0x2f2f }, 109 { 0x1e, 0x0000 }, 110 { 0x20, 0x0000 }, 111 { 0x27, 0x7060 }, 112 { 0x28, 0x7070 }, 113 { 0x29, 0x8080 }, 114 { 0x2a, 0x5656 }, 115 { 0x2b, 0x5454 }, 116 { 0x2c, 0xaaa0 }, 117 { 0x2d, 0x0000 }, 118 { 0x2f, 0x1002 }, 119 { 0x31, 0x5000 }, 120 { 0x32, 0x0000 }, 121 { 0x33, 0x0000 }, 122 { 0x34, 0x0000 }, 123 { 0x35, 0x0000 }, 124 { 0x3b, 0x0000 }, 125 { 0x3c, 0x007f }, 126 { 0x3d, 0x0000 }, 127 { 0x3e, 0x007f }, 128 { 0x3f, 0x0000 }, 129 { 0x40, 0x001f }, 130 { 0x41, 0x0000 }, 131 { 0x42, 0x001f }, 132 { 0x45, 0x6000 }, 133 { 0x46, 0x003e }, 134 { 0x47, 0x003e }, 135 { 0x48, 0xf807 }, 136 { 0x4a, 0x0004 }, 137 { 0x4d, 0x0000 }, 138 { 0x4e, 0x0000 }, 139 { 0x4f, 0x01ff }, 140 { 0x50, 0x0000 }, 141 { 0x51, 0x0000 }, 142 { 0x52, 0x01ff }, 143 { 0x53, 0xf000 }, 144 { 0x56, 0x0111 }, 145 { 0x57, 0x0064 }, 146 { 0x58, 0xef0e }, 147 { 0x59, 0xf0f0 }, 148 { 0x5a, 0xef0e }, 149 { 0x5b, 0xf0f0 }, 150 { 0x5c, 0xef0e }, 151 { 0x5d, 0xf0f0 }, 152 { 0x5e, 0xf000 }, 153 { 0x5f, 0x0000 }, 154 { 0x61, 0x0300 }, 155 { 0x62, 0x0000 }, 156 { 0x63, 0x00c2 }, 157 { 0x64, 0x0000 }, 158 { 0x65, 0x0000 }, 159 { 0x66, 0x0000 }, 160 { 0x6a, 0x0000 }, 161 { 0x6c, 0x0aaa }, 162 { 0x70, 0x8000 }, 163 { 0x71, 0x8000 }, 164 { 0x72, 0x8000 }, 165 { 0x73, 0x7770 }, 166 { 0x74, 0x3e00 }, 167 { 0x75, 0x2409 }, 168 { 0x76, 0x000a }, 169 { 0x77, 0x0c00 }, 170 { 0x78, 0x0000 }, 171 { 0x79, 0x0123 }, 172 { 0x80, 0x0000 }, 173 { 0x81, 0x0000 }, 174 { 0x82, 0x0000 }, 175 { 0x83, 0x0000 }, 176 { 0x84, 0x0000 }, 177 { 0x85, 0x0000 }, 178 { 0x8a, 0x0120 }, 179 { 0x8e, 0x0004 }, 180 { 0x8f, 0x1100 }, 181 { 0x90, 0x0646 }, 182 { 0x91, 0x0c06 }, 183 { 0x93, 0x0000 }, 184 { 0x94, 0x0200 }, 185 { 0x95, 0x0000 }, 186 { 0x9a, 0x2184 }, 187 { 0x9b, 0x010a }, 188 { 0x9c, 0x0aea }, 189 { 0x9d, 0x000c }, 190 { 0x9e, 0x0400 }, 191 { 0xa0, 0xa0a8 }, 192 { 0xa1, 0x0059 }, 193 { 0xa2, 0x0001 }, 194 { 0xae, 0x6000 }, 195 { 0xaf, 0x0000 }, 196 { 0xb0, 0x6000 }, 197 { 0xb1, 0x0000 }, 198 { 0xb2, 0x0000 }, 199 { 0xb3, 0x001f }, 200 { 0xb4, 0x020c }, 201 { 0xb5, 0x1f00 }, 202 { 0xb6, 0x0000 }, 203 { 0xbb, 0x0000 }, 204 { 0xbc, 0x0000 }, 205 { 0xbd, 0x0000 }, 206 { 0xbe, 0x0000 }, 207 { 0xbf, 0x3100 }, 208 { 0xc0, 0x0000 }, 209 { 0xc1, 0x0000 }, 210 { 0xc2, 0x0000 }, 211 { 0xc3, 0x2000 }, 212 { 0xcd, 0x0000 }, 213 { 0xce, 0x0000 }, 214 { 0xcf, 0x1813 }, 215 { 0xd0, 0x0690 }, 216 { 0xd1, 0x1c17 }, 217 { 0xd3, 0xb320 }, 218 { 0xd4, 0x0000 }, 219 { 0xd6, 0x0400 }, 220 { 0xd9, 0x0809 }, 221 { 0xda, 0x0000 }, 222 { 0xdb, 0x0003 }, 223 { 0xdc, 0x0049 }, 224 { 0xdd, 0x001b }, 225 { 0xdf, 0x0008 }, 226 { 0xe0, 0x4000 }, 227 { 0xe6, 0x8000 }, 228 { 0xe7, 0x0200 }, 229 { 0xec, 0xb300 }, 230 { 0xed, 0x0000 }, 231 { 0xf0, 0x001f }, 232 { 0xf1, 0x020c }, 233 { 0xf2, 0x1f00 }, 234 { 0xf3, 0x0000 }, 235 { 0xf4, 0x4000 }, 236 { 0xf8, 0x0000 }, 237 { 0xf9, 0x0000 }, 238 { 0xfa, 0x2060 }, 239 { 0xfb, 0x4040 }, 240 { 0xfc, 0x0000 }, 241 { 0xfd, 0x0002 }, 242 { 0xfe, 0x10ec }, 243 { 0xff, 0x6308 }, 244 }; 245 246 static const struct reg_default rt5650_reg[] = { 247 { 0x00, 0x0000 }, 248 { 0x01, 0xc8c8 }, 249 { 0x02, 0xc8c8 }, 250 { 0x03, 0xc8c8 }, 251 { 0x0a, 0x0002 }, 252 { 0x0b, 0x2827 }, 253 { 0x0c, 0xe000 }, 254 { 0x0d, 0x0000 }, 255 { 0x0e, 0x0000 }, 256 { 0x0f, 0x0808 }, 257 { 0x14, 0x3333 }, 258 { 0x16, 0x4b00 }, 259 { 0x18, 0x018b }, 260 { 0x19, 0xafaf }, 261 { 0x1a, 0xafaf }, 262 { 0x1b, 0x0001 }, 263 { 0x1c, 0x2f2f }, 264 { 0x1d, 0x2f2f }, 265 { 0x1e, 0x0000 }, 266 { 0x20, 0x0000 }, 267 { 0x27, 0x7060 }, 268 { 0x28, 0x7070 }, 269 { 0x29, 0x8080 }, 270 { 0x2a, 0x5656 }, 271 { 0x2b, 0x5454 }, 272 { 0x2c, 0xaaa0 }, 273 { 0x2d, 0x0000 }, 274 { 0x2f, 0x5002 }, 275 { 0x31, 0x5000 }, 276 { 0x32, 0x0000 }, 277 { 0x33, 0x0000 }, 278 { 0x34, 0x0000 }, 279 { 0x35, 0x0000 }, 280 { 0x3b, 0x0000 }, 281 { 0x3c, 0x007f }, 282 { 0x3d, 0x0000 }, 283 { 0x3e, 0x007f }, 284 { 0x3f, 0x0000 }, 285 { 0x40, 0x001f }, 286 { 0x41, 0x0000 }, 287 { 0x42, 0x001f }, 288 { 0x45, 0x6000 }, 289 { 0x46, 0x003e }, 290 { 0x47, 0x003e }, 291 { 0x48, 0xf807 }, 292 { 0x4a, 0x0004 }, 293 { 0x4d, 0x0000 }, 294 { 0x4e, 0x0000 }, 295 { 0x4f, 0x01ff }, 296 { 0x50, 0x0000 }, 297 { 0x51, 0x0000 }, 298 { 0x52, 0x01ff }, 299 { 0x53, 0xf000 }, 300 { 0x56, 0x0111 }, 301 { 0x57, 0x0064 }, 302 { 0x58, 0xef0e }, 303 { 0x59, 0xf0f0 }, 304 { 0x5a, 0xef0e }, 305 { 0x5b, 0xf0f0 }, 306 { 0x5c, 0xef0e }, 307 { 0x5d, 0xf0f0 }, 308 { 0x5e, 0xf000 }, 309 { 0x5f, 0x0000 }, 310 { 0x61, 0x0300 }, 311 { 0x62, 0x0000 }, 312 { 0x63, 0x00c2 }, 313 { 0x64, 0x0000 }, 314 { 0x65, 0x0000 }, 315 { 0x66, 0x0000 }, 316 { 0x6a, 0x0000 }, 317 { 0x6c, 0x0aaa }, 318 { 0x70, 0x8000 }, 319 { 0x71, 0x8000 }, 320 { 0x72, 0x8000 }, 321 { 0x73, 0x7770 }, 322 { 0x74, 0x3e00 }, 323 { 0x75, 0x2409 }, 324 { 0x76, 0x000a }, 325 { 0x77, 0x0c00 }, 326 { 0x78, 0x0000 }, 327 { 0x79, 0x0123 }, 328 { 0x7a, 0x0123 }, 329 { 0x80, 0x0000 }, 330 { 0x81, 0x0000 }, 331 { 0x82, 0x0000 }, 332 { 0x83, 0x0000 }, 333 { 0x84, 0x0000 }, 334 { 0x85, 0x0000 }, 335 { 0x8a, 0x0120 }, 336 { 0x8e, 0x0004 }, 337 { 0x8f, 0x1100 }, 338 { 0x90, 0x0646 }, 339 { 0x91, 0x0c06 }, 340 { 0x93, 0x0000 }, 341 { 0x94, 0x0200 }, 342 { 0x95, 0x0000 }, 343 { 0x9a, 0x2184 }, 344 { 0x9b, 0x010a }, 345 { 0x9c, 0x0aea }, 346 { 0x9d, 0x000c }, 347 { 0x9e, 0x0400 }, 348 { 0xa0, 0xa0a8 }, 349 { 0xa1, 0x0059 }, 350 { 0xa2, 0x0001 }, 351 { 0xae, 0x6000 }, 352 { 0xaf, 0x0000 }, 353 { 0xb0, 0x6000 }, 354 { 0xb1, 0x0000 }, 355 { 0xb2, 0x0000 }, 356 { 0xb3, 0x001f }, 357 { 0xb4, 0x020c }, 358 { 0xb5, 0x1f00 }, 359 { 0xb6, 0x0000 }, 360 { 0xbb, 0x0000 }, 361 { 0xbc, 0x0000 }, 362 { 0xbd, 0x0000 }, 363 { 0xbe, 0x0000 }, 364 { 0xbf, 0x3100 }, 365 { 0xc0, 0x0000 }, 366 { 0xc1, 0x0000 }, 367 { 0xc2, 0x0000 }, 368 { 0xc3, 0x2000 }, 369 { 0xcd, 0x0000 }, 370 { 0xce, 0x0000 }, 371 { 0xcf, 0x1813 }, 372 { 0xd0, 0x0690 }, 373 { 0xd1, 0x1c17 }, 374 { 0xd3, 0xb320 }, 375 { 0xd4, 0x0000 }, 376 { 0xd6, 0x0400 }, 377 { 0xd9, 0x0809 }, 378 { 0xda, 0x0000 }, 379 { 0xdb, 0x0003 }, 380 { 0xdc, 0x0049 }, 381 { 0xdd, 0x001b }, 382 { 0xdf, 0x0008 }, 383 { 0xe0, 0x4000 }, 384 { 0xe6, 0x8000 }, 385 { 0xe7, 0x0200 }, 386 { 0xec, 0xb300 }, 387 { 0xed, 0x0000 }, 388 { 0xf0, 0x001f }, 389 { 0xf1, 0x020c }, 390 { 0xf2, 0x1f00 }, 391 { 0xf3, 0x0000 }, 392 { 0xf4, 0x4000 }, 393 { 0xf8, 0x0000 }, 394 { 0xf9, 0x0000 }, 395 { 0xfa, 0x2060 }, 396 { 0xfb, 0x4040 }, 397 { 0xfc, 0x0000 }, 398 { 0xfd, 0x0002 }, 399 { 0xfe, 0x10ec }, 400 { 0xff, 0x6308 }, 401 }; 402 403 struct rt5645_eq_param_s { 404 unsigned short reg; 405 unsigned short val; 406 }; 407 408 struct rt5645_eq_param_s_be16 { 409 __be16 reg; 410 __be16 val; 411 }; 412 413 static const char *const rt5645_supply_names[] = { 414 "avdd", 415 "cpvdd", 416 }; 417 418 struct rt5645_platform_data { 419 /* IN2 can optionally be differential */ 420 bool in2_diff; 421 422 unsigned int dmic1_data_pin; 423 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ 424 unsigned int dmic2_data_pin; 425 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */ 426 427 unsigned int jd_mode; 428 /* Use level triggered irq */ 429 bool level_trigger_irq; 430 /* Invert JD1_1 status polarity */ 431 bool inv_jd1_1; 432 /* Invert HP detect status polarity */ 433 bool inv_hp_pol; 434 435 /* Only 1 speaker connected */ 436 bool mono_speaker; 437 438 /* Value to assign to snd_soc_card.long_name */ 439 const char *long_name; 440 441 /* Some (package) variants have the headset-mic pin not-connected */ 442 bool no_headset_mic; 443 }; 444 445 struct rt5645_priv { 446 struct snd_soc_component *component; 447 struct rt5645_platform_data pdata; 448 struct regmap *regmap; 449 struct i2c_client *i2c; 450 struct gpio_desc *gpiod_hp_det; 451 struct gpio_desc *gpiod_cbj_sleeve; 452 struct snd_soc_jack *hp_jack; 453 struct snd_soc_jack *mic_jack; 454 struct snd_soc_jack *btn_jack; 455 struct delayed_work jack_detect_work, rcclock_work; 456 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 457 struct rt5645_eq_param_s *eq_param; 458 struct timer_list btn_check_timer; 459 struct mutex jd_mutex; 460 461 int codec_type; 462 int sysclk; 463 int sysclk_src; 464 int lrck[RT5645_AIFS]; 465 int bclk[RT5645_AIFS]; 466 int master[RT5645_AIFS]; 467 468 int pll_src; 469 int pll_in; 470 int pll_out; 471 472 int jack_type; 473 bool en_button_func; 474 int v_id; 475 }; 476 477 static int rt5645_reset(struct snd_soc_component *component) 478 { 479 return snd_soc_component_write(component, RT5645_RESET, 0); 480 } 481 482 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 483 { 484 int i; 485 486 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 487 if (reg >= rt5645_ranges[i].range_min && 488 reg <= rt5645_ranges[i].range_max) { 489 return true; 490 } 491 } 492 493 switch (reg) { 494 case RT5645_RESET: 495 case RT5645_PRIV_INDEX: 496 case RT5645_PRIV_DATA: 497 case RT5645_IN1_CTRL1: 498 case RT5645_IN1_CTRL2: 499 case RT5645_IN1_CTRL3: 500 case RT5645_A_JD_CTRL1: 501 case RT5645_ADC_EQ_CTRL1: 502 case RT5645_EQ_CTRL1: 503 case RT5645_ALC_CTRL_1: 504 case RT5645_IRQ_CTRL2: 505 case RT5645_IRQ_CTRL3: 506 case RT5645_INT_IRQ_ST: 507 case RT5645_IL_CMD: 508 case RT5650_4BTN_IL_CMD1: 509 case RT5645_VENDOR_ID: 510 case RT5645_VENDOR_ID1: 511 case RT5645_VENDOR_ID2: 512 return true; 513 default: 514 return false; 515 } 516 } 517 518 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 519 { 520 int i; 521 522 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 523 if (reg >= rt5645_ranges[i].range_min && 524 reg <= rt5645_ranges[i].range_max) { 525 return true; 526 } 527 } 528 529 switch (reg) { 530 case RT5645_RESET: 531 case RT5645_SPK_VOL: 532 case RT5645_HP_VOL: 533 case RT5645_LOUT1: 534 case RT5645_IN1_CTRL1: 535 case RT5645_IN1_CTRL2: 536 case RT5645_IN1_CTRL3: 537 case RT5645_IN2_CTRL: 538 case RT5645_INL1_INR1_VOL: 539 case RT5645_SPK_FUNC_LIM: 540 case RT5645_ADJ_HPF_CTRL: 541 case RT5645_DAC1_DIG_VOL: 542 case RT5645_DAC2_DIG_VOL: 543 case RT5645_DAC_CTRL: 544 case RT5645_STO1_ADC_DIG_VOL: 545 case RT5645_MONO_ADC_DIG_VOL: 546 case RT5645_ADC_BST_VOL1: 547 case RT5645_ADC_BST_VOL2: 548 case RT5645_STO1_ADC_MIXER: 549 case RT5645_MONO_ADC_MIXER: 550 case RT5645_AD_DA_MIXER: 551 case RT5645_STO_DAC_MIXER: 552 case RT5645_MONO_DAC_MIXER: 553 case RT5645_DIG_MIXER: 554 case RT5650_A_DAC_SOUR: 555 case RT5645_DIG_INF1_DATA: 556 case RT5645_PDM_OUT_CTRL: 557 case RT5645_REC_L1_MIXER: 558 case RT5645_REC_L2_MIXER: 559 case RT5645_REC_R1_MIXER: 560 case RT5645_REC_R2_MIXER: 561 case RT5645_HPMIXL_CTRL: 562 case RT5645_HPOMIXL_CTRL: 563 case RT5645_HPMIXR_CTRL: 564 case RT5645_HPOMIXR_CTRL: 565 case RT5645_HPO_MIXER: 566 case RT5645_SPK_L_MIXER: 567 case RT5645_SPK_R_MIXER: 568 case RT5645_SPO_MIXER: 569 case RT5645_SPO_CLSD_RATIO: 570 case RT5645_OUT_L1_MIXER: 571 case RT5645_OUT_R1_MIXER: 572 case RT5645_OUT_L_GAIN1: 573 case RT5645_OUT_L_GAIN2: 574 case RT5645_OUT_R_GAIN1: 575 case RT5645_OUT_R_GAIN2: 576 case RT5645_LOUT_MIXER: 577 case RT5645_HAPTIC_CTRL1: 578 case RT5645_HAPTIC_CTRL2: 579 case RT5645_HAPTIC_CTRL3: 580 case RT5645_HAPTIC_CTRL4: 581 case RT5645_HAPTIC_CTRL5: 582 case RT5645_HAPTIC_CTRL6: 583 case RT5645_HAPTIC_CTRL7: 584 case RT5645_HAPTIC_CTRL8: 585 case RT5645_HAPTIC_CTRL9: 586 case RT5645_HAPTIC_CTRL10: 587 case RT5645_PWR_DIG1: 588 case RT5645_PWR_DIG2: 589 case RT5645_PWR_ANLG1: 590 case RT5645_PWR_ANLG2: 591 case RT5645_PWR_MIXER: 592 case RT5645_PWR_VOL: 593 case RT5645_PRIV_INDEX: 594 case RT5645_PRIV_DATA: 595 case RT5645_I2S1_SDP: 596 case RT5645_I2S2_SDP: 597 case RT5645_ADDA_CLK1: 598 case RT5645_ADDA_CLK2: 599 case RT5645_DMIC_CTRL1: 600 case RT5645_DMIC_CTRL2: 601 case RT5645_TDM_CTRL_1: 602 case RT5645_TDM_CTRL_2: 603 case RT5645_TDM_CTRL_3: 604 case RT5650_TDM_CTRL_4: 605 case RT5645_GLB_CLK: 606 case RT5645_PLL_CTRL1: 607 case RT5645_PLL_CTRL2: 608 case RT5645_ASRC_1: 609 case RT5645_ASRC_2: 610 case RT5645_ASRC_3: 611 case RT5645_ASRC_4: 612 case RT5645_DEPOP_M1: 613 case RT5645_DEPOP_M2: 614 case RT5645_DEPOP_M3: 615 case RT5645_CHARGE_PUMP: 616 case RT5645_MICBIAS: 617 case RT5645_A_JD_CTRL1: 618 case RT5645_VAD_CTRL4: 619 case RT5645_CLSD_OUT_CTRL: 620 case RT5645_ADC_EQ_CTRL1: 621 case RT5645_ADC_EQ_CTRL2: 622 case RT5645_EQ_CTRL1: 623 case RT5645_EQ_CTRL2: 624 case RT5645_ALC_CTRL_1: 625 case RT5645_ALC_CTRL_2: 626 case RT5645_ALC_CTRL_3: 627 case RT5645_ALC_CTRL_4: 628 case RT5645_ALC_CTRL_5: 629 case RT5645_JD_CTRL: 630 case RT5645_IRQ_CTRL1: 631 case RT5645_IRQ_CTRL2: 632 case RT5645_IRQ_CTRL3: 633 case RT5645_INT_IRQ_ST: 634 case RT5645_GPIO_CTRL1: 635 case RT5645_GPIO_CTRL2: 636 case RT5645_GPIO_CTRL3: 637 case RT5645_BASS_BACK: 638 case RT5645_MP3_PLUS1: 639 case RT5645_MP3_PLUS2: 640 case RT5645_ADJ_HPF1: 641 case RT5645_ADJ_HPF2: 642 case RT5645_HP_CALIB_AMP_DET: 643 case RT5645_SV_ZCD1: 644 case RT5645_SV_ZCD2: 645 case RT5645_IL_CMD: 646 case RT5645_IL_CMD2: 647 case RT5645_IL_CMD3: 648 case RT5650_4BTN_IL_CMD1: 649 case RT5650_4BTN_IL_CMD2: 650 case RT5645_DRC1_HL_CTRL1: 651 case RT5645_DRC2_HL_CTRL1: 652 case RT5645_ADC_MONO_HP_CTRL1: 653 case RT5645_ADC_MONO_HP_CTRL2: 654 case RT5645_DRC2_CTRL1: 655 case RT5645_DRC2_CTRL2: 656 case RT5645_DRC2_CTRL3: 657 case RT5645_DRC2_CTRL4: 658 case RT5645_DRC2_CTRL5: 659 case RT5645_JD_CTRL3: 660 case RT5645_JD_CTRL4: 661 case RT5645_GEN_CTRL1: 662 case RT5645_GEN_CTRL2: 663 case RT5645_GEN_CTRL3: 664 case RT5645_VENDOR_ID: 665 case RT5645_VENDOR_ID1: 666 case RT5645_VENDOR_ID2: 667 return true; 668 default: 669 return false; 670 } 671 } 672 673 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 674 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 675 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 676 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 677 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 678 679 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 680 static const DECLARE_TLV_DB_RANGE(bst_tlv, 681 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 682 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 683 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 684 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 685 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 686 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 687 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 688 ); 689 690 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 691 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 692 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 693 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 694 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 695 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 696 ); 697 698 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 699 struct snd_ctl_elem_info *uinfo) 700 { 701 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 702 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 703 704 return 0; 705 } 706 707 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 708 struct snd_ctl_elem_value *ucontrol) 709 { 710 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 711 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 712 struct rt5645_eq_param_s_be16 *eq_param = 713 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 714 int i; 715 716 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 717 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 718 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 719 } 720 721 return 0; 722 } 723 724 static bool rt5645_validate_hweq(unsigned short reg) 725 { 726 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) || 727 (reg == RT5645_EQ_CTRL2)) 728 return true; 729 730 return false; 731 } 732 733 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 734 struct snd_ctl_elem_value *ucontrol) 735 { 736 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 737 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 738 struct rt5645_eq_param_s_be16 *eq_param = 739 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 740 int i; 741 742 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 743 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 744 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); 745 } 746 747 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 748 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 749 if (rt5645->eq_param[i].reg == 0) 750 continue; 751 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) 752 return 0; 753 else 754 break; 755 } 756 757 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 758 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && 759 rt5645->eq_param[i].reg != 0) 760 return 0; 761 else if (rt5645->eq_param[i].reg == 0) 762 break; 763 } 764 765 return 0; 766 } 767 768 #define RT5645_HWEQ(xname) \ 769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 770 .info = rt5645_hweq_info, \ 771 .get = rt5645_hweq_get, \ 772 .put = rt5645_hweq_put \ 773 } 774 775 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 776 struct snd_ctl_elem_value *ucontrol) 777 { 778 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 779 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 780 int ret; 781 782 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 783 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 784 785 ret = snd_soc_put_volsw(kcontrol, ucontrol); 786 787 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 788 msecs_to_jiffies(200)); 789 790 return ret; 791 } 792 793 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { 794 "immediately", "zero crossing", "soft ramp" 795 }; 796 797 static SOC_ENUM_SINGLE_DECL( 798 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, 799 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); 800 801 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 802 /* Speaker Output Volume */ 803 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 804 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 805 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 806 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 807 rt5645_spk_put_volsw, out_vol_tlv), 808 809 /* ClassD modulator Speaker Gain Ratio */ 810 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 811 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 812 813 /* Headphone Output Volume */ 814 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 815 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 816 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 817 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 818 819 /* OUTPUT Control */ 820 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 821 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 822 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 823 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 824 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 825 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 826 827 /* DAC Digital Volume */ 828 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 829 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 830 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 831 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 832 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 833 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 834 835 /* IN1/IN2 Control */ 836 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 837 RT5645_BST_SFT1, 12, 0, bst_tlv), 838 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 839 RT5645_BST_SFT2, 8, 0, bst_tlv), 840 841 /* INL/INR Volume Control */ 842 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 843 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 844 845 /* ADC Digital Volume Control */ 846 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 847 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 848 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 849 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 850 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 851 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 852 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 853 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 854 855 /* ADC Boost Volume Control */ 856 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 857 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 858 adc_bst_tlv), 859 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 860 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 861 adc_bst_tlv), 862 863 /* I2S2 function select */ 864 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 865 1, 1), 866 RT5645_HWEQ("Speaker HWEQ"), 867 868 /* Digital Soft Volume Control */ 869 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode), 870 }; 871 872 /** 873 * set_dmic_clk - Set parameter of dmic. 874 * 875 * @w: DAPM widget. 876 * @kcontrol: The kcontrol of this widget. 877 * @event: Event id. 878 * 879 */ 880 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 881 struct snd_kcontrol *kcontrol, int event) 882 { 883 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 884 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 885 int idx, rate; 886 887 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 888 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 889 idx = rl6231_calc_dmic_clk(rate); 890 if (idx < 0) 891 dev_err(component->dev, "Failed to set DMIC clock\n"); 892 else 893 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, 894 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 895 return idx; 896 } 897 898 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 899 struct snd_soc_dapm_widget *sink) 900 { 901 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 902 unsigned int val; 903 904 val = snd_soc_component_read(component, RT5645_GLB_CLK); 905 val &= RT5645_SCLK_SRC_MASK; 906 if (val == RT5645_SCLK_SRC_PLL1) 907 return 1; 908 else 909 return 0; 910 } 911 912 static int is_using_asrc(struct snd_soc_dapm_widget *source, 913 struct snd_soc_dapm_widget *sink) 914 { 915 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 916 unsigned int reg, shift, val; 917 918 switch (source->shift) { 919 case 0: 920 reg = RT5645_ASRC_3; 921 shift = 0; 922 break; 923 case 1: 924 reg = RT5645_ASRC_3; 925 shift = 4; 926 break; 927 case 3: 928 reg = RT5645_ASRC_2; 929 shift = 0; 930 break; 931 case 8: 932 reg = RT5645_ASRC_2; 933 shift = 4; 934 break; 935 case 9: 936 reg = RT5645_ASRC_2; 937 shift = 8; 938 break; 939 case 10: 940 reg = RT5645_ASRC_2; 941 shift = 12; 942 break; 943 default: 944 return 0; 945 } 946 947 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 948 switch (val) { 949 case 1: 950 case 2: 951 case 3: 952 case 4: 953 return 1; 954 default: 955 return 0; 956 } 957 958 } 959 960 static int rt5645_enable_hweq(struct snd_soc_component *component) 961 { 962 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 963 int i; 964 965 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 966 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 967 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 968 rt5645->eq_param[i].val); 969 else 970 break; 971 } 972 973 return 0; 974 } 975 976 /** 977 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 978 * @component: SoC audio component device. 979 * @filter_mask: mask of filters. 980 * @clk_src: clock source 981 * 982 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 983 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 984 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 985 * ASRC function will track i2s clock and generate a corresponding system clock 986 * for codec. This function provides an API to select the clock source for a 987 * set of filters specified by the mask. And the codec driver will turn on ASRC 988 * for these filters if ASRC is selected as their clock source. 989 */ 990 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, 991 unsigned int filter_mask, unsigned int clk_src) 992 { 993 unsigned int asrc2_mask = 0; 994 unsigned int asrc2_value = 0; 995 unsigned int asrc3_mask = 0; 996 unsigned int asrc3_value = 0; 997 998 switch (clk_src) { 999 case RT5645_CLK_SEL_SYS: 1000 case RT5645_CLK_SEL_I2S1_ASRC: 1001 case RT5645_CLK_SEL_I2S2_ASRC: 1002 case RT5645_CLK_SEL_SYS2: 1003 break; 1004 1005 default: 1006 return -EINVAL; 1007 } 1008 1009 if (filter_mask & RT5645_DA_STEREO_FILTER) { 1010 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 1011 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 1012 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 1013 } 1014 1015 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 1016 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 1017 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 1018 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 1019 } 1020 1021 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 1022 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 1023 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 1024 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 1025 } 1026 1027 if (filter_mask & RT5645_AD_STEREO_FILTER) { 1028 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 1029 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 1030 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 1031 } 1032 1033 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 1034 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 1035 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 1036 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 1037 } 1038 1039 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 1040 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 1041 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 1042 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 1043 } 1044 1045 if (asrc2_mask) 1046 snd_soc_component_update_bits(component, RT5645_ASRC_2, 1047 asrc2_mask, asrc2_value); 1048 1049 if (asrc3_mask) 1050 snd_soc_component_update_bits(component, RT5645_ASRC_3, 1051 asrc3_mask, asrc3_value); 1052 1053 return 0; 1054 } 1055 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 1056 1057 /* Digital Mixer */ 1058 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 1059 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1060 RT5645_M_ADC_L1_SFT, 1, 1), 1061 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1062 RT5645_M_ADC_L2_SFT, 1, 1), 1063 }; 1064 1065 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 1066 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1067 RT5645_M_ADC_R1_SFT, 1, 1), 1068 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1069 RT5645_M_ADC_R2_SFT, 1, 1), 1070 }; 1071 1072 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 1073 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1074 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 1075 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1076 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 1077 }; 1078 1079 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 1080 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1081 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 1082 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1083 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 1084 }; 1085 1086 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 1087 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1088 RT5645_M_ADCMIX_L_SFT, 1, 1), 1089 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1090 RT5645_M_DAC1_L_SFT, 1, 1), 1091 }; 1092 1093 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 1094 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1095 RT5645_M_ADCMIX_R_SFT, 1, 1), 1096 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1097 RT5645_M_DAC1_R_SFT, 1, 1), 1098 }; 1099 1100 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 1101 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1102 RT5645_M_DAC_L1_SFT, 1, 1), 1103 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 1104 RT5645_M_DAC_L2_SFT, 1, 1), 1105 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1106 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 1107 }; 1108 1109 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 1110 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1111 RT5645_M_DAC_R1_SFT, 1, 1), 1112 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 1113 RT5645_M_DAC_R2_SFT, 1, 1), 1114 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1115 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 1116 }; 1117 1118 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 1119 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 1120 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 1121 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1122 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 1123 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1124 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 1125 }; 1126 1127 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 1128 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 1129 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 1130 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1131 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 1132 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1133 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 1134 }; 1135 1136 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 1137 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 1138 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 1139 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1140 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 1141 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1142 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 1143 }; 1144 1145 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 1146 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 1147 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 1148 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1149 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 1150 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1151 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 1152 }; 1153 1154 /* Analog Input Mixer */ 1155 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 1156 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 1157 RT5645_M_HP_L_RM_L_SFT, 1, 1), 1158 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 1159 RT5645_M_IN_L_RM_L_SFT, 1, 1), 1160 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 1161 RT5645_M_BST2_RM_L_SFT, 1, 1), 1162 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 1163 RT5645_M_BST1_RM_L_SFT, 1, 1), 1164 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 1165 RT5645_M_OM_L_RM_L_SFT, 1, 1), 1166 }; 1167 1168 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 1169 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 1170 RT5645_M_HP_R_RM_R_SFT, 1, 1), 1171 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 1172 RT5645_M_IN_R_RM_R_SFT, 1, 1), 1173 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 1174 RT5645_M_BST2_RM_R_SFT, 1, 1), 1175 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 1176 RT5645_M_BST1_RM_R_SFT, 1, 1), 1177 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 1178 RT5645_M_OM_R_RM_R_SFT, 1, 1), 1179 }; 1180 1181 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 1182 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 1183 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 1184 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 1185 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 1186 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 1187 RT5645_M_IN_L_SM_L_SFT, 1, 1), 1188 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 1189 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 1190 }; 1191 1192 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 1193 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 1194 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 1195 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 1196 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 1197 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 1198 RT5645_M_IN_R_SM_R_SFT, 1, 1), 1199 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 1200 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 1201 }; 1202 1203 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 1204 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 1205 RT5645_M_BST1_OM_L_SFT, 1, 1), 1206 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 1207 RT5645_M_IN_L_OM_L_SFT, 1, 1), 1208 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 1209 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 1210 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 1211 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 1212 }; 1213 1214 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 1215 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1216 RT5645_M_BST2_OM_R_SFT, 1, 1), 1217 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1218 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1219 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1220 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1221 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1222 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1223 }; 1224 1225 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1226 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1227 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1228 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1229 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1230 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1231 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1232 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1233 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1234 }; 1235 1236 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1237 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1238 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1239 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1240 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1241 }; 1242 1243 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1244 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1245 RT5645_M_DAC1_HM_SFT, 1, 1), 1246 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1247 RT5645_M_HPVOL_HM_SFT, 1, 1), 1248 }; 1249 1250 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1251 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1252 RT5645_M_DAC1_HV_SFT, 1, 1), 1253 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1254 RT5645_M_DAC2_HV_SFT, 1, 1), 1255 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1256 RT5645_M_IN_HV_SFT, 1, 1), 1257 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1258 RT5645_M_BST1_HV_SFT, 1, 1), 1259 }; 1260 1261 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1262 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1263 RT5645_M_DAC1_HV_SFT, 1, 1), 1264 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1265 RT5645_M_DAC2_HV_SFT, 1, 1), 1266 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1267 RT5645_M_IN_HV_SFT, 1, 1), 1268 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1269 RT5645_M_BST2_HV_SFT, 1, 1), 1270 }; 1271 1272 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1273 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1274 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1275 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1276 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1277 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1278 RT5645_M_OV_L_LM_SFT, 1, 1), 1279 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1280 RT5645_M_OV_R_LM_SFT, 1, 1), 1281 }; 1282 1283 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1284 static const char * const rt5645_dac1_src[] = { 1285 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1286 }; 1287 1288 static SOC_ENUM_SINGLE_DECL( 1289 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1290 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1291 1292 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1293 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1294 1295 static SOC_ENUM_SINGLE_DECL( 1296 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1297 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1298 1299 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1300 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1301 1302 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1303 static const char * const rt5645_dac12_src[] = { 1304 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1305 }; 1306 1307 static SOC_ENUM_SINGLE_DECL( 1308 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1309 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1310 1311 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1312 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1313 1314 static const char * const rt5645_dacr2_src[] = { 1315 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1316 }; 1317 1318 static SOC_ENUM_SINGLE_DECL( 1319 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1320 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1321 1322 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1323 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1324 1325 /* Stereo1 ADC source */ 1326 /* MX-27 [12] */ 1327 static const char * const rt5645_stereo_adc1_src[] = { 1328 "DAC MIX", "ADC" 1329 }; 1330 1331 static SOC_ENUM_SINGLE_DECL( 1332 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1333 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1334 1335 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1336 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1337 1338 /* MX-27 [11] */ 1339 static const char * const rt5645_stereo_adc2_src[] = { 1340 "DAC MIX", "DMIC" 1341 }; 1342 1343 static SOC_ENUM_SINGLE_DECL( 1344 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1345 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1346 1347 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1348 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1349 1350 /* MX-27 [8] */ 1351 static const char * const rt5645_stereo_dmic_src[] = { 1352 "DMIC1", "DMIC2" 1353 }; 1354 1355 static SOC_ENUM_SINGLE_DECL( 1356 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1357 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1358 1359 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1360 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1361 1362 /* Mono ADC source */ 1363 /* MX-28 [12] */ 1364 static const char * const rt5645_mono_adc_l1_src[] = { 1365 "Mono DAC MIXL", "ADC" 1366 }; 1367 1368 static SOC_ENUM_SINGLE_DECL( 1369 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1370 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1371 1372 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1373 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1374 /* MX-28 [11] */ 1375 static const char * const rt5645_mono_adc_l2_src[] = { 1376 "Mono DAC MIXL", "DMIC" 1377 }; 1378 1379 static SOC_ENUM_SINGLE_DECL( 1380 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1381 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1382 1383 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1384 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1385 1386 /* MX-28 [8] */ 1387 static const char * const rt5645_mono_dmic_src[] = { 1388 "DMIC1", "DMIC2" 1389 }; 1390 1391 static SOC_ENUM_SINGLE_DECL( 1392 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1393 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1394 1395 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1396 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1397 /* MX-28 [1:0] */ 1398 static SOC_ENUM_SINGLE_DECL( 1399 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1400 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1401 1402 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1403 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1404 /* MX-28 [4] */ 1405 static const char * const rt5645_mono_adc_r1_src[] = { 1406 "Mono DAC MIXR", "ADC" 1407 }; 1408 1409 static SOC_ENUM_SINGLE_DECL( 1410 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1411 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1412 1413 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1414 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1415 /* MX-28 [3] */ 1416 static const char * const rt5645_mono_adc_r2_src[] = { 1417 "Mono DAC MIXR", "DMIC" 1418 }; 1419 1420 static SOC_ENUM_SINGLE_DECL( 1421 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1422 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1423 1424 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1425 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1426 1427 /* MX-77 [9:8] */ 1428 static const char * const rt5645_if1_adc_in_src[] = { 1429 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1430 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1431 }; 1432 1433 static SOC_ENUM_SINGLE_DECL( 1434 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1435 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1436 1437 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1438 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1439 1440 /* MX-78 [4:0] */ 1441 static const char * const rt5650_if1_adc_in_src[] = { 1442 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1443 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1444 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1445 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1446 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1447 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1448 1449 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1450 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1451 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1452 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1453 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1454 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1455 1456 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1457 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1458 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1459 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1460 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1461 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1462 1463 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1464 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1465 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1466 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1467 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1468 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1469 }; 1470 1471 static SOC_ENUM_SINGLE_DECL( 1472 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1473 0, rt5650_if1_adc_in_src); 1474 1475 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1476 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1477 1478 /* MX-78 [15:14][13:12][11:10] */ 1479 static const char * const rt5645_tdm_adc_swap_select[] = { 1480 "L/R", "R/L", "L/L", "R/R" 1481 }; 1482 1483 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1484 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1485 1486 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1487 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1488 1489 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1490 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1491 1492 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1493 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1494 1495 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1496 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1497 1498 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1499 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1500 1501 /* MX-77 [7:6][5:4][3:2] */ 1502 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1503 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1504 1505 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1506 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1507 1508 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1509 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1510 1511 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1512 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1513 1514 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1515 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1516 1517 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1518 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1519 1520 /* MX-79 [14:12][10:8][6:4][2:0] */ 1521 static const char * const rt5645_tdm_dac_swap_select[] = { 1522 "Slot0", "Slot1", "Slot2", "Slot3" 1523 }; 1524 1525 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1526 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1527 1528 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1529 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1530 1531 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1532 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1533 1534 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1535 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1536 1537 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1538 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1539 1540 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1541 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1542 1543 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1544 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1545 1546 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1547 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1548 1549 /* MX-7a [14:12][10:8][6:4][2:0] */ 1550 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1551 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1552 1553 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1554 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1555 1556 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1557 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1558 1559 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1560 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1561 1562 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1563 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1564 1565 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1566 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1567 1568 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1569 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1570 1571 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1572 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1573 1574 /* MX-2d [3] [2] */ 1575 static const char * const rt5650_a_dac1_src[] = { 1576 "DAC1", "Stereo DAC Mixer" 1577 }; 1578 1579 static SOC_ENUM_SINGLE_DECL( 1580 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1581 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1582 1583 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1584 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1585 1586 static SOC_ENUM_SINGLE_DECL( 1587 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1588 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1589 1590 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1591 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1592 1593 /* MX-2d [1] [0] */ 1594 static const char * const rt5650_a_dac2_src[] = { 1595 "Stereo DAC Mixer", "Mono DAC Mixer" 1596 }; 1597 1598 static SOC_ENUM_SINGLE_DECL( 1599 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1600 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1601 1602 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1603 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1604 1605 static SOC_ENUM_SINGLE_DECL( 1606 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1607 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1608 1609 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1610 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1611 1612 /* MX-2F [13:12] */ 1613 static const char * const rt5645_if2_adc_in_src[] = { 1614 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1615 }; 1616 1617 static SOC_ENUM_SINGLE_DECL( 1618 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1619 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1620 1621 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1622 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1623 1624 /* MX-31 [15] [13] [11] [9] */ 1625 static const char * const rt5645_pdm_src[] = { 1626 "Mono DAC", "Stereo DAC" 1627 }; 1628 1629 static SOC_ENUM_SINGLE_DECL( 1630 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1631 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1632 1633 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1634 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1635 1636 static SOC_ENUM_SINGLE_DECL( 1637 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1638 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1639 1640 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1641 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1642 1643 /* MX-9D [9:8] */ 1644 static const char * const rt5645_vad_adc_src[] = { 1645 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1646 }; 1647 1648 static SOC_ENUM_SINGLE_DECL( 1649 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1650 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1651 1652 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1653 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1654 1655 static const struct snd_kcontrol_new spk_l_vol_control = 1656 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1657 RT5645_L_MUTE_SFT, 1, 1); 1658 1659 static const struct snd_kcontrol_new spk_r_vol_control = 1660 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1661 RT5645_R_MUTE_SFT, 1, 1); 1662 1663 static const struct snd_kcontrol_new hp_l_vol_control = 1664 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1665 RT5645_L_MUTE_SFT, 1, 1); 1666 1667 static const struct snd_kcontrol_new hp_r_vol_control = 1668 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1669 RT5645_R_MUTE_SFT, 1, 1); 1670 1671 static const struct snd_kcontrol_new pdm1_l_vol_control = 1672 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1673 RT5645_M_PDM1_L, 1, 1); 1674 1675 static const struct snd_kcontrol_new pdm1_r_vol_control = 1676 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1677 RT5645_M_PDM1_R, 1, 1); 1678 1679 static void hp_amp_power(struct snd_soc_component *component, int on) 1680 { 1681 static int hp_amp_power_count; 1682 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1683 int i, val; 1684 1685 if (on) { 1686 if (hp_amp_power_count <= 0) { 1687 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1688 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100); 1689 snd_soc_component_write(component, RT5645_CHARGE_PUMP, 1690 0x0e06); 1691 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1692 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1693 RT5645_HP_DCC_INT1, 0x9f01); 1694 for (i = 0; i < 20; i++) { 1695 usleep_range(1000, 1500); 1696 regmap_read(rt5645->regmap, RT5645_PR_BASE + 1697 RT5645_HP_DCC_INT1, &val); 1698 if (!(val & 0x8000)) 1699 break; 1700 } 1701 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1702 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1703 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1704 0x3e, 0x7400); 1705 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1706 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1707 RT5645_MAMP_INT_REG2, 0xfc00); 1708 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1709 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1710 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 1711 RT5645_PWR_HP_L | RT5645_PWR_HP_R); 1712 msleep(90); 1713 } else { 1714 /* depop parameters */ 1715 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1716 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1717 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1718 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1719 RT5645_HP_DCC_INT1, 0x9f01); 1720 mdelay(150); 1721 /* headphone amp power on */ 1722 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1723 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1724 snd_soc_component_update_bits(component, RT5645_PWR_VOL, 1725 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1726 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1727 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1728 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1729 RT5645_PWR_HA, 1730 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1731 RT5645_PWR_HA); 1732 mdelay(5); 1733 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1734 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1735 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1736 1737 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1738 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1739 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1740 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1741 0x14, 0x1aaa); 1742 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1743 0x24, 0x0430); 1744 } 1745 } 1746 hp_amp_power_count++; 1747 } else { 1748 hp_amp_power_count--; 1749 if (hp_amp_power_count <= 0) { 1750 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1751 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1752 0x3e, 0x7400); 1753 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1754 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1755 RT5645_MAMP_INT_REG2, 0xfc00); 1756 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1757 msleep(100); 1758 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001); 1759 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1760 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0); 1761 } else { 1762 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1763 RT5645_HP_SG_MASK | 1764 RT5645_HP_L_SMT_MASK | 1765 RT5645_HP_R_SMT_MASK, 1766 RT5645_HP_SG_DIS | 1767 RT5645_HP_L_SMT_DIS | 1768 RT5645_HP_R_SMT_DIS); 1769 /* headphone amp power down */ 1770 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000); 1771 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1772 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1773 RT5645_PWR_HA, 0); 1774 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1775 RT5645_DEPOP_MASK, 0); 1776 } 1777 } 1778 } 1779 } 1780 1781 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1782 struct snd_kcontrol *kcontrol, int event) 1783 { 1784 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1785 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1786 1787 switch (event) { 1788 case SND_SOC_DAPM_POST_PMU: 1789 hp_amp_power(component, 1); 1790 /* headphone unmute sequence */ 1791 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1792 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1793 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1794 RT5645_CP_FQ3_MASK, 1795 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1796 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1797 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1798 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1799 RT5645_MAMP_INT_REG2, 0xfc00); 1800 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1801 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1802 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1803 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1804 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1805 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1806 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1807 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1808 msleep(40); 1809 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1810 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1811 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1812 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1813 } 1814 break; 1815 1816 case SND_SOC_DAPM_PRE_PMD: 1817 /* headphone mute sequence */ 1818 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1819 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1820 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1821 RT5645_CP_FQ3_MASK, 1822 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1823 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1824 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1825 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1826 RT5645_MAMP_INT_REG2, 0xfc00); 1827 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1828 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1829 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1830 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1831 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1832 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1833 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1834 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1835 msleep(30); 1836 } 1837 hp_amp_power(component, 0); 1838 break; 1839 1840 default: 1841 return 0; 1842 } 1843 1844 return 0; 1845 } 1846 1847 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1848 struct snd_kcontrol *kcontrol, int event) 1849 { 1850 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1851 1852 switch (event) { 1853 case SND_SOC_DAPM_POST_PMU: 1854 rt5645_enable_hweq(component); 1855 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1856 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1857 RT5645_PWR_CLS_D_L, 1858 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1859 RT5645_PWR_CLS_D_L); 1860 break; 1861 1862 case SND_SOC_DAPM_PRE_PMD: 1863 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0); 1864 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1865 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1866 RT5645_PWR_CLS_D_L, 0); 1867 break; 1868 1869 default: 1870 return 0; 1871 } 1872 1873 return 0; 1874 } 1875 1876 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1877 struct snd_kcontrol *kcontrol, int event) 1878 { 1879 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1880 1881 switch (event) { 1882 case SND_SOC_DAPM_POST_PMU: 1883 hp_amp_power(component, 1); 1884 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1885 RT5645_PWR_LM, RT5645_PWR_LM); 1886 snd_soc_component_update_bits(component, RT5645_LOUT1, 1887 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1888 break; 1889 1890 case SND_SOC_DAPM_PRE_PMD: 1891 snd_soc_component_update_bits(component, RT5645_LOUT1, 1892 RT5645_L_MUTE | RT5645_R_MUTE, 1893 RT5645_L_MUTE | RT5645_R_MUTE); 1894 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1895 RT5645_PWR_LM, 0); 1896 hp_amp_power(component, 0); 1897 break; 1898 1899 default: 1900 return 0; 1901 } 1902 1903 return 0; 1904 } 1905 1906 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1907 struct snd_kcontrol *kcontrol, int event) 1908 { 1909 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1910 1911 switch (event) { 1912 case SND_SOC_DAPM_POST_PMU: 1913 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1914 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1915 break; 1916 1917 case SND_SOC_DAPM_PRE_PMD: 1918 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1919 RT5645_PWR_BST2_P, 0); 1920 break; 1921 1922 default: 1923 return 0; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, 1930 struct snd_kcontrol *k, int event) 1931 { 1932 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1933 1934 switch (event) { 1935 case SND_SOC_DAPM_PRE_PMU: 1936 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1937 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1938 RT5645_MICBIAS1_POW_CTRL_SEL_M); 1939 break; 1940 1941 case SND_SOC_DAPM_POST_PMD: 1942 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1943 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1944 RT5645_MICBIAS1_POW_CTRL_SEL_A); 1945 break; 1946 1947 default: 1948 return 0; 1949 } 1950 1951 return 0; 1952 } 1953 1954 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, 1955 struct snd_kcontrol *k, int event) 1956 { 1957 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1958 1959 switch (event) { 1960 case SND_SOC_DAPM_PRE_PMU: 1961 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1962 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1963 RT5645_MICBIAS2_POW_CTRL_SEL_M); 1964 break; 1965 1966 case SND_SOC_DAPM_POST_PMD: 1967 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1968 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1969 RT5645_MICBIAS2_POW_CTRL_SEL_A); 1970 break; 1971 1972 default: 1973 return 0; 1974 } 1975 1976 return 0; 1977 } 1978 1979 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1980 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1981 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1982 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1983 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1984 1985 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1986 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1987 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1988 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1989 1990 /* ASRC */ 1991 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1992 11, 0, NULL, 0), 1993 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1994 12, 0, NULL, 0), 1995 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1996 10, 0, NULL, 0), 1997 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1998 9, 0, NULL, 0), 1999 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 2000 8, 0, NULL, 0), 2001 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 2002 7, 0, NULL, 0), 2003 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 2004 5, 0, NULL, 0), 2005 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 2006 4, 0, NULL, 0), 2007 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 2008 3, 0, NULL, 0), 2009 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 2010 1, 0, NULL, 0), 2011 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 2012 0, 0, NULL, 0), 2013 2014 /* Input Side */ 2015 /* micbias */ 2016 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2, 2017 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, 2018 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2019 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2, 2020 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, 2021 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2022 /* Input Lines */ 2023 SND_SOC_DAPM_INPUT("DMIC L1"), 2024 SND_SOC_DAPM_INPUT("DMIC R1"), 2025 SND_SOC_DAPM_INPUT("DMIC L2"), 2026 SND_SOC_DAPM_INPUT("DMIC R2"), 2027 2028 SND_SOC_DAPM_INPUT("IN1P"), 2029 SND_SOC_DAPM_INPUT("IN1N"), 2030 SND_SOC_DAPM_INPUT("IN2P"), 2031 SND_SOC_DAPM_INPUT("IN2N"), 2032 2033 SND_SOC_DAPM_INPUT("Haptic Generator"), 2034 2035 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2036 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2037 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2038 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2039 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 2040 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 2041 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 2042 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 2043 /* Boost */ 2044 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 2045 RT5645_PWR_BST1_BIT, 0, NULL, 0), 2046 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 2047 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 2048 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2049 /* Input Volume */ 2050 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 2051 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 2052 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 2053 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 2054 /* REC Mixer */ 2055 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 2056 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 2057 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 2058 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 2059 /* ADCs */ 2060 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2061 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2062 2063 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 2064 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 2065 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 2066 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 2067 2068 /* ADC Mux */ 2069 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2070 &rt5645_sto1_dmic_mux), 2071 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2072 &rt5645_sto_adc2_mux), 2073 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2074 &rt5645_sto_adc2_mux), 2075 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2076 &rt5645_sto_adc1_mux), 2077 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2078 &rt5645_sto_adc1_mux), 2079 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2080 &rt5645_mono_dmic_l_mux), 2081 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2082 &rt5645_mono_dmic_r_mux), 2083 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2084 &rt5645_mono_adc_l2_mux), 2085 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2086 &rt5645_mono_adc_l1_mux), 2087 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2088 &rt5645_mono_adc_r1_mux), 2089 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2090 &rt5645_mono_adc_r2_mux), 2091 /* ADC Mixer */ 2092 2093 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 2094 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 2095 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2096 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 2097 NULL, 0), 2098 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2099 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 2100 NULL, 0), 2101 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 2102 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2103 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2104 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 2105 NULL, 0), 2106 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 2107 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2108 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2109 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 2110 NULL, 0), 2111 2112 /* ADC PGA */ 2113 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2114 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2115 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2116 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2117 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2118 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2119 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2120 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2121 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2122 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2123 2124 /* IF1 2 Mux */ 2125 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 2126 0, 0, &rt5645_if2_adc_in_mux), 2127 2128 /* Digital Interface */ 2129 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 2130 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 2131 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2132 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2133 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2134 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2135 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2136 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2137 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2138 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 2139 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 2140 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2141 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2142 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2143 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2144 2145 /* Digital Interface Select */ 2146 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 2147 0, 0, &rt5645_vad_adc_mux), 2148 2149 /* Audio Interface */ 2150 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2151 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2152 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2153 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2154 2155 /* Output Side */ 2156 /* DAC mixer before sound effect */ 2157 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2158 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 2159 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2160 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 2161 2162 /* DAC2 channel Mux */ 2163 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 2164 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 2165 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 2166 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 2167 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 2168 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 2169 2170 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 2171 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 2172 2173 /* DAC Mixer */ 2174 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 2175 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 2176 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 2177 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2178 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 2179 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2180 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2181 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 2182 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2183 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 2184 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2185 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 2186 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2187 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 2188 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 2189 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 2190 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 2191 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 2192 2193 /* DACs */ 2194 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 2195 0), 2196 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 2197 0), 2198 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 2199 0), 2200 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 2201 0), 2202 /* OUT Mixer */ 2203 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 2204 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 2205 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 2206 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 2207 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 2208 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 2209 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 2210 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 2211 /* Ouput Volume */ 2212 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 2213 &spk_l_vol_control), 2214 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 2215 &spk_r_vol_control), 2216 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 2217 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 2218 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 2219 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 2220 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2221 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2222 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2223 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2224 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2225 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2226 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2227 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2228 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2229 2230 /* HPO/LOUT/Mono Mixer */ 2231 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2232 ARRAY_SIZE(rt5645_spo_l_mix)), 2233 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2234 ARRAY_SIZE(rt5645_spo_r_mix)), 2235 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2236 ARRAY_SIZE(rt5645_hpo_mix)), 2237 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2238 ARRAY_SIZE(rt5645_lout_mix)), 2239 2240 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2241 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2242 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2243 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2244 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2245 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2246 2247 /* PDM */ 2248 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2249 0, NULL, 0), 2250 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2251 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2252 2253 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2254 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2255 2256 /* Output Lines */ 2257 SND_SOC_DAPM_OUTPUT("HPOL"), 2258 SND_SOC_DAPM_OUTPUT("HPOR"), 2259 SND_SOC_DAPM_OUTPUT("LOUTL"), 2260 SND_SOC_DAPM_OUTPUT("LOUTR"), 2261 SND_SOC_DAPM_OUTPUT("PDM1L"), 2262 SND_SOC_DAPM_OUTPUT("PDM1R"), 2263 SND_SOC_DAPM_OUTPUT("SPOL"), 2264 SND_SOC_DAPM_OUTPUT("SPOR"), 2265 }; 2266 2267 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2268 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2269 &rt5645_if1_dac0_tdm_sel_mux), 2270 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2271 &rt5645_if1_dac1_tdm_sel_mux), 2272 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2273 &rt5645_if1_dac2_tdm_sel_mux), 2274 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2275 &rt5645_if1_dac3_tdm_sel_mux), 2276 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2277 0, 0, &rt5645_if1_adc_in_mux), 2278 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2279 0, 0, &rt5645_if1_adc1_in_mux), 2280 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2281 0, 0, &rt5645_if1_adc2_in_mux), 2282 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2283 0, 0, &rt5645_if1_adc3_in_mux), 2284 }; 2285 2286 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2287 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2288 0, 0, &rt5650_a_dac1_l_mux), 2289 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2290 0, 0, &rt5650_a_dac1_r_mux), 2291 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2292 0, 0, &rt5650_a_dac2_l_mux), 2293 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2294 0, 0, &rt5650_a_dac2_r_mux), 2295 2296 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2297 0, 0, &rt5650_if1_adc1_in_mux), 2298 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2299 0, 0, &rt5650_if1_adc2_in_mux), 2300 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2301 0, 0, &rt5650_if1_adc3_in_mux), 2302 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2303 0, 0, &rt5650_if1_adc_in_mux), 2304 2305 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2306 &rt5650_if1_dac0_tdm_sel_mux), 2307 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2308 &rt5650_if1_dac1_tdm_sel_mux), 2309 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2310 &rt5650_if1_dac2_tdm_sel_mux), 2311 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2312 &rt5650_if1_dac3_tdm_sel_mux), 2313 }; 2314 2315 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2316 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2317 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2318 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2319 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2320 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2321 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2322 2323 { "I2S1", NULL, "I2S1 ASRC" }, 2324 { "I2S2", NULL, "I2S2 ASRC" }, 2325 2326 { "IN1P", NULL, "LDO2" }, 2327 { "IN2P", NULL, "LDO2" }, 2328 2329 { "DMIC1", NULL, "DMIC L1" }, 2330 { "DMIC1", NULL, "DMIC R1" }, 2331 { "DMIC2", NULL, "DMIC L2" }, 2332 { "DMIC2", NULL, "DMIC R2" }, 2333 2334 { "BST1", NULL, "IN1P" }, 2335 { "BST1", NULL, "IN1N" }, 2336 { "BST1", NULL, "JD Power" }, 2337 { "BST1", NULL, "Mic Det Power" }, 2338 { "BST2", NULL, "IN2P" }, 2339 { "BST2", NULL, "IN2N" }, 2340 2341 { "INL VOL", NULL, "IN2P" }, 2342 { "INR VOL", NULL, "IN2N" }, 2343 2344 { "RECMIXL", "HPOL Switch", "HPOL" }, 2345 { "RECMIXL", "INL Switch", "INL VOL" }, 2346 { "RECMIXL", "BST2 Switch", "BST2" }, 2347 { "RECMIXL", "BST1 Switch", "BST1" }, 2348 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2349 2350 { "RECMIXR", "HPOR Switch", "HPOR" }, 2351 { "RECMIXR", "INR Switch", "INR VOL" }, 2352 { "RECMIXR", "BST2 Switch", "BST2" }, 2353 { "RECMIXR", "BST1 Switch", "BST1" }, 2354 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2355 2356 { "ADC L", NULL, "RECMIXL" }, 2357 { "ADC L", NULL, "ADC L power" }, 2358 { "ADC R", NULL, "RECMIXR" }, 2359 { "ADC R", NULL, "ADC R power" }, 2360 2361 {"DMIC L1", NULL, "DMIC CLK"}, 2362 {"DMIC L1", NULL, "DMIC1 Power"}, 2363 {"DMIC R1", NULL, "DMIC CLK"}, 2364 {"DMIC R1", NULL, "DMIC1 Power"}, 2365 {"DMIC L2", NULL, "DMIC CLK"}, 2366 {"DMIC L2", NULL, "DMIC2 Power"}, 2367 {"DMIC R2", NULL, "DMIC CLK"}, 2368 {"DMIC R2", NULL, "DMIC2 Power"}, 2369 2370 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2371 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2372 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2373 2374 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2375 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2376 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2377 2378 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2379 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2380 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2381 2382 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2383 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2384 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2385 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2386 2387 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2388 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2389 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2390 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2391 2392 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2393 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2394 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2395 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2396 2397 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2398 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2399 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2400 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2401 2402 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2403 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2404 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2405 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2406 2407 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2408 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2409 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2410 2411 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2412 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2413 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2414 2415 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2416 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2417 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2418 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2419 2420 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2421 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2422 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2423 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2424 2425 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2426 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2427 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2428 2429 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2430 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2431 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2432 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2433 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2434 2435 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2436 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2437 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2438 2439 { "IF1 ADC", NULL, "I2S1" }, 2440 { "IF2 ADC", NULL, "I2S2" }, 2441 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2442 2443 { "AIF2TX", NULL, "IF2 ADC" }, 2444 2445 { "IF1 DAC0", NULL, "AIF1RX" }, 2446 { "IF1 DAC1", NULL, "AIF1RX" }, 2447 { "IF1 DAC2", NULL, "AIF1RX" }, 2448 { "IF1 DAC3", NULL, "AIF1RX" }, 2449 { "IF2 DAC", NULL, "AIF2RX" }, 2450 2451 { "IF1 DAC0", NULL, "I2S1" }, 2452 { "IF1 DAC1", NULL, "I2S1" }, 2453 { "IF1 DAC2", NULL, "I2S1" }, 2454 { "IF1 DAC3", NULL, "I2S1" }, 2455 { "IF2 DAC", NULL, "I2S2" }, 2456 2457 { "IF2 DAC L", NULL, "IF2 DAC" }, 2458 { "IF2 DAC R", NULL, "IF2 DAC" }, 2459 2460 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2461 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2462 2463 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2464 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2465 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2466 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2467 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2468 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2469 2470 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2471 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2472 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2473 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2474 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2475 2476 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2477 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2478 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2479 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2480 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2481 2482 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2483 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2484 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2485 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2486 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2487 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2488 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2489 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2490 2491 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2492 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2493 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2494 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2495 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2496 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2497 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2498 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2499 2500 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2501 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2502 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2503 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2504 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2505 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2506 2507 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2508 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2509 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2510 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2511 2512 { "SPK MIXL", "BST1 Switch", "BST1" }, 2513 { "SPK MIXL", "INL Switch", "INL VOL" }, 2514 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2515 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2516 { "SPK MIXR", "BST2 Switch", "BST2" }, 2517 { "SPK MIXR", "INR Switch", "INR VOL" }, 2518 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2519 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2520 2521 { "OUT MIXL", "BST1 Switch", "BST1" }, 2522 { "OUT MIXL", "INL Switch", "INL VOL" }, 2523 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2524 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2525 2526 { "OUT MIXR", "BST2 Switch", "BST2" }, 2527 { "OUT MIXR", "INR Switch", "INR VOL" }, 2528 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2529 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2530 2531 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2532 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2533 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2534 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2535 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2536 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2537 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2538 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2539 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2540 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2541 2542 { "DAC 2", NULL, "DAC L2" }, 2543 { "DAC 2", NULL, "DAC R2" }, 2544 { "DAC 1", NULL, "DAC L1" }, 2545 { "DAC 1", NULL, "DAC R1" }, 2546 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2547 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2548 { "HPOVOL", NULL, "HPOVOL L" }, 2549 { "HPOVOL", NULL, "HPOVOL R" }, 2550 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2551 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2552 2553 { "SPKVOL L", "Switch", "SPK MIXL" }, 2554 { "SPKVOL R", "Switch", "SPK MIXR" }, 2555 2556 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2557 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2558 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2559 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2560 2561 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2562 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2563 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2564 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2565 2566 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2567 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2568 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2569 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2570 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2571 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2572 2573 { "HP amp", NULL, "HPO MIX" }, 2574 { "HP amp", NULL, "JD Power" }, 2575 { "HP amp", NULL, "Mic Det Power" }, 2576 { "HP amp", NULL, "LDO2" }, 2577 { "HPOL", NULL, "HP amp" }, 2578 { "HPOR", NULL, "HP amp" }, 2579 2580 { "LOUT amp", NULL, "LOUT MIX" }, 2581 { "LOUTL", NULL, "LOUT amp" }, 2582 { "LOUTR", NULL, "LOUT amp" }, 2583 2584 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2585 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2586 2587 { "PDM1L", NULL, "PDM1 L" }, 2588 { "PDM1R", NULL, "PDM1 R" }, 2589 2590 { "SPK amp", NULL, "SPOL MIX" }, 2591 { "SPK amp", NULL, "SPOR MIX" }, 2592 { "SPOL", NULL, "SPK amp" }, 2593 { "SPOR", NULL, "SPK amp" }, 2594 }; 2595 2596 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2597 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2598 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2599 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2600 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2601 2602 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2603 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2604 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2605 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2606 2607 { "DAC L1", NULL, "A DAC1 L Mux" }, 2608 { "DAC R1", NULL, "A DAC1 R Mux" }, 2609 { "DAC L2", NULL, "A DAC2 L Mux" }, 2610 { "DAC R2", NULL, "A DAC2 R Mux" }, 2611 2612 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2613 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2614 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2615 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2616 2617 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2618 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2619 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2620 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2621 2622 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2623 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2624 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2625 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2626 2627 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2628 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2629 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2630 2631 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2632 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2633 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2634 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2635 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2636 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2637 2638 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2639 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2640 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2641 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2642 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2643 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2644 2645 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2646 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2647 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2648 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2649 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2650 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2651 2652 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2653 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2654 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2655 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2656 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2657 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2658 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2659 2660 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2661 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2662 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2663 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2664 2665 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2666 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2667 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2668 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2669 2670 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2671 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2672 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2673 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2674 2675 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2676 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2677 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2678 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2679 2680 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2681 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2682 2683 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2684 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2685 }; 2686 2687 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2688 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2689 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2690 { "DAC L2", NULL, "Mono DAC MIXL" }, 2691 { "DAC R2", NULL, "Mono DAC MIXR" }, 2692 2693 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2694 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2695 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2696 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2697 2698 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2699 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2700 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2701 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2702 2703 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2704 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2705 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2706 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2707 2708 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2709 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2710 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2711 2712 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2713 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2714 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2715 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2716 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2717 2718 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2719 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2720 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2721 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2722 2723 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2724 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2725 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2726 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2727 2728 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2729 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2730 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2731 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2732 2733 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2734 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2735 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2736 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2737 2738 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2739 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2740 2741 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2742 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2743 }; 2744 2745 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { 2746 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2747 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2748 }; 2749 2750 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2751 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2752 { 2753 struct snd_soc_component *component = dai->component; 2754 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2755 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2756 int pre_div, bclk_ms, frame_size; 2757 2758 rt5645->lrck[dai->id] = params_rate(params); 2759 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2760 if (pre_div < 0) { 2761 dev_err(component->dev, "Unsupported clock setting\n"); 2762 return -EINVAL; 2763 } 2764 frame_size = snd_soc_params_to_frame_size(params); 2765 if (frame_size < 0) { 2766 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2767 return -EINVAL; 2768 } 2769 2770 switch (rt5645->codec_type) { 2771 case CODEC_TYPE_RT5650: 2772 dl_sft = 4; 2773 break; 2774 default: 2775 dl_sft = 2; 2776 break; 2777 } 2778 2779 bclk_ms = frame_size > 32; 2780 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2781 2782 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2783 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2784 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2785 bclk_ms, pre_div, dai->id); 2786 2787 switch (params_width(params)) { 2788 case 16: 2789 break; 2790 case 20: 2791 val_len = 0x1; 2792 break; 2793 case 24: 2794 val_len = 0x2; 2795 break; 2796 case 8: 2797 val_len = 0x3; 2798 break; 2799 default: 2800 return -EINVAL; 2801 } 2802 2803 switch (dai->id) { 2804 case RT5645_AIF1: 2805 mask_clk = RT5645_I2S_PD1_MASK; 2806 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2807 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2808 (0x3 << dl_sft), (val_len << dl_sft)); 2809 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2810 break; 2811 case RT5645_AIF2: 2812 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2813 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2814 pre_div << RT5645_I2S_PD2_SFT; 2815 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2816 (0x3 << dl_sft), (val_len << dl_sft)); 2817 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2818 break; 2819 default: 2820 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2821 return -EINVAL; 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2828 { 2829 struct snd_soc_component *component = dai->component; 2830 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2831 unsigned int reg_val = 0, pol_sft; 2832 2833 switch (rt5645->codec_type) { 2834 case CODEC_TYPE_RT5650: 2835 pol_sft = 8; 2836 break; 2837 default: 2838 pol_sft = 7; 2839 break; 2840 } 2841 2842 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2843 case SND_SOC_DAIFMT_CBP_CFP: 2844 rt5645->master[dai->id] = 1; 2845 break; 2846 case SND_SOC_DAIFMT_CBC_CFC: 2847 reg_val |= RT5645_I2S_MS_S; 2848 rt5645->master[dai->id] = 0; 2849 break; 2850 default: 2851 return -EINVAL; 2852 } 2853 2854 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2855 case SND_SOC_DAIFMT_NB_NF: 2856 break; 2857 case SND_SOC_DAIFMT_IB_NF: 2858 reg_val |= (1 << pol_sft); 2859 break; 2860 default: 2861 return -EINVAL; 2862 } 2863 2864 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2865 case SND_SOC_DAIFMT_I2S: 2866 break; 2867 case SND_SOC_DAIFMT_LEFT_J: 2868 reg_val |= RT5645_I2S_DF_LEFT; 2869 break; 2870 case SND_SOC_DAIFMT_DSP_A: 2871 reg_val |= RT5645_I2S_DF_PCM_A; 2872 break; 2873 case SND_SOC_DAIFMT_DSP_B: 2874 reg_val |= RT5645_I2S_DF_PCM_B; 2875 break; 2876 default: 2877 return -EINVAL; 2878 } 2879 switch (dai->id) { 2880 case RT5645_AIF1: 2881 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2882 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2883 RT5645_I2S_DF_MASK, reg_val); 2884 break; 2885 case RT5645_AIF2: 2886 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2887 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2888 RT5645_I2S_DF_MASK, reg_val); 2889 break; 2890 default: 2891 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2892 return -EINVAL; 2893 } 2894 return 0; 2895 } 2896 2897 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2898 int clk_id, unsigned int freq, int dir) 2899 { 2900 struct snd_soc_component *component = dai->component; 2901 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2902 unsigned int reg_val = 0; 2903 2904 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2905 return 0; 2906 2907 switch (clk_id) { 2908 case RT5645_SCLK_S_MCLK: 2909 reg_val |= RT5645_SCLK_SRC_MCLK; 2910 break; 2911 case RT5645_SCLK_S_PLL1: 2912 reg_val |= RT5645_SCLK_SRC_PLL1; 2913 break; 2914 case RT5645_SCLK_S_RCCLK: 2915 reg_val |= RT5645_SCLK_SRC_RCCLK; 2916 break; 2917 default: 2918 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2919 return -EINVAL; 2920 } 2921 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2922 RT5645_SCLK_SRC_MASK, reg_val); 2923 rt5645->sysclk = freq; 2924 rt5645->sysclk_src = clk_id; 2925 2926 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2927 2928 return 0; 2929 } 2930 2931 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2932 unsigned int freq_in, unsigned int freq_out) 2933 { 2934 struct snd_soc_component *component = dai->component; 2935 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2936 struct rl6231_pll_code pll_code; 2937 int ret; 2938 2939 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2940 freq_out == rt5645->pll_out) 2941 return 0; 2942 2943 if (!freq_in || !freq_out) { 2944 dev_dbg(component->dev, "PLL disabled\n"); 2945 2946 rt5645->pll_in = 0; 2947 rt5645->pll_out = 0; 2948 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2949 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2950 return 0; 2951 } 2952 2953 switch (source) { 2954 case RT5645_PLL1_S_MCLK: 2955 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2956 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2957 break; 2958 case RT5645_PLL1_S_BCLK1: 2959 case RT5645_PLL1_S_BCLK2: 2960 switch (dai->id) { 2961 case RT5645_AIF1: 2962 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2963 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2964 break; 2965 case RT5645_AIF2: 2966 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2967 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2968 break; 2969 default: 2970 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2971 return -EINVAL; 2972 } 2973 break; 2974 default: 2975 dev_err(component->dev, "Unknown PLL source %d\n", source); 2976 return -EINVAL; 2977 } 2978 2979 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2980 if (ret < 0) { 2981 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2982 return ret; 2983 } 2984 2985 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2986 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2987 pll_code.n_code, pll_code.k_code); 2988 2989 snd_soc_component_write(component, RT5645_PLL_CTRL1, 2990 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2991 snd_soc_component_write(component, RT5645_PLL_CTRL2, 2992 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) | 2993 (pll_code.m_bp << RT5645_PLL_M_BP_SFT)); 2994 2995 rt5645->pll_in = freq_in; 2996 rt5645->pll_out = freq_out; 2997 rt5645->pll_src = source; 2998 2999 return 0; 3000 } 3001 3002 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 3003 unsigned int rx_mask, int slots, int slot_width) 3004 { 3005 struct snd_soc_component *component = dai->component; 3006 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3007 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 3008 unsigned int mask, val = 0; 3009 3010 switch (rt5645->codec_type) { 3011 case CODEC_TYPE_RT5650: 3012 en_sft = 15; 3013 i_slot_sft = 10; 3014 o_slot_sft = 8; 3015 i_width_sht = 6; 3016 o_width_sht = 4; 3017 mask = 0x8ff0; 3018 break; 3019 default: 3020 en_sft = 14; 3021 i_slot_sft = o_slot_sft = 12; 3022 i_width_sht = o_width_sht = 10; 3023 mask = 0x7c00; 3024 break; 3025 } 3026 if (rx_mask || tx_mask) { 3027 val |= (1 << en_sft); 3028 if (rt5645->codec_type == CODEC_TYPE_RT5645) 3029 snd_soc_component_update_bits(component, RT5645_BASS_BACK, 3030 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 3031 } 3032 3033 switch (slots) { 3034 case 4: 3035 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 3036 break; 3037 case 6: 3038 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 3039 break; 3040 case 8: 3041 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 3042 break; 3043 case 2: 3044 default: 3045 break; 3046 } 3047 3048 switch (slot_width) { 3049 case 20: 3050 val |= (1 << i_width_sht) | (1 << o_width_sht); 3051 break; 3052 case 24: 3053 val |= (2 << i_width_sht) | (2 << o_width_sht); 3054 break; 3055 case 32: 3056 val |= (3 << i_width_sht) | (3 << o_width_sht); 3057 break; 3058 case 16: 3059 default: 3060 break; 3061 } 3062 3063 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); 3064 3065 return 0; 3066 } 3067 3068 static int rt5645_set_bias_level(struct snd_soc_component *component, 3069 enum snd_soc_bias_level level) 3070 { 3071 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3072 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3073 3074 switch (level) { 3075 case SND_SOC_BIAS_PREPARE: 3076 if (SND_SOC_BIAS_STANDBY == snd_soc_dapm_get_bias_level(dapm)) { 3077 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3078 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3079 RT5645_PWR_BG | RT5645_PWR_VREF2, 3080 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3081 RT5645_PWR_BG | RT5645_PWR_VREF2); 3082 mdelay(10); 3083 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3084 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3085 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3086 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3087 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3088 } 3089 break; 3090 3091 case SND_SOC_BIAS_STANDBY: 3092 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3093 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3094 RT5645_PWR_BG | RT5645_PWR_VREF2, 3095 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3096 RT5645_PWR_BG | RT5645_PWR_VREF2); 3097 mdelay(10); 3098 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3099 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3100 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3101 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 3102 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 3103 msleep(40); 3104 if (rt5645->en_button_func) 3105 queue_delayed_work(system_power_efficient_wq, 3106 &rt5645->jack_detect_work, 3107 msecs_to_jiffies(0)); 3108 } 3109 break; 3110 3111 case SND_SOC_BIAS_OFF: 3112 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100); 3113 if (!rt5645->en_button_func) 3114 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3115 RT5645_DIG_GATE_CTRL, 0); 3116 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3117 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3118 RT5645_PWR_BG | RT5645_PWR_VREF2 | 3119 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 3120 break; 3121 3122 default: 3123 break; 3124 } 3125 3126 return 0; 3127 } 3128 3129 static void rt5645_enable_push_button_irq(struct snd_soc_component *component, 3130 bool enable) 3131 { 3132 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3133 int ret; 3134 3135 if (enable) { 3136 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3137 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3138 snd_soc_dapm_sync(dapm); 3139 3140 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3141 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3142 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST); 3143 usleep_range(10000, 15000); 3144 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 3145 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK, 3146 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM); 3147 msleep(50); 3148 ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST); 3149 pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST, 3150 snd_soc_component_read(component, RT5645_INT_IRQ_ST)); 3151 snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret); 3152 ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3153 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3154 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3155 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret); 3156 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3157 snd_soc_component_update_bits(component, 3158 RT5645_INT_IRQ_ST, 0x8, 0x8); 3159 } else { 3160 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3161 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0); 3162 3163 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 3164 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 3165 snd_soc_dapm_sync(dapm); 3166 } 3167 } 3168 3169 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) 3170 { 3171 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3172 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3173 unsigned int val; 3174 3175 if (jack_insert) { 3176 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206); 3177 3178 /* for jack type detect */ 3179 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3180 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 3181 snd_soc_dapm_sync(dapm); 3182 if (!snd_soc_card_is_instantiated(component->card)) { 3183 /* Power up necessary bits for JD if dapm is 3184 not ready yet */ 3185 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 3186 RT5645_PWR_MB | RT5645_PWR_VREF2, 3187 RT5645_PWR_MB | RT5645_PWR_VREF2); 3188 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 3189 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 3190 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 3191 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 3192 } 3193 3194 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 3195 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3196 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3197 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3198 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3199 msleep(100); 3200 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3201 RT5645_CBJ_MN_JD, 0); 3202 3203 if (rt5645->gpiod_cbj_sleeve) 3204 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1); 3205 3206 msleep(600); 3207 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 3208 val &= 0x7; 3209 dev_dbg(component->dev, "val = %d\n", val); 3210 3211 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) { 3212 rt5645->jack_type = SND_JACK_HEADSET; 3213 if (rt5645->en_button_func) { 3214 rt5645_enable_push_button_irq(component, true); 3215 } 3216 } else { 3217 if (rt5645->en_button_func) 3218 rt5645_enable_push_button_irq(component, false); 3219 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3220 snd_soc_dapm_sync(dapm); 3221 rt5645->jack_type = SND_JACK_HEADPHONE; 3222 if (rt5645->gpiod_cbj_sleeve) 3223 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 3224 } 3225 if (rt5645->pdata.level_trigger_irq) 3226 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3227 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3228 3229 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); 3230 } else { /* jack out */ 3231 rt5645->jack_type = 0; 3232 3233 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 3234 RT5645_L_MUTE | RT5645_R_MUTE, 3235 RT5645_L_MUTE | RT5645_R_MUTE); 3236 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3237 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3238 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3239 RT5645_CBJ_BST1_EN, 0); 3240 3241 if (rt5645->en_button_func) 3242 rt5645_enable_push_button_irq(component, false); 3243 3244 if (rt5645->pdata.jd_mode == 0) 3245 snd_soc_dapm_disable_pin(dapm, "LDO2"); 3246 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3247 snd_soc_dapm_sync(dapm); 3248 if (rt5645->pdata.level_trigger_irq) 3249 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3250 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 3251 3252 if (rt5645->gpiod_cbj_sleeve) 3253 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 3254 } 3255 3256 return rt5645->jack_type; 3257 } 3258 3259 static int rt5645_button_detect(struct snd_soc_component *component) 3260 { 3261 int btn_type, val; 3262 3263 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3264 pr_debug("val=0x%x\n", val); 3265 btn_type = val & 0xfff0; 3266 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); 3267 3268 return btn_type; 3269 } 3270 3271 static irqreturn_t rt5645_irq(int irq, void *data); 3272 3273 int rt5645_set_jack_detect(struct snd_soc_component *component, 3274 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3275 struct snd_soc_jack *btn_jack) 3276 { 3277 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3278 3279 rt5645->hp_jack = hp_jack; 3280 rt5645->mic_jack = mic_jack; 3281 rt5645->btn_jack = btn_jack; 3282 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3283 rt5645->en_button_func = true; 3284 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3285 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3286 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3287 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3288 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, 3289 RT5645_HP_CB_MASK, RT5645_HP_CB_PU); 3290 } 3291 rt5645_irq(0, rt5645); 3292 3293 return 0; 3294 } 3295 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3296 3297 static int rt5645_component_set_jack(struct snd_soc_component *component, 3298 struct snd_soc_jack *hs_jack, void *data) 3299 { 3300 struct snd_soc_jack *mic_jack = NULL; 3301 struct snd_soc_jack *btn_jack = NULL; 3302 int type; 3303 3304 if (hs_jack) { 3305 type = *(int *)data; 3306 3307 if (type & SND_JACK_MICROPHONE) 3308 mic_jack = hs_jack; 3309 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3310 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 3311 btn_jack = hs_jack; 3312 } 3313 3314 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack); 3315 } 3316 3317 static void rt5645_jack_detect_work(struct work_struct *work) 3318 { 3319 struct rt5645_priv *rt5645 = 3320 container_of(work, struct rt5645_priv, jack_detect_work.work); 3321 int val, btn_type, gpio_state = 0, report = 0; 3322 3323 if (!rt5645->component) 3324 return; 3325 3326 mutex_lock(&rt5645->jd_mutex); 3327 3328 switch (rt5645->pdata.jd_mode) { 3329 case 0: /* Not using rt5645 JD */ 3330 if (rt5645->gpiod_hp_det) { 3331 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3332 if (rt5645->pdata.inv_hp_pol) 3333 gpio_state ^= 1; 3334 dev_dbg(rt5645->component->dev, "gpio_state = %d\n", 3335 gpio_state); 3336 report = rt5645_jack_detect(rt5645->component, gpio_state); 3337 } 3338 snd_soc_jack_report(rt5645->hp_jack, 3339 report, SND_JACK_HEADPHONE); 3340 snd_soc_jack_report(rt5645->mic_jack, 3341 report, SND_JACK_MICROPHONE); 3342 mutex_unlock(&rt5645->jd_mutex); 3343 return; 3344 case 4: 3345 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; 3346 break; 3347 default: /* read rt5645 jd1_1 status */ 3348 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; 3349 break; 3350 3351 } 3352 3353 if (!val && (rt5645->jack_type == 0)) { /* jack in */ 3354 report = rt5645_jack_detect(rt5645->component, 1); 3355 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) { 3356 /* for push button and jack out */ 3357 btn_type = 0; 3358 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { 3359 /* button pressed */ 3360 report = SND_JACK_HEADSET; 3361 btn_type = rt5645_button_detect(rt5645->component); 3362 /* rt5650 can report three kinds of button behavior, 3363 one click, double click and hold. However, 3364 currently we will report button pressed/released 3365 event. So all the three button behaviors are 3366 treated as button pressed. */ 3367 switch (btn_type) { 3368 case 0x8000: 3369 case 0x4000: 3370 case 0x2000: 3371 report |= SND_JACK_BTN_0; 3372 break; 3373 case 0x1000: 3374 case 0x0800: 3375 case 0x0400: 3376 report |= SND_JACK_BTN_1; 3377 break; 3378 case 0x0200: 3379 case 0x0100: 3380 case 0x0080: 3381 report |= SND_JACK_BTN_2; 3382 break; 3383 case 0x0040: 3384 case 0x0020: 3385 case 0x0010: 3386 report |= SND_JACK_BTN_3; 3387 break; 3388 case 0x0000: /* unpressed */ 3389 break; 3390 default: 3391 dev_err(rt5645->component->dev, 3392 "Unexpected button code 0x%04x\n", 3393 btn_type); 3394 break; 3395 } 3396 } 3397 if (btn_type == 0)/* button release */ 3398 report = rt5645->jack_type; 3399 else { 3400 mod_timer(&rt5645->btn_check_timer, 3401 msecs_to_jiffies(100)); 3402 } 3403 } else { 3404 /* jack out */ 3405 report = 0; 3406 snd_soc_component_update_bits(rt5645->component, 3407 RT5645_INT_IRQ_ST, 0x1, 0x0); 3408 rt5645_jack_detect(rt5645->component, 0); 3409 } 3410 3411 mutex_unlock(&rt5645->jd_mutex); 3412 3413 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3414 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3415 if (rt5645->en_button_func) 3416 snd_soc_jack_report(rt5645->btn_jack, 3417 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3418 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3419 } 3420 3421 static void rt5645_rcclock_work(struct work_struct *work) 3422 { 3423 struct rt5645_priv *rt5645 = 3424 container_of(work, struct rt5645_priv, rcclock_work.work); 3425 3426 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3427 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3428 } 3429 3430 static irqreturn_t rt5645_irq(int irq, void *data) 3431 { 3432 struct rt5645_priv *rt5645 = data; 3433 3434 queue_delayed_work(system_power_efficient_wq, 3435 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3436 3437 return IRQ_HANDLED; 3438 } 3439 3440 static void rt5645_btn_check_callback(struct timer_list *t) 3441 { 3442 struct rt5645_priv *rt5645 = timer_container_of(rt5645, t, 3443 btn_check_timer); 3444 3445 queue_delayed_work(system_power_efficient_wq, 3446 &rt5645->jack_detect_work, msecs_to_jiffies(5)); 3447 } 3448 3449 static int rt5645_probe(struct snd_soc_component *component) 3450 { 3451 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3452 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3453 3454 rt5645->component = component; 3455 3456 switch (rt5645->codec_type) { 3457 case CODEC_TYPE_RT5645: 3458 snd_soc_dapm_new_controls(dapm, 3459 rt5645_specific_dapm_widgets, 3460 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3461 snd_soc_dapm_add_routes(dapm, 3462 rt5645_specific_dapm_routes, 3463 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3464 if (rt5645->v_id < 3) { 3465 snd_soc_dapm_add_routes(dapm, 3466 rt5645_old_dapm_routes, 3467 ARRAY_SIZE(rt5645_old_dapm_routes)); 3468 } 3469 break; 3470 case CODEC_TYPE_RT5650: 3471 snd_soc_dapm_new_controls(dapm, 3472 rt5650_specific_dapm_widgets, 3473 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3474 snd_soc_dapm_add_routes(dapm, 3475 rt5650_specific_dapm_routes, 3476 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3477 break; 3478 } 3479 3480 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 3481 3482 /* for JD function */ 3483 if (rt5645->pdata.jd_mode) { 3484 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3485 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3486 snd_soc_dapm_sync(dapm); 3487 } 3488 3489 if (rt5645->pdata.long_name) 3490 component->card->long_name = rt5645->pdata.long_name; 3491 3492 rt5645->eq_param = devm_kcalloc(component->dev, 3493 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s), 3494 GFP_KERNEL); 3495 3496 if (!rt5645->eq_param) 3497 return -ENOMEM; 3498 3499 return 0; 3500 } 3501 3502 static void rt5645_remove(struct snd_soc_component *component) 3503 { 3504 rt5645_reset(component); 3505 } 3506 3507 #ifdef CONFIG_PM 3508 static int rt5645_suspend(struct snd_soc_component *component) 3509 { 3510 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3511 3512 regcache_cache_only(rt5645->regmap, true); 3513 regcache_mark_dirty(rt5645->regmap); 3514 3515 return 0; 3516 } 3517 3518 static int rt5645_resume(struct snd_soc_component *component) 3519 { 3520 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3521 3522 regcache_cache_only(rt5645->regmap, false); 3523 regcache_sync(rt5645->regmap); 3524 3525 return 0; 3526 } 3527 #else 3528 #define rt5645_suspend NULL 3529 #define rt5645_resume NULL 3530 #endif 3531 3532 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3533 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3534 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3535 3536 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3537 .hw_params = rt5645_hw_params, 3538 .set_fmt = rt5645_set_dai_fmt, 3539 .set_sysclk = rt5645_set_dai_sysclk, 3540 .set_tdm_slot = rt5645_set_tdm_slot, 3541 .set_pll = rt5645_set_dai_pll, 3542 }; 3543 3544 static struct snd_soc_dai_driver rt5645_dai[] = { 3545 { 3546 .name = "rt5645-aif1", 3547 .id = RT5645_AIF1, 3548 .playback = { 3549 .stream_name = "AIF1 Playback", 3550 .channels_min = 1, 3551 .channels_max = 2, 3552 .rates = RT5645_STEREO_RATES, 3553 .formats = RT5645_FORMATS, 3554 }, 3555 .capture = { 3556 .stream_name = "AIF1 Capture", 3557 .channels_min = 1, 3558 .channels_max = 4, 3559 .rates = RT5645_STEREO_RATES, 3560 .formats = RT5645_FORMATS, 3561 }, 3562 .ops = &rt5645_aif_dai_ops, 3563 }, 3564 { 3565 .name = "rt5645-aif2", 3566 .id = RT5645_AIF2, 3567 .playback = { 3568 .stream_name = "AIF2 Playback", 3569 .channels_min = 1, 3570 .channels_max = 2, 3571 .rates = RT5645_STEREO_RATES, 3572 .formats = RT5645_FORMATS, 3573 }, 3574 .capture = { 3575 .stream_name = "AIF2 Capture", 3576 .channels_min = 1, 3577 .channels_max = 2, 3578 .rates = RT5645_STEREO_RATES, 3579 .formats = RT5645_FORMATS, 3580 }, 3581 .ops = &rt5645_aif_dai_ops, 3582 }, 3583 }; 3584 3585 static const struct snd_soc_component_driver soc_component_dev_rt5645 = { 3586 .probe = rt5645_probe, 3587 .remove = rt5645_remove, 3588 .suspend = rt5645_suspend, 3589 .resume = rt5645_resume, 3590 .set_bias_level = rt5645_set_bias_level, 3591 .controls = rt5645_snd_controls, 3592 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3593 .dapm_widgets = rt5645_dapm_widgets, 3594 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3595 .dapm_routes = rt5645_dapm_routes, 3596 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3597 .set_jack = rt5645_component_set_jack, 3598 .use_pmdown_time = 1, 3599 .endianness = 1, 3600 }; 3601 3602 static const struct regmap_config rt5645_regmap = { 3603 .reg_bits = 8, 3604 .val_bits = 16, 3605 .use_single_read = true, 3606 .use_single_write = true, 3607 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3608 RT5645_PR_SPACING), 3609 .volatile_reg = rt5645_volatile_register, 3610 .readable_reg = rt5645_readable_register, 3611 3612 .cache_type = REGCACHE_MAPLE, 3613 .reg_defaults = rt5645_reg, 3614 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3615 .ranges = rt5645_ranges, 3616 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3617 }; 3618 3619 static const struct regmap_config rt5650_regmap = { 3620 .reg_bits = 8, 3621 .val_bits = 16, 3622 .use_single_read = true, 3623 .use_single_write = true, 3624 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3625 RT5645_PR_SPACING), 3626 .volatile_reg = rt5645_volatile_register, 3627 .readable_reg = rt5645_readable_register, 3628 3629 .cache_type = REGCACHE_MAPLE, 3630 .reg_defaults = rt5650_reg, 3631 .num_reg_defaults = ARRAY_SIZE(rt5650_reg), 3632 .ranges = rt5645_ranges, 3633 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3634 }; 3635 3636 static const struct regmap_config temp_regmap = { 3637 .name="nocache", 3638 .reg_bits = 8, 3639 .val_bits = 16, 3640 .use_single_read = true, 3641 .use_single_write = true, 3642 .max_register = RT5645_VENDOR_ID2 + 1, 3643 .cache_type = REGCACHE_NONE, 3644 }; 3645 3646 static const struct i2c_device_id rt5645_i2c_id[] = { 3647 { .name = "rt5645" }, 3648 { .name = "rt5650" }, 3649 { } 3650 }; 3651 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3652 3653 #ifdef CONFIG_OF 3654 static const struct of_device_id rt5645_of_match[] = { 3655 { .compatible = "realtek,rt5645", }, 3656 { .compatible = "realtek,rt5650", }, 3657 { } 3658 }; 3659 MODULE_DEVICE_TABLE(of, rt5645_of_match); 3660 #endif 3661 3662 #ifdef CONFIG_ACPI 3663 static const struct acpi_device_id rt5645_acpi_match[] = { 3664 { "10EC3270" }, 3665 { "10EC5640" }, 3666 { "10EC5645" }, 3667 { "10EC5648" }, 3668 { "10EC5650" }, 3669 { } 3670 }; 3671 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3672 #endif 3673 3674 static const struct rt5645_platform_data intel_braswell_platform_data = { 3675 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3676 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3677 .jd_mode = 3, 3678 }; 3679 3680 static const struct rt5645_platform_data buddy_platform_data = { 3681 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3682 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3683 .jd_mode = 4, 3684 .level_trigger_irq = true, 3685 }; 3686 3687 static const struct rt5645_platform_data gpd_win_platform_data = { 3688 .jd_mode = 3, 3689 .inv_jd1_1 = true, 3690 .mono_speaker = true, 3691 .long_name = "gpd-win-pocket-rt5645", 3692 /* The GPD pocket has a diff. mic, for the win this does not matter. */ 3693 .in2_diff = true, 3694 }; 3695 3696 static const struct rt5645_platform_data asus_t100ha_platform_data = { 3697 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3698 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3699 .jd_mode = 3, 3700 .inv_jd1_1 = true, 3701 }; 3702 3703 static const struct rt5645_platform_data asus_t101ha_platform_data = { 3704 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3705 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3706 .jd_mode = 3, 3707 }; 3708 3709 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { 3710 .jd_mode = 3, 3711 .in2_diff = true, 3712 }; 3713 3714 static const struct rt5645_platform_data jd_mode3_monospk_platform_data = { 3715 .jd_mode = 3, 3716 .mono_speaker = true, 3717 }; 3718 3719 static const struct rt5645_platform_data jd_mode3_inv_data = { 3720 .jd_mode = 3, 3721 .inv_jd1_1 = true, 3722 }; 3723 3724 static const struct rt5645_platform_data jd_mode3_platform_data = { 3725 .jd_mode = 3, 3726 }; 3727 3728 static const struct rt5645_platform_data lattepanda_board_platform_data = { 3729 .jd_mode = 2, 3730 .inv_jd1_1 = true 3731 }; 3732 3733 static const struct rt5645_platform_data kahlee_platform_data = { 3734 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3735 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3736 .jd_mode = 3, 3737 }; 3738 3739 static const struct rt5645_platform_data ecs_ef20_platform_data = { 3740 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3741 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3742 .inv_hp_pol = 1, 3743 }; 3744 3745 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; 3746 3747 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { 3748 { "hp-detect-gpios", &ef20_hp_detect, 1 }, 3749 { }, 3750 }; 3751 3752 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) 3753 { 3754 cht_rt5645_gpios = cht_rt5645_ef20_gpios; 3755 return 1; 3756 } 3757 3758 static const struct dmi_system_id dmi_platform_data[] = { 3759 { 3760 .ident = "Chrome Buddy", 3761 .matches = { 3762 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3763 }, 3764 .driver_data = (void *)&buddy_platform_data, 3765 }, 3766 { 3767 .ident = "Intel Strago", 3768 .matches = { 3769 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3770 }, 3771 .driver_data = (void *)&intel_braswell_platform_data, 3772 }, 3773 { 3774 .ident = "Google Chrome", 3775 .matches = { 3776 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 3777 }, 3778 .driver_data = (void *)&intel_braswell_platform_data, 3779 }, 3780 { 3781 .ident = "Google Setzer", 3782 .matches = { 3783 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 3784 }, 3785 .driver_data = (void *)&intel_braswell_platform_data, 3786 }, 3787 { 3788 .ident = "Microsoft Surface 3", 3789 .matches = { 3790 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 3791 }, 3792 .driver_data = (void *)&intel_braswell_platform_data, 3793 }, 3794 { 3795 /* 3796 * Match for the GPDwin which unfortunately uses somewhat 3797 * generic dmi strings, which is why we test for 4 strings. 3798 * Comparing against 23 other byt/cht boards, board_vendor 3799 * and board_name are unique to the GPDwin, where as only one 3800 * other board has the same board_serial and 3 others have 3801 * the same default product_name. Also the GPDwin is the 3802 * only device to have both board_ and product_name not set. 3803 */ 3804 .ident = "GPD Win / Pocket", 3805 .matches = { 3806 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3807 DMI_MATCH(DMI_BOARD_NAME, "Default string"), 3808 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"), 3809 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3810 }, 3811 .driver_data = (void *)&gpd_win_platform_data, 3812 }, 3813 { 3814 .ident = "ASUS T100HAN", 3815 .matches = { 3816 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3817 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"), 3818 }, 3819 .driver_data = (void *)&asus_t100ha_platform_data, 3820 }, 3821 { 3822 .ident = "ASUS T101HA", 3823 .matches = { 3824 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3825 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"), 3826 }, 3827 .driver_data = (void *)&asus_t101ha_platform_data, 3828 }, 3829 { 3830 .ident = "MINIX Z83-4", 3831 .matches = { 3832 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"), 3833 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"), 3834 }, 3835 .driver_data = (void *)&jd_mode3_platform_data, 3836 }, 3837 { 3838 .ident = "Teclast X80 Pro", 3839 .matches = { 3840 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"), 3841 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"), 3842 }, 3843 .driver_data = (void *)&jd_mode3_monospk_platform_data, 3844 }, 3845 { 3846 .ident = "Lenovo Ideapad Miix 310", 3847 .matches = { 3848 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3849 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), 3850 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), 3851 }, 3852 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, 3853 }, 3854 { 3855 .ident = "Lenovo Ideapad Miix 320", 3856 .matches = { 3857 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3858 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), 3859 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 3860 }, 3861 .driver_data = (void *)&intel_braswell_platform_data, 3862 }, 3863 { 3864 .ident = "LattePanda board", 3865 .matches = { 3866 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3867 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"), 3868 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"), 3869 /* 3870 * Above strings are too generic, LattePanda BIOS versions for 3871 * all 4 hw revisions are: 3872 * DF-BI-7-S70CR100-* 3873 * DF-BI-7-S70CR110-* 3874 * DF-BI-7-S70CR200-* 3875 * LP-BS-7-S70CR700-* 3876 * Do a partial match for S70CR to avoid false positive matches. 3877 */ 3878 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"), 3879 }, 3880 .driver_data = (void *)&lattepanda_board_platform_data, 3881 }, 3882 { 3883 .ident = "Chrome Kahlee", 3884 .matches = { 3885 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"), 3886 }, 3887 .driver_data = (void *)&kahlee_platform_data, 3888 }, 3889 { 3890 .ident = "Medion E1239T", 3891 .matches = { 3892 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"), 3893 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"), 3894 }, 3895 .driver_data = (void *)&intel_braswell_platform_data, 3896 }, 3897 { 3898 .ident = "EF20", 3899 .callback = cht_rt5645_ef20_quirk_cb, 3900 .matches = { 3901 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), 3902 }, 3903 .driver_data = (void *)&ecs_ef20_platform_data, 3904 }, 3905 { 3906 .ident = "Acer Switch V 10 (SW5-017)", 3907 .matches = { 3908 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"), 3909 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"), 3910 }, 3911 .driver_data = (void *)&intel_braswell_platform_data, 3912 }, 3913 { 3914 .ident = "Meegopad T08", 3915 .matches = { 3916 DMI_MATCH(DMI_SYS_VENDOR, "Default string"), 3917 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3918 DMI_MATCH(DMI_BOARD_NAME, "T3 MRD"), 3919 DMI_MATCH(DMI_BOARD_VERSION, "V1.1"), 3920 }, 3921 .driver_data = (void *)&jd_mode3_inv_data, 3922 }, 3923 { } 3924 }; 3925 3926 static bool rt5645_check_dp(struct device *dev) 3927 { 3928 if (device_property_present(dev, "realtek,in2-differential") || 3929 device_property_present(dev, "realtek,dmic1-data-pin") || 3930 device_property_present(dev, "realtek,dmic2-data-pin") || 3931 device_property_present(dev, "realtek,jd-mode")) 3932 return true; 3933 3934 return false; 3935 } 3936 3937 static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata) 3938 { 3939 pdata->in2_diff = device_property_read_bool(dev, "realtek,in2-differential"); 3940 device_property_read_u32(dev, "realtek,dmic1-data-pin", &pdata->dmic1_data_pin); 3941 device_property_read_u32(dev, "realtek,dmic2-data-pin", &pdata->dmic2_data_pin); 3942 device_property_read_u32(dev, "realtek,jd-mode", &pdata->jd_mode); 3943 } 3944 3945 static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata) 3946 { 3947 const struct dmi_system_id *dmi_data; 3948 3949 dmi_data = dmi_first_match(dmi_platform_data); 3950 if (dmi_data) { 3951 dev_info(codec_dev, "Detected %s platform\n", dmi_data->ident); 3952 *pdata = *((struct rt5645_platform_data *)dmi_data->driver_data); 3953 } else if (rt5645_check_dp(codec_dev)) { 3954 rt5645_parse_dt(codec_dev, pdata); 3955 } else { 3956 *pdata = jd_mode3_platform_data; 3957 } 3958 3959 if (quirk != -1) { 3960 pdata->in2_diff = QUIRK_IN2_DIFF(quirk); 3961 pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); 3962 pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk); 3963 pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk); 3964 pdata->jd_mode = QUIRK_JD_MODE(quirk); 3965 pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); 3966 pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); 3967 } 3968 } 3969 3970 const char *rt5645_components(struct device *codec_dev) 3971 { 3972 struct rt5645_platform_data pdata = { }; 3973 static char buf[32]; 3974 const char *mic; 3975 int spk = 2; 3976 3977 rt5645_get_pdata(codec_dev, &pdata); 3978 3979 if (pdata.mono_speaker) 3980 spk = 1; 3981 3982 if (pdata.dmic1_data_pin && pdata.dmic2_data_pin) 3983 mic = "dmics12"; 3984 else if (pdata.dmic1_data_pin) 3985 mic = "dmic1"; 3986 else if (pdata.dmic2_data_pin) 3987 mic = "dmic2"; 3988 else 3989 mic = "in2"; 3990 3991 snprintf(buf, sizeof(buf), "cfg-spk:%d cfg-mic:%s", spk, mic); 3992 3993 return buf; 3994 } 3995 EXPORT_SYMBOL_GPL(rt5645_components); 3996 3997 static int rt5645_i2c_probe(struct i2c_client *i2c) 3998 { 3999 struct rt5645_priv *rt5645; 4000 int ret, i; 4001 unsigned int val; 4002 struct regmap *regmap; 4003 4004 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 4005 GFP_KERNEL); 4006 if (rt5645 == NULL) 4007 return -ENOMEM; 4008 4009 rt5645->i2c = i2c; 4010 i2c_set_clientdata(i2c, rt5645); 4011 rt5645_get_pdata(&i2c->dev, &rt5645->pdata); 4012 4013 if (has_acpi_companion(&i2c->dev)) { 4014 if (cht_rt5645_gpios) { 4015 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios)) 4016 dev_dbg(&i2c->dev, "Failed to add driver gpios\n"); 4017 } 4018 4019 /* The ALC3270 package has the headset-mic pin not-connected */ 4020 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL)) 4021 rt5645->pdata.no_headset_mic = true; 4022 } 4023 4024 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 4025 GPIOD_IN); 4026 4027 if (IS_ERR(rt5645->gpiod_hp_det)) { 4028 dev_info(&i2c->dev, "failed to initialize gpiod\n"); 4029 ret = PTR_ERR(rt5645->gpiod_hp_det); 4030 /* 4031 * Continue if optional gpiod is missing, bail for all other 4032 * errors, including -EPROBE_DEFER 4033 */ 4034 if (ret != -ENOENT) 4035 return ret; 4036 } 4037 4038 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve", 4039 GPIOD_OUT_LOW); 4040 4041 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) { 4042 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve); 4043 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret); 4044 if (ret != -ENOENT) 4045 return ret; 4046 } 4047 4048 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 4049 rt5645->supplies[i].supply = rt5645_supply_names[i]; 4050 4051 ret = devm_regulator_bulk_get(&i2c->dev, 4052 ARRAY_SIZE(rt5645->supplies), 4053 rt5645->supplies); 4054 if (ret) { 4055 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 4056 return ret; 4057 } 4058 4059 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 4060 rt5645->supplies); 4061 if (ret) { 4062 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 4063 return ret; 4064 } 4065 4066 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 4067 if (IS_ERR(regmap)) { 4068 ret = PTR_ERR(regmap); 4069 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 4070 ret); 4071 goto err_enable; 4072 } 4073 4074 /* 4075 * Read after 400msec, as it is the interval required between 4076 * read and power On. 4077 */ 4078 msleep(TIME_TO_POWER_MS); 4079 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val); 4080 if (ret < 0) { 4081 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret); 4082 goto err_enable; 4083 } 4084 4085 switch (val) { 4086 case RT5645_DEVICE_ID: 4087 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 4088 rt5645->codec_type = CODEC_TYPE_RT5645; 4089 break; 4090 case RT5650_DEVICE_ID: 4091 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); 4092 rt5645->codec_type = CODEC_TYPE_RT5650; 4093 break; 4094 default: 4095 dev_err(&i2c->dev, 4096 "Device with ID register %#x is not rt5645 or rt5650\n", 4097 val); 4098 ret = -ENODEV; 4099 goto err_enable; 4100 } 4101 4102 if (IS_ERR(rt5645->regmap)) { 4103 ret = PTR_ERR(rt5645->regmap); 4104 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4105 ret); 4106 goto err_enable; 4107 } 4108 4109 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4110 4111 regmap_read(regmap, RT5645_VENDOR_ID, &val); 4112 rt5645->v_id = val & 0xff; 4113 4114 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); 4115 4116 ret = regmap_multi_reg_write(rt5645->regmap, init_list, 4117 ARRAY_SIZE(init_list)); 4118 if (ret != 0) 4119 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4120 4121 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 4122 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list, 4123 ARRAY_SIZE(rt5650_init_list)); 4124 if (ret != 0) 4125 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 4126 ret); 4127 } 4128 4129 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0); 4130 4131 if (rt5645->pdata.in2_diff) 4132 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 4133 RT5645_IN_DF2, RT5645_IN_DF2); 4134 4135 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 4136 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4137 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 4138 } 4139 switch (rt5645->pdata.dmic1_data_pin) { 4140 case RT5645_DMIC_DATA_IN2N: 4141 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4142 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 4143 break; 4144 4145 case RT5645_DMIC_DATA_GPIO5: 4146 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4147 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 4148 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4149 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 4150 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4151 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 4152 break; 4153 4154 case RT5645_DMIC_DATA_GPIO11: 4155 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4156 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 4157 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4158 RT5645_GP11_PIN_MASK, 4159 RT5645_GP11_PIN_DMIC1_SDA); 4160 break; 4161 4162 default: 4163 break; 4164 } 4165 4166 switch (rt5645->pdata.dmic2_data_pin) { 4167 case RT5645_DMIC_DATA_IN2P: 4168 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4169 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 4170 break; 4171 4172 case RT5645_DMIC_DATA_GPIO6: 4173 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4174 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 4175 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4176 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 4177 break; 4178 4179 case RT5645_DMIC_DATA_GPIO10: 4180 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4181 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 4182 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4183 RT5645_GP10_PIN_MASK, 4184 RT5645_GP10_PIN_DMIC2_SDA); 4185 break; 4186 4187 case RT5645_DMIC_DATA_GPIO12: 4188 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4189 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 4190 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4191 RT5645_GP12_PIN_MASK, 4192 RT5645_GP12_PIN_DMIC2_SDA); 4193 break; 4194 4195 default: 4196 break; 4197 } 4198 4199 if (rt5645->pdata.jd_mode) { 4200 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4201 RT5645_IRQ_CLK_GATE_CTRL, 4202 RT5645_IRQ_CLK_GATE_CTRL); 4203 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4204 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 4205 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4206 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 4207 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4208 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 4209 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 4210 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 4211 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4212 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 4213 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4214 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 4215 switch (rt5645->pdata.jd_mode) { 4216 case 1: 4217 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4218 RT5645_JD1_MODE_MASK, 4219 RT5645_JD1_MODE_0); 4220 break; 4221 case 2: 4222 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4223 RT5645_JD1_MODE_MASK, 4224 RT5645_JD1_MODE_1); 4225 break; 4226 case 3: 4227 case 4: 4228 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4229 RT5645_JD1_MODE_MASK, 4230 RT5645_JD1_MODE_2); 4231 break; 4232 default: 4233 break; 4234 } 4235 if (rt5645->pdata.inv_jd1_1) { 4236 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4237 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4238 } 4239 } 4240 4241 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1, 4242 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); 4243 4244 if (rt5645->pdata.level_trigger_irq) { 4245 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4246 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4247 } 4248 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); 4249 4250 mutex_init(&rt5645->jd_mutex); 4251 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 4252 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 4253 4254 if (rt5645->i2c->irq) { 4255 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 4256 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4257 | IRQF_ONESHOT, "rt5645", rt5645); 4258 if (ret) { 4259 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 4260 goto err_enable; 4261 } 4262 } 4263 4264 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645, 4265 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 4266 if (ret) 4267 goto err_irq; 4268 4269 return 0; 4270 4271 err_irq: 4272 if (rt5645->i2c->irq) 4273 free_irq(rt5645->i2c->irq, rt5645); 4274 err_enable: 4275 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4276 return ret; 4277 } 4278 4279 static void rt5645_i2c_remove(struct i2c_client *i2c) 4280 { 4281 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4282 4283 if (i2c->irq) 4284 free_irq(i2c->irq, rt5645); 4285 4286 /* 4287 * Since the rt5645_btn_check_callback() can queue jack_detect_work, 4288 * the timer need to be delted first 4289 */ 4290 timer_delete_sync(&rt5645->btn_check_timer); 4291 4292 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4293 cancel_delayed_work_sync(&rt5645->rcclock_work); 4294 4295 if (rt5645->gpiod_cbj_sleeve) 4296 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 4297 4298 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4299 } 4300 4301 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 4302 { 4303 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4304 4305 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4306 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 4307 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 4308 RT5645_CBJ_MN_JD); 4309 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 4310 0); 4311 msleep(20); 4312 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4313 4314 if (rt5645->gpiod_cbj_sleeve) 4315 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0); 4316 } 4317 4318 static int rt5645_sys_suspend(struct device *dev) 4319 { 4320 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4321 4322 timer_delete_sync(&rt5645->btn_check_timer); 4323 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4324 cancel_delayed_work_sync(&rt5645->rcclock_work); 4325 4326 regcache_cache_only(rt5645->regmap, true); 4327 regcache_mark_dirty(rt5645->regmap); 4328 return 0; 4329 } 4330 4331 static int rt5645_sys_resume(struct device *dev) 4332 { 4333 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4334 4335 regcache_cache_only(rt5645->regmap, false); 4336 regcache_sync(rt5645->regmap); 4337 4338 if (rt5645->hp_jack) { 4339 rt5645->jack_type = 0; 4340 rt5645_jack_detect_work(&rt5645->jack_detect_work.work); 4341 } 4342 return 0; 4343 } 4344 4345 static const struct dev_pm_ops rt5645_pm = { 4346 SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume) 4347 }; 4348 4349 static struct i2c_driver rt5645_i2c_driver = { 4350 .driver = { 4351 .name = "rt5645", 4352 .of_match_table = of_match_ptr(rt5645_of_match), 4353 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 4354 .pm = pm_ptr(&rt5645_pm), 4355 }, 4356 .probe = rt5645_i2c_probe, 4357 .remove = rt5645_i2c_remove, 4358 .shutdown = rt5645_i2c_shutdown, 4359 .id_table = rt5645_i2c_id, 4360 }; 4361 module_i2c_driver(rt5645_i2c_driver); 4362 4363 MODULE_DESCRIPTION("ASoC RT5645 driver"); 4364 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4365 MODULE_LICENSE("GPL v2"); 4366