1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver
4 //
5 // Copyright(c) 2024 Realtek Semiconductor Corp.
6 //
7 //
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/dmi.h>
15 #include <linux/firmware.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <sound/initval.h>
21 #include <sound/tlv.h>
22 #include <sound/sdw.h>
23 #include "rt1320-sdw.h"
24 #include "rt-sdw-common.h"
25
26 /*
27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization.
28 * It might include vendor-specific or SDCA control registers.
29 */
30 static const struct reg_sequence rt1320_blind_write[] = {
31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x10 },
36 { 0xc5c4, 0x12 },
37 { 0xc5c8, 0x03 },
38 { 0xc5d8, 0x0a },
39 { 0xc5f7, 0x22 },
40 { 0xc5f6, 0x22 },
41 { 0xc5d0, 0x0f },
42 { 0xc5d1, 0x89 },
43 { 0xc057, 0x51 },
44 { 0xc054, 0x35 },
45 { 0xc053, 0x55 },
46 { 0xc052, 0x55 },
47 { 0xc051, 0x13 },
48 { 0xc050, 0x15 },
49 { 0xc060, 0x77 },
50 { 0xc061, 0x55 },
51 { 0xc063, 0x55 },
52 { 0xc065, 0xa5 },
53 { 0xc06b, 0x0a },
54 { 0xca05, 0xd6 },
55 { 0xca25, 0xd6 },
56 { 0xcd00, 0x05 },
57 { 0xc604, 0x40 },
58 { 0xc609, 0x40 },
59 { 0xc046, 0xff },
60 { 0xc045, 0xff },
61 { 0xc044, 0xff },
62 { 0xc043, 0xff },
63 { 0xc042, 0xff },
64 { 0xc041, 0xff },
65 { 0xc040, 0xff },
66 { 0xcc10, 0x01 },
67 { 0xc700, 0xf0 },
68 { 0xc701, 0x13 },
69 { 0xc901, 0x04 },
70 { 0xc900, 0x73 },
71 { 0xde03, 0x05 },
72 { 0xdd0b, 0x0d },
73 { 0xdd0a, 0xff },
74 { 0xdd09, 0x0d },
75 { 0xdd08, 0xff },
76 { 0xc570, 0x08 },
77 { 0xe803, 0xbe },
78 { 0xc003, 0xc0 },
79 { 0xc081, 0xfe },
80 { 0xce31, 0x0d },
81 { 0xce30, 0xae },
82 { 0xce37, 0x0b },
83 { 0xce36, 0xd2 },
84 { 0xce39, 0x04 },
85 { 0xce38, 0x80 },
86 { 0xce3f, 0x00 },
87 { 0xce3e, 0x00 },
88 { 0xd470, 0x8b },
89 { 0xd471, 0x18 },
90 { 0xc019, 0x10 },
91 { 0xd487, 0x3f },
92 { 0xd486, 0xc3 },
93 { 0x3fc2bfc7, 0x00 },
94 { 0x3fc2bfc6, 0x00 },
95 { 0x3fc2bfc5, 0x00 },
96 { 0x3fc2bfc4, 0x01 },
97 { 0x0000d486, 0x43 },
98 { 0x1000db00, 0x02 },
99 { 0x1000db01, 0x00 },
100 { 0x1000db02, 0x11 },
101 { 0x1000db03, 0x00 },
102 { 0x1000db04, 0x00 },
103 { 0x1000db05, 0x82 },
104 { 0x1000db06, 0x04 },
105 { 0x1000db07, 0xf1 },
106 { 0x1000db08, 0x00 },
107 { 0x1000db09, 0x00 },
108 { 0x1000db0a, 0x40 },
109 { 0x0000d540, 0x01 },
110 { 0xd172, 0x2a },
111 { 0xc5d6, 0x01 },
112 { 0xd478, 0xff },
113 };
114
115 static const struct reg_sequence rt1320_vc_blind_write[] = {
116 { 0xc003, 0xe0 },
117 { 0xe80a, 0x01 },
118 { 0xc5c3, 0xf2 },
119 { 0xc5c8, 0x03 },
120 { 0xc057, 0x51 },
121 { 0xc054, 0x35 },
122 { 0xca05, 0xd6 },
123 { 0xca07, 0x07 },
124 { 0xca25, 0xd6 },
125 { 0xca27, 0x07 },
126 { 0xc604, 0x40 },
127 { 0xc609, 0x40 },
128 { 0xc046, 0xff },
129 { 0xc045, 0xff },
130 { 0xc044, 0xff },
131 { 0xc043, 0xff },
132 { 0xc042, 0xff },
133 { 0xc041, 0x7f },
134 { 0xc040, 0xff },
135 { 0xcc10, 0x01 },
136 { 0xc700, 0xf0 },
137 { 0xc701, 0x13 },
138 { 0xc901, 0x04 },
139 { 0xc900, 0x73 },
140 { 0xde03, 0x05 },
141 { 0xdd0b, 0x0d },
142 { 0xdd0a, 0xff },
143 { 0xdd09, 0x0d },
144 { 0xdd08, 0xff },
145 { 0xc570, 0x08 },
146 { 0xc086, 0x02 },
147 { 0xc085, 0x7f },
148 { 0xc084, 0x00 },
149 { 0xc081, 0xfe },
150 { 0xf084, 0x0f },
151 { 0xf083, 0xff },
152 { 0xf082, 0xff },
153 { 0xf081, 0xff },
154 { 0xf080, 0xff },
155 { 0xe801, 0x01 },
156 { 0xe802, 0xf8 },
157 { 0xe803, 0xbe },
158 { 0xc003, 0xc0 },
159 { 0xd470, 0xec },
160 { 0xd471, 0x3a },
161 { 0xd474, 0x11 },
162 { 0xd475, 0x32 },
163 { 0xd478, 0xff },
164 { 0xd479, 0x20 },
165 { 0xd47a, 0x10 },
166 { 0xd47c, 0xff },
167 { 0xc019, 0x10 },
168 { 0xd487, 0x0b },
169 { 0xd487, 0x3b },
170 { 0xd486, 0xc3 },
171 { 0xc598, 0x04 },
172 { 0xdb03, 0xf0 },
173 { 0xdb09, 0x00 },
174 { 0xdb08, 0x7a },
175 { 0xdb19, 0x02 },
176 { 0xdb07, 0x5a },
177 { 0xdb05, 0x45 },
178 { 0xd500, 0x00 },
179 { 0xd500, 0x17 },
180 { 0xd600, 0x01 },
181 { 0xd601, 0x02 },
182 { 0xd602, 0x03 },
183 { 0xd603, 0x04 },
184 { 0xd64c, 0x03 },
185 { 0xd64d, 0x03 },
186 { 0xd64e, 0x03 },
187 { 0xd64f, 0x03 },
188 { 0xd650, 0x03 },
189 { 0xd651, 0x03 },
190 { 0xd652, 0x03 },
191 { 0xd610, 0x01 },
192 { 0xd608, 0x03 },
193 { 0xd609, 0x00 },
194 { 0x3fc2bf83, 0x00 },
195 { 0x3fc2bf82, 0x00 },
196 { 0x3fc2bf81, 0x00 },
197 { 0x3fc2bf80, 0x00 },
198 { 0x3fc2bfc7, 0x00 },
199 { 0x3fc2bfc6, 0x00 },
200 { 0x3fc2bfc5, 0x00 },
201 { 0x3fc2bfc4, 0x00 },
202 { 0x3fc2bfc3, 0x00 },
203 { 0x3fc2bfc2, 0x00 },
204 { 0x3fc2bfc1, 0x00 },
205 { 0x3fc2bfc0, 0x07 },
206 { 0x1000cc46, 0x00 },
207 { 0x0000d486, 0x43 },
208 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 },
209 { 0x1000db00, 0x07 },
210 { 0x1000db01, 0x00 },
211 { 0x1000db02, 0x11 },
212 { 0x1000db03, 0x00 },
213 { 0x1000db04, 0x00 },
214 { 0x1000db05, 0x82 },
215 { 0x1000db06, 0x04 },
216 { 0x1000db07, 0xf1 },
217 { 0x1000db08, 0x00 },
218 { 0x1000db09, 0x00 },
219 { 0x1000db0a, 0x40 },
220 { 0x1000db0b, 0x02 },
221 { 0x1000db0c, 0xf2 },
222 { 0x1000db0d, 0x00 },
223 { 0x1000db0e, 0x00 },
224 { 0x1000db0f, 0xe0 },
225 { 0x1000db10, 0x00 },
226 { 0x1000db11, 0x10 },
227 { 0x1000db12, 0x00 },
228 { 0x1000db13, 0x00 },
229 { 0x1000db14, 0x45 },
230 { 0x1000db15, 0x0d },
231 { 0x1000db16, 0x01 },
232 { 0x1000db17, 0x00 },
233 { 0x1000db18, 0x00 },
234 { 0x1000db19, 0xbf },
235 { 0x1000db1a, 0x13 },
236 { 0x1000db1b, 0x09 },
237 { 0x1000db1c, 0x00 },
238 { 0x1000db1d, 0x00 },
239 { 0x1000db1e, 0x00 },
240 { 0x1000db1f, 0x12 },
241 { 0x1000db20, 0x09 },
242 { 0x1000db21, 0x00 },
243 { 0x1000db22, 0x00 },
244 { 0x1000db23, 0x00 },
245 { 0x0000d540, 0x21 },
246 { 0xc01b, 0xfc },
247 { 0xc5d1, 0x89 },
248 { 0xc5d8, 0x0a },
249 { 0xc5f7, 0x22 },
250 { 0xc5f6, 0x22 },
251 { 0xc065, 0xa5 },
252 { 0xc06b, 0x0a },
253 { 0xd172, 0x2a },
254 { 0xc5d6, 0x01 },
255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
256 };
257
258 static const struct reg_sequence rt1321_blind_write[] = {
259 { 0x0000c003, 0xf0 },
260 { 0x0000c01b, 0xfc },
261 { 0x0000c5c3, 0xf2 },
262 { 0x0000c5c2, 0x00 },
263 { 0x0000c5c1, 0x10 },
264 { 0x0000c5c0, 0x04 },
265 { 0x0000c5c7, 0x03 },
266 { 0x0000c5c6, 0x10 },
267 { 0x0000c526, 0x47 },
268 { 0x0000c5c4, 0x12 },
269 { 0x0000c5c5, 0x60 },
270 { 0x0000c520, 0x10 },
271 { 0x0000c521, 0x32 },
272 { 0x0000c5c7, 0x00 },
273 { 0x0000c5c8, 0x03 },
274 { 0x0000c5d3, 0x08 },
275 { 0x0000c5d2, 0x0a },
276 { 0x0000c5d1, 0x49 },
277 { 0x0000c5d0, 0x0f },
278 { 0x0000c580, 0x10 },
279 { 0x0000c581, 0x32 },
280 { 0x0000c582, 0x01 },
281 { 0x0000cb00, 0x03 },
282 { 0x0000cb02, 0x52 },
283 { 0x0000cb04, 0x80 },
284 { 0x0000cb0b, 0x01 },
285 { 0x0000c682, 0x60 },
286 { 0x0000c019, 0x10 },
287 { 0x0000c5f0, 0x01 },
288 { 0x0000c5f7, 0x22 },
289 { 0x0000c5f6, 0x22 },
290 { 0x0000c057, 0x51 },
291 { 0x0000c054, 0x55 },
292 { 0x0000c053, 0x55 },
293 { 0x0000c052, 0x55 },
294 { 0x0000c051, 0x01 },
295 { 0x0000c050, 0x15 },
296 { 0x0000c060, 0x99 },
297 { 0x0000c030, 0x55 },
298 { 0x0000c061, 0x55 },
299 { 0x0000c063, 0x55 },
300 { 0x0000c065, 0xa5 },
301 { 0x0000c06b, 0x0a },
302 { 0x0000ca05, 0xd6 },
303 { 0x0000ca07, 0x07 },
304 { 0x0000ca25, 0xd6 },
305 { 0x0000ca27, 0x07 },
306 { 0x0000cd00, 0x05 },
307 { 0x0000c604, 0x40 },
308 { 0x0000c609, 0x40 },
309 { 0x0000c046, 0xf7 },
310 { 0x0000c045, 0xff },
311 { 0x0000c044, 0xff },
312 { 0x0000c043, 0xff },
313 { 0x0000c042, 0xff },
314 { 0x0000c041, 0xff },
315 { 0x0000c040, 0xff },
316 { 0x0000c049, 0xff },
317 { 0x0000c028, 0x3f },
318 { 0x0000c020, 0x3f },
319 { 0x0000c032, 0x13 },
320 { 0x0000c033, 0x01 },
321 { 0x0000cc10, 0x01 },
322 { 0x0000dc20, 0x03 },
323 { 0x0000de03, 0x05 },
324 { 0x0000dc00, 0x00 },
325 { 0x0000c700, 0xf0 },
326 { 0x0000c701, 0x13 },
327 { 0x0000c900, 0xc3 },
328 { 0x0000c570, 0x08 },
329 { 0x0000c086, 0x02 },
330 { 0x0000c085, 0x7f },
331 { 0x0000c084, 0x00 },
332 { 0x0000c081, 0xff },
333 { 0x0000f084, 0x0f },
334 { 0x0000f083, 0xff },
335 { 0x0000f082, 0xff },
336 { 0x0000f081, 0xff },
337 { 0x0000f080, 0xff },
338 { 0x20003003, 0x3f },
339 { 0x20005818, 0x81 },
340 { 0x20009018, 0x81 },
341 { 0x2000301c, 0x81 },
342 { 0x0000c003, 0xc0 },
343 { 0x0000c047, 0x80 },
344 { 0x0000d541, 0x80 },
345 { 0x0000d487, 0x0b },
346 { 0x0000d487, 0x3b },
347 { 0x0000d486, 0xc3 },
348 { 0x0000d470, 0x89 },
349 { 0x0000d471, 0x3a },
350 { 0x0000d472, 0x1d },
351 { 0x0000d478, 0xff },
352 { 0x0000d479, 0x20 },
353 { 0x0000d47a, 0x10 },
354 { 0x0000d73c, 0xb7 },
355 { 0x0000d73d, 0xd7 },
356 { 0x0000d73e, 0x00 },
357 { 0x0000d73f, 0x10 },
358 { 0x1000cd56, 0x00 },
359 { 0x3fc2dfc3, 0x00 },
360 { 0x3fc2dfc2, 0x00 },
361 { 0x3fc2dfc1, 0x00 },
362 { 0x3fc2dfc0, 0x07 },
363 { 0x3fc2dfc7, 0x00 },
364 { 0x3fc2dfc6, 0x00 },
365 { 0x3fc2dfc5, 0x00 },
366 { 0x3fc2dfc4, 0x01 },
367 { 0x3fc2df83, 0x00 },
368 { 0x3fc2df82, 0x00 },
369 { 0x3fc2df81, 0x00 },
370 { 0x3fc2df80, 0x00 },
371 { 0x0000d541, 0x40 },
372 { 0x0000d486, 0x43 },
373 { 0x1000db00, 0x03 },
374 { 0x1000db01, 0x00 },
375 { 0x1000db02, 0x10 },
376 { 0x1000db03, 0x00 },
377 { 0x1000db04, 0x00 },
378 { 0x1000db05, 0x45 },
379 { 0x1000db06, 0x12 },
380 { 0x1000db07, 0x09 },
381 { 0x1000db08, 0x00 },
382 { 0x1000db09, 0x00 },
383 { 0x1000db0a, 0x00 },
384 { 0x1000db0b, 0x13 },
385 { 0x1000db0c, 0x09 },
386 { 0x1000db0d, 0x00 },
387 { 0x1000db0e, 0x00 },
388 { 0x1000db0f, 0x00 },
389 { 0x0000d540, 0x21 },
390 { 0x41000189, 0x00 },
391 { 0x4100018a, 0x00 },
392 { 0x41001988, 0x00 },
393 { 0x41081400, 0x09 },
394 { 0x40801508, 0x03 },
395 { 0x40801588, 0x03 },
396 { 0x40801809, 0x00 },
397 { 0x4080180a, 0x00 },
398 { 0x4080180b, 0x00 },
399 { 0x4080180c, 0x00 },
400 { 0x40801b09, 0x00 },
401 { 0x40801b0a, 0x00 },
402 { 0x40801b0b, 0x00 },
403 { 0x40801b0c, 0x00 },
404 { 0x0000d714, 0x17 },
405 { 0x20009012, 0x00 },
406 { 0x0000dd0b, 0x0d },
407 { 0x0000dd0a, 0xff },
408 { 0x0000dd09, 0x0d },
409 { 0x0000dd08, 0xff },
410 { 0x0000d172, 0x2a },
411 { 0x41001988, 0x03 },
412 };
413
414 static const struct reg_default rt1320_reg_defaults[] = {
415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
421 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
422 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
428 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
429 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
430 };
431
432 static const struct reg_default rt1320_mbq_defaults[] = {
433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
435 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
436 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
437 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
438 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
439 };
440
rt1320_readable_register(struct device * dev,unsigned int reg)441 static bool rt1320_readable_register(struct device *dev, unsigned int reg)
442 {
443 switch (reg) {
444 case 0xc000 ... 0xc086:
445 case 0xc400 ... 0xc409:
446 case 0xc480 ... 0xc48f:
447 case 0xc4c0 ... 0xc4c4:
448 case 0xc4e0 ... 0xc4e7:
449 case 0xc500:
450 case 0xc560 ... 0xc56b:
451 case 0xc570:
452 case 0xc580 ... 0xc59a:
453 case 0xc5b0 ... 0xc60f:
454 case 0xc640 ... 0xc64f:
455 case 0xc670:
456 case 0xc680 ... 0xc683:
457 case 0xc700 ... 0xc76f:
458 case 0xc800 ... 0xc801:
459 case 0xc820:
460 case 0xc900 ... 0xc901:
461 case 0xc920 ... 0xc921:
462 case 0xca00 ... 0xca07:
463 case 0xca20 ... 0xca27:
464 case 0xca40 ... 0xca4b:
465 case 0xca60 ... 0xca68:
466 case 0xca80 ... 0xca88:
467 case 0xcb00 ... 0xcb0c:
468 case 0xcc00 ... 0xcc12:
469 case 0xcc80 ... 0xcc81:
470 case 0xcd00:
471 case 0xcd80 ... 0xcd82:
472 case 0xce00 ... 0xce4d:
473 case 0xcf00 ... 0xcf25:
474 case 0xd000 ... 0xd0ff:
475 case 0xd100 ... 0xd1ff:
476 case 0xd200 ... 0xd2ff:
477 case 0xd300 ... 0xd3ff:
478 case 0xd400 ... 0xd403:
479 case 0xd410 ... 0xd417:
480 case 0xd470 ... 0xd497:
481 case 0xd4dc ... 0xd50f:
482 case 0xd520 ... 0xd543:
483 case 0xd560 ... 0xd5ef:
484 case 0xd600 ... 0xd663:
485 case 0xda00 ... 0xda6e:
486 case 0xda80 ... 0xda9e:
487 case 0xdb00 ... 0xdb7f:
488 case 0xdc00:
489 case 0xdc20 ... 0xdc21:
490 case 0xdd00 ... 0xdd17:
491 case 0xde00 ... 0xde09:
492 case 0xdf00 ... 0xdf1b:
493 case 0xe000 ... 0xe847:
494 case 0xf01e:
495 case 0xf717 ... 0xf719:
496 case 0xf720 ... 0xf723:
497 case 0x1000cd91 ... 0x1000cd96:
498 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER:
499 case 0x1000f008:
500 case 0x1000f021:
501 case 0x2000300f:
502 case 0x2000301c:
503 case 0x2000900f:
504 case 0x20009018:
505 case 0x3fc29d80 ... 0x3fc29d83:
506 case 0x3fe2e000 ... 0x3fe2e003:
507 case 0x3fc2ab80 ... 0x3fc2abd4:
508 case 0x3fc2bfc0 ... 0x3fc2bfc8:
509 case 0x3fc2d300 ... 0x3fc2d354:
510 case 0x3fc2dfc0 ... 0x3fc2dfc8:
511 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
513 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01):
514 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02):
515 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01):
516 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02):
517 /* 0x40880900/0x40880980 */
518 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
519 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
520 /* 0x40881500 */
521 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
522 /* 0x41000189/0x4100018a */
523 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
525 /* 0x41001388 */
526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
527 /* 0x41001988 */
528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
529 /* 0x41080000 */
530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
531 /* 0x41080200 */
532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
533 /* 0x41080900 */
534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
535 /* 0x41080980 */
536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
537 /* 0x41081080 */
538 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
539 /* 0x41081480/0x41081488 */
540 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
541 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
542 /* 0x41081980 */
543 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
544 return true;
545 default:
546 return false;
547 }
548 }
549
rt1320_volatile_register(struct device * dev,unsigned int reg)550 static bool rt1320_volatile_register(struct device *dev, unsigned int reg)
551 {
552 switch (reg) {
553 case 0xc000:
554 case 0xc003:
555 case 0xc081:
556 case 0xc402 ... 0xc406:
557 case 0xc48c ... 0xc48f:
558 case 0xc560:
559 case 0xc5b5 ... 0xc5b7:
560 case 0xc5fc ... 0xc5ff:
561 case 0xc680 ... 0xc683:
562 case 0xc820:
563 case 0xc900:
564 case 0xc920:
565 case 0xca42:
566 case 0xca62:
567 case 0xca82:
568 case 0xcd00:
569 case 0xce03:
570 case 0xce10:
571 case 0xce14 ... 0xce17:
572 case 0xce44 ... 0xce49:
573 case 0xce4c ... 0xce4d:
574 case 0xcf0c:
575 case 0xcf10 ... 0xcf25:
576 case 0xd486 ... 0xd487:
577 case 0xd4e5 ... 0xd4e6:
578 case 0xd4e8 ... 0xd4ff:
579 case 0xd530:
580 case 0xd540 ... 0xd541:
581 case 0xd543:
582 case 0xdb58 ... 0xdb5f:
583 case 0xdb60 ... 0xdb63:
584 case 0xdb68 ... 0xdb69:
585 case 0xdb6d:
586 case 0xdb70 ... 0xdb71:
587 case 0xdb76:
588 case 0xdb7a:
589 case 0xdb7c ... 0xdb7f:
590 case 0xdd0c ... 0xdd13:
591 case 0xde02:
592 case 0xdf14 ... 0xdf1b:
593 case 0xe83c ... 0xe847:
594 case 0xf01e:
595 case 0xf717 ... 0xf719:
596 case 0xf720 ... 0xf723:
597 case 0x10000000 ... 0x10008fff:
598 case 0x1000c000 ... 0x1000dfff:
599 case 0x1000f008:
600 case 0x1000f021:
601 case 0x2000300f:
602 case 0x2000301c:
603 case 0x2000900f:
604 case 0x20009018:
605 case 0x3fc2ab80 ... 0x3fc2abd4:
606 case 0x3fc2b780:
607 case 0x3fc2bf80 ... 0x3fc2bf83:
608 case 0x3fc2bfc0 ... 0x3fc2bfc8:
609 case 0x3fc2d300 ... 0x3fc2d354:
610 case 0x3fc2dfc0 ... 0x3fc2dfc8:
611 case 0x3fe2e000 ... 0x3fe2e003:
612 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
615 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
616 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
617 return true;
618 default:
619 return false;
620 }
621 }
622
rt1320_mbq_readable_register(struct device * dev,unsigned int reg)623 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
624 {
625 switch (reg) {
626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
627 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
628 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
629 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
630 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
631 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
632 return true;
633 default:
634 return false;
635 }
636 }
637
638 static const struct regmap_config rt1320_sdw_regmap = {
639 .reg_bits = 32,
640 .val_bits = 8,
641 .readable_reg = rt1320_readable_register,
642 .volatile_reg = rt1320_volatile_register,
643 .max_register = 0x41081980,
644 .reg_defaults = rt1320_reg_defaults,
645 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults),
646 .cache_type = REGCACHE_MAPLE,
647 .use_single_read = true,
648 .use_single_write = true,
649 };
650
651 static const struct regmap_config rt1320_mbq_regmap = {
652 .name = "sdw-mbq",
653 .reg_bits = 32,
654 .val_bits = 16,
655 .readable_reg = rt1320_mbq_readable_register,
656 .max_register = 0x41000192,
657 .reg_defaults = rt1320_mbq_defaults,
658 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults),
659 .cache_type = REGCACHE_MAPLE,
660 .use_single_read = true,
661 .use_single_write = true,
662 };
663
rt1320_read_prop(struct sdw_slave * slave)664 static int rt1320_read_prop(struct sdw_slave *slave)
665 {
666 struct sdw_slave_prop *prop = &slave->prop;
667 int nval;
668 int i, j;
669 u32 bit;
670 unsigned long addr;
671 struct sdw_dpn_prop *dpn;
672
673 /*
674 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping
675 */
676 sdw_slave_read_prop(slave);
677
678 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
679 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
680
681 prop->paging_support = true;
682 prop->lane_control_support = true;
683
684 /* first we need to allocate memory for set bits in port lists */
685 prop->source_ports = BIT(4) | BIT(8) | BIT(10);
686 prop->sink_ports = BIT(1);
687
688 nval = hweight32(prop->source_ports);
689 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
690 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
691 if (!prop->src_dpn_prop)
692 return -ENOMEM;
693
694 i = 0;
695 dpn = prop->src_dpn_prop;
696 addr = prop->source_ports;
697 for_each_set_bit(bit, &addr, 32) {
698 dpn[i].num = bit;
699 dpn[i].type = SDW_DPN_FULL;
700 dpn[i].simple_ch_prep_sm = true;
701 dpn[i].ch_prep_timeout = 10;
702 i++;
703 }
704
705 /* do this again for sink now */
706 nval = hweight32(prop->sink_ports);
707 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
708 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
709 if (!prop->sink_dpn_prop)
710 return -ENOMEM;
711
712 j = 0;
713 dpn = prop->sink_dpn_prop;
714 addr = prop->sink_ports;
715 for_each_set_bit(bit, &addr, 32) {
716 dpn[j].num = bit;
717 dpn[j].type = SDW_DPN_FULL;
718 dpn[j].simple_ch_prep_sm = true;
719 dpn[j].ch_prep_timeout = 10;
720 j++;
721 }
722
723 /* set the timeout values */
724 prop->clk_stop_timeout = 64;
725
726 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */
727 prop->wake_capable = 0;
728
729 return 0;
730 }
731
rt1320_pde_transition_delay(struct rt1320_sdw_priv * rt1320,unsigned char func,unsigned char entity,unsigned char ps)732 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func,
733 unsigned char entity, unsigned char ps)
734 {
735 unsigned int delay = 2000, val;
736
737 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev);
738
739 /* waiting for Actual PDE becomes to PS0/PS3 */
740 while (delay) {
741 regmap_read(rt1320->regmap,
742 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
743 if (val == ps)
744 break;
745
746 usleep_range(1000, 1500);
747 delay--;
748 }
749 if (!delay) {
750 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
751 return -ETIMEDOUT;
752 }
753
754 return 0;
755 }
756
757 /*
758 * The 'patch code' is written to the patch code area.
759 * The patch code area is used for SDCA register expansion flexibility.
760 */
rt1320_load_mcu_patch(struct rt1320_sdw_priv * rt1320)761 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320)
762 {
763 struct sdw_slave *slave = rt1320->sdw_slave;
764 const struct firmware *patch;
765 const char *filename;
766 unsigned int addr, val, min_addr, max_addr;
767 const unsigned char *ptr;
768 int ret, i;
769
770 switch (rt1320->dev_id) {
771 case RT1320_DEV_ID:
772 if (rt1320->version_id <= RT1320_VB)
773 filename = RT1320_VAB_MCU_PATCH;
774 else
775 filename = RT1320_VC_MCU_PATCH;
776 min_addr = 0x10007000;
777 max_addr = 0x10007fff;
778 break;
779 case RT1321_DEV_ID:
780 filename = RT1321_VA_MCU_PATCH;
781 min_addr = 0x10008000;
782 max_addr = 0x10008fff;
783 break;
784 default:
785 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
786 return;
787 }
788
789 /* load the patch code here */
790 ret = request_firmware(&patch, filename, &slave->dev);
791 if (ret) {
792 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename);
793 regmap_write(rt1320->regmap, 0xc598, 0x00);
794 regmap_write(rt1320->regmap, min_addr, 0x67);
795 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80);
796 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00);
797 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00);
798 if (rt1320->dev_id == RT1321_DEV_ID) {
799 regmap_write(rt1320->regmap, 0xd73c, 0x67);
800 regmap_write(rt1320->regmap, 0xd73d, 0x80);
801 regmap_write(rt1320->regmap, 0xd73e, 0x00);
802 regmap_write(rt1320->regmap, 0xd73f, 0x00);
803 }
804 } else {
805 ptr = (const unsigned char *)patch->data;
806 if ((patch->size % 8) == 0) {
807 for (i = 0; i < patch->size; i += 8) {
808 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 |
809 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24;
810 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 |
811 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24;
812
813 if (addr > max_addr || addr < min_addr) {
814 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr);
815 goto _exit_;
816 }
817 if (val > 0xff) {
818 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val);
819 goto _exit_;
820 }
821 regmap_write(rt1320->regmap, addr, val);
822 }
823 }
824 _exit_:
825 release_firmware(patch);
826 }
827 }
828
rt1320_vab_preset(struct rt1320_sdw_priv * rt1320)829 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320)
830 {
831 unsigned int i, reg, val, delay;
832
833 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) {
834 reg = rt1320_blind_write[i].reg;
835 val = rt1320_blind_write[i].def;
836 delay = rt1320_blind_write[i].delay_us;
837
838 if (reg == 0x3fc2bfc7)
839 rt1320_load_mcu_patch(rt1320);
840
841 regmap_write(rt1320->regmap, reg, val);
842 if (delay)
843 usleep_range(delay, delay + 1000);
844 }
845 }
846
rt1320_vc_preset(struct rt1320_sdw_priv * rt1320)847 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320)
848 {
849 struct sdw_slave *slave = rt1320->sdw_slave;
850 unsigned int i, reg, val, delay, retry, tmp;
851
852 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) {
853 reg = rt1320_vc_blind_write[i].reg;
854 val = rt1320_vc_blind_write[i].def;
855 delay = rt1320_vc_blind_write[i].delay_us;
856
857 if (reg == 0x3fc2bf83)
858 rt1320_load_mcu_patch(rt1320);
859
860 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) &&
861 (val == 0x00)) {
862 retry = 200;
863 while (retry) {
864 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp);
865 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp);
866 if (tmp == 0x1f)
867 break;
868 usleep_range(1000, 1500);
869 retry--;
870 }
871 if (!retry)
872 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__);
873 }
874 regmap_write(rt1320->regmap, reg, val);
875 if (delay)
876 usleep_range(delay, delay + 1000);
877
878 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
879 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
880 }
881 }
882
rt1321_preset(struct rt1320_sdw_priv * rt1320)883 static void rt1321_preset(struct rt1320_sdw_priv *rt1320)
884 {
885 unsigned int i, reg, val, delay;
886
887 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) {
888 reg = rt1321_blind_write[i].reg;
889 val = rt1321_blind_write[i].def;
890 delay = rt1321_blind_write[i].delay_us;
891
892 if (reg == 0x3fc2dfc3)
893 rt1320_load_mcu_patch(rt1320);
894
895 regmap_write(rt1320->regmap, reg, val);
896
897 if (delay)
898 usleep_range(delay, delay + 1000);
899
900 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
901 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
902 }
903 }
904
rt1320_io_init(struct device * dev,struct sdw_slave * slave)905 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave)
906 {
907 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
908 unsigned int amp_func_status, val, tmp;
909
910 if (rt1320->hw_init)
911 return 0;
912
913 regcache_cache_only(rt1320->regmap, false);
914 regcache_cache_only(rt1320->mbq_regmap, false);
915 if (rt1320->first_hw_init) {
916 regcache_cache_bypass(rt1320->regmap, true);
917 regcache_cache_bypass(rt1320->mbq_regmap, true);
918 } else {
919 /*
920 * PM runtime status is marked as 'active' only when a Slave reports as Attached
921 */
922 /* update count of parent 'active' children */
923 pm_runtime_set_active(&slave->dev);
924 }
925
926 pm_runtime_get_noresume(&slave->dev);
927
928 if (rt1320->version_id < 0) {
929 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val);
930 rt1320->version_id = val;
931 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val);
932 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp);
933 rt1320->dev_id = (val << 8) | tmp;
934 }
935
936 regmap_read(rt1320->regmap,
937 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
938 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
939
940 /* initialization write */
941 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) {
942 switch (rt1320->dev_id) {
943 case RT1320_DEV_ID:
944 if (rt1320->version_id < RT1320_VC)
945 rt1320_vab_preset(rt1320);
946 else
947 rt1320_vc_preset(rt1320);
948 break;
949 case RT1321_DEV_ID:
950 rt1321_preset(rt1320);
951 break;
952 default:
953 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
954 }
955
956 regmap_write(rt1320->regmap,
957 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
958 FUNCTION_NEEDS_INITIALIZATION);
959 }
960 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) {
961 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
962 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
963 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val);
964 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp);
965 val = (tmp << 8) | val;
966 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp);
967 val = (tmp << 16) | val;
968 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp);
969 val = (tmp << 24) | val;
970 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
971 /*
972 * We call the version b which has the new DSP ROM code against version a.
973 * Therefore, we read the DSP address to check the ID.
974 */
975 if (val == RT1320_VER_B_ID)
976 rt1320->version_id = RT1320_VB;
977 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
978 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
979 }
980 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id);
981
982 if (rt1320->first_hw_init) {
983 regcache_cache_bypass(rt1320->regmap, false);
984 regcache_cache_bypass(rt1320->mbq_regmap, false);
985 regcache_mark_dirty(rt1320->regmap);
986 regcache_mark_dirty(rt1320->mbq_regmap);
987 }
988
989 /* Mark Slave initialization complete */
990 rt1320->first_hw_init = true;
991 rt1320->hw_init = true;
992
993 pm_runtime_put_autosuspend(&slave->dev);
994
995 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
996 return 0;
997 }
998
rt1320_update_status(struct sdw_slave * slave,enum sdw_slave_status status)999 static int rt1320_update_status(struct sdw_slave *slave,
1000 enum sdw_slave_status status)
1001 {
1002 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
1003
1004 if (status == SDW_SLAVE_UNATTACHED)
1005 rt1320->hw_init = false;
1006
1007 /*
1008 * Perform initialization only if slave status is present and
1009 * hw_init flag is false
1010 */
1011 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED)
1012 return 0;
1013
1014 /* perform I/O transfers required for Slave initialization */
1015 return rt1320_io_init(&slave->dev, slave);
1016 }
1017
rt1320_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1018 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w,
1019 struct snd_kcontrol *kcontrol, int event)
1020 {
1021 struct snd_soc_component *component =
1022 snd_soc_dapm_to_component(w->dapm);
1023 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1024 unsigned char ps0 = 0x0, ps3 = 0x3;
1025
1026 switch (event) {
1027 case SND_SOC_DAPM_POST_PMU:
1028 regmap_write(rt1320->regmap,
1029 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
1030 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1031 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0);
1032 break;
1033 case SND_SOC_DAPM_PRE_PMD:
1034 regmap_write(rt1320->regmap,
1035 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
1036 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1037 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3);
1038 break;
1039 default:
1040 break;
1041 }
1042
1043 return 0;
1044 }
1045
rt1320_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1046 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
1047 struct snd_kcontrol *kcontrol, int event)
1048 {
1049 struct snd_soc_component *component =
1050 snd_soc_dapm_to_component(w->dapm);
1051 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1052 unsigned char ps0 = 0x0, ps3 = 0x3;
1053
1054 switch (event) {
1055 case SND_SOC_DAPM_POST_PMU:
1056 regmap_write(rt1320->regmap,
1057 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1058 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1059 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0);
1060 break;
1061 case SND_SOC_DAPM_PRE_PMD:
1062 regmap_write(rt1320->regmap,
1063 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1064 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1065 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3);
1066 break;
1067 default:
1068 break;
1069 }
1070
1071 return 0;
1072 }
1073
rt1320_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1074 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol,
1075 struct snd_ctl_elem_value *ucontrol)
1076 {
1077 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1078 struct soc_mixer_control *mc =
1079 (struct soc_mixer_control *)kcontrol->private_value;
1080 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1081 unsigned int gain_l_val, gain_r_val;
1082 unsigned int lvalue, rvalue;
1083 const unsigned int interval_offset = 0xc0;
1084 unsigned int changed = 0, reg_base;
1085 struct rt_sdca_dmic_kctrl_priv *p;
1086 unsigned int regvalue[4], gain_val[4], i;
1087 int err;
1088
1089 if (strstr(ucontrol->id.name, "FU Capture Volume"))
1090 goto _dmic_vol_;
1091
1092 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
1093 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
1094
1095 /* L Channel */
1096 gain_l_val = ucontrol->value.integer.value[0];
1097 if (gain_l_val > mc->max)
1098 gain_l_val = mc->max;
1099 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
1100 gain_l_val &= 0xffff;
1101
1102 /* R Channel */
1103 gain_r_val = ucontrol->value.integer.value[1];
1104 if (gain_r_val > mc->max)
1105 gain_r_val = mc->max;
1106 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
1107 gain_r_val &= 0xffff;
1108
1109 if (lvalue == gain_l_val && rvalue == gain_r_val)
1110 return 0;
1111
1112 /* Lch*/
1113 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
1114 /* Rch */
1115 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
1116 goto _done_;
1117
1118 _dmic_vol_:
1119 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
1120
1121 /* check all channels */
1122 for (i = 0; i < p->count; i++) {
1123 switch (rt1320->dev_id) {
1124 case RT1320_DEV_ID:
1125 if (i < 2) {
1126 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1127 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
1128 } else {
1129 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1130 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]);
1131 }
1132 break;
1133 case RT1321_DEV_ID:
1134 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1135 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
1136 break;
1137 }
1138
1139 gain_val[i] = ucontrol->value.integer.value[i];
1140 if (gain_val[i] > p->max)
1141 gain_val[i] = p->max;
1142
1143 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
1144 gain_val[i] &= 0xffff;
1145 if (regvalue[i] != gain_val[i])
1146 changed = 1;
1147 }
1148
1149 if (!changed)
1150 return 0;
1151
1152 for (i = 0; i < p->count; i++) {
1153 switch (rt1320->dev_id) {
1154 case RT1320_DEV_ID:
1155 if (i < 2) {
1156 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1157 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
1158 } else {
1159 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1160 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]);
1161 }
1162 break;
1163 case RT1321_DEV_ID:
1164 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1165 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
1166 break;
1167 }
1168
1169 if (err < 0)
1170 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
1171 }
1172
1173 _done_:
1174 return 1;
1175 }
1176
rt1320_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1177 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol,
1178 struct snd_ctl_elem_value *ucontrol)
1179 {
1180 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1181 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1182 struct soc_mixer_control *mc =
1183 (struct soc_mixer_control *)kcontrol->private_value;
1184 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
1185 const unsigned int interval_offset = 0xc0;
1186 unsigned int reg_base, regvalue, ctl, i;
1187 struct rt_sdca_dmic_kctrl_priv *p;
1188
1189 if (strstr(ucontrol->id.name, "FU Capture Volume"))
1190 goto _dmic_vol_;
1191
1192 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
1193 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
1194
1195 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
1196
1197 if (read_l != read_r)
1198 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
1199 else
1200 ctl_r = ctl_l;
1201
1202 ucontrol->value.integer.value[0] = ctl_l;
1203 ucontrol->value.integer.value[1] = ctl_r;
1204 goto _done_;
1205
1206 _dmic_vol_:
1207 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
1208
1209 /* check all channels */
1210 for (i = 0; i < p->count; i++) {
1211 switch (rt1320->dev_id) {
1212 case RT1320_DEV_ID:
1213 if (i < 2) {
1214 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1215 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
1216 } else {
1217 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1218 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value);
1219 }
1220 break;
1221 case RT1321_DEV_ID:
1222 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
1223 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
1224 break;
1225 }
1226
1227 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
1228 ucontrol->value.integer.value[i] = ctl;
1229 }
1230 _done_:
1231 return 0;
1232 }
1233
rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv * rt1320)1234 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320)
1235 {
1236 int err, i;
1237 unsigned int ch_mute;
1238
1239 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
1240 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
1241
1242 switch (rt1320->dev_id) {
1243 case RT1320_DEV_ID:
1244 if (i < 2)
1245 err = regmap_write(rt1320->regmap,
1246 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
1247 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
1248 else
1249 err = regmap_write(rt1320->regmap,
1250 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14,
1251 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute);
1252 break;
1253 case RT1321_DEV_ID:
1254 err = regmap_write(rt1320->regmap,
1255 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
1256 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
1257 break;
1258 default:
1259 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1260 return -EINVAL;
1261 }
1262 if (err < 0)
1263 return err;
1264 }
1265
1266 return 0;
1267 }
1268
rt1320_dmic_fu_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1269 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol,
1270 struct snd_ctl_elem_value *ucontrol)
1271 {
1272 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1273 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1274 struct rt_sdca_dmic_kctrl_priv *p =
1275 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
1276 unsigned int i;
1277
1278 for (i = 0; i < p->count; i++)
1279 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i];
1280
1281 return 0;
1282 }
1283
rt1320_dmic_fu_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1284 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol,
1285 struct snd_ctl_elem_value *ucontrol)
1286 {
1287 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1288 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1289 struct rt_sdca_dmic_kctrl_priv *p =
1290 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
1291 int err, changed = 0, i;
1292
1293 for (i = 0; i < p->count; i++) {
1294 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i])
1295 changed = 1;
1296 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i];
1297 }
1298
1299 err = rt1320_set_fu_capture_ctl(rt1320);
1300 if (err < 0)
1301 return err;
1302
1303 return changed;
1304 }
1305
rt1320_dmic_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1306 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol,
1307 struct snd_ctl_elem_info *uinfo)
1308 {
1309 struct rt_sdca_dmic_kctrl_priv *p =
1310 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
1311
1312 if (p->max == 1)
1313 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1314 else
1315 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1316 uinfo->count = p->count;
1317 uinfo->value.integer.min = 0;
1318 uinfo->value.integer.max = p->max;
1319 return 0;
1320 }
1321
rt1320_dmic_fu_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1322 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w,
1323 struct snd_kcontrol *kcontrol, int event)
1324 {
1325 struct snd_soc_component *component =
1326 snd_soc_dapm_to_component(w->dapm);
1327 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1328
1329 switch (event) {
1330 case SND_SOC_DAPM_POST_PMU:
1331 rt1320->fu_dapm_mute = false;
1332 rt1320_set_fu_capture_ctl(rt1320);
1333 break;
1334 case SND_SOC_DAPM_PRE_PMD:
1335 rt1320->fu_dapm_mute = true;
1336 rt1320_set_fu_capture_ctl(rt1320);
1337 break;
1338 }
1339 return 0;
1340 }
1341
1342 static const char * const rt1320_rx_data_ch_select[] = {
1343 "L,R",
1344 "R,L",
1345 "L,L",
1346 "R,R",
1347 "L,L+R",
1348 "R,L+R",
1349 "L+R,L",
1350 "L+R,R",
1351 "L+R,L+R",
1352 };
1353
1354 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum,
1355 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
1356 rt1320_rx_data_ch_select);
1357
1358 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
1359 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
1360
1361 static const struct snd_kcontrol_new rt1320_snd_controls[] = {
1362 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
1363 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
1364 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
1365 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
1366 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
1367
1368 RT_SDCA_FU_CTRL("FU Capture Switch",
1369 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01),
1370 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put),
1371 RT_SDCA_EXT_TLV("FU Capture Volume",
1372 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
1373 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
1374 };
1375
1376 static const struct snd_kcontrol_new rt1320_spk_l_dac =
1377 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
1378 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01),
1379 0, 1, 1);
1380 static const struct snd_kcontrol_new rt1320_spk_r_dac =
1381 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
1382 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02),
1383 0, 1, 1);
1384
1385 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = {
1386 /* Audio Interface */
1387 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
1388 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
1389 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
1390
1391 /* Digital Interface */
1392 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
1393 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1394 rt1320_pde23_event,
1395 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1396 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1397 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1398 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
1399 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
1400 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
1401 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1402
1403 /* Output */
1404 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
1405 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
1406 SND_SOC_DAPM_OUTPUT("SPOL"),
1407 SND_SOC_DAPM_OUTPUT("SPOR"),
1408
1409 /* Input */
1410 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
1411 SND_SOC_DAPM_SIGGEN("AEC Gen"),
1412 SND_SOC_DAPM_INPUT("DMIC1"),
1413 SND_SOC_DAPM_INPUT("DMIC2"),
1414 };
1415
1416 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
1417 { "FU21", NULL, "DP1RX" },
1418 { "FU21", NULL, "PDE 23" },
1419 { "OT23 L", "Switch", "FU21" },
1420 { "OT23 R", "Switch", "FU21" },
1421 { "SPOL", NULL, "OT23 L" },
1422 { "SPOR", NULL, "OT23 R" },
1423
1424 { "AEC Data", NULL, "AEC Gen" },
1425 { "DP4TX", NULL, "AEC Data" },
1426
1427 {"DP8-10TX", NULL, "FU"},
1428 {"FU", NULL, "PDE 11"},
1429 {"FU", NULL, "FU 113"},
1430 {"FU", NULL, "FU 14"},
1431 {"FU 113", NULL, "DMIC1"},
1432 {"FU 14", NULL, "DMIC2"},
1433 };
1434
rt1320_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)1435 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1436 int direction)
1437 {
1438 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1439 return 0;
1440 }
1441
rt1320_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1442 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream,
1443 struct snd_soc_dai *dai)
1444 {
1445 snd_soc_dai_set_dma_data(dai, substream, NULL);
1446 }
1447
rt1320_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1448 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream,
1449 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1450 {
1451 struct snd_soc_component *component = dai->component;
1452 struct rt1320_sdw_priv *rt1320 =
1453 snd_soc_component_get_drvdata(component);
1454 struct sdw_stream_config stream_config;
1455 struct sdw_port_config port_config;
1456 struct sdw_port_config dmic_port_config[2];
1457 struct sdw_stream_runtime *sdw_stream;
1458 int retval;
1459 unsigned int sampling_rate;
1460
1461 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1462 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1463
1464 if (!sdw_stream)
1465 return -EINVAL;
1466
1467 if (!rt1320->sdw_slave)
1468 return -EINVAL;
1469
1470 /* SoundWire specific configuration */
1471 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
1472
1473 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1474 if (dai->id == RT1320_AIF1)
1475 port_config.num = 1;
1476 else
1477 return -EINVAL;
1478 } else {
1479 if (dai->id == RT1320_AIF1)
1480 port_config.num = 4;
1481 else if (dai->id == RT1320_AIF2) {
1482 switch (rt1320->dev_id) {
1483 case RT1320_DEV_ID:
1484 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
1485 dmic_port_config[0].num = 8;
1486 dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
1487 dmic_port_config[1].num = 10;
1488 break;
1489 case RT1321_DEV_ID:
1490 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
1491 dmic_port_config[0].num = 8;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496 } else
1497 return -EINVAL;
1498 }
1499
1500 if (dai->id == RT1320_AIF1)
1501 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
1502 &port_config, 1, sdw_stream);
1503 else if (dai->id == RT1320_AIF2) {
1504 switch (rt1320->dev_id) {
1505 case RT1320_DEV_ID:
1506 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
1507 dmic_port_config, 2, sdw_stream);
1508 break;
1509 case RT1321_DEV_ID:
1510 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
1511 dmic_port_config, 1, sdw_stream);
1512 break;
1513 default:
1514 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1515 return -EINVAL;
1516 }
1517 } else
1518 return -EINVAL;
1519 if (retval) {
1520 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1521 return retval;
1522 }
1523
1524 /* sampling rate configuration */
1525 switch (params_rate(params)) {
1526 case 16000:
1527 sampling_rate = RT1320_SDCA_RATE_16000HZ;
1528 break;
1529 case 32000:
1530 sampling_rate = RT1320_SDCA_RATE_32000HZ;
1531 break;
1532 case 44100:
1533 sampling_rate = RT1320_SDCA_RATE_44100HZ;
1534 break;
1535 case 48000:
1536 sampling_rate = RT1320_SDCA_RATE_48000HZ;
1537 break;
1538 case 96000:
1539 sampling_rate = RT1320_SDCA_RATE_96000HZ;
1540 break;
1541 case 192000:
1542 sampling_rate = RT1320_SDCA_RATE_192000HZ;
1543 break;
1544 default:
1545 dev_err(component->dev, "%s: Rate %d is not supported\n",
1546 __func__, params_rate(params));
1547 return -EINVAL;
1548 }
1549
1550 /* set sampling frequency */
1551 if (dai->id == RT1320_AIF1)
1552 regmap_write(rt1320->regmap,
1553 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1554 sampling_rate);
1555 else {
1556 regmap_write(rt1320->regmap,
1557 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1558 sampling_rate);
1559
1560 if (rt1320->dev_id == RT1320_DEV_ID)
1561 regmap_write(rt1320->regmap,
1562 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1563 sampling_rate);
1564 }
1565
1566 return 0;
1567 }
1568
rt1320_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1569 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
1570 struct snd_soc_dai *dai)
1571 {
1572 struct snd_soc_component *component = dai->component;
1573 struct rt1320_sdw_priv *rt1320 =
1574 snd_soc_component_get_drvdata(component);
1575 struct sdw_stream_runtime *sdw_stream =
1576 snd_soc_dai_get_dma_data(dai, substream);
1577
1578 if (!rt1320->sdw_slave)
1579 return -EINVAL;
1580
1581 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream);
1582 return 0;
1583 }
1584
1585 /*
1586 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
1587 * port_prep are not defined for now
1588 */
1589 static const struct sdw_slave_ops rt1320_slave_ops = {
1590 .read_prop = rt1320_read_prop,
1591 .update_status = rt1320_update_status,
1592 };
1593
rt1320_sdw_component_probe(struct snd_soc_component * component)1594 static int rt1320_sdw_component_probe(struct snd_soc_component *component)
1595 {
1596 int ret;
1597 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1598
1599 rt1320->component = component;
1600
1601 if (!rt1320->first_hw_init)
1602 return 0;
1603
1604 ret = pm_runtime_resume(component->dev);
1605 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
1606 if (ret < 0 && ret != -EACCES)
1607 return ret;
1608
1609 return 0;
1610 }
1611
1612 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = {
1613 .probe = rt1320_sdw_component_probe,
1614 .controls = rt1320_snd_controls,
1615 .num_controls = ARRAY_SIZE(rt1320_snd_controls),
1616 .dapm_widgets = rt1320_dapm_widgets,
1617 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets),
1618 .dapm_routes = rt1320_dapm_routes,
1619 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes),
1620 .endianness = 1,
1621 };
1622
1623 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = {
1624 .hw_params = rt1320_sdw_hw_params,
1625 .hw_free = rt1320_sdw_pcm_hw_free,
1626 .set_stream = rt1320_set_sdw_stream,
1627 .shutdown = rt1320_sdw_shutdown,
1628 };
1629
1630 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
1631 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
1632 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
1633 SNDRV_PCM_FMTBIT_S32_LE)
1634
1635 static struct snd_soc_dai_driver rt1320_sdw_dai[] = {
1636 {
1637 .name = "rt1320-aif1",
1638 .id = RT1320_AIF1,
1639 .playback = {
1640 .stream_name = "DP1 Playback",
1641 .channels_min = 1,
1642 .channels_max = 2,
1643 .rates = RT1320_STEREO_RATES,
1644 .formats = RT1320_FORMATS,
1645 },
1646 .capture = {
1647 .stream_name = "DP4 Capture",
1648 .channels_min = 1,
1649 .channels_max = 2,
1650 .rates = RT1320_STEREO_RATES,
1651 .formats = RT1320_FORMATS,
1652 },
1653 .ops = &rt1320_aif_dai_ops,
1654 },
1655 /* DMIC: DP8 2ch + DP10 2ch */
1656 {
1657 .name = "rt1320-aif2",
1658 .id = RT1320_AIF2,
1659 .capture = {
1660 .stream_name = "DP8-10 Capture",
1661 .channels_min = 1,
1662 .channels_max = 4,
1663 .rates = RT1320_STEREO_RATES,
1664 .formats = RT1320_FORMATS,
1665 },
1666 .ops = &rt1320_aif_dai_ops,
1667 },
1668 };
1669
rt1320_sdw_init(struct device * dev,struct regmap * regmap,struct regmap * mbq_regmap,struct sdw_slave * slave)1670 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
1671 struct regmap *mbq_regmap, struct sdw_slave *slave)
1672 {
1673 struct rt1320_sdw_priv *rt1320;
1674 int ret;
1675
1676 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL);
1677 if (!rt1320)
1678 return -ENOMEM;
1679
1680 dev_set_drvdata(dev, rt1320);
1681 rt1320->sdw_slave = slave;
1682 rt1320->mbq_regmap = mbq_regmap;
1683 rt1320->regmap = regmap;
1684
1685 regcache_cache_only(rt1320->regmap, true);
1686 regcache_cache_only(rt1320->mbq_regmap, true);
1687
1688 /*
1689 * Mark hw_init to false
1690 * HW init will be performed when device reports present
1691 */
1692 rt1320->hw_init = false;
1693 rt1320->first_hw_init = false;
1694 rt1320->version_id = -1;
1695 rt1320->fu_dapm_mute = true;
1696 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
1697 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true;
1698
1699 ret = devm_snd_soc_register_component(dev,
1700 &soc_component_sdw_rt1320,
1701 rt1320_sdw_dai,
1702 ARRAY_SIZE(rt1320_sdw_dai));
1703 if (ret < 0)
1704 return ret;
1705
1706 /* set autosuspend parameters */
1707 pm_runtime_set_autosuspend_delay(dev, 3000);
1708 pm_runtime_use_autosuspend(dev);
1709
1710 /* make sure the device does not suspend immediately */
1711 pm_runtime_mark_last_busy(dev);
1712
1713 pm_runtime_enable(dev);
1714
1715 /* important note: the device is NOT tagged as 'active' and will remain
1716 * 'suspended' until the hardware is enumerated/initialized. This is required
1717 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
1718 * fail with -EACCESS because of race conditions between card creation and enumeration
1719 */
1720
1721 dev_dbg(dev, "%s\n", __func__);
1722
1723 return ret;
1724 }
1725
rt1320_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)1726 static int rt1320_sdw_probe(struct sdw_slave *slave,
1727 const struct sdw_device_id *id)
1728 {
1729 struct regmap *regmap, *mbq_regmap;
1730
1731 /* Regmap Initialization */
1732 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap);
1733 if (IS_ERR(mbq_regmap))
1734 return PTR_ERR(mbq_regmap);
1735
1736 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap);
1737 if (IS_ERR(regmap))
1738 return PTR_ERR(regmap);
1739
1740 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave);
1741 }
1742
rt1320_sdw_remove(struct sdw_slave * slave)1743 static int rt1320_sdw_remove(struct sdw_slave *slave)
1744 {
1745 pm_runtime_disable(&slave->dev);
1746
1747 return 0;
1748 }
1749
1750 /*
1751 * Version A/B will use the class id 0
1752 * The newer version than A/B will use the class id 1, so add it in advance
1753 */
1754 static const struct sdw_device_id rt1320_id[] = {
1755 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
1756 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
1757 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0),
1758 {},
1759 };
1760 MODULE_DEVICE_TABLE(sdw, rt1320_id);
1761
rt1320_dev_suspend(struct device * dev)1762 static int rt1320_dev_suspend(struct device *dev)
1763 {
1764 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
1765
1766 if (!rt1320->hw_init)
1767 return 0;
1768
1769 regcache_cache_only(rt1320->regmap, true);
1770 regcache_cache_only(rt1320->mbq_regmap, true);
1771 return 0;
1772 }
1773
1774 #define RT1320_PROBE_TIMEOUT 5000
1775
rt1320_dev_resume(struct device * dev)1776 static int rt1320_dev_resume(struct device *dev)
1777 {
1778 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1779 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
1780 unsigned long time;
1781
1782 if (!rt1320->first_hw_init)
1783 return 0;
1784
1785 if (!slave->unattach_request)
1786 goto regmap_sync;
1787
1788 time = wait_for_completion_timeout(&slave->initialization_complete,
1789 msecs_to_jiffies(RT1320_PROBE_TIMEOUT));
1790 if (!time) {
1791 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
1792 return -ETIMEDOUT;
1793 }
1794
1795 regmap_sync:
1796 slave->unattach_request = 0;
1797 regcache_cache_only(rt1320->regmap, false);
1798 regcache_sync(rt1320->regmap);
1799 regcache_cache_only(rt1320->mbq_regmap, false);
1800 regcache_sync(rt1320->mbq_regmap);
1801 return 0;
1802 }
1803
1804 static const struct dev_pm_ops rt1320_pm = {
1805 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume)
1806 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL)
1807 };
1808
1809 static struct sdw_driver rt1320_sdw_driver = {
1810 .driver = {
1811 .name = "rt1320-sdca",
1812 .pm = pm_ptr(&rt1320_pm),
1813 },
1814 .probe = rt1320_sdw_probe,
1815 .remove = rt1320_sdw_remove,
1816 .ops = &rt1320_slave_ops,
1817 .id_table = rt1320_id,
1818 };
1819 module_sdw_driver(rt1320_sdw_driver);
1820
1821 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW");
1822 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1823 MODULE_LICENSE("GPL");
1824