1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 { 0xd478, 0xff }, 113 }; 114 115 static const struct reg_sequence rt1320_vc_blind_write[] = { 116 { 0xc003, 0xe0 }, 117 { 0xe80a, 0x01 }, 118 { 0xc5c3, 0xf3 }, 119 { 0xc057, 0x51 }, 120 { 0xc054, 0x35 }, 121 { 0xca05, 0xd6 }, 122 { 0xca07, 0x07 }, 123 { 0xca25, 0xd6 }, 124 { 0xca27, 0x07 }, 125 { 0xc604, 0x40 }, 126 { 0xc609, 0x40 }, 127 { 0xc046, 0xff }, 128 { 0xc045, 0xff }, 129 { 0xda81, 0x14 }, 130 { 0xda8d, 0x14 }, 131 { 0xc044, 0xff }, 132 { 0xc043, 0xff }, 133 { 0xc042, 0xff }, 134 { 0xc041, 0x7f }, 135 { 0xc040, 0xff }, 136 { 0xcc10, 0x01 }, 137 { 0xc700, 0xf0 }, 138 { 0xc701, 0x13 }, 139 { 0xc901, 0x09 }, 140 { 0xc900, 0xd0 }, 141 { 0xde03, 0x05 }, 142 { 0xdd0b, 0x0d }, 143 { 0xdd0a, 0xff }, 144 { 0xdd09, 0x0d }, 145 { 0xdd08, 0xff }, 146 { 0xc570, 0x08 }, 147 { 0xc086, 0x02 }, 148 { 0xc085, 0x7f }, 149 { 0xc084, 0x00 }, 150 { 0xc081, 0xfe }, 151 { 0xf084, 0x0f }, 152 { 0xf083, 0xff }, 153 { 0xf082, 0xff }, 154 { 0xf081, 0xff }, 155 { 0xf080, 0xff }, 156 { 0xe802, 0xf8 }, 157 { 0xe803, 0xbe }, 158 { 0xc003, 0xc0 }, 159 { 0xd470, 0xec }, 160 { 0xd471, 0x3a }, 161 { 0xd474, 0x11 }, 162 { 0xd475, 0x32 }, 163 { 0xd478, 0xff }, 164 { 0xd479, 0x20 }, 165 { 0xd47a, 0x10 }, 166 { 0xd47c, 0xff }, 167 { 0xc019, 0x10 }, 168 { 0xd487, 0x0b }, 169 { 0xd487, 0x3b }, 170 { 0xd486, 0xc3 }, 171 { 0xc598, 0x04 }, 172 { 0xdb03, 0xf0 }, 173 { 0xdb09, 0x00 }, 174 { 0xdb08, 0x7a }, 175 { 0xdb19, 0x02 }, 176 { 0xdb07, 0x5a }, 177 { 0xdb05, 0x45 }, 178 { 0xd500, 0x00 }, 179 { 0xd500, 0x17 }, 180 { 0xd600, 0x01 }, 181 { 0xd601, 0x02 }, 182 { 0xd602, 0x03 }, 183 { 0xd603, 0x04 }, 184 { 0xd64c, 0x03 }, 185 { 0xd64d, 0x03 }, 186 { 0xd64e, 0x03 }, 187 { 0xd64f, 0x03 }, 188 { 0xd650, 0x03 }, 189 { 0xd651, 0x03 }, 190 { 0xd652, 0x03 }, 191 { 0xd610, 0x01 }, 192 { 0xd608, 0x03 }, 193 { 0xd609, 0x00 }, 194 { 0x3fc2bf83, 0x00 }, 195 { 0x3fc2bf82, 0x00 }, 196 { 0x3fc2bf81, 0x00 }, 197 { 0x3fc2bf80, 0x00 }, 198 { 0x3fc2bfc7, 0x00 }, 199 { 0x3fc2bfc6, 0x00 }, 200 { 0x3fc2bfc5, 0x00 }, 201 { 0x3fc2bfc4, 0x00 }, 202 { 0x3fc2bfc3, 0x00 }, 203 { 0x3fc2bfc2, 0x00 }, 204 { 0x3fc2bfc1, 0x00 }, 205 { 0x3fc2bfc0, 0x03 }, 206 { 0x0000d486, 0x43 }, 207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 208 { 0x1000db00, 0x07 }, 209 { 0x1000db01, 0x00 }, 210 { 0x1000db02, 0x11 }, 211 { 0x1000db03, 0x00 }, 212 { 0x1000db04, 0x00 }, 213 { 0x1000db05, 0x82 }, 214 { 0x1000db06, 0x04 }, 215 { 0x1000db07, 0xf1 }, 216 { 0x1000db08, 0x00 }, 217 { 0x1000db09, 0x00 }, 218 { 0x1000db0a, 0x40 }, 219 { 0x1000db0b, 0x02 }, 220 { 0x1000db0c, 0xf2 }, 221 { 0x1000db0d, 0x00 }, 222 { 0x1000db0e, 0x00 }, 223 { 0x1000db0f, 0xe0 }, 224 { 0x1000db10, 0x00 }, 225 { 0x1000db11, 0x10 }, 226 { 0x1000db12, 0x00 }, 227 { 0x1000db13, 0x00 }, 228 { 0x1000db14, 0x45 }, 229 { 0x1000db15, 0x0d }, 230 { 0x1000db16, 0x01 }, 231 { 0x1000db17, 0x00 }, 232 { 0x1000db18, 0x00 }, 233 { 0x1000db19, 0xbf }, 234 { 0x1000db1a, 0x13 }, 235 { 0x1000db1b, 0x09 }, 236 { 0x1000db1c, 0x00 }, 237 { 0x1000db1d, 0x00 }, 238 { 0x1000db1e, 0x00 }, 239 { 0x1000db1f, 0x12 }, 240 { 0x1000db20, 0x09 }, 241 { 0x1000db21, 0x00 }, 242 { 0x1000db22, 0x00 }, 243 { 0x1000db23, 0x00 }, 244 { 0x0000d540, 0x01 }, 245 { 0x0000c081, 0xfc }, 246 { 0x0000f01e, 0x80 }, 247 { 0xc01b, 0xfc }, 248 { 0xc5d1, 0x89 }, 249 { 0xc5d8, 0x0a }, 250 { 0xc5f7, 0x22 }, 251 { 0xc5f6, 0x22 }, 252 { 0xc065, 0xa5 }, 253 { 0xc06b, 0x0a }, 254 { 0xd172, 0x2a }, 255 { 0xc5d6, 0x01 }, 256 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 257 }; 258 259 static const struct reg_default rt1320_reg_defaults[] = { 260 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 261 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 262 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 263 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 264 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 265 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 266 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 267 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 268 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 269 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 270 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 271 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 272 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 273 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 274 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 275 }; 276 277 static const struct reg_default rt1320_mbq_defaults[] = { 278 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 279 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 280 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 281 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 282 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 283 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 284 }; 285 286 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 287 { 288 switch (reg) { 289 case 0xc000 ... 0xc086: 290 case 0xc400 ... 0xc409: 291 case 0xc480 ... 0xc48f: 292 case 0xc4c0 ... 0xc4c4: 293 case 0xc4e0 ... 0xc4e7: 294 case 0xc500: 295 case 0xc560 ... 0xc56b: 296 case 0xc570: 297 case 0xc580 ... 0xc59a: 298 case 0xc5b0 ... 0xc60f: 299 case 0xc640 ... 0xc64f: 300 case 0xc670: 301 case 0xc680 ... 0xc683: 302 case 0xc700 ... 0xc76f: 303 case 0xc800 ... 0xc801: 304 case 0xc820: 305 case 0xc900 ... 0xc901: 306 case 0xc920 ... 0xc921: 307 case 0xca00 ... 0xca07: 308 case 0xca20 ... 0xca27: 309 case 0xca40 ... 0xca4b: 310 case 0xca60 ... 0xca68: 311 case 0xca80 ... 0xca88: 312 case 0xcb00 ... 0xcb0c: 313 case 0xcc00 ... 0xcc12: 314 case 0xcc80 ... 0xcc81: 315 case 0xcd00: 316 case 0xcd80 ... 0xcd82: 317 case 0xce00 ... 0xce4d: 318 case 0xcf00 ... 0xcf25: 319 case 0xd000 ... 0xd0ff: 320 case 0xd100 ... 0xd1ff: 321 case 0xd200 ... 0xd2ff: 322 case 0xd300 ... 0xd3ff: 323 case 0xd400 ... 0xd403: 324 case 0xd410 ... 0xd417: 325 case 0xd470 ... 0xd497: 326 case 0xd4dc ... 0xd50f: 327 case 0xd520 ... 0xd543: 328 case 0xd560 ... 0xd5ef: 329 case 0xd600 ... 0xd663: 330 case 0xda00 ... 0xda6e: 331 case 0xda80 ... 0xda9e: 332 case 0xdb00 ... 0xdb7f: 333 case 0xdc00: 334 case 0xdc20 ... 0xdc21: 335 case 0xdd00 ... 0xdd17: 336 case 0xde00 ... 0xde09: 337 case 0xdf00 ... 0xdf1b: 338 case 0xe000 ... 0xe847: 339 case 0xf01e: 340 case 0xf717 ... 0xf719: 341 case 0xf720 ... 0xf723: 342 case 0x1000cd91 ... 0x1000cd96: 343 case 0x1000f008: 344 case 0x1000f021: 345 case 0x3fe2e000 ... 0x3fe2e003: 346 case 0x3fc2ab80 ... 0x3fc2abd4: 347 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 348 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 349 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 350 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 351 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 352 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 353 /* 0x40880900/0x40880980 */ 354 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 355 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 356 /* 0x40881500 */ 357 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 358 /* 0x41000189/0x4100018a */ 359 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 360 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 361 /* 0x41001388 */ 362 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 363 /* 0x41001988 */ 364 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 365 /* 0x41080000 */ 366 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 367 /* 0x41080200 */ 368 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 369 /* 0x41080900 */ 370 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 371 /* 0x41080980 */ 372 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 373 /* 0x41081080 */ 374 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 375 /* 0x41081480/0x41081488 */ 376 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 377 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 378 /* 0x41081980 */ 379 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 380 return true; 381 default: 382 return false; 383 } 384 } 385 386 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 387 { 388 switch (reg) { 389 case 0xc000: 390 case 0xc003: 391 case 0xc081: 392 case 0xc402 ... 0xc406: 393 case 0xc48c ... 0xc48f: 394 case 0xc560: 395 case 0xc5b5 ... 0xc5b7: 396 case 0xc5fc ... 0xc5ff: 397 case 0xc820: 398 case 0xc900: 399 case 0xc920: 400 case 0xca42: 401 case 0xca62: 402 case 0xca82: 403 case 0xcd00: 404 case 0xce03: 405 case 0xce10: 406 case 0xce14 ... 0xce17: 407 case 0xce44 ... 0xce49: 408 case 0xce4c ... 0xce4d: 409 case 0xcf0c: 410 case 0xcf10 ... 0xcf25: 411 case 0xd486 ... 0xd487: 412 case 0xd4e5 ... 0xd4e6: 413 case 0xd4e8 ... 0xd4ff: 414 case 0xd530: 415 case 0xd540: 416 case 0xd543: 417 case 0xdb58 ... 0xdb5f: 418 case 0xdb60 ... 0xdb63: 419 case 0xdb68 ... 0xdb69: 420 case 0xdb6d: 421 case 0xdb70 ... 0xdb71: 422 case 0xdb76: 423 case 0xdb7a: 424 case 0xdb7c ... 0xdb7f: 425 case 0xdd0c ... 0xdd13: 426 case 0xde02: 427 case 0xdf14 ... 0xdf1b: 428 case 0xe83c ... 0xe847: 429 case 0xf01e: 430 case 0xf717 ... 0xf719: 431 case 0xf720 ... 0xf723: 432 case 0x10000000 ... 0x10007fff: 433 case 0x1000c000 ... 0x1000dfff: 434 case 0x1000f008: 435 case 0x1000f021: 436 case 0x3fc2ab80 ... 0x3fc2abd4: 437 case 0x3fc2bf80 ... 0x3fc2bf83: 438 case 0x3fc2bfc0 ... 0x3fc2bfc7: 439 case 0x3fe2e000 ... 0x3fe2e003: 440 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 441 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 442 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 443 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 444 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 445 return true; 446 default: 447 return false; 448 } 449 } 450 451 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 452 { 453 switch (reg) { 454 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 455 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 456 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 457 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 458 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 459 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 460 return true; 461 default: 462 return false; 463 } 464 } 465 466 static const struct regmap_config rt1320_sdw_regmap = { 467 .reg_bits = 32, 468 .val_bits = 8, 469 .readable_reg = rt1320_readable_register, 470 .volatile_reg = rt1320_volatile_register, 471 .max_register = 0x41081980, 472 .reg_defaults = rt1320_reg_defaults, 473 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 474 .cache_type = REGCACHE_MAPLE, 475 .use_single_read = true, 476 .use_single_write = true, 477 }; 478 479 static const struct regmap_config rt1320_mbq_regmap = { 480 .name = "sdw-mbq", 481 .reg_bits = 32, 482 .val_bits = 16, 483 .readable_reg = rt1320_mbq_readable_register, 484 .max_register = 0x41000192, 485 .reg_defaults = rt1320_mbq_defaults, 486 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 487 .cache_type = REGCACHE_MAPLE, 488 .use_single_read = true, 489 .use_single_write = true, 490 }; 491 492 static int rt1320_read_prop(struct sdw_slave *slave) 493 { 494 struct sdw_slave_prop *prop = &slave->prop; 495 int nval; 496 int i, j; 497 u32 bit; 498 unsigned long addr; 499 struct sdw_dpn_prop *dpn; 500 501 /* 502 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 503 */ 504 sdw_slave_read_prop(slave); 505 506 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 507 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 508 509 prop->paging_support = true; 510 prop->lane_control_support = true; 511 512 /* first we need to allocate memory for set bits in port lists */ 513 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 514 prop->sink_ports = BIT(1); 515 516 nval = hweight32(prop->source_ports); 517 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 518 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 519 if (!prop->src_dpn_prop) 520 return -ENOMEM; 521 522 i = 0; 523 dpn = prop->src_dpn_prop; 524 addr = prop->source_ports; 525 for_each_set_bit(bit, &addr, 32) { 526 dpn[i].num = bit; 527 dpn[i].type = SDW_DPN_FULL; 528 dpn[i].simple_ch_prep_sm = true; 529 dpn[i].ch_prep_timeout = 10; 530 i++; 531 } 532 533 /* do this again for sink now */ 534 nval = hweight32(prop->sink_ports); 535 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 536 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 537 if (!prop->sink_dpn_prop) 538 return -ENOMEM; 539 540 j = 0; 541 dpn = prop->sink_dpn_prop; 542 addr = prop->sink_ports; 543 for_each_set_bit(bit, &addr, 32) { 544 dpn[j].num = bit; 545 dpn[j].type = SDW_DPN_FULL; 546 dpn[j].simple_ch_prep_sm = true; 547 dpn[j].ch_prep_timeout = 10; 548 j++; 549 } 550 551 /* set the timeout values */ 552 prop->clk_stop_timeout = 64; 553 554 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 555 prop->wake_capable = 0; 556 557 return 0; 558 } 559 560 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 561 unsigned char entity, unsigned char ps) 562 { 563 unsigned int delay = 1000, val; 564 565 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 566 567 /* waiting for Actual PDE becomes to PS0/PS3 */ 568 while (delay) { 569 regmap_read(rt1320->regmap, 570 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 571 if (val == ps) 572 break; 573 574 usleep_range(1000, 1500); 575 delay--; 576 } 577 if (!delay) { 578 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 579 return -ETIMEDOUT; 580 } 581 582 return 0; 583 } 584 585 /* 586 * The 'patch code' is written to the patch code area. 587 * The patch code area is used for SDCA register expansion flexibility. 588 */ 589 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 590 { 591 struct sdw_slave *slave = rt1320->sdw_slave; 592 const struct firmware *patch; 593 const char *filename; 594 unsigned int addr, val; 595 const unsigned char *ptr; 596 int ret, i; 597 598 if (rt1320->version_id <= RT1320_VB) 599 filename = RT1320_VAB_MCU_PATCH; 600 else 601 filename = RT1320_VC_MCU_PATCH; 602 603 /* load the patch code here */ 604 ret = request_firmware(&patch, filename, &slave->dev); 605 if (ret) { 606 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 607 regmap_write(rt1320->regmap, 0xc598, 0x00); 608 regmap_write(rt1320->regmap, 0x10007000, 0x67); 609 regmap_write(rt1320->regmap, 0x10007001, 0x80); 610 regmap_write(rt1320->regmap, 0x10007002, 0x00); 611 regmap_write(rt1320->regmap, 0x10007003, 0x00); 612 } else { 613 ptr = (const unsigned char *)patch->data; 614 if ((patch->size % 8) == 0) { 615 for (i = 0; i < patch->size; i += 8) { 616 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 617 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 618 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 619 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 620 621 if (addr > 0x10007fff || addr < 0x10007000) { 622 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 623 goto _exit_; 624 } 625 if (val > 0xff) { 626 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 627 goto _exit_; 628 } 629 regmap_write(rt1320->regmap, addr, val); 630 } 631 } 632 _exit_: 633 release_firmware(patch); 634 } 635 } 636 637 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 638 { 639 unsigned int i, reg, val, delay; 640 641 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 642 reg = rt1320_blind_write[i].reg; 643 val = rt1320_blind_write[i].def; 644 delay = rt1320_blind_write[i].delay_us; 645 646 if (reg == 0x3fc2bfc7) 647 rt1320_load_mcu_patch(rt1320); 648 649 regmap_write(rt1320->regmap, reg, val); 650 if (delay) 651 usleep_range(delay, delay + 1000); 652 } 653 } 654 655 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 656 { 657 struct sdw_slave *slave = rt1320->sdw_slave; 658 unsigned int i, reg, val, delay, retry, tmp; 659 660 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 661 reg = rt1320_vc_blind_write[i].reg; 662 val = rt1320_vc_blind_write[i].def; 663 delay = rt1320_vc_blind_write[i].delay_us; 664 665 if (reg == 0x3fc2bf83) 666 rt1320_load_mcu_patch(rt1320); 667 668 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 669 (val == 0x00)) { 670 retry = 200; 671 while (retry) { 672 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 673 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 674 if (tmp == 0x1f) 675 break; 676 usleep_range(1000, 1500); 677 retry--; 678 } 679 if (!retry) 680 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 681 } 682 regmap_write(rt1320->regmap, reg, val); 683 if (delay) 684 usleep_range(delay, delay + 1000); 685 686 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 687 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 688 } 689 } 690 691 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 692 { 693 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 694 unsigned int amp_func_status, val, tmp; 695 696 if (rt1320->hw_init) 697 return 0; 698 699 regcache_cache_only(rt1320->regmap, false); 700 regcache_cache_only(rt1320->mbq_regmap, false); 701 if (rt1320->first_hw_init) { 702 regcache_cache_bypass(rt1320->regmap, true); 703 regcache_cache_bypass(rt1320->mbq_regmap, true); 704 } else { 705 /* 706 * PM runtime status is marked as 'active' only when a Slave reports as Attached 707 */ 708 /* update count of parent 'active' children */ 709 pm_runtime_set_active(&slave->dev); 710 } 711 712 pm_runtime_get_noresume(&slave->dev); 713 714 if (rt1320->version_id < 0) { 715 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 716 rt1320->version_id = val; 717 } 718 719 regmap_read(rt1320->regmap, 720 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 721 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 722 723 /* initialization write */ 724 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 725 if (rt1320->version_id < RT1320_VC) 726 rt1320_vab_preset(rt1320); 727 else 728 rt1320_vc_preset(rt1320); 729 730 regmap_write(rt1320->regmap, 731 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 732 FUNCTION_NEEDS_INITIALIZATION); 733 } 734 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 735 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 736 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 737 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 738 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 739 val = (tmp << 8) | val; 740 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 741 val = (tmp << 16) | val; 742 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 743 val = (tmp << 24) | val; 744 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 745 /* 746 * We call the version b which has the new DSP ROM code against version a. 747 * Therefore, we read the DSP address to check the ID. 748 */ 749 if (val == RT1320_VER_B_ID) 750 rt1320->version_id = RT1320_VB; 751 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 752 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 753 } 754 dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 755 756 if (rt1320->first_hw_init) { 757 regcache_cache_bypass(rt1320->regmap, false); 758 regcache_cache_bypass(rt1320->mbq_regmap, false); 759 regcache_mark_dirty(rt1320->regmap); 760 regcache_mark_dirty(rt1320->mbq_regmap); 761 } 762 763 /* Mark Slave initialization complete */ 764 rt1320->first_hw_init = true; 765 rt1320->hw_init = true; 766 767 pm_runtime_put_autosuspend(&slave->dev); 768 769 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 770 return 0; 771 } 772 773 static int rt1320_update_status(struct sdw_slave *slave, 774 enum sdw_slave_status status) 775 { 776 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 777 778 if (status == SDW_SLAVE_UNATTACHED) 779 rt1320->hw_init = false; 780 781 /* 782 * Perform initialization only if slave status is present and 783 * hw_init flag is false 784 */ 785 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 786 return 0; 787 788 /* perform I/O transfers required for Slave initialization */ 789 return rt1320_io_init(&slave->dev, slave); 790 } 791 792 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 793 struct snd_kcontrol *kcontrol, int event) 794 { 795 struct snd_soc_component *component = 796 snd_soc_dapm_to_component(w->dapm); 797 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 798 unsigned char ps0 = 0x0, ps3 = 0x3; 799 800 switch (event) { 801 case SND_SOC_DAPM_POST_PMU: 802 regmap_write(rt1320->regmap, 803 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 804 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 805 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 806 break; 807 case SND_SOC_DAPM_PRE_PMD: 808 regmap_write(rt1320->regmap, 809 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 810 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 811 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 812 break; 813 default: 814 break; 815 } 816 817 return 0; 818 } 819 820 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 821 struct snd_kcontrol *kcontrol, int event) 822 { 823 struct snd_soc_component *component = 824 snd_soc_dapm_to_component(w->dapm); 825 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 826 unsigned char ps0 = 0x0, ps3 = 0x3; 827 828 switch (event) { 829 case SND_SOC_DAPM_POST_PMU: 830 regmap_write(rt1320->regmap, 831 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 832 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 833 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 834 break; 835 case SND_SOC_DAPM_PRE_PMD: 836 regmap_write(rt1320->regmap, 837 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 838 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 839 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 840 break; 841 default: 842 break; 843 } 844 845 return 0; 846 } 847 848 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 849 struct snd_ctl_elem_value *ucontrol) 850 { 851 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 852 struct soc_mixer_control *mc = 853 (struct soc_mixer_control *)kcontrol->private_value; 854 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 855 unsigned int gain_l_val, gain_r_val; 856 unsigned int lvalue, rvalue; 857 const unsigned int interval_offset = 0xc0; 858 unsigned int changed = 0, reg_base; 859 struct rt_sdca_dmic_kctrl_priv *p; 860 unsigned int regvalue[4], gain_val[4], i; 861 int err; 862 863 if (strstr(ucontrol->id.name, "FU Capture Volume")) 864 goto _dmic_vol_; 865 866 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 867 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 868 869 /* L Channel */ 870 gain_l_val = ucontrol->value.integer.value[0]; 871 if (gain_l_val > mc->max) 872 gain_l_val = mc->max; 873 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 874 gain_l_val &= 0xffff; 875 876 /* R Channel */ 877 gain_r_val = ucontrol->value.integer.value[1]; 878 if (gain_r_val > mc->max) 879 gain_r_val = mc->max; 880 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 881 gain_r_val &= 0xffff; 882 883 if (lvalue == gain_l_val && rvalue == gain_r_val) 884 return 0; 885 886 /* Lch*/ 887 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 888 /* Rch */ 889 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 890 goto _done_; 891 892 _dmic_vol_: 893 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 894 895 /* check all channels */ 896 for (i = 0; i < p->count; i++) { 897 if (i < 2) { 898 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 899 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 900 } else { 901 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 902 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 903 } 904 905 gain_val[i] = ucontrol->value.integer.value[i]; 906 if (gain_val[i] > p->max) 907 gain_val[i] = p->max; 908 909 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 910 gain_val[i] &= 0xffff; 911 if (regvalue[i] != gain_val[i]) 912 changed = 1; 913 } 914 915 if (!changed) 916 return 0; 917 918 for (i = 0; i < p->count; i++) { 919 if (i < 2) { 920 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 921 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 922 } else { 923 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 924 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 925 } 926 927 if (err < 0) 928 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 929 } 930 931 _done_: 932 return 1; 933 } 934 935 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 936 struct snd_ctl_elem_value *ucontrol) 937 { 938 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 939 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 940 struct soc_mixer_control *mc = 941 (struct soc_mixer_control *)kcontrol->private_value; 942 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 943 const unsigned int interval_offset = 0xc0; 944 unsigned int reg_base, regvalue, ctl, i; 945 struct rt_sdca_dmic_kctrl_priv *p; 946 947 if (strstr(ucontrol->id.name, "FU Capture Volume")) 948 goto _dmic_vol_; 949 950 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 951 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 952 953 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 954 955 if (read_l != read_r) 956 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 957 else 958 ctl_r = ctl_l; 959 960 ucontrol->value.integer.value[0] = ctl_l; 961 ucontrol->value.integer.value[1] = ctl_r; 962 goto _done_; 963 964 _dmic_vol_: 965 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 966 967 /* check all channels */ 968 for (i = 0; i < p->count; i++) { 969 if (i < 2) { 970 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 971 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 972 } else { 973 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 974 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 975 } 976 977 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 978 ucontrol->value.integer.value[i] = ctl; 979 } 980 _done_: 981 return 0; 982 } 983 984 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 985 { 986 int err, i; 987 unsigned int ch_mute; 988 989 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 990 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 991 992 if (i < 2) 993 err = regmap_write(rt1320->regmap, 994 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 995 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 996 else 997 err = regmap_write(rt1320->regmap, 998 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 999 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 1000 if (err < 0) 1001 return err; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 1008 struct snd_ctl_elem_value *ucontrol) 1009 { 1010 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1011 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1012 struct rt_sdca_dmic_kctrl_priv *p = 1013 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1014 unsigned int i; 1015 1016 for (i = 0; i < p->count; i++) 1017 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 1018 1019 return 0; 1020 } 1021 1022 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 1023 struct snd_ctl_elem_value *ucontrol) 1024 { 1025 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1026 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1027 struct rt_sdca_dmic_kctrl_priv *p = 1028 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1029 int err, changed = 0, i; 1030 1031 for (i = 0; i < p->count; i++) { 1032 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 1033 changed = 1; 1034 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 1035 } 1036 1037 err = rt1320_set_fu_capture_ctl(rt1320); 1038 if (err < 0) 1039 return err; 1040 1041 return changed; 1042 } 1043 1044 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 1045 struct snd_ctl_elem_info *uinfo) 1046 { 1047 struct rt_sdca_dmic_kctrl_priv *p = 1048 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1049 1050 if (p->max == 1) 1051 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1052 else 1053 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1054 uinfo->count = p->count; 1055 uinfo->value.integer.min = 0; 1056 uinfo->value.integer.max = p->max; 1057 return 0; 1058 } 1059 1060 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 1061 struct snd_kcontrol *kcontrol, int event) 1062 { 1063 struct snd_soc_component *component = 1064 snd_soc_dapm_to_component(w->dapm); 1065 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1066 1067 switch (event) { 1068 case SND_SOC_DAPM_POST_PMU: 1069 rt1320->fu_dapm_mute = false; 1070 rt1320_set_fu_capture_ctl(rt1320); 1071 break; 1072 case SND_SOC_DAPM_PRE_PMD: 1073 rt1320->fu_dapm_mute = true; 1074 rt1320_set_fu_capture_ctl(rt1320); 1075 break; 1076 } 1077 return 0; 1078 } 1079 1080 static const char * const rt1320_rx_data_ch_select[] = { 1081 "L,R", 1082 "R,L", 1083 "L,L", 1084 "R,R", 1085 "L,L+R", 1086 "R,L+R", 1087 "L+R,L", 1088 "L+R,R", 1089 "L+R,L+R", 1090 }; 1091 1092 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 1093 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 1094 rt1320_rx_data_ch_select); 1095 1096 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1097 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 1098 1099 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 1100 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 1101 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1102 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 1103 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 1104 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 1105 1106 RT_SDCA_FU_CTRL("FU Capture Switch", 1107 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1108 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 1109 RT_SDCA_EXT_TLV("FU Capture Volume", 1110 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1111 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 1112 }; 1113 1114 static const struct snd_kcontrol_new rt1320_spk_l_dac = 1115 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1116 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1117 0, 1, 1); 1118 static const struct snd_kcontrol_new rt1320_spk_r_dac = 1119 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1120 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 1121 0, 1, 1); 1122 1123 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 1124 /* Audio Interface */ 1125 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 1126 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 1127 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 1128 1129 /* Digital Interface */ 1130 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 1131 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1132 rt1320_pde23_event, 1133 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1134 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1135 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1136 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 1137 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 1138 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 1139 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1140 1141 /* Output */ 1142 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 1143 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 1144 SND_SOC_DAPM_OUTPUT("SPOL"), 1145 SND_SOC_DAPM_OUTPUT("SPOR"), 1146 1147 /* Input */ 1148 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 1149 SND_SOC_DAPM_SIGGEN("AEC Gen"), 1150 SND_SOC_DAPM_INPUT("DMIC1"), 1151 SND_SOC_DAPM_INPUT("DMIC2"), 1152 }; 1153 1154 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 1155 { "FU21", NULL, "DP1RX" }, 1156 { "FU21", NULL, "PDE 23" }, 1157 { "OT23 L", "Switch", "FU21" }, 1158 { "OT23 R", "Switch", "FU21" }, 1159 { "SPOL", NULL, "OT23 L" }, 1160 { "SPOR", NULL, "OT23 R" }, 1161 1162 { "AEC Data", NULL, "AEC Gen" }, 1163 { "DP4TX", NULL, "AEC Data" }, 1164 1165 {"DP8-10TX", NULL, "FU"}, 1166 {"FU", NULL, "PDE 11"}, 1167 {"FU", NULL, "FU 113"}, 1168 {"FU", NULL, "FU 14"}, 1169 {"FU 113", NULL, "DMIC1"}, 1170 {"FU 14", NULL, "DMIC2"}, 1171 }; 1172 1173 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1174 int direction) 1175 { 1176 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1177 return 0; 1178 } 1179 1180 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 1181 struct snd_soc_dai *dai) 1182 { 1183 snd_soc_dai_set_dma_data(dai, substream, NULL); 1184 } 1185 1186 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 1187 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1188 { 1189 struct snd_soc_component *component = dai->component; 1190 struct rt1320_sdw_priv *rt1320 = 1191 snd_soc_component_get_drvdata(component); 1192 struct sdw_stream_config stream_config; 1193 struct sdw_port_config port_config; 1194 struct sdw_port_config dmic_port_config[2]; 1195 struct sdw_stream_runtime *sdw_stream; 1196 int retval; 1197 unsigned int sampling_rate; 1198 1199 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1200 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1201 1202 if (!sdw_stream) 1203 return -EINVAL; 1204 1205 if (!rt1320->sdw_slave) 1206 return -EINVAL; 1207 1208 /* SoundWire specific configuration */ 1209 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 1210 1211 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1212 if (dai->id == RT1320_AIF1) 1213 port_config.num = 1; 1214 else 1215 return -EINVAL; 1216 } else { 1217 if (dai->id == RT1320_AIF1) 1218 port_config.num = 4; 1219 else if (dai->id == RT1320_AIF2) { 1220 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1221 dmic_port_config[0].num = 8; 1222 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1223 dmic_port_config[1].num = 10; 1224 } else 1225 return -EINVAL; 1226 } 1227 1228 if (dai->id == RT1320_AIF1) 1229 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1230 &port_config, 1, sdw_stream); 1231 else if (dai->id == RT1320_AIF2) 1232 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1233 dmic_port_config, 2, sdw_stream); 1234 else 1235 return -EINVAL; 1236 if (retval) { 1237 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1238 return retval; 1239 } 1240 1241 /* sampling rate configuration */ 1242 switch (params_rate(params)) { 1243 case 16000: 1244 sampling_rate = RT1320_SDCA_RATE_16000HZ; 1245 break; 1246 case 32000: 1247 sampling_rate = RT1320_SDCA_RATE_32000HZ; 1248 break; 1249 case 44100: 1250 sampling_rate = RT1320_SDCA_RATE_44100HZ; 1251 break; 1252 case 48000: 1253 sampling_rate = RT1320_SDCA_RATE_48000HZ; 1254 break; 1255 case 96000: 1256 sampling_rate = RT1320_SDCA_RATE_96000HZ; 1257 break; 1258 case 192000: 1259 sampling_rate = RT1320_SDCA_RATE_192000HZ; 1260 break; 1261 default: 1262 dev_err(component->dev, "%s: Rate %d is not supported\n", 1263 __func__, params_rate(params)); 1264 return -EINVAL; 1265 } 1266 1267 /* set sampling frequency */ 1268 if (dai->id == RT1320_AIF1) 1269 regmap_write(rt1320->regmap, 1270 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1271 sampling_rate); 1272 else { 1273 regmap_write(rt1320->regmap, 1274 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1275 sampling_rate); 1276 regmap_write(rt1320->regmap, 1277 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1278 sampling_rate); 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 1285 struct snd_soc_dai *dai) 1286 { 1287 struct snd_soc_component *component = dai->component; 1288 struct rt1320_sdw_priv *rt1320 = 1289 snd_soc_component_get_drvdata(component); 1290 struct sdw_stream_runtime *sdw_stream = 1291 snd_soc_dai_get_dma_data(dai, substream); 1292 1293 if (!rt1320->sdw_slave) 1294 return -EINVAL; 1295 1296 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1297 return 0; 1298 } 1299 1300 /* 1301 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1302 * port_prep are not defined for now 1303 */ 1304 static const struct sdw_slave_ops rt1320_slave_ops = { 1305 .read_prop = rt1320_read_prop, 1306 .update_status = rt1320_update_status, 1307 }; 1308 1309 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1310 { 1311 int ret; 1312 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1313 1314 rt1320->component = component; 1315 1316 if (!rt1320->first_hw_init) 1317 return 0; 1318 1319 ret = pm_runtime_resume(component->dev); 1320 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1321 if (ret < 0 && ret != -EACCES) 1322 return ret; 1323 1324 return 0; 1325 } 1326 1327 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1328 .probe = rt1320_sdw_component_probe, 1329 .controls = rt1320_snd_controls, 1330 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1331 .dapm_widgets = rt1320_dapm_widgets, 1332 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1333 .dapm_routes = rt1320_dapm_routes, 1334 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1335 .endianness = 1, 1336 }; 1337 1338 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1339 .hw_params = rt1320_sdw_hw_params, 1340 .hw_free = rt1320_sdw_pcm_hw_free, 1341 .set_stream = rt1320_set_sdw_stream, 1342 .shutdown = rt1320_sdw_shutdown, 1343 }; 1344 1345 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1346 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1347 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1348 SNDRV_PCM_FMTBIT_S32_LE) 1349 1350 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1351 { 1352 .name = "rt1320-aif1", 1353 .id = RT1320_AIF1, 1354 .playback = { 1355 .stream_name = "DP1 Playback", 1356 .channels_min = 1, 1357 .channels_max = 2, 1358 .rates = RT1320_STEREO_RATES, 1359 .formats = RT1320_FORMATS, 1360 }, 1361 .capture = { 1362 .stream_name = "DP4 Capture", 1363 .channels_min = 1, 1364 .channels_max = 2, 1365 .rates = RT1320_STEREO_RATES, 1366 .formats = RT1320_FORMATS, 1367 }, 1368 .ops = &rt1320_aif_dai_ops, 1369 }, 1370 /* DMIC: DP8 2ch + DP10 2ch */ 1371 { 1372 .name = "rt1320-aif2", 1373 .id = RT1320_AIF2, 1374 .capture = { 1375 .stream_name = "DP8-10 Capture", 1376 .channels_min = 1, 1377 .channels_max = 4, 1378 .rates = RT1320_STEREO_RATES, 1379 .formats = RT1320_FORMATS, 1380 }, 1381 .ops = &rt1320_aif_dai_ops, 1382 }, 1383 }; 1384 1385 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1386 struct regmap *mbq_regmap, struct sdw_slave *slave) 1387 { 1388 struct rt1320_sdw_priv *rt1320; 1389 int ret; 1390 1391 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1392 if (!rt1320) 1393 return -ENOMEM; 1394 1395 dev_set_drvdata(dev, rt1320); 1396 rt1320->sdw_slave = slave; 1397 rt1320->mbq_regmap = mbq_regmap; 1398 rt1320->regmap = regmap; 1399 1400 regcache_cache_only(rt1320->regmap, true); 1401 regcache_cache_only(rt1320->mbq_regmap, true); 1402 1403 /* 1404 * Mark hw_init to false 1405 * HW init will be performed when device reports present 1406 */ 1407 rt1320->hw_init = false; 1408 rt1320->first_hw_init = false; 1409 rt1320->version_id = -1; 1410 rt1320->fu_dapm_mute = true; 1411 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 1412 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 1413 1414 ret = devm_snd_soc_register_component(dev, 1415 &soc_component_sdw_rt1320, 1416 rt1320_sdw_dai, 1417 ARRAY_SIZE(rt1320_sdw_dai)); 1418 if (ret < 0) 1419 return ret; 1420 1421 /* set autosuspend parameters */ 1422 pm_runtime_set_autosuspend_delay(dev, 3000); 1423 pm_runtime_use_autosuspend(dev); 1424 1425 /* make sure the device does not suspend immediately */ 1426 pm_runtime_mark_last_busy(dev); 1427 1428 pm_runtime_enable(dev); 1429 1430 /* important note: the device is NOT tagged as 'active' and will remain 1431 * 'suspended' until the hardware is enumerated/initialized. This is required 1432 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1433 * fail with -EACCESS because of race conditions between card creation and enumeration 1434 */ 1435 1436 dev_dbg(dev, "%s\n", __func__); 1437 1438 return ret; 1439 } 1440 1441 static int rt1320_sdw_probe(struct sdw_slave *slave, 1442 const struct sdw_device_id *id) 1443 { 1444 struct regmap *regmap, *mbq_regmap; 1445 1446 /* Regmap Initialization */ 1447 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1448 if (IS_ERR(mbq_regmap)) 1449 return PTR_ERR(mbq_regmap); 1450 1451 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1452 if (IS_ERR(regmap)) 1453 return PTR_ERR(regmap); 1454 1455 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1456 } 1457 1458 static int rt1320_sdw_remove(struct sdw_slave *slave) 1459 { 1460 pm_runtime_disable(&slave->dev); 1461 1462 return 0; 1463 } 1464 1465 /* 1466 * Version A/B will use the class id 0 1467 * The newer version than A/B will use the class id 1, so add it in advance 1468 */ 1469 static const struct sdw_device_id rt1320_id[] = { 1470 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1471 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1472 {}, 1473 }; 1474 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1475 1476 static int rt1320_dev_suspend(struct device *dev) 1477 { 1478 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1479 1480 if (!rt1320->hw_init) 1481 return 0; 1482 1483 regcache_cache_only(rt1320->regmap, true); 1484 regcache_cache_only(rt1320->mbq_regmap, true); 1485 return 0; 1486 } 1487 1488 #define RT1320_PROBE_TIMEOUT 5000 1489 1490 static int rt1320_dev_resume(struct device *dev) 1491 { 1492 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1493 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1494 unsigned long time; 1495 1496 if (!rt1320->first_hw_init) 1497 return 0; 1498 1499 if (!slave->unattach_request) 1500 goto regmap_sync; 1501 1502 time = wait_for_completion_timeout(&slave->initialization_complete, 1503 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1504 if (!time) { 1505 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1506 return -ETIMEDOUT; 1507 } 1508 1509 regmap_sync: 1510 slave->unattach_request = 0; 1511 regcache_cache_only(rt1320->regmap, false); 1512 regcache_sync(rt1320->regmap); 1513 regcache_cache_only(rt1320->mbq_regmap, false); 1514 regcache_sync(rt1320->mbq_regmap); 1515 return 0; 1516 } 1517 1518 static const struct dev_pm_ops rt1320_pm = { 1519 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1520 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1521 }; 1522 1523 static struct sdw_driver rt1320_sdw_driver = { 1524 .driver = { 1525 .name = "rt1320-sdca", 1526 .pm = pm_ptr(&rt1320_pm), 1527 }, 1528 .probe = rt1320_sdw_probe, 1529 .remove = rt1320_sdw_remove, 1530 .ops = &rt1320_slave_ops, 1531 .id_table = rt1320_id, 1532 }; 1533 module_sdw_driver(rt1320_sdw_driver); 1534 1535 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1536 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1537 MODULE_LICENSE("GPL"); 1538