1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 /* 25 * The default cluster table is based on the assumption that the PLLCA55 clock 26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 27 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 28 * clocked to 1.8GHz as well). The table below should be overridden in the board 29 * DTS based on the PLLCA55 clock frequency. 30 */ 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 34 opp-1700000000 { 35 opp-hz = /bits/ 64 <1700000000>; 36 opp-microvolt = <900000>; 37 clock-latency-ns = <300000>; 38 }; 39 opp-850000000 { 40 opp-hz = /bits/ 64 <850000000>; 41 opp-microvolt = <800000>; 42 clock-latency-ns = <300000>; 43 }; 44 opp-425000000 { 45 opp-hz = /bits/ 64 <425000000>; 46 opp-microvolt = <800000>; 47 clock-latency-ns = <300000>; 48 }; 49 opp-212500000 { 50 opp-hz = /bits/ 64 <212500000>; 51 opp-microvolt = <800000>; 52 clock-latency-ns = <300000>; 53 opp-suspend; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 compatible = "arm,cortex-a55"; 63 reg = <0>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu1: cpu@100 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x100>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu2: cpu@200 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x200>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 cpu3: cpu@300 { 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 device_type = "cpu"; 98 next-level-cache = <&L3_CA55>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 101 #cooling-cells = <2>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 L3_CA55: cache-controller-0 { 106 compatible = "cache"; 107 cache-unified; 108 cache-size = <0x100000>; 109 cache-level = <3>; 110 }; 111 }; 112 113 gpu_opp_table: opp-table-1 { 114 compatible = "operating-points-v2"; 115 116 opp-630000000 { 117 opp-hz = /bits/ 64 <630000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-315000000 { 122 opp-hz = /bits/ 64 <315000000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-157500000 { 127 opp-hz = /bits/ 64 <157500000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-78750000 { 132 opp-hz = /bits/ 64 <78750000>; 133 opp-microvolt = <800000>; 134 }; 135 136 opp-19687500 { 137 opp-hz = /bits/ 64 <19687500>; 138 opp-microvolt = <800000>; 139 }; 140 }; 141 142 pmu { 143 compatible = "arm,cortex-a55-pmu"; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0", "arm,psci-0.2"; 149 method = "smc"; 150 }; 151 152 qextal_clk: qextal-clk { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 /* This value must be overridden by the board */ 156 clock-frequency = <0>; 157 }; 158 159 rtxin_clk: rtxin-clk { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 /* This value must be overridden by the board */ 163 clock-frequency = <0>; 164 }; 165 166 soc: soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 icu: interrupt-controller@10400000 { 173 compatible = "renesas,r9a09g057-icu"; 174 reg = <0 0x10400000 0 0x10000>; 175 #interrupt-cells = <2>; 176 #address-cells = <0>; 177 interrupt-controller; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "nmi", 237 "port_irq0", "port_irq1", "port_irq2", 238 "port_irq3", "port_irq4", "port_irq5", 239 "port_irq6", "port_irq7", "port_irq8", 240 "port_irq9", "port_irq10", "port_irq11", 241 "port_irq12", "port_irq13", "port_irq14", 242 "port_irq15", 243 "tint0", "tint1", "tint2", "tint3", 244 "tint4", "tint5", "tint6", "tint7", 245 "tint8", "tint9", "tint10", "tint11", 246 "tint12", "tint13", "tint14", "tint15", 247 "tint16", "tint17", "tint18", "tint19", 248 "tint20", "tint21", "tint22", "tint23", 249 "tint24", "tint25", "tint26", "tint27", 250 "tint28", "tint29", "tint30", "tint31", 251 "int-ca55-0", "int-ca55-1", 252 "int-ca55-2", "int-ca55-3", 253 "icu-error-ca55", 254 "gpt-u0-gtciada", "gpt-u0-gtciadb", 255 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 256 clocks = <&cpg CPG_MOD 0x5>; 257 power-domains = <&cpg>; 258 resets = <&cpg 0x36>; 259 }; 260 261 pinctrl: pinctrl@10410000 { 262 compatible = "renesas,r9a09g057-pinctrl"; 263 reg = <0 0x10410000 0 0x10000>; 264 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 gpio-ranges = <&pinctrl 0 0 96>; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 interrupt-parent = <&icu>; 271 power-domains = <&cpg>; 272 resets = <&cpg 0xa5>, <&cpg 0xa6>; 273 }; 274 275 cpg: clock-controller@10420000 { 276 compatible = "renesas,r9a09g057-cpg"; 277 reg = <0 0x10420000 0 0x10000>; 278 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 279 clock-names = "audio_extal", "rtxin", "qextal"; 280 #clock-cells = <2>; 281 #reset-cells = <1>; 282 #power-domain-cells = <0>; 283 }; 284 285 sys: system-controller@10430000 { 286 compatible = "renesas,r9a09g057-sys"; 287 reg = <0 0x10430000 0 0x10000>; 288 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 289 resets = <&cpg 0x30>; 290 }; 291 292 tsu0: thermal@11000000 { 293 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 294 reg = <0 0x11000000 0 0x1000>; 295 interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "adi", "adcmpi"; 298 clocks = <&cpg CPG_MOD 0x109>; 299 resets = <&cpg 0xf7>; 300 power-domains = <&cpg>; 301 #thermal-sensor-cells = <0>; 302 renesas,tsu-trim = <&sys 0x320>; 303 }; 304 305 tsu1: thermal@14002000 { 306 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 307 reg = <0 0x14002000 0 0x1000>; 308 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "adi", "adcmpi"; 311 clocks = <&cpg CPG_MOD 0x10a>; 312 resets = <&cpg 0xf8>; 313 power-domains = <&cpg>; 314 #thermal-sensor-cells = <0>; 315 renesas,tsu-trim = <&sys 0x330>; 316 }; 317 318 xspi: spi@11030000 { 319 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 320 reg = <0 0x11030000 0 0x10000>, 321 <0 0x20000000 0 0x10000000>; 322 reg-names = "regs", "dirmap"; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 325 interrupt-names = "pulse", "err_pulse"; 326 clocks = <&cpg CPG_MOD 0x9f>, 327 <&cpg CPG_MOD 0xa0>, 328 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 329 <&cpg CPG_MOD 0xa1>; 330 clock-names = "ahb", "axi", "spi", "spix2"; 331 resets = <&cpg 0xa3>, <&cpg 0xa4>; 332 reset-names = "hresetn", "aresetn"; 333 power-domains = <&cpg>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 dmac0: dma-controller@11400000 { 340 compatible = "renesas,r9a09g057-dmac"; 341 reg = <0 0x11400000 0 0x10000>; 342 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 359 interrupt-names = "error", 360 "ch0", "ch1", "ch2", "ch3", 361 "ch4", "ch5", "ch6", "ch7", 362 "ch8", "ch9", "ch10", "ch11", 363 "ch12", "ch13", "ch14", "ch15"; 364 clocks = <&cpg CPG_MOD 0x0>; 365 power-domains = <&cpg>; 366 resets = <&cpg 0x31>; 367 #dma-cells = <1>; 368 dma-channels = <16>; 369 renesas,icu = <&icu 4>; 370 }; 371 372 dmac1: dma-controller@14830000 { 373 compatible = "renesas,r9a09g057-dmac"; 374 reg = <0 0x14830000 0 0x10000>; 375 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 392 interrupt-names = "error", 393 "ch0", "ch1", "ch2", "ch3", 394 "ch4", "ch5", "ch6", "ch7", 395 "ch8", "ch9", "ch10", "ch11", 396 "ch12", "ch13", "ch14", "ch15"; 397 clocks = <&cpg CPG_MOD 0x1>; 398 power-domains = <&cpg>; 399 resets = <&cpg 0x32>; 400 #dma-cells = <1>; 401 dma-channels = <16>; 402 renesas,icu = <&icu 0>; 403 }; 404 405 dmac2: dma-controller@14840000 { 406 compatible = "renesas,r9a09g057-dmac"; 407 reg = <0 0x14840000 0 0x10000>; 408 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 425 interrupt-names = "error", 426 "ch0", "ch1", "ch2", "ch3", 427 "ch4", "ch5", "ch6", "ch7", 428 "ch8", "ch9", "ch10", "ch11", 429 "ch12", "ch13", "ch14", "ch15"; 430 clocks = <&cpg CPG_MOD 0x2>; 431 power-domains = <&cpg>; 432 resets = <&cpg 0x33>; 433 #dma-cells = <1>; 434 dma-channels = <16>; 435 renesas,icu = <&icu 1>; 436 }; 437 438 dmac3: dma-controller@12000000 { 439 compatible = "renesas,r9a09g057-dmac"; 440 reg = <0 0x12000000 0 0x10000>; 441 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 458 interrupt-names = "error", 459 "ch0", "ch1", "ch2", "ch3", 460 "ch4", "ch5", "ch6", "ch7", 461 "ch8", "ch9", "ch10", "ch11", 462 "ch12", "ch13", "ch14", "ch15"; 463 clocks = <&cpg CPG_MOD 0x3>; 464 power-domains = <&cpg>; 465 resets = <&cpg 0x34>; 466 #dma-cells = <1>; 467 dma-channels = <16>; 468 renesas,icu = <&icu 2>; 469 }; 470 471 dmac4: dma-controller@12010000 { 472 compatible = "renesas,r9a09g057-dmac"; 473 reg = <0 0x12010000 0 0x10000>; 474 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 491 interrupt-names = "error", 492 "ch0", "ch1", "ch2", "ch3", 493 "ch4", "ch5", "ch6", "ch7", 494 "ch8", "ch9", "ch10", "ch11", 495 "ch12", "ch13", "ch14", "ch15"; 496 clocks = <&cpg CPG_MOD 0x4>; 497 power-domains = <&cpg>; 498 resets = <&cpg 0x35>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 3>; 502 }; 503 504 ostm0: timer@11800000 { 505 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 506 reg = <0x0 0x11800000 0x0 0x1000>; 507 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 508 clocks = <&cpg CPG_MOD 0x43>; 509 resets = <&cpg 0x6d>; 510 power-domains = <&cpg>; 511 status = "disabled"; 512 }; 513 514 ostm1: timer@11801000 { 515 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 516 reg = <0x0 0x11801000 0x0 0x1000>; 517 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 518 clocks = <&cpg CPG_MOD 0x44>; 519 resets = <&cpg 0x6e>; 520 power-domains = <&cpg>; 521 status = "disabled"; 522 }; 523 524 ostm2: timer@14000000 { 525 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 526 reg = <0x0 0x14000000 0x0 0x1000>; 527 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 528 clocks = <&cpg CPG_MOD 0x45>; 529 resets = <&cpg 0x6f>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 }; 533 534 ostm3: timer@14001000 { 535 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 536 reg = <0x0 0x14001000 0x0 0x1000>; 537 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 538 clocks = <&cpg CPG_MOD 0x46>; 539 resets = <&cpg 0x70>; 540 power-domains = <&cpg>; 541 status = "disabled"; 542 }; 543 544 ostm4: timer@12c00000 { 545 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 546 reg = <0x0 0x12c00000 0x0 0x1000>; 547 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 548 clocks = <&cpg CPG_MOD 0x47>; 549 resets = <&cpg 0x71>; 550 power-domains = <&cpg>; 551 status = "disabled"; 552 }; 553 554 ostm5: timer@12c01000 { 555 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 556 reg = <0x0 0x12c01000 0x0 0x1000>; 557 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 558 clocks = <&cpg CPG_MOD 0x48>; 559 resets = <&cpg 0x72>; 560 power-domains = <&cpg>; 561 status = "disabled"; 562 }; 563 564 ostm6: timer@12c02000 { 565 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 566 reg = <0x0 0x12c02000 0x0 0x1000>; 567 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 568 clocks = <&cpg CPG_MOD 0x49>; 569 resets = <&cpg 0x73>; 570 power-domains = <&cpg>; 571 status = "disabled"; 572 }; 573 574 ostm7: timer@12c03000 { 575 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 576 reg = <0x0 0x12c03000 0x0 0x1000>; 577 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 578 clocks = <&cpg CPG_MOD 0x4a>; 579 resets = <&cpg 0x74>; 580 power-domains = <&cpg>; 581 status = "disabled"; 582 }; 583 584 wdt1: watchdog@14400000 { 585 compatible = "renesas,r9a09g057-wdt"; 586 reg = <0 0x14400000 0 0x400>; 587 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 588 clock-names = "pclk", "oscclk"; 589 resets = <&cpg 0x76>; 590 power-domains = <&cpg>; 591 status = "disabled"; 592 }; 593 594 rtc: rtc@11c00800 { 595 compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; 596 reg = <0 0x11c00800 0 0x400>; 597 interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>, 598 <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>, 599 <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>; 600 interrupt-names = "alarm", "period", "carry"; 601 clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; 602 clock-names = "bus", "counter"; 603 power-domains = <&cpg>; 604 resets = <&cpg 0x79>, <&cpg 0x7a>; 605 reset-names = "rtc", "rtest"; 606 status = "disabled"; 607 }; 608 609 scif: serial@11c01400 { 610 compatible = "renesas,scif-r9a09g057"; 611 reg = <0 0x11c01400 0 0x400>; 612 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 621 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 622 "tei", "tei-dri", "rxi-edge", "txi-edge"; 623 clocks = <&cpg CPG_MOD 0x8f>; 624 clock-names = "fck"; 625 power-domains = <&cpg>; 626 resets = <&cpg 0x95>; 627 status = "disabled"; 628 }; 629 630 i3c: i3c@12400000 { 631 compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; 632 reg = <0 0x12400000 0 0x10000>; 633 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 634 clock-names = "pclk", "tclk", "pclkrw"; 635 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 639 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 640 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 641 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 642 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 643 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 644 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "ierr", "terr", "abort", "resp", 652 "cmd", "ibi", "rx", "tx", "rcv", 653 "st", "sp", "tend", "nack", 654 "al", "tmo", "wu"; 655 resets = <&cpg 0x96>, <&cpg 0x97>; 656 reset-names = "presetn", "tresetn"; 657 power-domains = <&cpg>; 658 #address-cells = <3>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 canfd: can@12440000 { 664 compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd"; 665 reg = <0 0x12440000 0 0x40000>; 666 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 686 interrupt-names = "g_err", "g_recc", 687 "ch0_err", "ch0_rec", "ch0_trx", 688 "ch1_err", "ch1_rec", "ch1_trx", 689 "ch2_err", "ch2_rec", "ch2_trx", 690 "ch3_err", "ch3_rec", "ch3_trx", 691 "ch4_err", "ch4_rec", "ch4_trx", 692 "ch5_err", "ch5_rec", "ch5_trx"; 693 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 694 <&cpg CPG_MOD 0x9e>; 695 clock-names = "fck", "ram_clk", "can_clk"; 696 assigned-clocks = <&cpg CPG_MOD 0x9e>; 697 assigned-clock-rates = <80000000>; 698 resets = <&cpg 0xa1>, <&cpg 0xa2>; 699 reset-names = "rstp_n", "rstc_n"; 700 power-domains = <&cpg>; 701 status = "disabled"; 702 703 channel0 { 704 status = "disabled"; 705 }; 706 channel1 { 707 status = "disabled"; 708 }; 709 channel2 { 710 status = "disabled"; 711 }; 712 channel3 { 713 status = "disabled"; 714 }; 715 channel4 { 716 status = "disabled"; 717 }; 718 channel5 { 719 status = "disabled"; 720 }; 721 }; 722 723 rspi0: spi@12800000 { 724 compatible = "renesas,r9a09g057-rspi"; 725 reg = <0x0 0x12800000 0x0 0x400>; 726 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 729 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 730 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 731 interrupt-names = "idle", "error", "end", "rx", "tx"; 732 clocks = <&cpg CPG_MOD 0x54>, 733 <&cpg CPG_MOD 0x55>, 734 <&cpg CPG_MOD 0x56>; 735 clock-names = "pclk", "pclk_sfr", "tclk"; 736 resets = <&cpg 0x7b>, <&cpg 0x7c>; 737 reset-names = "presetn", "tresetn"; 738 power-domains = <&cpg>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 status = "disabled"; 742 }; 743 744 rspi1: spi@12800400 { 745 compatible = "renesas,r9a09g057-rspi"; 746 reg = <0x0 0x12800400 0x0 0x400>; 747 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 750 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 751 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 752 interrupt-names = "idle", "error", "end", "rx", "tx"; 753 clocks = <&cpg CPG_MOD 0x57>, 754 <&cpg CPG_MOD 0x58>, 755 <&cpg CPG_MOD 0x59>; 756 clock-names = "pclk", "pclk_sfr", "tclk"; 757 resets = <&cpg 0x7d>, <&cpg 0x7e>; 758 reset-names = "presetn", "tresetn"; 759 power-domains = <&cpg>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 status = "disabled"; 763 }; 764 765 rspi2: spi@12800800 { 766 compatible = "renesas,r9a09g057-rspi"; 767 reg = <0x0 0x12800800 0x0 0x400>; 768 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 771 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 772 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 773 interrupt-names = "idle", "error", "end", "rx", "tx"; 774 clocks = <&cpg CPG_MOD 0x5a>, 775 <&cpg CPG_MOD 0x5b>, 776 <&cpg CPG_MOD 0x5c>; 777 clock-names = "pclk", "pclk_sfr", "tclk"; 778 resets = <&cpg 0x7f>, <&cpg 0x80>; 779 reset-names = "presetn", "tresetn"; 780 power-domains = <&cpg>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 status = "disabled"; 784 }; 785 786 rsci0: serial@12800c00 { 787 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 788 reg = <0 0x12800c00 0 0x400>; 789 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 791 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 792 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 794 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "eri", "rxi", "txi", "tei", 796 "aed", "bfd"; 797 clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, 798 <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, 799 <&cpg CPG_MOD 0x5f>; 800 clock-names = "pclk", "tclk", "tclk_div4", 801 "tclk_div16", "tclk_div64"; 802 power-domains = <&cpg>; 803 resets = <&cpg 0x81>, <&cpg 0x82>; 804 reset-names = "presetn", "tresetn"; 805 status = "disabled"; 806 }; 807 808 rsci1: serial@12801000 { 809 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 810 reg = <0 0x12801000 0 0x400>; 811 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 813 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 814 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 816 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "eri", "rxi", "txi", "tei", 818 "aed", "bfd"; 819 clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, 820 <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, 821 <&cpg CPG_MOD 0x64>; 822 clock-names = "pclk", "tclk", "tclk_div4", 823 "tclk_div16", "tclk_div64"; 824 power-domains = <&cpg>; 825 resets = <&cpg 0x83>, <&cpg 0x84>; 826 reset-names = "presetn", "tresetn"; 827 status = "disabled"; 828 }; 829 830 rsci2: serial@12801400 { 831 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 832 reg = <0 0x12801400 0 0x400>; 833 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 835 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 836 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 838 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "eri", "rxi", "txi", "tei", 840 "aed", "bfd"; 841 clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, 842 <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, 843 <&cpg CPG_MOD 0x69>; 844 clock-names = "pclk", "tclk", "tclk_div4", 845 "tclk_div16", "tclk_div64"; 846 power-domains = <&cpg>; 847 resets = <&cpg 0x85>, <&cpg 0x86>; 848 reset-names = "presetn", "tresetn"; 849 status = "disabled"; 850 }; 851 852 rsci3: serial@12801800 { 853 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 854 reg = <0 0x12801800 0 0x400>; 855 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 857 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 858 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 860 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "eri", "rxi", "txi", "tei", 862 "aed", "bfd"; 863 clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, 864 <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, 865 <&cpg CPG_MOD 0x6e>; 866 clock-names = "pclk", "tclk", "tclk_div4", 867 "tclk_div16", "tclk_div64"; 868 power-domains = <&cpg>; 869 resets = <&cpg 0x87>, <&cpg 0x88>; 870 reset-names = "presetn", "tresetn"; 871 status = "disabled"; 872 }; 873 874 rsci4: serial@12801c00 { 875 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 876 reg = <0 0x12801c00 0 0x400>; 877 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 879 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 880 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 882 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "eri", "rxi", "txi", "tei", 884 "aed", "bfd"; 885 clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, 886 <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, 887 <&cpg CPG_MOD 0x73>; 888 clock-names = "pclk", "tclk", "tclk_div4", 889 "tclk_div16", "tclk_div64"; 890 power-domains = <&cpg>; 891 resets = <&cpg 0x89>, <&cpg 0x8a>; 892 reset-names = "presetn", "tresetn"; 893 status = "disabled"; 894 }; 895 896 rsci5: serial@12802000 { 897 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 898 reg = <0 0x12802000 0 0x400>; 899 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-names = "eri", "rxi", "txi", "tei", 906 "aed", "bfd"; 907 clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, 908 <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, 909 <&cpg CPG_MOD 0x78>; 910 clock-names = "pclk", "tclk", "tclk_div4", 911 "tclk_div16", "tclk_div64"; 912 power-domains = <&cpg>; 913 resets = <&cpg 0x8b>, <&cpg 0x8c>; 914 reset-names = "presetn", "tresetn"; 915 status = "disabled"; 916 }; 917 918 rsci6: serial@12802400 { 919 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 920 reg = <0 0x12802400 0 0x400>; 921 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, 923 <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, 924 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, 926 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "eri", "rxi", "txi", "tei", 928 "aed", "bfd"; 929 clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, 930 <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, 931 <&cpg CPG_MOD 0x7d>; 932 clock-names = "pclk", "tclk", "tclk_div4", 933 "tclk_div16", "tclk_div64"; 934 power-domains = <&cpg>; 935 resets = <&cpg 0x8d>, <&cpg 0x8e>; 936 reset-names = "presetn", "tresetn"; 937 status = "disabled"; 938 }; 939 940 rsci7: serial@12802800 { 941 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 942 reg = <0 0x12802800 0 0x400>; 943 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, 945 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 946 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, 948 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "eri", "rxi", "txi", "tei", 950 "aed", "bfd"; 951 clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, 952 <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, 953 <&cpg CPG_MOD 0x82>; 954 clock-names = "pclk", "tclk", "tclk_div4", 955 "tclk_div16", "tclk_div64"; 956 power-domains = <&cpg>; 957 resets = <&cpg 0x8f>, <&cpg 0x90>; 958 reset-names = "presetn", "tresetn"; 959 status = "disabled"; 960 }; 961 962 rsci8: serial@12802c00 { 963 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 964 reg = <0 0x12802c00 0 0x400>; 965 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, 967 <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, 968 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 970 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "eri", "rxi", "txi", "tei", 972 "aed", "bfd"; 973 clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, 974 <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, 975 <&cpg CPG_MOD 0x87>; 976 clock-names = "pclk", "tclk", "tclk_div4", 977 "tclk_div16", "tclk_div64"; 978 power-domains = <&cpg>; 979 resets = <&cpg 0x91>, <&cpg 0x92>; 980 reset-names = "presetn", "tresetn"; 981 status = "disabled"; 982 }; 983 984 rsci9: serial@12803000 { 985 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 986 reg = <0 0x12803000 0 0x400>; 987 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, 989 <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 990 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 992 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "eri", "rxi", "txi", "tei", 994 "aed", "bfd"; 995 clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, 996 <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, 997 <&cpg CPG_MOD 0x8c>; 998 clock-names = "pclk", "tclk", "tclk_div4", 999 "tclk_div16", "tclk_div64"; 1000 power-domains = <&cpg>; 1001 resets = <&cpg 0x93>, <&cpg 0x94>; 1002 reset-names = "presetn", "tresetn"; 1003 status = "disabled"; 1004 }; 1005 1006 i2c0: i2c@14400400 { 1007 compatible = "renesas,riic-r9a09g057"; 1008 reg = <0 0x14400400 0 0x400>; 1009 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 1011 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 1012 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1017 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1018 "naki", "ali", "tmoi"; 1019 clocks = <&cpg CPG_MOD 0x94>; 1020 resets = <&cpg 0x98>; 1021 power-domains = <&cpg>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 i2c1: i2c@14400800 { 1028 compatible = "renesas,riic-r9a09g057"; 1029 reg = <0 0x14400800 0 0x400>; 1030 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 1032 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 1033 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1039 "naki", "ali", "tmoi"; 1040 clocks = <&cpg CPG_MOD 0x95>; 1041 resets = <&cpg 0x99>; 1042 power-domains = <&cpg>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c2: i2c@14400c00 { 1049 compatible = "renesas,riic-r9a09g057"; 1050 reg = <0 0x14400c00 0 0x400>; 1051 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 1053 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 1054 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1060 "naki", "ali", "tmoi"; 1061 clocks = <&cpg CPG_MOD 0x96>; 1062 resets = <&cpg 0x9a>; 1063 power-domains = <&cpg>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c3: i2c@14401000 { 1070 compatible = "renesas,riic-r9a09g057"; 1071 reg = <0 0x14401000 0 0x400>; 1072 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 1074 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 1075 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1080 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1081 "naki", "ali", "tmoi"; 1082 clocks = <&cpg CPG_MOD 0x97>; 1083 resets = <&cpg 0x9b>; 1084 power-domains = <&cpg>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c4: i2c@14401400 { 1091 compatible = "renesas,riic-r9a09g057"; 1092 reg = <0 0x14401400 0 0x400>; 1093 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 1095 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 1096 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1102 "naki", "ali", "tmoi"; 1103 clocks = <&cpg CPG_MOD 0x98>; 1104 resets = <&cpg 0x9c>; 1105 power-domains = <&cpg>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c5: i2c@14401800 { 1112 compatible = "renesas,riic-r9a09g057"; 1113 reg = <0 0x14401800 0 0x400>; 1114 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 1116 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 1117 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1123 "naki", "ali", "tmoi"; 1124 clocks = <&cpg CPG_MOD 0x99>; 1125 resets = <&cpg 0x9d>; 1126 power-domains = <&cpg>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c6: i2c@14401c00 { 1133 compatible = "renesas,riic-r9a09g057"; 1134 reg = <0 0x14401c00 0 0x400>; 1135 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 1137 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 1138 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1143 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1144 "naki", "ali", "tmoi"; 1145 clocks = <&cpg CPG_MOD 0x9a>; 1146 resets = <&cpg 0x9e>; 1147 power-domains = <&cpg>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c7: i2c@14402000 { 1154 compatible = "renesas,riic-r9a09g057"; 1155 reg = <0 0x14402000 0 0x400>; 1156 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 1158 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 1159 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1165 "naki", "ali", "tmoi"; 1166 clocks = <&cpg CPG_MOD 0x9b>; 1167 resets = <&cpg 0x9f>; 1168 power-domains = <&cpg>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c8: i2c@11c01000 { 1175 compatible = "renesas,riic-r9a09g057"; 1176 reg = <0 0x11c01000 0 0x400>; 1177 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 1179 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 1180 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1185 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1186 "naki", "ali", "tmoi"; 1187 clocks = <&cpg CPG_MOD 0x93>; 1188 resets = <&cpg 0xa0>; 1189 power-domains = <&cpg>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 gpu: gpu@14850000 { 1196 compatible = "renesas,r9a09g057-mali", 1197 "arm,mali-bifrost"; 1198 reg = <0x0 0x14850000 0x0 0x10000>; 1199 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 1203 interrupt-names = "job", "mmu", "gpu", "event"; 1204 clocks = <&cpg CPG_MOD 0xf0>, 1205 <&cpg CPG_MOD 0xf1>, 1206 <&cpg CPG_MOD 0xf2>; 1207 clock-names = "gpu", "bus", "bus_ace"; 1208 power-domains = <&cpg>; 1209 resets = <&cpg 0xdd>, 1210 <&cpg 0xde>, 1211 <&cpg 0xdf>; 1212 reset-names = "rst", "axi_rst", "ace_rst"; 1213 operating-points-v2 = <&gpu_opp_table>; 1214 status = "disabled"; 1215 }; 1216 1217 gic: interrupt-controller@14900000 { 1218 compatible = "arm,gic-v3"; 1219 reg = <0x0 0x14900000 0 0x20000>, 1220 <0x0 0x14940000 0 0x80000>; 1221 #interrupt-cells = <3>; 1222 #address-cells = <0>; 1223 interrupt-controller; 1224 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1225 }; 1226 1227 ohci0: usb@15800000 { 1228 compatible = "generic-ohci"; 1229 reg = <0 0x15800000 0 0x100>; 1230 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 1232 resets = <&usb20phyrst>, <&cpg 0xac>; 1233 phys = <&usb2_phy0 1>; 1234 phy-names = "usb"; 1235 power-domains = <&cpg>; 1236 status = "disabled"; 1237 }; 1238 1239 ohci1: usb@15810000 { 1240 compatible = "generic-ohci"; 1241 reg = <0 0x15810000 0 0x100>; 1242 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 1244 resets = <&usb21phyrst>, <&cpg 0xad>; 1245 phys = <&usb2_phy1 1>; 1246 phy-names = "usb"; 1247 power-domains = <&cpg>; 1248 status = "disabled"; 1249 }; 1250 1251 ehci0: usb@15800100 { 1252 compatible = "generic-ehci"; 1253 reg = <0 0x15800100 0 0x100>; 1254 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 1256 resets = <&usb20phyrst>, <&cpg 0xac>; 1257 phys = <&usb2_phy0 2>; 1258 phy-names = "usb"; 1259 companion = <&ohci0>; 1260 power-domains = <&cpg>; 1261 status = "disabled"; 1262 }; 1263 1264 ehci1: usb@15810100 { 1265 compatible = "generic-ehci"; 1266 reg = <0 0x15810100 0 0x100>; 1267 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 1269 resets = <&usb21phyrst>, <&cpg 0xad>; 1270 phys = <&usb2_phy1 2>; 1271 phy-names = "usb"; 1272 companion = <&ohci1>; 1273 power-domains = <&cpg>; 1274 status = "disabled"; 1275 }; 1276 1277 usb2_phy0: usb-phy@15800200 { 1278 compatible = "renesas,usb2-phy-r9a09g057"; 1279 reg = <0 0x15800200 0 0x700>; 1280 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&cpg CPG_MOD 0xb3>, 1282 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 1283 clock-names = "fck", "usb_x1"; 1284 resets = <&usb20phyrst>; 1285 #phy-cells = <1>; 1286 power-domains = <&cpg>; 1287 status = "disabled"; 1288 }; 1289 1290 usb2_phy1: usb-phy@15810200 { 1291 compatible = "renesas,usb2-phy-r9a09g057"; 1292 reg = <0 0x15810200 0 0x700>; 1293 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cpg CPG_MOD 0xb4>, 1295 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 1296 clock-names = "fck", "usb_x1"; 1297 resets = <&usb21phyrst>; 1298 #phy-cells = <1>; 1299 power-domains = <&cpg>; 1300 status = "disabled"; 1301 }; 1302 1303 hsusb: usb@15820000 { 1304 compatible = "renesas,usbhs-r9a09g057", 1305 "renesas,rzg2l-usbhs"; 1306 reg = <0 0x15820000 0 0x10000>; 1307 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 1308 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 1312 resets = <&usb20phyrst>, 1313 <&cpg 0xae>; 1314 phys = <&usb2_phy0 3>; 1315 phy-names = "usb"; 1316 power-domains = <&cpg>; 1317 status = "disabled"; 1318 }; 1319 1320 usb20phyrst: usb20phy-reset@15830000 { 1321 compatible = "renesas,r9a09g057-usb2phy-reset"; 1322 reg = <0 0x15830000 0 0x10000>; 1323 clocks = <&cpg CPG_MOD 0xb6>; 1324 resets = <&cpg 0xaf>; 1325 power-domains = <&cpg>; 1326 #reset-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 usb21phyrst: usb21phy-reset@15840000 { 1331 compatible = "renesas,r9a09g057-usb2phy-reset"; 1332 reg = <0 0x15840000 0 0x10000>; 1333 clocks = <&cpg CPG_MOD 0xb7>; 1334 resets = <&cpg 0xaf>; 1335 power-domains = <&cpg>; 1336 #reset-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 xhci0: usb@15850000 { 1341 compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; 1342 reg = <0 0x15850000 0 0x10000>; 1343 interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1348 interrupt-names = "all", "smi", "hse", "pme", "xhc"; 1349 clocks = <&cpg CPG_MOD 0xaf>; 1350 power-domains = <&cpg>; 1351 resets = <&cpg 0xaa>; 1352 phys = <&usb3_phy0>, <&usb3_phy0>; 1353 phy-names = "usb2-phy", "usb3-phy"; 1354 status = "disabled"; 1355 }; 1356 1357 xhci1: usb@15860000 { 1358 compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; 1359 reg = <0 0x15860000 0 0x10000>; 1360 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>; 1365 interrupt-names = "all", "smi", "hse", "pme", "xhc"; 1366 clocks = <&cpg CPG_MOD 0xb1>; 1367 power-domains = <&cpg>; 1368 resets = <&cpg 0xab>; 1369 phys = <&usb3_phy1>, <&usb3_phy1>; 1370 phy-names = "usb2-phy", "usb3-phy"; 1371 status = "disabled"; 1372 }; 1373 1374 usb3_phy0: usb-phy@15870000 { 1375 compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; 1376 reg = <0 0x15870000 0 0x10000>; 1377 clocks = <&cpg CPG_MOD 0xb0>, 1378 <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>, 1379 <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>; 1380 clock-names = "pclk", "core", "ref_alt_clk_p"; 1381 power-domains = <&cpg>; 1382 resets = <&cpg 0xaa>; 1383 #phy-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 usb3_phy1: usb-phy@15880000 { 1388 compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; 1389 reg = <0 0x15880000 0 0x10000>; 1390 clocks = <&cpg CPG_MOD 0xb2>, 1391 <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>, 1392 <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>; 1393 clock-names = "pclk", "core", "ref_alt_clk_p"; 1394 power-domains = <&cpg>; 1395 resets = <&cpg 0xab>; 1396 #phy-cells = <0>; 1397 status = "disabled"; 1398 }; 1399 1400 sdhi0: mmc@15c00000 { 1401 compatible = "renesas,sdhi-r9a09g057"; 1402 reg = <0x0 0x15c00000 0 0x10000>; 1403 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1406 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1407 clock-names = "core", "clkh", "cd", "aclk"; 1408 resets = <&cpg 0xa7>; 1409 power-domains = <&cpg>; 1410 status = "disabled"; 1411 1412 sdhi0_vqmmc: vqmmc-regulator { 1413 regulator-name = "SDHI0-VQMMC"; 1414 regulator-min-microvolt = <1800000>; 1415 regulator-max-microvolt = <3300000>; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 sdhi1: mmc@15c10000 { 1421 compatible = "renesas,sdhi-r9a09g057"; 1422 reg = <0x0 0x15c10000 0 0x10000>; 1423 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1426 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1427 clock-names = "core", "clkh", "cd", "aclk"; 1428 resets = <&cpg 0xa8>; 1429 power-domains = <&cpg>; 1430 status = "disabled"; 1431 1432 sdhi1_vqmmc: vqmmc-regulator { 1433 regulator-name = "SDHI1-VQMMC"; 1434 regulator-min-microvolt = <1800000>; 1435 regulator-max-microvolt = <3300000>; 1436 status = "disabled"; 1437 }; 1438 }; 1439 1440 sdhi2: mmc@15c20000 { 1441 compatible = "renesas,sdhi-r9a09g057"; 1442 reg = <0x0 0x15c20000 0 0x10000>; 1443 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1446 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1447 clock-names = "core", "clkh", "cd", "aclk"; 1448 resets = <&cpg 0xa9>; 1449 power-domains = <&cpg>; 1450 status = "disabled"; 1451 1452 sdhi2_vqmmc: vqmmc-regulator { 1453 regulator-name = "SDHI2-VQMMC"; 1454 regulator-min-microvolt = <1800000>; 1455 regulator-max-microvolt = <3300000>; 1456 status = "disabled"; 1457 }; 1458 }; 1459 1460 eth0: ethernet@15c30000 { 1461 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1462 "snps,dwmac-5.20"; 1463 reg = <0 0x15c30000 0 0x10000>; 1464 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1475 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1476 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1477 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1478 "tx-queue-2", "tx-queue-3"; 1479 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1480 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1481 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1482 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1483 clock-names = "stmmaceth", "pclk", "ptp_ref", 1484 "tx", "rx", "tx-180", "rx-180"; 1485 resets = <&cpg 0xb0>; 1486 power-domains = <&cpg>; 1487 snps,multicast-filter-bins = <256>; 1488 snps,perfect-filter-entries = <128>; 1489 rx-fifo-depth = <8192>; 1490 tx-fifo-depth = <8192>; 1491 snps,fixed-burst; 1492 snps,no-pbl-x8; 1493 snps,force_thresh_dma_mode; 1494 snps,axi-config = <&stmmac_axi_setup>; 1495 snps,mtl-rx-config = <&mtl_rx_setup0>; 1496 snps,mtl-tx-config = <&mtl_tx_setup0>; 1497 snps,txpbl = <32>; 1498 snps,rxpbl = <32>; 1499 status = "disabled"; 1500 1501 mdio0: mdio { 1502 compatible = "snps,dwmac-mdio"; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 }; 1506 1507 mtl_rx_setup0: rx-queues-config { 1508 snps,rx-queues-to-use = <4>; 1509 snps,rx-sched-sp; 1510 1511 queue0 { 1512 snps,dcb-algorithm; 1513 snps,priority = <0x1>; 1514 snps,map-to-dma-channel = <0>; 1515 }; 1516 1517 queue1 { 1518 snps,dcb-algorithm; 1519 snps,priority = <0x2>; 1520 snps,map-to-dma-channel = <1>; 1521 }; 1522 1523 queue2 { 1524 snps,dcb-algorithm; 1525 snps,priority = <0x4>; 1526 snps,map-to-dma-channel = <2>; 1527 }; 1528 1529 queue3 { 1530 snps,dcb-algorithm; 1531 snps,priority = <0x8>; 1532 snps,map-to-dma-channel = <3>; 1533 }; 1534 }; 1535 1536 mtl_tx_setup0: tx-queues-config { 1537 snps,tx-queues-to-use = <4>; 1538 1539 queue0 { 1540 snps,dcb-algorithm; 1541 snps,priority = <0x1>; 1542 }; 1543 1544 queue1 { 1545 snps,dcb-algorithm; 1546 snps,priority = <0x2>; 1547 }; 1548 1549 queue2 { 1550 snps,dcb-algorithm; 1551 snps,priority = <0x4>; 1552 }; 1553 1554 queue3 { 1555 snps,dcb-algorithm; 1556 snps,priority = <0x8>; 1557 }; 1558 }; 1559 }; 1560 1561 eth1: ethernet@15c40000 { 1562 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1563 "snps,dwmac-5.20"; 1564 reg = <0 0x15c40000 0 0x10000>; 1565 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1576 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1577 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1578 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1579 "tx-queue-2", "tx-queue-3"; 1580 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1581 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1582 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1583 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1584 clock-names = "stmmaceth", "pclk", "ptp_ref", 1585 "tx", "rx", "tx-180", "rx-180"; 1586 resets = <&cpg 0xb1>; 1587 power-domains = <&cpg>; 1588 snps,multicast-filter-bins = <256>; 1589 snps,perfect-filter-entries = <128>; 1590 rx-fifo-depth = <8192>; 1591 tx-fifo-depth = <8192>; 1592 snps,fixed-burst; 1593 snps,no-pbl-x8; 1594 snps,force_thresh_dma_mode; 1595 snps,axi-config = <&stmmac_axi_setup>; 1596 snps,mtl-rx-config = <&mtl_rx_setup1>; 1597 snps,mtl-tx-config = <&mtl_tx_setup1>; 1598 snps,txpbl = <32>; 1599 snps,rxpbl = <32>; 1600 status = "disabled"; 1601 1602 mdio1: mdio { 1603 compatible = "snps,dwmac-mdio"; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 }; 1607 1608 mtl_rx_setup1: rx-queues-config { 1609 snps,rx-queues-to-use = <4>; 1610 snps,rx-sched-sp; 1611 1612 queue0 { 1613 snps,dcb-algorithm; 1614 snps,priority = <0x1>; 1615 snps,map-to-dma-channel = <0>; 1616 }; 1617 1618 queue1 { 1619 snps,dcb-algorithm; 1620 snps,priority = <0x2>; 1621 snps,map-to-dma-channel = <1>; 1622 }; 1623 1624 queue2 { 1625 snps,dcb-algorithm; 1626 snps,priority = <0x4>; 1627 snps,map-to-dma-channel = <2>; 1628 }; 1629 1630 queue3 { 1631 snps,dcb-algorithm; 1632 snps,priority = <0x8>; 1633 snps,map-to-dma-channel = <3>; 1634 }; 1635 }; 1636 1637 mtl_tx_setup1: tx-queues-config { 1638 snps,tx-queues-to-use = <4>; 1639 1640 queue0 { 1641 snps,dcb-algorithm; 1642 snps,priority = <0x1>; 1643 }; 1644 1645 queue1 { 1646 snps,dcb-algorithm; 1647 snps,priority = <0x2>; 1648 }; 1649 1650 queue2 { 1651 snps,dcb-algorithm; 1652 snps,priority = <0x4>; 1653 }; 1654 1655 queue3 { 1656 snps,dcb-algorithm; 1657 snps,priority = <0x8>; 1658 }; 1659 }; 1660 }; 1661 1662 dsi: dsi@16430000 { 1663 compatible = "renesas,r9a09g057-mipi-dsi"; 1664 reg = <0 0x16430000 0 0x20000>; 1665 interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>; 1672 interrupt-names = "seq0", "seq1", "vin1", "rcv", 1673 "ferr", "ppi", "debug"; 1674 clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, 1675 <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, 1676 <&cpg CPG_MOD 0xeb>; 1677 clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; 1678 resets = <&cpg 0xd8>, <&cpg 0xd7>; 1679 reset-names = "arst", "prst"; 1680 power-domains = <&cpg>; 1681 status = "disabled"; 1682 1683 ports { 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 1687 port@0 { 1688 reg = <0>; 1689 dsi_in: endpoint { 1690 remote-endpoint = <&du_out_dsi>; 1691 }; 1692 }; 1693 1694 port@1 { 1695 reg = <1>; 1696 dsi_out: endpoint { 1697 }; 1698 }; 1699 }; 1700 }; 1701 1702 du: display@16460000 { 1703 compatible = "renesas,r9a09g057-du"; 1704 reg = <0 0x16460000 0 0x10000>; 1705 interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>; 1706 clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, 1707 <&cpg CPG_MOD 0xef>; 1708 clock-names = "aclk", "pclk", "vclk"; 1709 power-domains = <&cpg>; 1710 resets = <&cpg 0xdc>; 1711 renesas,vsps = <&vspd 0>; 1712 status = "disabled"; 1713 1714 ports { 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 1718 port@0 { 1719 reg = <0>; 1720 du_out_dsi: endpoint { 1721 remote-endpoint = <&dsi_in>; 1722 }; 1723 }; 1724 }; 1725 }; 1726 1727 fcpvd: fcp@16470000 { 1728 compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; 1729 reg = <0 0x16470000 0 0x10000>; 1730 clocks = <&cpg CPG_MOD 0xed>, 1731 <&cpg CPG_MOD 0xee>, 1732 <&cpg CPG_MOD 0xef>; 1733 clock-names = "aclk", "pclk", "vclk"; 1734 power-domains = <&cpg>; 1735 resets = <&cpg 0xdc>; 1736 }; 1737 1738 vspd: vsp@16480000 { 1739 compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2"; 1740 reg = <0 0x16480000 0 0x10000>; 1741 interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>; 1742 clocks = <&cpg CPG_MOD 0xed>, 1743 <&cpg CPG_MOD 0xee>, 1744 <&cpg CPG_MOD 0xef>; 1745 clock-names = "aclk", "pclk", "vclk"; 1746 power-domains = <&cpg>; 1747 resets = <&cpg 0xdc>; 1748 renesas,fcp = <&fcpvd>; 1749 }; 1750 }; 1751 1752 stmmac_axi_setup: stmmac-axi-config { 1753 snps,lpi_en; 1754 snps,wr_osr_lmt = <0xf>; 1755 snps,rd_osr_lmt = <0xf>; 1756 snps,blen = <16 8 4 0 0 0 0>; 1757 }; 1758 1759 thermal-zones { 1760 sensor1_thermal: sensor1-thermal { 1761 polling-delay = <1000>; 1762 polling-delay-passive = <250>; 1763 thermal-sensors = <&tsu0>; 1764 1765 trips { 1766 sensor1_crit: sensor1-crit { 1767 temperature = <120000>; 1768 hysteresis = <1000>; 1769 type = "critical"; 1770 }; 1771 }; 1772 }; 1773 1774 sensor2_thermal: sensor2-thermal { 1775 polling-delay = <1000>; 1776 polling-delay-passive = <250>; 1777 thermal-sensors = <&tsu1>; 1778 1779 cooling-maps { 1780 map0 { 1781 trip = <&sensor2_target>; 1782 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 1783 <&cpu2 0 3>, <&cpu3 0 3>; 1784 contribution = <1024>; 1785 }; 1786 }; 1787 1788 trips { 1789 sensor2_target: trip-point { 1790 temperature = <95000>; 1791 hysteresis = <1000>; 1792 type = "passive"; 1793 }; 1794 1795 sensor2_crit: sensor2-crit { 1796 temperature = <120000>; 1797 hysteresis = <1000>; 1798 type = "critical"; 1799 }; 1800 }; 1801 }; 1802 }; 1803 1804 timer { 1805 compatible = "arm,armv8-timer"; 1806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1810 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1811 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1812 }; 1813}; 1814