1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2023 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "efuse.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "reg.h"
13 #include "rtw8922a.h"
14 #include "rtw8922a_rfk.h"
15 #include "sar.h"
16 #include "util.h"
17
18 #define RTW8922A_FW_FORMAT_MAX 4
19 #define RTW8922A_FW_BASENAME "rtw89/rtw8922a_fw"
20 #define RTW8922A_MODULE_FIRMWARE \
21 RTW89_GEN_MODULE_FWNAME(RTW8922A_FW_BASENAME, RTW8922A_FW_FORMAT_MAX)
22
23 #define HE_N_USER_MAX_8922A 4
24
25 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_pcie[] = {
26 {2, 1641, grp_0}, /* ACH 0 */
27 {2, 1641, grp_0}, /* ACH 1 */
28 {2, 1641, grp_0}, /* ACH 2 */
29 {2, 1641, grp_0}, /* ACH 3 */
30 {2, 1641, grp_1}, /* ACH 4 */
31 {2, 1641, grp_1}, /* ACH 5 */
32 {2, 1641, grp_1}, /* ACH 6 */
33 {2, 1641, grp_1}, /* ACH 7 */
34 {2, 1641, grp_0}, /* B0MGQ */
35 {2, 1641, grp_0}, /* B0HIQ */
36 {2, 1641, grp_1}, /* B1MGQ */
37 {2, 1641, grp_1}, /* B1HIQ */
38 {0, 0, 0}, /* FWCMDQ */
39 {0, 0, 0}, /* BMC */
40 {0, 0, 0}, /* H2D */
41 };
42
43 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_pcie = {
44 1651, /* Group 0 */
45 1651, /* Group 1 */
46 3302, /* Public Max */
47 0, /* WP threshold */
48 };
49
50 static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_pcie[] = {
51 [RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_pcie, &rtw8922a_hfc_pubcfg_pcie,
52 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
53 [RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_pcie, &rtw8922a_hfc_pubcfg_pcie,
54 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
55 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
56 RTW89_HCIFC_POH},
57 [RTW89_QTA_INVALID] = {NULL},
58 };
59
60 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch7[] = {
61 {54, 222, grp_0}, /* ACH 0 */
62 {0, 0, grp_0}, /* ACH 1 */
63 {54, 222, grp_0}, /* ACH 2 */
64 {0, 0, grp_0}, /* ACH 3 */
65 {54, 222, grp_0}, /* ACH 4 */
66 {0, 0, grp_0}, /* ACH 5 */
67 {54, 222, grp_0}, /* ACH 6 */
68 {0, 0, grp_0}, /* ACH 7 */
69 {54, 222, grp_0}, /* B0MGQ */
70 {0, 0, grp_0}, /* B0HIQ */
71 {54, 222, grp_0}, /* B1MGQ */
72 {0, 0, grp_0}, /* B1HIQ */
73 {0, 0, 0}, /* FWCMDQ */
74 {0, 0, 0}, /* BMC */
75 {0, 0, 0}, /* H2D */
76 };
77
78 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p7 = {
79 492, /* Group 0 */
80 0, /* Group 1 */
81 492, /* Public Max */
82 0, /* WP threshold */
83 };
84
85 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch8[] = {
86 {24, 196, grp_0}, /* ACH 0 */
87 {0, 0, grp_0}, /* ACH 1 */
88 {54, 226, grp_0}, /* ACH 2 */
89 {0, 0, grp_0}, /* ACH 3 */
90 {54, 196, grp_1}, /* ACH 4 */
91 {0, 0, grp_1}, /* ACH 5 */
92 {54, 196, grp_1}, /* ACH 6 */
93 {0, 0, grp_1}, /* ACH 7 */
94 {54, 226, grp_0}, /* B0MGQ */
95 {0, 0, grp_0}, /* B0HIQ */
96 {54, 196, grp_1}, /* B1MGQ */
97 {0, 0, grp_0}, /* B1HIQ */
98 {0, 0, 0}, /* FWCMDQ */
99 {0, 0, 0}, /* BMC */
100 {0, 0, 0}, /* H2D */
101 };
102
103 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p8 = {
104 304, /* Group 0 */
105 304, /* Group 1 */
106 608, /* Public Max */
107 96, /* WP threshold */
108 };
109
110 static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_usb2[] = {
111 [RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_ch7, &rtw8922a_hfc_pubcfg_p7,
112 &rtw89_mac_size.hfc_prec_cfg_c5, RTW89_HCIFC_STF},
113 [RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_ch8, &rtw8922a_hfc_pubcfg_p8,
114 &rtw89_mac_size.hfc_prec_cfg_c6, RTW89_HCIFC_STF},
115 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
116 RTW89_HCIFC_POH},
117 [RTW89_QTA_INVALID] = {NULL},
118 };
119
120 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch4[] = {
121 {54, 606, grp_0}, /* ACH 0 */
122 {0, 0, grp_0}, /* ACH 1 */
123 {54, 606, grp_0}, /* ACH 2 */
124 {0, 0, grp_0}, /* ACH 3 */
125 {54, 606, grp_0}, /* ACH 4 */
126 {0, 0, grp_0}, /* ACH 5 */
127 {54, 606, grp_0}, /* ACH 6 */
128 {0, 0, grp_0}, /* ACH 7 */
129 {54, 606, grp_0}, /* B0MGQ */
130 {0, 0, grp_0}, /* B0HIQ */
131 {54, 606, grp_0}, /* B1MGQ */
132 {0, 0, grp_0}, /* B1HIQ */
133 {0, 0, 0}, /* FWCMDQ */
134 {0, 0, 0}, /* BMC */
135 {0, 0, 0}, /* H2D */
136 };
137
138 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p4 = {
139 876, /* Group 0 */
140 0, /* Group 1 */
141 876, /* Public Max */
142 0, /* WP threshold */
143 };
144
145 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_ch5[] = {
146 {54, 311, grp_0}, /* ACH 0 */
147 {0, 0, grp_0}, /* ACH 1 */
148 {54, 311, grp_0}, /* ACH 2 */
149 {0, 0, grp_0}, /* ACH 3 */
150 {54, 311, grp_1}, /* ACH 4 */
151 {0, 0, grp_1}, /* ACH 5 */
152 {54, 311, grp_1}, /* ACH 6 */
153 {0, 0, grp_1}, /* ACH 7 */
154 {54, 311, grp_0}, /* B0MGQ */
155 {0, 0, grp_0}, /* B0HIQ */
156 {54, 311, grp_1}, /* B1MGQ */
157 {0, 0, grp_0}, /* B1HIQ */
158 {0, 0, 0}, /* FWCMDQ */
159 {0, 0, 0}, /* BMC */
160 {0, 0, 0}, /* H2D */
161 };
162
163 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_p5 = {
164 419, /* Group 0 */
165 419, /* Group 1 */
166 838, /* Public Max */
167 0, /* WP threshold */
168 };
169
170 static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_usb3[] = {
171 [RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_ch4, &rtw8922a_hfc_pubcfg_p4,
172 &rtw89_mac_size.hfc_prec_cfg_c3, RTW89_HCIFC_STF},
173 [RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_ch5, &rtw8922a_hfc_pubcfg_p5,
174 &rtw89_mac_size.hfc_prec_cfg_c3, RTW89_HCIFC_STF},
175 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
176 RTW89_HCIFC_POH},
177 [RTW89_QTA_INVALID] = {NULL},
178 };
179
180 static const struct rtw89_dle_mem rtw8922a_dle_mem_pcie[] = {
181 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0_v1,
182 &rtw89_mac_size.ple_size0_v1, &rtw89_mac_size.wde_qt0_v1,
183 &rtw89_mac_size.wde_qt0_v1, &rtw89_mac_size.ple_qt0,
184 &rtw89_mac_size.ple_qt1, &rtw89_mac_size.ple_rsvd_qt0,
185 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
186 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size0_v1,
187 &rtw89_mac_size.ple_size0_v1, &rtw89_mac_size.wde_qt0_v1,
188 &rtw89_mac_size.wde_qt0_v1, &rtw89_mac_size.ple_qt0,
189 &rtw89_mac_size.ple_qt1, &rtw89_mac_size.ple_rsvd_qt0,
190 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
191 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
192 &rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
193 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
194 &rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
195 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
196 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
197 NULL},
198 };
199
200 static const struct rtw89_dle_mem rtw8922a_dle_mem_usb2[] = {
201 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7_v1,
202 &rtw89_mac_size.ple_size6_v1, &rtw89_mac_size.wde_qt7_v1,
203 &rtw89_mac_size.wde_qt7_v1, &rtw89_mac_size.ple_qt12_v1,
204 &rtw89_mac_size.ple_qt13_v1, &rtw89_mac_size.ple_rsvd_qt2,
205 &rtw89_mac_size.rsvd0_size5, &rtw89_mac_size.rsvd1_size0},
206 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size8_v1,
207 &rtw89_mac_size.ple_size7_v1, &rtw89_mac_size.wde_qt8_v1,
208 &rtw89_mac_size.wde_qt8_v1, &rtw89_mac_size.ple_qt14_v1,
209 &rtw89_mac_size.ple_qt15_v1, &rtw89_mac_size.ple_rsvd_qt2,
210 &rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size0},
211 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
212 &rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
213 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
214 &rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
215 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
216 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
217 NULL},
218 };
219
220 static const struct rtw89_dle_mem rtw8922a_dle_mem_usb3[] = {
221 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size4_v1,
222 &rtw89_mac_size.ple_size4_v1, &rtw89_mac_size.wde_qt4_v1,
223 &rtw89_mac_size.wde_qt4_v1, &rtw89_mac_size.ple_qt6_v1,
224 &rtw89_mac_size.ple_qt7_v1, &rtw89_mac_size.ple_rsvd_qt2,
225 &rtw89_mac_size.rsvd0_size3, &rtw89_mac_size.rsvd1_size0},
226 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size5_v1,
227 &rtw89_mac_size.ple_size4_v1, &rtw89_mac_size.wde_qt5_v1,
228 &rtw89_mac_size.wde_qt5_v1, &rtw89_mac_size.ple_qt8_v1,
229 &rtw89_mac_size.ple_qt9_v1, &rtw89_mac_size.ple_rsvd_qt2,
230 &rtw89_mac_size.rsvd0_size3, &rtw89_mac_size.rsvd1_size0},
231 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size3_v1,
232 &rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
233 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
234 &rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
235 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
236 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
237 NULL},
238 };
239
240 static const u32 rtw8922a_h2c_regs[RTW89_H2CREG_MAX] = {
241 R_BE_H2CREG_DATA0, R_BE_H2CREG_DATA1, R_BE_H2CREG_DATA2,
242 R_BE_H2CREG_DATA3
243 };
244
245 static const u32 rtw8922a_c2h_regs[RTW89_H2CREG_MAX] = {
246 R_BE_C2HREG_DATA0, R_BE_C2HREG_DATA1, R_BE_C2HREG_DATA2,
247 R_BE_C2HREG_DATA3
248 };
249
250 static const u32 rtw8922a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
251 R_AX_C2HREG_DATA3_V1 + 3, R_BE_DBG_WOW,
252 };
253
254 static const struct rtw89_page_regs rtw8922a_page_regs = {
255 .hci_fc_ctrl = R_BE_HCI_FC_CTRL,
256 .ch_page_ctrl = R_BE_CH_PAGE_CTRL,
257 .ach_page_ctrl = R_BE_CH0_PAGE_CTRL,
258 .ach_page_info = R_BE_CH0_PAGE_INFO,
259 .pub_page_info3 = R_BE_PUB_PAGE_INFO3,
260 .pub_page_ctrl1 = R_BE_PUB_PAGE_CTRL1,
261 .pub_page_ctrl2 = R_BE_PUB_PAGE_CTRL2,
262 .pub_page_info1 = R_BE_PUB_PAGE_INFO1,
263 .pub_page_info2 = R_BE_PUB_PAGE_INFO2,
264 .wp_page_ctrl1 = R_BE_WP_PAGE_CTRL1,
265 .wp_page_ctrl2 = R_BE_WP_PAGE_CTRL2,
266 .wp_page_info1 = R_BE_WP_PAGE_INFO1,
267 };
268
269 static const struct rtw89_reg_imr rtw8922a_imr_dmac_regs[] = {
270 {R_BE_DISP_HOST_IMR, B_BE_DISP_HOST_IMR_CLR, B_BE_DISP_HOST_IMR_SET},
271 {R_BE_DISP_CPU_IMR, B_BE_DISP_CPU_IMR_CLR, B_BE_DISP_CPU_IMR_SET},
272 {R_BE_DISP_OTHER_IMR, B_BE_DISP_OTHER_IMR_CLR, B_BE_DISP_OTHER_IMR_SET},
273 {R_BE_PKTIN_ERR_IMR, B_BE_PKTIN_ERR_IMR_CLR, B_BE_PKTIN_ERR_IMR_SET},
274 {R_BE_INTERRUPT_MASK_REG, B_BE_INTERRUPT_MASK_REG_CLR, B_BE_INTERRUPT_MASK_REG_SET},
275 {R_BE_MLO_ERR_IDCT_IMR, B_BE_MLO_ERR_IDCT_IMR_CLR, B_BE_MLO_ERR_IDCT_IMR_SET},
276 {R_BE_MPDU_TX_ERR_IMR, B_BE_MPDU_TX_ERR_IMR_CLR, B_BE_MPDU_TX_ERR_IMR_SET},
277 {R_BE_MPDU_RX_ERR_IMR, B_BE_MPDU_RX_ERR_IMR_CLR, B_BE_MPDU_RX_ERR_IMR_SET},
278 {R_BE_SEC_ERROR_IMR, B_BE_SEC_ERROR_IMR_CLR, B_BE_SEC_ERROR_IMR_SET},
279 {R_BE_CPUIO_ERR_IMR, B_BE_CPUIO_ERR_IMR_CLR, B_BE_CPUIO_ERR_IMR_SET},
280 {R_BE_WDE_ERR_IMR, B_BE_WDE_ERR_IMR_CLR, B_BE_WDE_ERR_IMR_SET},
281 {R_BE_WDE_ERR1_IMR, B_BE_WDE_ERR1_IMR_CLR, B_BE_WDE_ERR1_IMR_SET},
282 {R_BE_PLE_ERR_IMR, B_BE_PLE_ERR_IMR_CLR, B_BE_PLE_ERR_IMR_SET},
283 {R_BE_PLE_ERRFLAG1_IMR, B_BE_PLE_ERRFLAG1_IMR_CLR, B_BE_PLE_ERRFLAG1_IMR_SET},
284 {R_BE_WDRLS_ERR_IMR, B_BE_WDRLS_ERR_IMR_CLR, B_BE_WDRLS_ERR_IMR_SET},
285 {R_BE_TXPKTCTL_B0_ERRFLAG_IMR, B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR,
286 B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET},
287 {R_BE_TXPKTCTL_B1_ERRFLAG_IMR, B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR,
288 B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET},
289 {R_BE_BBRPT_COM_ERR_IMR, B_BE_BBRPT_COM_ERR_IMR_CLR, B_BE_BBRPT_COM_ERR_IMR_SET},
290 {R_BE_BBRPT_CHINFO_ERR_IMR, B_BE_BBRPT_CHINFO_ERR_IMR_CLR,
291 B_BE_BBRPT_CHINFO_ERR_IMR_SET},
292 {R_BE_BBRPT_DFS_ERR_IMR, B_BE_BBRPT_DFS_ERR_IMR_CLR, B_BE_BBRPT_DFS_ERR_IMR_SET},
293 {R_BE_LA_ERRFLAG_IMR, B_BE_LA_ERRFLAG_IMR_CLR, B_BE_LA_ERRFLAG_IMR_SET},
294 {R_BE_CH_INFO_DBGFLAG_IMR, B_BE_CH_INFO_DBGFLAG_IMR_CLR, B_BE_CH_INFO_DBGFLAG_IMR_SET},
295 {R_BE_PLRLS_ERR_IMR, B_BE_PLRLS_ERR_IMR_CLR, B_BE_PLRLS_ERR_IMR_SET},
296 {R_BE_HAXI_IDCT_MSK, B_BE_HAXI_IDCT_MSK_CLR, B_BE_HAXI_IDCT_MSK_SET},
297 };
298
299 static const struct rtw89_imr_table rtw8922a_imr_dmac_table = {
300 .regs = rtw8922a_imr_dmac_regs,
301 .n_regs = ARRAY_SIZE(rtw8922a_imr_dmac_regs),
302 };
303
304 static const struct rtw89_reg_imr rtw8922a_imr_cmac_regs[] = {
305 {R_BE_RESP_IMR, B_BE_RESP_IMR_CLR, B_BE_RESP_IMR_SET},
306 {R_BE_RX_ERROR_FLAG_IMR, B_BE_RX_ERROR_FLAG_IMR_CLR, B_BE_RX_ERROR_FLAG_IMR_SET},
307 {R_BE_TX_ERROR_FLAG_IMR, B_BE_TX_ERROR_FLAG_IMR_CLR, B_BE_TX_ERROR_FLAG_IMR_SET},
308 {R_BE_RX_ERROR_FLAG_IMR_1, B_BE_TX_ERROR_FLAG_IMR_1_CLR, B_BE_TX_ERROR_FLAG_IMR_1_SET},
309 {R_BE_PTCL_IMR1, B_BE_PTCL_IMR1_CLR, B_BE_PTCL_IMR1_SET},
310 {R_BE_PTCL_IMR0, B_BE_PTCL_IMR0_CLR, B_BE_PTCL_IMR0_SET},
311 {R_BE_PTCL_IMR_2, B_BE_PTCL_IMR_2_CLR, B_BE_PTCL_IMR_2_SET},
312 {R_BE_SCHEDULE_ERR_IMR, B_BE_SCHEDULE_ERR_IMR_CLR, B_BE_SCHEDULE_ERR_IMR_SET},
313 {R_BE_C0_TXPWR_IMR, B_BE_C0_TXPWR_IMR_CLR, B_BE_C0_TXPWR_IMR_SET},
314 {R_BE_TRXPTCL_ERROR_INDICA_MASK, B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR,
315 B_BE_TRXPTCL_ERROR_INDICA_MASK_SET},
316 {R_BE_RX_ERR_IMR, B_BE_RX_ERR_IMR_CLR, B_BE_RX_ERR_IMR_SET},
317 {R_BE_PHYINFO_ERR_IMR_V1, B_BE_PHYINFO_ERR_IMR_V1_CLR, B_BE_PHYINFO_ERR_IMR_V1_SET},
318 };
319
320 static const struct rtw89_imr_table rtw8922a_imr_cmac_table = {
321 .regs = rtw8922a_imr_cmac_regs,
322 .n_regs = ARRAY_SIZE(rtw8922a_imr_cmac_regs),
323 };
324
325 static const struct rtw89_rrsr_cfgs rtw8922a_rrsr_cfgs = {
326 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
327 .rsc = {R_BE_PTCL_RRSR1, B_BE_RSC_MASK, 2},
328 };
329
330 static const struct rtw89_rfkill_regs rtw8922a_rfkill_regs = {
331 .pinmux = {R_BE_GPIO8_15_FUNC_SEL,
332 B_BE_PINMUX_GPIO9_FUNC_SEL_MASK,
333 0xf},
334 .mode = {R_BE_GPIO_EXT_CTRL + 2,
335 (B_BE_GPIO_MOD_9 | B_BE_GPIO_IO_SEL_9) >> 16,
336 0x0},
337 };
338
339 static const struct rtw89_dig_regs rtw8922a_dig_regs = {
340 .seg0_pd_reg = R_SEG0R_PD_V2,
341 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
342 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
343 .bmode_pd_reg = R_BMODE_PDTH_EN_V2,
344 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
345 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V2,
346 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
347 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
348 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
349 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
350 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
351 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
352 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
353 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3,
354 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
355 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3,
356 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
357 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3,
358 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
359 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3,
360 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
361 };
362
363 static const struct rtw89_edcca_regs rtw8922a_edcca_regs = {
364 .edcca_level = R_SEG0R_EDCCA_LVL_BE,
365 .edcca_mask = B_EDCCA_LVL_MSK0,
366 .edcca_p_mask = B_EDCCA_LVL_MSK1,
367 .ppdu_level = R_SEG0R_PPDU_LVL_BE,
368 .ppdu_mask = B_EDCCA_LVL_MSK1,
369 .p = {{
370 .rpt_a = R_EDCCA_RPT_A_BE,
371 .rpt_b = R_EDCCA_RPT_B_BE,
372 .rpt_sel = R_EDCCA_RPT_SEL_BE,
373 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
374 }, {
375 .rpt_a = R_EDCCA_RPT_P1_A_BE,
376 .rpt_b = R_EDCCA_RPT_P1_B_BE,
377 .rpt_sel = R_EDCCA_RPT_SEL_BE,
378 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
379 }},
380 .rpt_sel_be = R_EDCCA_RPTREG_SEL_BE,
381 .rpt_sel_be_mask = B_EDCCA_RPTREG_SEL_BE_MSK,
382 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST_BE,
383 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
384 };
385
386 static const struct rtw89_pmac_regs rtw8922a_pmac_regs = {
387 .cck_txon = {R_CNT_CCKTXON_V1, B_CNT_CCKTXON},
388 .cck_txen = {R_CNT_CCKTXEN_V1, B_CNT_CCKTXEN},
389 .cck_cca = {R_CNT_CCK_CCA_P0_V1, B_CNT_CCK_CCA_P0},
390 .cck_sfd_gg = {R_SFD_GG_CNT_V2, B_SFD_GG_CNT},
391 .cck_sig_gg = {R_SIG_GG_CNT_V2, B_SIG_GG_CNT_V1},
392 .cck_spoofing = {R_SPOOF_CNT_V2, B_SPOOF_CNT_V1},
393 .cck_brk = {R_BRK_CNT_V1, B_BRK_CNT},
394 .brk = {R_CNT_BRK_V1, B_CNT_BRK},
395 .brk_option = {},
396 .search_fail = {R_CNT_SEARCH_FAIL_V1, B_CNT_SEARCH_FAIL},
397 .lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_V1, B_CNT_LSIG_BRK_S_TH},
398 .lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_V1, B_CNT_LSIG_BRK_L_TH},
399 .rxl_err_parity = {R_CNT_RXL_ERR_PARITY_V1, B_CNT_RXL_ERR_PARITY},
400 .rxl_err_rate = {R_CNT_RXL_ERR_RATE_V1, B_CNT_RXL_ERR_RATE},
401 .ofdm_cca = {R_CNT_OFDM_CCA_V1, B_CNT_OFDM_CCA},
402 .cca_spoofing = {R_CNT_CCA_SPOOFING_V1, B_CNT_CCA_SPOOFING},
403 .ampdu_miss = {R_CNT_AMPDU_MISS_V1, B_CNT_AMPDU_MISS},
404 .r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE, B_R1B_RX_RPT_RST_V1},
405 .r1b_rr_sel = {},
406 .enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
407 .rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
408 .cck_crc32 = R_CNT_CCK_CRC32_P0_V1,
409 .cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
410 .cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
411 .ofdm_txon = R_CNT_OFDMTXON_V1,
412 .ofdm_txon_mask = B_CNT_OFDMTXON,
413 .ofdm_txen_mask = B_CNT_OFDMTXEN,
414 .l_crc = R_CNT_L_CRC_V1,
415 .l_crc_ok_mask = B_CNT_L_CRC_OK,
416 .l_crc_err_mask = B_CNT_L_CRC_ERR,
417 .ht_crc = R_CNT_HT_CRC_V1,
418 .ht_crc_ok_mask = B_CNT_HT_CRC_OK,
419 .ht_crc_err_mask = B_CNT_HT_CRC_ERR,
420 .vht_crc = R_CNT_VHT_CRC_V1,
421 .vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
422 .vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
423 .he_crc = R_CNT_HE_CRC_V1,
424 .he_crc_ok_mask = B_CNT_HE_CRC_OK,
425 .he_crc_err_mask = B_CNT_HE_CRC_ERR,
426 .eht_crc = R_CNT_EHT_CRC,
427 .eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
428 .eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
429 .ampdu_crc = R_CNT_AMPDU_RX_CRC32_V1,
430 .ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
431 .ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
432 };
433
434 static const struct rtw89_efuse_block_cfg rtw8922a_efuse_blocks[] = {
435 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
436 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
437 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
438 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
439 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
440 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
441 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
442 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
443 };
444
rtw8922a_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)445 static void rtw8922a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
446 enum rtw89_phy_idx phy_idx)
447 {
448 if (en) {
449 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx);
450 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx);
451 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx);
452 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx);
453 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx);
454 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx);
455 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx);
456 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx);
457 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx);
458 rtw89_phy_write32_idx(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
459 0x1, phy_idx);
460 } else {
461 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx);
462 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx);
463 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx);
464 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx);
465 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx);
466 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx);
467 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx);
468 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx);
469 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx);
470 rtw89_phy_write32_idx(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
471 0x0, phy_idx);
472 }
473 }
474
rtw8922a_pwr_on_func(struct rtw89_dev * rtwdev)475 static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
476 {
477 struct rtw89_hal *hal = &rtwdev->hal;
478 u32 val32;
479 int ret;
480
481 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_AFSM_WLSUS_EN |
482 B_BE_AFSM_PCIE_SUS_EN);
483 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_DIS_WLBT_PDNSUSEN_SOPC);
484 rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_DIS_WLBT_LPSEN_LOPC);
485 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APDM_HPDN);
486 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
487
488 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_RDY_SYSPWR,
489 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
490 if (ret)
491 return ret;
492
493 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
494 rtw89_write32_set(rtwdev, R_BE_WLRESUME_CTRL, B_BE_LPSROP_CMAC0 |
495 B_BE_LPSROP_CMAC1);
496 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFN_ONMAC);
497
498 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFN_ONMAC),
499 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
500 if (ret)
501 return ret;
502
503 rtw89_write32_clr(rtwdev, R_BE_AFE_ON_CTRL1, B_BE_REG_CK_MON_CK960M_EN);
504 rtw89_write8_set(rtwdev, R_BE_ANAPAR_POW_MAC, B_BE_POW_PC_LDO_PORT0 |
505 B_BE_POW_PC_LDO_PORT1);
506 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
507 B_BE_R_SYM_ISO_ADDA_P12PP);
508 rtw89_write8_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_PLATFORM_EN);
509
510 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
511 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
512
513 ret = read_poll_timeout(rtw89_read32, val32,
514 val32 & B_BE_HAXIDMA_IO_ST,
515 1000, 3000000, false, rtwdev,
516 R_BE_HCI_OPT_CTRL);
517 if (ret)
518 return ret;
519
520 ret = read_poll_timeout(rtw89_read32, val32,
521 !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
522 1000, 3000000, false, rtwdev,
523 R_BE_HCI_OPT_CTRL);
524 if (ret)
525 return ret;
526 }
527
528 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
529
530 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HCI_WLAN_IO_ST,
531 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
532 if (ret)
533 return ret;
534
535 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
536 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL,
537 B_BE_PCIE_FORCE_IBX_EN);
538
539 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02);
540 if (ret)
541 return ret;
542 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01);
543 if (ret)
544 return ret;
545
546 rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC1_1P3);
547
548 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
549 if (ret)
550 return ret;
551
552 rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC0_1P3);
553
554 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
555 if (ret)
556 return ret;
557 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
558 if (ret)
559 return ret;
560 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
561 if (ret)
562 return ret;
563 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10);
564 if (ret)
565 return ret;
566 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF);
567 if (ret)
568 return ret;
569 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF);
570 if (ret)
571 return ret;
572 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
573 if (ret)
574 return ret;
575 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
576 if (ret)
577 return ret;
578 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80);
579 if (ret)
580 return ret;
581 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40);
582 if (ret)
583 return ret;
584 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40);
585 if (ret)
586 return ret;
587 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60);
588 if (ret)
589 return ret;
590
591 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
592 if (ret)
593 return ret;
594
595 if (hal->cv != CHIP_CAV) {
596 rtw89_write32_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
597 rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
598 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
599
600 mdelay(1);
601
602 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
603 rtw89_write32_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
604 }
605
606 val32 = B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN | B_BE_MPDU_PROC_EN |
607 B_BE_WD_RLS_EN | B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
608 B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN | B_BE_PKT_BUF_EN |
609 B_BE_DMAC_TBL_EN | B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
610 B_BE_DISPATCHER_EN | B_BE_BBRPT_EN | B_BE_MAC_SEC_EN |
611 B_BE_H_AXIDMA_EN | B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
612 B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN;
613 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
614 val32 |= B_BE_LTR_CTL_EN;
615 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN, val32);
616
617 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
618
619 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
620 B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN | B_BE_ADDRSRCH_EN |
621 B_BE_BTCOEX_EN);
622 rtw89_write32_set(rtwdev, R_BE_CMAC_FUNC_EN,
623 B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN |
624 B_BE_SIGB_EN | B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN |
625 B_BE_PTCLTOP_EN | B_BE_SCHEDULER_EN | B_BE_TMAC_EN |
626 B_BE_RMAC_EN | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN);
627
628 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
629
630 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
631 B_BE_FEN_BBPLAT_RSTB);
632
633 return 0;
634 }
635
rtw8922a_pwr_off_func(struct rtw89_dev * rtwdev)636 static int rtw8922a_pwr_off_func(struct rtw89_dev *rtwdev)
637 {
638 u32 val32;
639 int ret;
640
641 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
642 if (ret)
643 return ret;
644 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08);
645 if (ret)
646 return ret;
647 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04);
648 if (ret)
649 return ret;
650 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF);
651 if (ret)
652 return ret;
653 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF);
654 if (ret)
655 return ret;
656 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
657 if (ret)
658 return ret;
659 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02);
660 if (ret)
661 return ret;
662 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01);
663 if (ret)
664 return ret;
665 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF);
666 if (ret)
667 return ret;
668 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF);
669 if (ret)
670 return ret;
671
672 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
673 B_BE_R_SYM_ISO_ADDA_P12PP);
674 rtw89_write8_clr(rtwdev, R_BE_ANAPAR_POW_MAC, B_BE_POW_PC_LDO_PORT0 |
675 B_BE_POW_PC_LDO_PORT1);
676 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
677 rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
678 B_BE_FEN_BBPLAT_RSTB);
679 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC0_1P3);
680
681 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20);
682 if (ret)
683 return ret;
684
685 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC1_1P3);
686
687 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40);
688 if (ret)
689 return ret;
690
691 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
692 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
693
694 ret = read_poll_timeout(rtw89_read32, val32,
695 !(val32 & B_BE_HAXIDMA_IO_ST),
696 1000, 3000000, false, rtwdev,
697 R_BE_HCI_OPT_CTRL);
698 if (ret)
699 return ret;
700
701 ret = read_poll_timeout(rtw89_read32, val32,
702 !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
703 1000, 3000000, false, rtwdev,
704 R_BE_HCI_OPT_CTRL);
705 if (ret)
706 return ret;
707 }
708
709 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
710
711 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HCI_WLAN_IO_ST),
712 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
713 if (ret)
714 return ret;
715
716 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
717
718 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFM_OFFMAC),
719 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
720 if (ret)
721 return ret;
722
723 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
724 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
725 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
726 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_SOP_EASWR);
727
728 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
729
730 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
731 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
732 } else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) {
733 val32 = rtw89_read32(rtwdev, R_BE_SYS_PW_CTRL);
734 val32 |= B_BE_AFSM_WLSUS_EN;
735 val32 &= ~B_BE_AFSM_PCIE_SUS_EN;
736 rtw89_write32(rtwdev, R_BE_SYS_PW_CTRL, val32);
737 }
738
739 rtw89_write32(rtwdev, R_BE_UDM1, 0);
740
741 return 0;
742 }
743
rtw8922a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8922a_efuse * map)744 static void rtw8922a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
745 struct rtw8922a_efuse *map)
746 {
747 struct rtw8922a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
748 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
749 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
750 u8 i, j;
751
752 tssi->thermal[RF_PATH_A] = map->path_a_therm;
753 tssi->thermal[RF_PATH_B] = map->path_b_therm;
754
755 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
756 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
757 sizeof(ofst[i]->cck_tssi));
758
759 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
760 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
761 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
762 i, j, tssi->tssi_cck[i][j]);
763
764 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
765 sizeof(ofst[i]->bw40_tssi));
766 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
767 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
768 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
769 sizeof(tssi->tssi_6g_mcs[i]));
770
771 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
772 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
773 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
774 i, j, tssi->tssi_mcs[i][j]);
775 }
776 }
777
rtw8922a_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8922a_efuse * map)778 static void rtw8922a_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
779 struct rtw8922a_efuse *map)
780 {
781 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
782 bool all_0xff = true, all_0x00 = true;
783 int i, j;
784 u8 t;
785
786 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK] = map->rx_gain_a._2g_cck;
787 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK] = map->rx_gain_b._2g_cck;
788 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM] = map->rx_gain_a._2g_ofdm;
789 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM] = map->rx_gain_b._2g_ofdm;
790 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW] = map->rx_gain_a._5g_low;
791 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW] = map->rx_gain_b._5g_low;
792 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID] = map->rx_gain_a._5g_mid;
793 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID] = map->rx_gain_b._5g_mid;
794 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH] = map->rx_gain_a._5g_high;
795 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH] = map->rx_gain_b._5g_high;
796 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0] = map->rx_gain_6g_a._6g_l0;
797 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0] = map->rx_gain_6g_b._6g_l0;
798 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1] = map->rx_gain_6g_a._6g_l1;
799 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1] = map->rx_gain_6g_b._6g_l1;
800 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0] = map->rx_gain_6g_a._6g_m0;
801 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0] = map->rx_gain_6g_b._6g_m0;
802 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1] = map->rx_gain_6g_a._6g_m1;
803 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1] = map->rx_gain_6g_b._6g_m1;
804 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0] = map->rx_gain_6g_a._6g_h0;
805 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0] = map->rx_gain_6g_b._6g_h0;
806 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1] = map->rx_gain_6g_a._6g_h1;
807 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1] = map->rx_gain_6g_b._6g_h1;
808 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0] = map->rx_gain_6g_a._6g_uh0;
809 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0] = map->rx_gain_6g_b._6g_uh0;
810 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1] = map->rx_gain_6g_a._6g_uh1;
811 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1] = map->rx_gain_6g_b._6g_uh1;
812
813 for (i = RF_PATH_A; i <= RF_PATH_B; i++)
814 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) {
815 t = gain->offset[i][j];
816 if (t != 0xff)
817 all_0xff = false;
818 if (t != 0x0)
819 all_0x00 = false;
820
821 /* transform: sign-bit + U(7,2) to S(8,2) */
822 if (t & 0x80)
823 gain->offset[i][j] = (t ^ 0x7f) + 1;
824 }
825
826 gain->offset_valid = !all_0xff && !all_0x00;
827 }
828
rtw8922a_read_efuse_mac_addr(struct rtw89_dev * rtwdev,u32 addr)829 static void rtw8922a_read_efuse_mac_addr(struct rtw89_dev *rtwdev, u32 addr)
830 {
831 struct rtw89_efuse *efuse = &rtwdev->efuse;
832 u16 val;
833 int i;
834
835 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) {
836 val = rtw89_read16(rtwdev, addr);
837 efuse->addr[i] = val & 0xff;
838 efuse->addr[i + 1] = val >> 8;
839 }
840 }
841
rtw8922a_read_efuse_pci_sdio(struct rtw89_dev * rtwdev,u8 * log_map)842 static int rtw8922a_read_efuse_pci_sdio(struct rtw89_dev *rtwdev, u8 *log_map)
843 {
844 struct rtw89_efuse *efuse = &rtwdev->efuse;
845
846 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
847 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104);
848 else
849 ether_addr_copy(efuse->addr, log_map + 0x001A);
850
851 return 0;
852 }
853
rtw8922a_read_efuse_usb(struct rtw89_dev * rtwdev,u8 * log_map)854 static int rtw8922a_read_efuse_usb(struct rtw89_dev *rtwdev, u8 *log_map)
855 {
856 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078);
857
858 return 0;
859 }
860
rtw8922a_read_efuse_rf(struct rtw89_dev * rtwdev,u8 * log_map)861 static int rtw8922a_read_efuse_rf(struct rtw89_dev *rtwdev, u8 *log_map)
862 {
863 struct rtw8922a_efuse *map = (struct rtw8922a_efuse *)log_map;
864 struct rtw89_efuse *efuse = &rtwdev->efuse;
865
866 efuse->rfe_type = map->rfe_type;
867 efuse->xtal_cap = map->xtal_k;
868 efuse->country_code[0] = map->country_code[0];
869 efuse->country_code[1] = map->country_code[1];
870 rtw8922a_efuse_parsing_tssi(rtwdev, map);
871 rtw8922a_efuse_parsing_gain_offset(rtwdev, map);
872
873 return 0;
874 }
875
rtw8922a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)876 static int rtw8922a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
877 enum rtw89_efuse_block block)
878 {
879 struct rtw89_efuse *efuse = &rtwdev->efuse;
880 int ret;
881
882 switch (block) {
883 case RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO:
884 ret = rtw8922a_read_efuse_pci_sdio(rtwdev, log_map);
885 break;
886 case RTW89_EFUSE_BLOCK_HCI_DIG_USB:
887 ret = rtw8922a_read_efuse_usb(rtwdev, log_map);
888 break;
889 case RTW89_EFUSE_BLOCK_RF:
890 ret = rtw8922a_read_efuse_rf(rtwdev, log_map);
891 break;
892 default:
893 ret = 0;
894 break;
895 }
896
897 if (!ret && is_zero_ether_addr(efuse->addr)) {
898 rtw89_info(rtwdev, "efuse mac address is zero, using random mac\n");
899 eth_random_addr(efuse->addr);
900 }
901
902 return ret;
903 }
904
905 #define THM_TRIM_POSITIVE_MASK BIT(6)
906 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
907
rtw8922a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)908 static void rtw8922a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
909 u8 *phycap_map)
910 {
911 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733};
912 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
913 u32 addr = rtwdev->chip->phycap_addr;
914 bool pg = true;
915 u8 pg_th;
916 s8 val;
917 u8 i;
918
919 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
920 pg_th = phycap_map[thm_trim_addr[i] - addr];
921 if (pg_th == 0xff) {
922 info->thermal_trim[i] = 0;
923 pg = false;
924 break;
925 }
926
927 val = u8_get_bits(pg_th, THM_TRIM_MAGNITUDE_MASK);
928
929 if (!(pg_th & THM_TRIM_POSITIVE_MASK))
930 val *= -1;
931
932 info->thermal_trim[i] = val;
933
934 rtw89_debug(rtwdev, RTW89_DBG_RFK,
935 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n",
936 i, pg_th, val);
937 }
938
939 info->pg_thermal_trim = pg;
940 }
941
rtw8922a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)942 static void rtw8922a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
943 u8 *phycap_map)
944 {
945 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734};
946 static const u32 check_pa_pad_trim_addr = 0x1700;
947 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
948 u32 addr = rtwdev->chip->phycap_addr;
949 u8 val;
950 u8 i;
951
952 val = phycap_map[check_pa_pad_trim_addr - addr];
953 if (val != 0xff)
954 info->pg_pa_bias_trim = true;
955
956 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
957 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
958
959 rtw89_debug(rtwdev, RTW89_DBG_RFK,
960 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
961 i, info->pa_bias_trim[i]);
962 }
963 }
964
rtw8922a_pa_bias_trim(struct rtw89_dev * rtwdev)965 static void rtw8922a_pa_bias_trim(struct rtw89_dev *rtwdev)
966 {
967 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
968 u8 pabias_2g, pabias_5g;
969 u8 i;
970
971 if (!info->pg_pa_bias_trim) {
972 rtw89_debug(rtwdev, RTW89_DBG_RFK,
973 "[PA_BIAS][TRIM] no PG, do nothing\n");
974
975 return;
976 }
977
978 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
979 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
980 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
981
982 rtw89_debug(rtwdev, RTW89_DBG_RFK,
983 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
984 i, pabias_2g, pabias_5g);
985
986 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG_V1, pabias_2g);
987 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA_V1, pabias_5g);
988 }
989 }
990
rtw8922a_phycap_parsing_pad_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)991 static void rtw8922a_phycap_parsing_pad_bias_trim(struct rtw89_dev *rtwdev,
992 u8 *phycap_map)
993 {
994 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735};
995 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
996 u32 addr = rtwdev->chip->phycap_addr;
997 u8 i;
998
999 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
1000 info->pad_bias_trim[i] = phycap_map[pad_bias_trim_addr[i] - addr];
1001
1002 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1003 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n",
1004 i, info->pad_bias_trim[i]);
1005 }
1006 }
1007
rtw8922a_pad_bias_trim(struct rtw89_dev * rtwdev)1008 static void rtw8922a_pad_bias_trim(struct rtw89_dev *rtwdev)
1009 {
1010 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1011 u8 pad_bias_2g, pad_bias_5g;
1012 u8 i;
1013
1014 if (!info->pg_pa_bias_trim) {
1015 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1016 "[PAD_BIAS][TRIM] no PG, do nothing\n");
1017 return;
1018 }
1019
1020 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
1021 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0));
1022 pad_bias_5g = u8_get_bits(info->pad_bias_trim[i], GENMASK(7, 4));
1023
1024 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1025 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
1026 i, pad_bias_2g, pad_bias_5g);
1027
1028 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXG_V1, pad_bias_2g);
1029 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXA_V1, pad_bias_5g);
1030 }
1031 }
1032
rtw8922a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)1033 static int rtw8922a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
1034 {
1035 rtw8922a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
1036 rtw8922a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
1037 rtw8922a_phycap_parsing_pad_bias_trim(rtwdev, phycap_map);
1038
1039 return 0;
1040 }
1041
rtw8922a_power_trim(struct rtw89_dev * rtwdev)1042 static void rtw8922a_power_trim(struct rtw89_dev *rtwdev)
1043 {
1044 rtw8922a_pa_bias_trim(rtwdev);
1045 rtw8922a_pad_bias_trim(rtwdev);
1046 }
1047
rtw8922a_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)1048 static void rtw8922a_set_channel_mac(struct rtw89_dev *rtwdev,
1049 const struct rtw89_chan *chan,
1050 u8 mac_idx)
1051 {
1052 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_BE_TX_SUB_BAND_VALUE, mac_idx);
1053 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_BE_TXRATE_CHK, mac_idx);
1054 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_RFMOD, mac_idx);
1055 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0;
1056 u8 rf_mod_val, chk_rate_mask;
1057 u32 txsb;
1058 u32 reg;
1059
1060 switch (chan->band_width) {
1061 case RTW89_CHANNEL_WIDTH_160:
1062 txsb80 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_80);
1063 fallthrough;
1064 case RTW89_CHANNEL_WIDTH_80:
1065 txsb40 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
1066 fallthrough;
1067 case RTW89_CHANNEL_WIDTH_40:
1068 txsb20 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
1069 break;
1070 default:
1071 break;
1072 }
1073
1074 switch (chan->band_width) {
1075 case RTW89_CHANNEL_WIDTH_160:
1076 rf_mod_val = BE_WMAC_RFMOD_160M;
1077 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
1078 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK) |
1079 u32_encode_bits(txsb80, B_BE_TXSB_80M_MASK);
1080 break;
1081 case RTW89_CHANNEL_WIDTH_80:
1082 rf_mod_val = BE_WMAC_RFMOD_80M;
1083 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
1084 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK);
1085 break;
1086 case RTW89_CHANNEL_WIDTH_40:
1087 rf_mod_val = BE_WMAC_RFMOD_40M;
1088 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK);
1089 break;
1090 case RTW89_CHANNEL_WIDTH_20:
1091 default:
1092 rf_mod_val = BE_WMAC_RFMOD_20M;
1093 txsb = 0;
1094 break;
1095 }
1096
1097 if (txsb20 <= BE_PRI20_BITMAP_MAX)
1098 txsb |= u32_encode_bits(BIT(txsb20), B_BE_PRI20_BITMAP_MASK);
1099
1100 rtw89_write8_mask(rtwdev, rf_mod, B_BE_WMAC_RFMOD_MASK, rf_mod_val);
1101 rtw89_write32(rtwdev, sub_carr, txsb);
1102
1103 switch (chan->band_type) {
1104 case RTW89_BAND_2G:
1105 chk_rate_mask = B_BE_BAND_MODE;
1106 break;
1107 case RTW89_BAND_5G:
1108 case RTW89_BAND_6G:
1109 chk_rate_mask = B_BE_CHECK_CCK_EN | B_BE_RTS_LIMIT_IN_OFDM6;
1110 break;
1111 default:
1112 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
1113 return;
1114 }
1115
1116 rtw89_write8_clr(rtwdev, chk_rate, B_BE_BAND_MODE | B_BE_CHECK_CCK_EN |
1117 B_BE_RTS_LIMIT_IN_OFDM6);
1118 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
1119
1120 switch (chan->band_width) {
1121 case RTW89_CHANNEL_WIDTH_320:
1122 case RTW89_CHANNEL_WIDTH_160:
1123 case RTW89_CHANNEL_WIDTH_80:
1124 case RTW89_CHANNEL_WIDTH_40:
1125 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_1, mac_idx);
1126 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41);
1127 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
1128 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41);
1129 break;
1130 default:
1131 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_1, mac_idx);
1132 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f);
1133 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
1134 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e);
1135 break;
1136 }
1137 }
1138
1139 static const u32 rtw8922a_sco_barker_threshold[14] = {
1140 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
1141 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
1142 };
1143
1144 static const u32 rtw8922a_sco_cck_threshold[14] = {
1145 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
1146 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
1147 };
1148
rtw8922a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch,enum rtw89_bandwidth bw,enum rtw89_phy_idx phy_idx)1149 static int rtw8922a_ctrl_sco_cck(struct rtw89_dev *rtwdev,
1150 u8 primary_ch, enum rtw89_bandwidth bw,
1151 enum rtw89_phy_idx phy_idx)
1152 {
1153 u8 ch_element;
1154
1155 if (primary_ch >= 14)
1156 return -EINVAL;
1157
1158 ch_element = primary_ch - 1;
1159
1160 rtw89_phy_write32_idx(rtwdev, R_BK_FC0INV, B_BK_FC0INV,
1161 rtw8922a_sco_barker_threshold[ch_element],
1162 phy_idx);
1163 rtw89_phy_write32_idx(rtwdev, R_CCK_FC0INV, B_CCK_FC0INV,
1164 rtw8922a_sco_cck_threshold[ch_element],
1165 phy_idx);
1166
1167 return 0;
1168 }
1169
1170 struct rtw8922a_bb_gain {
1171 u32 gain_g[BB_PATH_NUM_8922A];
1172 u32 gain_a[BB_PATH_NUM_8922A];
1173 u32 gain_g_mask;
1174 u32 gain_a_mask;
1175 };
1176
1177 static const struct rtw89_reg_def rpl_comp_bw160[RTW89_BW20_SC_160M] = {
1178 { .addr = 0x41E8, .mask = 0xFF00},
1179 { .addr = 0x41E8, .mask = 0xFF0000},
1180 { .addr = 0x41E8, .mask = 0xFF000000},
1181 { .addr = 0x41EC, .mask = 0xFF},
1182 { .addr = 0x41EC, .mask = 0xFF00},
1183 { .addr = 0x41EC, .mask = 0xFF0000},
1184 { .addr = 0x41EC, .mask = 0xFF000000},
1185 { .addr = 0x41F0, .mask = 0xFF}
1186 };
1187
1188 static const struct rtw89_reg_def rpl_comp_bw80[RTW89_BW20_SC_80M] = {
1189 { .addr = 0x41F4, .mask = 0xFF},
1190 { .addr = 0x41F4, .mask = 0xFF00},
1191 { .addr = 0x41F4, .mask = 0xFF0000},
1192 { .addr = 0x41F4, .mask = 0xFF000000}
1193 };
1194
1195 static const struct rtw89_reg_def rpl_comp_bw40[RTW89_BW20_SC_40M] = {
1196 { .addr = 0x41F0, .mask = 0xFF0000},
1197 { .addr = 0x41F0, .mask = 0xFF000000}
1198 };
1199
1200 static const struct rtw89_reg_def rpl_comp_bw20[RTW89_BW20_SC_20M] = {
1201 { .addr = 0x41F0, .mask = 0xFF00}
1202 };
1203
1204 static const struct rtw8922a_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
1205 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
1206 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1207 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
1208 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1209 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
1210 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1211 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
1212 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1213 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
1214 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1215 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
1216 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1217 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
1218 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1219 };
1220
1221 static const struct rtw8922a_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
1222 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
1223 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
1224 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
1225 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
1226 };
1227
1228 static const struct rtw8922a_bb_gain bb_op1db_lna[LNA_GAIN_NUM] = {
1229 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x4078, 0x4478},
1230 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1231 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
1232 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1233 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
1234 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1235 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
1236 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
1237 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
1238 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1239 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
1240 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1241 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
1242 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1243 };
1244
1245 static const struct rtw8922a_bb_gain bb_op1db_tia_lna[TIA_LNA_OP1DB_NUM] = {
1246 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4080, 0x4480},
1247 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1248 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4084, 0x4484},
1249 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1250 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1251 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1252 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1253 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1254 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1255 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1256 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4088, 0x4488},
1257 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1258 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1259 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1260 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1261 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1262 };
1263
1264 struct rtw8922a_bb_gain_bypass {
1265 u32 gain_g[BB_PATH_NUM_8922A];
1266 u32 gain_a[BB_PATH_NUM_8922A];
1267 u32 gain_mask_g;
1268 u32 gain_mask_a;
1269 };
1270
rtw8922a_set_rpl_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1271 static void rtw8922a_set_rpl_gain(struct rtw89_dev *rtwdev,
1272 const struct rtw89_chan *chan,
1273 enum rtw89_rf_path path,
1274 enum rtw89_phy_idx phy_idx)
1275 {
1276 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1277 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1278 u32 reg_path_ofst = 0;
1279 u32 mask;
1280 s32 val;
1281 u32 reg;
1282 int i;
1283
1284 if (path == RF_PATH_B)
1285 reg_path_ofst = 0x400;
1286
1287 for (i = 0; i < RTW89_BW20_SC_160M; i++) {
1288 reg = rpl_comp_bw160[i].addr | reg_path_ofst;
1289 mask = rpl_comp_bw160[i].mask;
1290 val = gain->rpl_ofst_160[gain_band][path][i];
1291 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1292 }
1293
1294 for (i = 0; i < RTW89_BW20_SC_80M; i++) {
1295 reg = rpl_comp_bw80[i].addr | reg_path_ofst;
1296 mask = rpl_comp_bw80[i].mask;
1297 val = gain->rpl_ofst_80[gain_band][path][i];
1298 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1299 }
1300
1301 for (i = 0; i < RTW89_BW20_SC_40M; i++) {
1302 reg = rpl_comp_bw40[i].addr | reg_path_ofst;
1303 mask = rpl_comp_bw40[i].mask;
1304 val = gain->rpl_ofst_40[gain_band][path][i];
1305 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1306 }
1307
1308 for (i = 0; i < RTW89_BW20_SC_20M; i++) {
1309 reg = rpl_comp_bw20[i].addr | reg_path_ofst;
1310 mask = rpl_comp_bw20[i].mask;
1311 val = gain->rpl_ofst_20[gain_band][path][i];
1312 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1313 }
1314 }
1315
rtw8922a_set_lna_tia_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1316 static void rtw8922a_set_lna_tia_gain(struct rtw89_dev *rtwdev,
1317 const struct rtw89_chan *chan,
1318 enum rtw89_rf_path path,
1319 enum rtw89_phy_idx phy_idx)
1320 {
1321 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1322 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1323 enum rtw89_phy_bb_bw_be bw_type;
1324 s32 val;
1325 u32 reg;
1326 u32 mask;
1327 int i;
1328
1329 bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1330 RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1331
1332 for (i = 0; i < LNA_GAIN_NUM; i++) {
1333 if (chan->band_type == RTW89_BAND_2G) {
1334 reg = bb_gain_lna[i].gain_g[path];
1335 mask = bb_gain_lna[i].gain_g_mask;
1336 } else {
1337 reg = bb_gain_lna[i].gain_a[path];
1338 mask = bb_gain_lna[i].gain_a_mask;
1339 }
1340 val = gain->lna_gain[gain_band][bw_type][path][i];
1341 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1342 }
1343
1344 for (i = 0; i < TIA_GAIN_NUM; i++) {
1345 if (chan->band_type == RTW89_BAND_2G) {
1346 reg = bb_gain_tia[i].gain_g[path];
1347 mask = bb_gain_tia[i].gain_g_mask;
1348 } else {
1349 reg = bb_gain_tia[i].gain_a[path];
1350 mask = bb_gain_tia[i].gain_a_mask;
1351 }
1352 val = gain->tia_gain[gain_band][bw_type][path][i];
1353 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1354 }
1355
1356 for (i = 0; i < LNA_GAIN_NUM; i++) {
1357 if (chan->band_type == RTW89_BAND_2G) {
1358 reg = bb_op1db_lna[i].gain_g[path];
1359 mask = bb_op1db_lna[i].gain_g_mask;
1360 } else {
1361 reg = bb_op1db_lna[i].gain_a[path];
1362 mask = bb_op1db_lna[i].gain_a_mask;
1363 }
1364 val = gain->lna_op1db[gain_band][bw_type][path][i];
1365 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1366 }
1367
1368 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) {
1369 if (chan->band_type == RTW89_BAND_2G) {
1370 reg = bb_op1db_tia_lna[i].gain_g[path];
1371 mask = bb_op1db_tia_lna[i].gain_g_mask;
1372 } else {
1373 reg = bb_op1db_tia_lna[i].gain_a[path];
1374 mask = bb_op1db_tia_lna[i].gain_a_mask;
1375 }
1376 val = gain->tia_lna_op1db[gain_band][bw_type][path][i];
1377 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1378 }
1379 }
1380
rtw8922a_set_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1381 static void rtw8922a_set_gain(struct rtw89_dev *rtwdev,
1382 const struct rtw89_chan *chan,
1383 enum rtw89_rf_path path,
1384 enum rtw89_phy_idx phy_idx)
1385 {
1386 rtw8922a_set_lna_tia_gain(rtwdev, chan, path, phy_idx);
1387 rtw8922a_set_rpl_gain(rtwdev, chan, path, phy_idx);
1388 }
1389
rtw8922a_set_rx_gain_normal_cck(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1390 static void rtw8922a_set_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1391 const struct rtw89_chan *chan,
1392 enum rtw89_rf_path path)
1393 {
1394 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1395 s8 value = -gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; /* S(8,2) */
1396 u8 fraction = value & 0x3;
1397
1398 if (fraction) {
1399 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20,
1400 (0x4 - fraction) << 1);
1401 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40,
1402 (0x4 - fraction) << 1);
1403
1404 value >>= 2;
1405 rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
1406 value + 1 + 0xdc);
1407 } else {
1408 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0);
1409 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0);
1410
1411 value >>= 2;
1412 rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
1413 value + 0xdc);
1414 }
1415 }
1416
rtw8922a_set_rx_gain_normal_ofdm(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1417 static void rtw8922a_set_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1418 const struct rtw89_chan *chan,
1419 enum rtw89_rf_path path)
1420 {
1421 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8};
1422 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608};
1423 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8};
1424 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8};
1425 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8};
1426 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1427 enum rtw89_gain_offset gain_band;
1428 s8 v1, v2, v3;
1429 s32 value;
1430
1431 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
1432 value = gain->offset[path][gain_band];
1433 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8);
1434
1435 value *= -4;
1436 v1 = clamp_t(s32, value, S8_MIN, S8_MAX);
1437 value -= v1;
1438 v2 = clamp_t(s32, value, S8_MIN, S8_MAX);
1439 value -= v2;
1440 v3 = clamp_t(s32, value, S8_MIN, S8_MAX);
1441
1442 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1);
1443 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2);
1444 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3);
1445
1446 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1);
1447 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2);
1448 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3);
1449 }
1450
rtw8922a_set_rx_gain_normal(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1451 static void rtw8922a_set_rx_gain_normal(struct rtw89_dev *rtwdev,
1452 const struct rtw89_chan *chan,
1453 enum rtw89_rf_path path)
1454 {
1455 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1456
1457 if (!gain->offset_valid)
1458 return;
1459
1460 if (chan->band_type == RTW89_BAND_2G)
1461 rtw8922a_set_rx_gain_normal_cck(rtwdev, chan, path);
1462
1463 rtw8922a_set_rx_gain_normal_ofdm(rtwdev, chan, path);
1464 }
1465
rtw8922a_set_cck_parameters(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)1466 static void rtw8922a_set_cck_parameters(struct rtw89_dev *rtwdev, u8 central_ch,
1467 enum rtw89_phy_idx phy_idx)
1468 {
1469 if (central_ch == 14) {
1470 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx);
1471 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx);
1472 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx);
1473 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx);
1474 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx);
1475 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx);
1476 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx);
1477 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx);
1478 } else {
1479 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx);
1480 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx);
1481 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx);
1482 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx);
1483 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx);
1484 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx);
1485 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx);
1486 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx);
1487 }
1488 }
1489
rtw8922a_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1490 static void rtw8922a_ctrl_ch(struct rtw89_dev *rtwdev,
1491 const struct rtw89_chan *chan,
1492 enum rtw89_phy_idx phy_idx)
1493 {
1494 static const u32 band_sel[2] = {0x4160, 0x4560};
1495 u16 central_freq = chan->freq;
1496 u8 central_ch = chan->channel;
1497 u8 band = chan->band_type;
1498 bool is_2g = band == RTW89_BAND_2G;
1499 u8 chan_idx;
1500 u8 path;
1501 u8 sco;
1502
1503 if (!central_freq) {
1504 rtw89_warn(rtwdev, "Invalid central_freq\n");
1505 return;
1506 }
1507
1508 rtw8922a_set_gain(rtwdev, chan, RF_PATH_A, phy_idx);
1509 rtw8922a_set_gain(rtwdev, chan, RF_PATH_B, phy_idx);
1510
1511 for (path = RF_PATH_A; path < BB_PATH_NUM_8922A; path++)
1512 rtw89_phy_write32_idx(rtwdev, band_sel[path], BIT((26)), is_2g, phy_idx);
1513
1514 rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_A);
1515 rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_B);
1516
1517 rtw89_phy_write32_idx(rtwdev, R_FC0, B_FC0, central_freq, phy_idx);
1518 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1519 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_FC0_INV, sco, phy_idx);
1520
1521 if (band == RTW89_BAND_2G)
1522 rtw8922a_set_cck_parameters(rtwdev, central_ch, phy_idx);
1523
1524 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1525 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1526 }
1527
1528 static void
rtw8922a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_sb,u8 bw,enum rtw89_phy_idx phy_idx)1529 rtw8922a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_sb, u8 bw,
1530 enum rtw89_phy_idx phy_idx)
1531 {
1532 switch (bw) {
1533 case RTW89_CHANNEL_WIDTH_5:
1534 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1535 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx);
1536 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1537 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1538 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1539 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1540 break;
1541 case RTW89_CHANNEL_WIDTH_10:
1542 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1543 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx);
1544 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1545 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1546 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1547 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1548 break;
1549 case RTW89_CHANNEL_WIDTH_20:
1550 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1551 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1552 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1553 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1554 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1555 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1556 break;
1557 case RTW89_CHANNEL_WIDTH_40:
1558 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx);
1559 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1560 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1561 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1562 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1563 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1564 break;
1565 case RTW89_CHANNEL_WIDTH_80:
1566 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx);
1567 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1568 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1569 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1570 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
1571 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
1572 break;
1573 case RTW89_CHANNEL_WIDTH_160:
1574 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx);
1575 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1576 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1577 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1578 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
1579 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
1580 break;
1581 default:
1582 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri_sb:%d)\n", bw,
1583 pri_sb);
1584 break;
1585 }
1586
1587 if (bw == RTW89_CHANNEL_WIDTH_40)
1588 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 1, phy_idx);
1589 else
1590 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx);
1591 }
1592
rtw8922a_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1593 static u32 rtw8922a_spur_freq(struct rtw89_dev *rtwdev,
1594 const struct rtw89_chan *chan)
1595 {
1596 return 0;
1597 }
1598
1599 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1600 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1601 #define MAX_TONE_NUM 2048
1602
rtw8922a_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1603 static void rtw8922a_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1604 const struct rtw89_chan *chan,
1605 enum rtw89_phy_idx phy_idx)
1606 {
1607 s32 freq_diff, csi_idx, csi_tone_idx;
1608 u32 spur_freq;
1609
1610 spur_freq = rtw8922a_spur_freq(rtwdev, chan);
1611 if (spur_freq == 0) {
1612 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN,
1613 0, phy_idx);
1614 return;
1615 }
1616
1617 freq_diff = (spur_freq - chan->freq) * 1000000;
1618 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1619 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1620
1621 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_TONE_IDX,
1622 csi_tone_idx, phy_idx);
1623 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN, 1, phy_idx);
1624 }
1625
1626 static const struct rtw89_nbi_reg_def rtw8922a_nbi_reg_def[] = {
1627 [RF_PATH_A] = {
1628 .notch1_idx = {0x41a0, 0xFF},
1629 .notch1_frac_idx = {0x41a0, 0xC00},
1630 .notch1_en = {0x41a0, 0x1000},
1631 .notch2_idx = {0x41ac, 0xFF},
1632 .notch2_frac_idx = {0x41ac, 0xC00},
1633 .notch2_en = {0x41ac, 0x1000},
1634 },
1635 [RF_PATH_B] = {
1636 .notch1_idx = {0x45a0, 0xFF},
1637 .notch1_frac_idx = {0x45a0, 0xC00},
1638 .notch1_en = {0x45a0, 0x1000},
1639 .notch2_idx = {0x45ac, 0xFF},
1640 .notch2_frac_idx = {0x45ac, 0xC00},
1641 .notch2_en = {0x45ac, 0x1000},
1642 },
1643 };
1644
rtw8922a_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1645 static void rtw8922a_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1646 const struct rtw89_chan *chan,
1647 enum rtw89_rf_path path,
1648 enum rtw89_phy_idx phy_idx)
1649 {
1650 const struct rtw89_nbi_reg_def *nbi = &rtw8922a_nbi_reg_def[path];
1651 s32 nbi_frac_idx, nbi_frac_tone_idx;
1652 s32 nbi_idx, nbi_tone_idx;
1653 bool notch2_chk = false;
1654 u32 spur_freq, fc;
1655 s32 freq_diff;
1656
1657 spur_freq = rtw8922a_spur_freq(rtwdev, chan);
1658 if (spur_freq == 0) {
1659 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1660 nbi->notch1_en.mask, 0, phy_idx);
1661 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1662 nbi->notch2_en.mask, 0, phy_idx);
1663 return;
1664 }
1665
1666 fc = chan->freq;
1667 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1668 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1669 if ((fc > spur_freq &&
1670 chan->channel < chan->primary_channel) ||
1671 (fc < spur_freq &&
1672 chan->channel > chan->primary_channel))
1673 notch2_chk = true;
1674 }
1675
1676 freq_diff = (spur_freq - fc) * 1000000;
1677 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1678 &nbi_frac_idx);
1679
1680 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1681 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1682 } else {
1683 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1684 128 : 256;
1685
1686 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1687 }
1688 nbi_frac_tone_idx =
1689 s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1690
1691 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1692 rtw89_phy_write32_idx(rtwdev, nbi->notch2_idx.addr,
1693 nbi->notch2_idx.mask, nbi_tone_idx, phy_idx);
1694 rtw89_phy_write32_idx(rtwdev, nbi->notch2_frac_idx.addr,
1695 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx,
1696 phy_idx);
1697 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1698 nbi->notch2_en.mask, 0, phy_idx);
1699 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1700 nbi->notch2_en.mask, 1, phy_idx);
1701 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1702 nbi->notch1_en.mask, 0, phy_idx);
1703 } else {
1704 rtw89_phy_write32_idx(rtwdev, nbi->notch1_idx.addr,
1705 nbi->notch1_idx.mask, nbi_tone_idx, phy_idx);
1706 rtw89_phy_write32_idx(rtwdev, nbi->notch1_frac_idx.addr,
1707 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx,
1708 phy_idx);
1709 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1710 nbi->notch1_en.mask, 0, phy_idx);
1711 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1712 nbi->notch1_en.mask, 1, phy_idx);
1713 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1714 nbi->notch2_en.mask, 0, phy_idx);
1715 }
1716 }
1717
rtw8922a_spur_elimination(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1718 static void rtw8922a_spur_elimination(struct rtw89_dev *rtwdev,
1719 const struct rtw89_chan *chan,
1720 enum rtw89_phy_idx phy_idx)
1721 {
1722 rtw8922a_set_csi_tone_idx(rtwdev, chan, phy_idx);
1723 rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A, phy_idx);
1724 rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B, phy_idx);
1725 }
1726
rtw8922a_ctrl_afe_dac(struct rtw89_dev * rtwdev,enum rtw89_bandwidth bw,enum rtw89_rf_path path)1727 static void rtw8922a_ctrl_afe_dac(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
1728 enum rtw89_rf_path path)
1729 {
1730 u32 cr_ofst = 0x0;
1731
1732 if (path == RF_PATH_B)
1733 cr_ofst = 0x100;
1734
1735 switch (bw) {
1736 case RTW89_CHANNEL_WIDTH_5:
1737 case RTW89_CHANNEL_WIDTH_10:
1738 case RTW89_CHANNEL_WIDTH_20:
1739 case RTW89_CHANNEL_WIDTH_40:
1740 case RTW89_CHANNEL_WIDTH_80:
1741 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE);
1742 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7);
1743 break;
1744 case RTW89_CHANNEL_WIDTH_160:
1745 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD);
1746 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6);
1747 break;
1748 default:
1749 break;
1750 }
1751 }
1752
1753 static const struct rtw89_reg2_def bb_mcu0_init_reg[] = {
1754 {0x6990, 0x00000000},
1755 {0x6994, 0x00000000},
1756 {0x6998, 0x00000000},
1757 {0x6820, 0xFFFFFFFE},
1758 {0x6800, 0xC0000FFE},
1759 {0x6808, 0x76543210},
1760 {0x6814, 0xBFBFB000},
1761 {0x6818, 0x0478C009},
1762 {0x6800, 0xC0000FFF},
1763 {0x6820, 0xFFFFFFFF},
1764 };
1765
1766 static const struct rtw89_reg2_def bb_mcu1_init_reg[] = {
1767 {0x6990, 0x00000000},
1768 {0x6994, 0x00000000},
1769 {0x6998, 0x00000000},
1770 {0x6820, 0xFFFFFFFE},
1771 {0x6800, 0xC0000FFE},
1772 {0x6808, 0x76543210},
1773 {0x6814, 0xBFBFB000},
1774 {0x6818, 0x0478C009},
1775 {0x6800, 0xC0000FFF},
1776 {0x6820, 0xFFFFFFFF},
1777 };
1778
rtw8922a_bbmcu_cr_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1779 static void rtw8922a_bbmcu_cr_init(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1780 {
1781 const struct rtw89_reg2_def *reg;
1782 int size;
1783 int i;
1784
1785 if (phy_idx == RTW89_PHY_0) {
1786 reg = bb_mcu0_init_reg;
1787 size = ARRAY_SIZE(bb_mcu0_init_reg);
1788 } else {
1789 reg = bb_mcu1_init_reg;
1790 size = ARRAY_SIZE(bb_mcu1_init_reg);
1791 }
1792
1793 for (i = 0; i < size; i++, reg++)
1794 rtw89_bbmcu_write32(rtwdev, reg->addr, reg->data, phy_idx);
1795 }
1796
1797 static const u32 dmac_sys_mask[2] = {B_BE_DMAC_BB_PHY0_MASK, B_BE_DMAC_BB_PHY1_MASK};
1798 static const u32 bbrst_mask[2] = {B_BE_FEN_BBPLAT_RSTB, B_BE_FEN_BB1PLAT_RSTB};
1799 static const u32 glbrst_mask[2] = {B_BE_FEN_BB_IP_RSTN, B_BE_FEN_BB1_IP_RSTN};
1800 static const u32 mcu_bootrdy_mask[2] = {B_BE_BOOT_RDY0, B_BE_BOOT_RDY1};
1801
rtw8922a_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1802 static void rtw8922a_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1803 {
1804 u32 rdy = 0;
1805
1806 if (phy_idx == RTW89_PHY_1)
1807 rdy = 1;
1808
1809 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9);
1810 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0);
1811 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0);
1812 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1);
1813 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx], rdy);
1814 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0);
1815
1816 fsleep(1);
1817 rtw8922a_bbmcu_cr_init(rtwdev, phy_idx);
1818 }
1819
rtw8922a_bb_postinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1820 static void rtw8922a_bb_postinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1821 {
1822 if (phy_idx == RTW89_PHY_0)
1823 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx]);
1824 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx]);
1825
1826 rtw89_phy_write32_set(rtwdev, R_BBCLK, B_CLK_640M);
1827 rtw89_phy_write32_clr(rtwdev, R_TXSCALE, B_TXFCTR_EN);
1828 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200);
1829 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA);
1830 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA);
1831 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA);
1832 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1);
1833 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1);
1834 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0);
1835 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0);
1836 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0);
1837 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0);
1838 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1);
1839 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1);
1840 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1);
1841 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1);
1842 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0);
1843 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000);
1844 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0);
1845 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0);
1846 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200);
1847 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx);
1848 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx);
1849 }
1850
rtw8922a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,bool en,enum rtw89_phy_idx phy_idx)1851 static void rtw8922a_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1852 bool en, enum rtw89_phy_idx phy_idx)
1853 {
1854 if (en) {
1855 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1856 if (band == RTW89_BAND_2G)
1857 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1,
1858 B_RXCCA_BE1_DIS, 0x0, phy_idx);
1859 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx);
1860 } else {
1861 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx);
1862 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx);
1863 fsleep(1);
1864 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1865 }
1866 }
1867
rtw8922a_ctrl_tx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,enum rtw89_phy_idx phy_idx)1868 static int rtw8922a_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev,
1869 enum rtw89_rf_path tx_path,
1870 enum rtw89_phy_idx phy_idx)
1871 {
1872 struct rtw89_reg2_def path_com_cr[] = {
1873 {0x11A00, 0x21C86900},
1874 {0x11A04, 0x00E4E433},
1875 {0x11A08, 0x39390CC9},
1876 {0x11A0C, 0x4E433240},
1877 {0x11A10, 0x90CC900E},
1878 {0x11A14, 0x00240393},
1879 {0x11A18, 0x201C8600},
1880 };
1881 int ret = 0;
1882 u32 reg;
1883 int i;
1884
1885 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx);
1886
1887 if (phy_idx == RTW89_PHY_1 && !rtwdev->dbcc_en)
1888 return 0;
1889
1890 if (tx_path == RF_PATH_A) {
1891 path_com_cr[0].data = 0x21C82900;
1892 path_com_cr[1].data = 0x00E4E431;
1893 path_com_cr[2].data = 0x39390C49;
1894 path_com_cr[3].data = 0x4E431240;
1895 path_com_cr[4].data = 0x90C4900E;
1896 path_com_cr[6].data = 0x201C8200;
1897 } else if (tx_path == RF_PATH_B) {
1898 path_com_cr[0].data = 0x21C04900;
1899 path_com_cr[1].data = 0x00E4E032;
1900 path_com_cr[2].data = 0x39380C89;
1901 path_com_cr[3].data = 0x4E032240;
1902 path_com_cr[4].data = 0x80C8900E;
1903 path_com_cr[6].data = 0x201C0400;
1904 } else if (tx_path == RF_PATH_AB) {
1905 path_com_cr[0].data = 0x21C86900;
1906 path_com_cr[1].data = 0x00E4E433;
1907 path_com_cr[2].data = 0x39390CC9;
1908 path_com_cr[3].data = 0x4E433240;
1909 path_com_cr[4].data = 0x90CC900E;
1910 path_com_cr[6].data = 0x201C8600;
1911 } else {
1912 ret = -EINVAL;
1913 }
1914
1915 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) {
1916 reg = rtw89_mac_reg_by_idx(rtwdev, path_com_cr[i].addr, phy_idx);
1917 rtw89_write32(rtwdev, reg, path_com_cr[i].data);
1918 }
1919
1920 return ret;
1921 }
1922
rtw8922a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1923 static void rtw8922a_bb_reset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1924 {
1925 }
1926
rtw8922a_cfg_rx_nss_limit(struct rtw89_dev * rtwdev,u8 rx_nss,enum rtw89_phy_idx phy_idx)1927 static int rtw8922a_cfg_rx_nss_limit(struct rtw89_dev *rtwdev, u8 rx_nss,
1928 enum rtw89_phy_idx phy_idx)
1929 {
1930 if (rx_nss == 1) {
1931 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx);
1932 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx);
1933 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_N_USR_MAX,
1934 HE_N_USER_MAX_8922A, phy_idx);
1935 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx);
1936 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx);
1937 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx);
1938 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0,
1939 phy_idx);
1940 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHT_N_USER_MAX,
1941 HE_N_USER_MAX_8922A, phy_idx);
1942 } else if (rx_nss == 2) {
1943 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 1, phy_idx);
1944 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 1, phy_idx);
1945 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_N_USR_MAX,
1946 HE_N_USER_MAX_8922A, phy_idx);
1947 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 1, phy_idx);
1948 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 1, phy_idx);
1949 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 1, phy_idx);
1950 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 1,
1951 phy_idx);
1952 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHT_N_USER_MAX,
1953 HE_N_USER_MAX_8922A, phy_idx);
1954 } else {
1955 return -EINVAL;
1956 }
1957
1958 return 0;
1959 }
1960
rtw8922a_tssi_reset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1961 static void rtw8922a_tssi_reset(struct rtw89_dev *rtwdev,
1962 enum rtw89_rf_path path,
1963 enum rtw89_phy_idx phy_idx)
1964 {
1965 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
1966 if (phy_idx == RTW89_PHY_0) {
1967 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0);
1968 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1);
1969 } else {
1970 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0);
1971 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1);
1972 }
1973 } else {
1974 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0);
1975 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1);
1976 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0);
1977 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1);
1978 }
1979 }
1980
rtw8922a_ctrl_rx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path rx_path,enum rtw89_phy_idx phy_idx)1981 static int rtw8922a_ctrl_rx_path_tmac(struct rtw89_dev *rtwdev,
1982 enum rtw89_rf_path rx_path,
1983 enum rtw89_phy_idx phy_idx)
1984 {
1985 u8 rx_nss = (rx_path == RF_PATH_AB) ? 2 : 1;
1986
1987 /* Set to 0 first to avoid abnormal EDCCA report */
1988 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx);
1989
1990 if (rx_path == RF_PATH_A) {
1991 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx);
1992 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 1, phy_idx);
1993 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
1994 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
1995 } else if (rx_path == RF_PATH_B) {
1996 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx);
1997 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 2, phy_idx);
1998 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
1999 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
2000 } else if (rx_path == RF_PATH_AB) {
2001 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx);
2002 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 3, phy_idx);
2003 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
2004 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
2005 } else {
2006 return -EINVAL;
2007 }
2008
2009 return 0;
2010 }
2011
2012 #define DIGITAL_PWR_COMP_REG_NUM 22
2013 static const u32 rtw8922a_digital_pwr_comp_2g_s0_val[][DIGITAL_PWR_COMP_REG_NUM] = {
2014 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
2015 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010000, 0x00000101,
2016 0x01010101, 0x02020201, 0x02010000, 0x03030202, 0x00000303,
2017 0x03020101, 0x06060504, 0x01010000, 0x06050403, 0x01000606,
2018 0x05040202, 0x07070706},
2019 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
2020 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101,
2021 0x01000000, 0x01010101, 0x01010000, 0x02020202, 0x00000404,
2022 0x03020101, 0x04040303, 0x02010000, 0x03030303, 0x00000505,
2023 0x03030201, 0x05050303},
2024 };
2025
2026 static const u32 rtw8922a_digital_pwr_comp_2g_s1_val[][DIGITAL_PWR_COMP_REG_NUM] = {
2027 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
2028 0x0D05091D, 0x14D50FA0, 0x01010000, 0x01010101, 0x00000101,
2029 0x01010100, 0x01010101, 0x01010000, 0x02020202, 0x01000202,
2030 0x02020101, 0x03030202, 0x02010000, 0x05040403, 0x01000606,
2031 0x05040302, 0x07070605},
2032 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
2033 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101,
2034 0x01010000, 0x02020201, 0x02010100, 0x03030202, 0x01000404,
2035 0x04030201, 0x05050404, 0x01010100, 0x04030303, 0x01000505,
2036 0x03030101, 0x05050404},
2037 };
2038
2039 static const u32 rtw8922a_digital_pwr_comp_val[][DIGITAL_PWR_COMP_REG_NUM] = {
2040 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
2041 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
2042 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
2043 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
2044 0x0D0C0907, 0x12121210},
2045 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
2046 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
2047 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
2048 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
2049 0x100D0B08, 0x15151512},
2050 };
2051
rtw8922a_set_digital_pwr_comp(struct rtw89_dev * rtwdev,u8 band,u8 nss,enum rtw89_rf_path path)2052 static void rtw8922a_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
2053 u8 band, u8 nss,
2054 enum rtw89_rf_path path)
2055 {
2056 static const u32 ltpc_t0[2] = {R_BE_LTPC_T0_PATH0, R_BE_LTPC_T0_PATH1};
2057 const u32 *digital_pwr_comp;
2058 u32 addr, val;
2059 u32 i;
2060
2061 if (nss == 1) {
2062 if (band == RTW89_BAND_2G)
2063 digital_pwr_comp = path == RF_PATH_A ?
2064 rtw8922a_digital_pwr_comp_2g_s0_val[0] :
2065 rtw8922a_digital_pwr_comp_2g_s1_val[0];
2066 else
2067 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0];
2068 } else {
2069 if (band == RTW89_BAND_2G)
2070 digital_pwr_comp = path == RF_PATH_A ?
2071 rtw8922a_digital_pwr_comp_2g_s0_val[1] :
2072 rtw8922a_digital_pwr_comp_2g_s1_val[1];
2073 else
2074 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1];
2075 }
2076
2077 addr = ltpc_t0[path];
2078 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) {
2079 val = digital_pwr_comp[i];
2080 rtw89_phy_write32(rtwdev, addr, val);
2081 }
2082 }
2083
rtw8922a_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2084 static void rtw8922a_digital_pwr_comp(struct rtw89_dev *rtwdev,
2085 enum rtw89_phy_idx phy_idx)
2086 {
2087 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2088 u8 band = chan->band_type;
2089 u8 path;
2090
2091 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
2092 if (phy_idx == RTW89_PHY_0)
2093 path = RF_PATH_A;
2094 else
2095 path = RF_PATH_B;
2096 rtw8922a_set_digital_pwr_comp(rtwdev, band, 1, path);
2097 } else {
2098 rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_A);
2099 rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_B);
2100 }
2101 }
2102
rtw8922a_ctrl_mlo(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode)2103 static int rtw8922a_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode)
2104 {
2105 struct rtw89_entity_conf conf;
2106
2107 if (mode == MLO_1_PLUS_1_1RF || mode == DBCC_LEGACY) {
2108 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1);
2109 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0);
2110 } else if (mode == MLO_2_PLUS_0_1RF || mode == MLO_0_PLUS_2_1RF ||
2111 mode == MLO_DBCC_NOT_SUPPORT) {
2112 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
2113 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1);
2114 } else {
2115 return -EOPNOTSUPP;
2116 }
2117
2118 rtw89_entity_get_conf(rtwdev, &conf);
2119
2120 rtw8922a_ctrl_afe_dac(rtwdev, conf.chans[0]->band_width, RF_PATH_A);
2121 rtw8922a_ctrl_afe_dac(rtwdev, conf.chans[1]->band_width, RF_PATH_B);
2122
2123 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180);
2124
2125 if (mode == MLO_2_PLUS_0_1RF) {
2126 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
2127 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9);
2128 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9);
2129 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9);
2130 } else if (mode == MLO_0_PLUS_2_1RF) {
2131 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
2132 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF);
2133 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF);
2134 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF);
2135 } else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
2136 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB);
2137 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB);
2138 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB);
2139 } else {
2140 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180);
2141 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0);
2142 }
2143
2144 return 0;
2145 }
2146
rtw8922a_bb_sethw(struct rtw89_dev * rtwdev)2147 static void rtw8922a_bb_sethw(struct rtw89_dev *rtwdev)
2148 {
2149 u32 reg;
2150
2151 rtw89_phy_write32_clr(rtwdev, R_EN_SND_WO_NDP, B_EN_SND_WO_NDP);
2152 rtw89_phy_write32_clr(rtwdev, R_EN_SND_WO_NDP_C1, B_EN_SND_WO_NDP);
2153
2154 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0);
2155 if (rtwdev->dbcc_en) {
2156 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_MAC_1);
2157 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0);
2158 }
2159
2160 rtw8922a_ctrl_mlo(rtwdev, rtwdev->mlo_dbcc_mode);
2161 }
2162
rtw8922a_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en,enum rtw89_phy_idx phy_idx)2163 static void rtw8922a_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en,
2164 enum rtw89_phy_idx phy_idx)
2165 {
2166 if (cck_en) {
2167 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx);
2168 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1, phy_idx);
2169 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
2170 0, phy_idx);
2171 } else {
2172 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 1, phy_idx);
2173 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx);
2174 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
2175 1, phy_idx);
2176 }
2177 }
2178
rtw8922a_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2179 static void rtw8922a_set_channel_bb(struct rtw89_dev *rtwdev,
2180 const struct rtw89_chan *chan,
2181 enum rtw89_phy_idx phy_idx)
2182 {
2183 bool cck_en = chan->band_type == RTW89_BAND_2G;
2184 u8 pri_sb = chan->pri_sb_idx;
2185
2186 if (cck_en)
2187 rtw8922a_ctrl_sco_cck(rtwdev, chan->primary_channel,
2188 chan->band_width, phy_idx);
2189
2190 rtw8922a_ctrl_ch(rtwdev, chan, phy_idx);
2191 rtw8922a_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
2192 rtw8922a_ctrl_cck_en(rtwdev, cck_en, phy_idx);
2193 rtw8922a_spur_elimination(rtwdev, chan, phy_idx);
2194
2195 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
2196 rtw8922a_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
2197 }
2198
rtw8922a_pre_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2199 static void rtw8922a_pre_set_channel_bb(struct rtw89_dev *rtwdev,
2200 enum rtw89_phy_idx phy_idx)
2201 {
2202 if (!rtwdev->dbcc_en)
2203 return;
2204
2205 if (phy_idx == RTW89_PHY_0) {
2206 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
2207 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180);
2208 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
2209 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9);
2210 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9);
2211 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9);
2212 } else {
2213 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
2214 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
2215 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF);
2216 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF);
2217 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF);
2218 }
2219 }
2220
rtw8922a_post_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode,enum rtw89_phy_idx phy_idx)2221 static void rtw8922a_post_set_channel_bb(struct rtw89_dev *rtwdev,
2222 enum rtw89_mlo_dbcc_mode mode,
2223 enum rtw89_phy_idx phy_idx)
2224 {
2225 if (!rtwdev->dbcc_en)
2226 return;
2227
2228 rtw8922a_digital_pwr_comp(rtwdev, phy_idx);
2229 rtw8922a_ctrl_mlo(rtwdev, mode);
2230 }
2231
rtw8922a_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)2232 static void rtw8922a_set_channel(struct rtw89_dev *rtwdev,
2233 const struct rtw89_chan *chan,
2234 enum rtw89_mac_idx mac_idx,
2235 enum rtw89_phy_idx phy_idx)
2236 {
2237 rtw8922a_set_channel_mac(rtwdev, chan, mac_idx);
2238 rtw8922a_set_channel_bb(rtwdev, chan, phy_idx);
2239 rtw8922a_set_channel_rf(rtwdev, chan, phy_idx);
2240 }
2241
rtw8922a_dfs_en_idx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_rf_path path,bool en)2242 static void rtw8922a_dfs_en_idx(struct rtw89_dev *rtwdev,
2243 enum rtw89_phy_idx phy_idx, enum rtw89_rf_path path,
2244 bool en)
2245 {
2246 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0;
2247
2248 if (en)
2249 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1,
2250 phy_idx);
2251 else
2252 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0,
2253 phy_idx);
2254 }
2255
rtw8922a_dfs_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2256 static void rtw8922a_dfs_en(struct rtw89_dev *rtwdev, bool en,
2257 enum rtw89_phy_idx phy_idx)
2258 {
2259 rtw8922a_dfs_en_idx(rtwdev, phy_idx, RF_PATH_A, en);
2260 rtw8922a_dfs_en_idx(rtwdev, phy_idx, RF_PATH_B, en);
2261 }
2262
rtw8922a_adc_en_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool en)2263 static void rtw8922a_adc_en_path(struct rtw89_dev *rtwdev,
2264 enum rtw89_rf_path path, bool en)
2265 {
2266 u32 val;
2267
2268 val = rtw89_phy_read32_mask(rtwdev, R_ADC_FIFO_V1, B_ADC_FIFO_EN_V1);
2269
2270 if (en) {
2271 if (path == RF_PATH_A)
2272 val &= ~0x1;
2273 else
2274 val &= ~0x2;
2275 } else {
2276 if (path == RF_PATH_A)
2277 val |= 0x1;
2278 else
2279 val |= 0x2;
2280 }
2281
2282 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO_V1, B_ADC_FIFO_EN_V1, val);
2283 }
2284
rtw8922a_adc_en(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)2285 static void rtw8922a_adc_en(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
2286 {
2287 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
2288 if (phy_idx == RTW89_PHY_0)
2289 rtw8922a_adc_en_path(rtwdev, RF_PATH_A, en);
2290 else
2291 rtw8922a_adc_en_path(rtwdev, RF_PATH_B, en);
2292 } else {
2293 rtw8922a_adc_en_path(rtwdev, RF_PATH_A, en);
2294 rtw8922a_adc_en_path(rtwdev, RF_PATH_B, en);
2295 }
2296 }
2297
2298 static
rtw8922a_hal_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_mac_idx mac_idx,enum rtw89_band band,u32 * tx_en,bool enter)2299 void rtw8922a_hal_reset(struct rtw89_dev *rtwdev,
2300 enum rtw89_phy_idx phy_idx, enum rtw89_mac_idx mac_idx,
2301 enum rtw89_band band, u32 *tx_en, bool enter)
2302 {
2303 if (enter) {
2304 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en, RTW89_SCH_TX_SEL_ALL);
2305 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
2306 rtw8922a_dfs_en(rtwdev, false, phy_idx);
2307 rtw8922a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
2308 rtw8922a_adc_en(rtwdev, false, phy_idx);
2309 fsleep(40);
2310 rtw8922a_bb_reset_en(rtwdev, band, false, phy_idx);
2311 } else {
2312 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
2313 rtw8922a_adc_en(rtwdev, true, phy_idx);
2314 rtw8922a_dfs_en(rtwdev, true, phy_idx);
2315 rtw8922a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
2316 rtw8922a_bb_reset_en(rtwdev, band, true, phy_idx);
2317 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, *tx_en);
2318 }
2319 }
2320
rtw8922a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)2321 static void rtw8922a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
2322 struct rtw89_channel_help_params *p,
2323 const struct rtw89_chan *chan,
2324 enum rtw89_mac_idx mac_idx,
2325 enum rtw89_phy_idx phy_idx)
2326 {
2327 if (enter) {
2328 rtw8922a_pre_set_channel_bb(rtwdev, phy_idx);
2329 rtw8922a_pre_set_channel_rf(rtwdev, phy_idx);
2330 }
2331
2332 rtw8922a_hal_reset(rtwdev, phy_idx, mac_idx, chan->band_type, &p->tx_en, enter);
2333
2334 if (!enter) {
2335 rtw8922a_post_set_channel_bb(rtwdev, rtwdev->mlo_dbcc_mode, phy_idx);
2336 rtw8922a_post_set_channel_rf(rtwdev, phy_idx);
2337 }
2338 }
2339
rtw8922a_rfk_init(struct rtw89_dev * rtwdev)2340 static void rtw8922a_rfk_init(struct rtw89_dev *rtwdev)
2341 {
2342 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
2343
2344 rtwdev->is_tssi_mode[RF_PATH_A] = false;
2345 rtwdev->is_tssi_mode[RF_PATH_B] = false;
2346 memset(rfk_mcc, 0, sizeof(*rfk_mcc));
2347 }
2348
__rtw8922a_rfk_init_late(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2349 static void __rtw8922a_rfk_init_late(struct rtw89_dev *rtwdev,
2350 enum rtw89_phy_idx phy_idx,
2351 const struct rtw89_chan *chan)
2352 {
2353 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2354
2355 rtw89_phy_rfk_dack_and_wait(rtwdev, phy_idx, chan, 58);
2356 if (!test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2357 rtw89_phy_rfk_rxdck_and_wait(rtwdev, phy_idx, chan, false, 128);
2358 }
2359
rtw8922a_rfk_init_late(struct rtw89_dev * rtwdev)2360 static void rtw8922a_rfk_init_late(struct rtw89_dev *rtwdev)
2361 {
2362 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2363
2364 __rtw8922a_rfk_init_late(rtwdev, RTW89_PHY_0, chan);
2365 if (rtwdev->dbcc_en)
2366 __rtw8922a_rfk_init_late(rtwdev, RTW89_PHY_1, chan);
2367 }
2368
_wait_rx_mode(struct rtw89_dev * rtwdev,u8 kpath)2369 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
2370 {
2371 u32 rf_mode;
2372 u8 path;
2373 int ret;
2374
2375 for (path = 0; path < RF_PATH_NUM_8922A; path++) {
2376 if (!(kpath & BIT(path)))
2377 continue;
2378
2379 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2380 2, 5000, false, rtwdev, path, 0x00,
2381 RR_MOD_MASK);
2382 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2383 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
2384 path, ret);
2385 }
2386 }
2387
rtw8922a_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2388 static void rtw8922a_rfk_channel(struct rtw89_dev *rtwdev,
2389 struct rtw89_vif_link *rtwvif_link)
2390 {
2391 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
2392 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2393 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
2394 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
2395 u32 tx_en;
2396
2397 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_START);
2398 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
2399 _wait_rx_mode(rtwdev, RF_AB);
2400
2401 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2402 rtw89_phy_rfk_txgapk_and_wait(rtwdev, phy_idx, chan, 54);
2403 rtw89_phy_rfk_iqk_and_wait(rtwdev, phy_idx, chan, 84);
2404 rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, RTW89_TSSI_NORMAL, 20);
2405 rtw89_phy_rfk_dpk_and_wait(rtwdev, phy_idx, chan, 34);
2406 rtw89_phy_rfk_rxdck_and_wait(rtwdev, RTW89_PHY_0, chan, true, 32);
2407
2408 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
2409 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_STOP);
2410 }
2411
rtw8922a_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2412 static void rtw8922a_rfk_band_changed(struct rtw89_dev *rtwdev,
2413 enum rtw89_phy_idx phy_idx,
2414 const struct rtw89_chan *chan)
2415 {
2416 rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, RTW89_TSSI_SCAN, 6);
2417 }
2418
rtw8922a_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)2419 static void rtw8922a_rfk_scan(struct rtw89_dev *rtwdev,
2420 struct rtw89_vif_link *rtwvif_link,
2421 bool start)
2422 {
2423 }
2424
rtw8922a_rfk_track(struct rtw89_dev * rtwdev)2425 static void rtw8922a_rfk_track(struct rtw89_dev *rtwdev)
2426 {
2427 }
2428
rtw8922a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2429 static void rtw8922a_set_txpwr_ref(struct rtw89_dev *rtwdev,
2430 enum rtw89_phy_idx phy_idx)
2431 {
2432 s16 ref_ofdm = 0;
2433 s16 ref_cck = 0;
2434
2435 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
2436
2437 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2438 B_BE_PWR_REF_CTRL_OFDM, ref_ofdm);
2439 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2440 B_BE_PWR_REF_CTRL_CCK, ref_cck);
2441 }
2442
2443 static const struct rtw89_reg_def rtw8922a_txpwr_ref[][3] = {
2444 {{ .addr = R_TXAGC_REF_DBM_P0, .mask = B_TXAGC_OFDM_REF_DBM_P0},
2445 { .addr = R_TXAGC_REF_DBM_P0, .mask = B_TXAGC_CCK_REF_DBM_P0},
2446 { .addr = R_TSSI_K_P0, .mask = B_TSSI_K_OFDM_P0}
2447 },
2448 {{ .addr = R_TXAGC_REF_DBM_RF1_P0, .mask = B_TXAGC_OFDM_REF_DBM_RF1_P0},
2449 { .addr = R_TXAGC_REF_DBM_RF1_P0, .mask = B_TXAGC_CCK_REF_DBM_RF1_P0},
2450 { .addr = R_TSSI_K_RF1_P0, .mask = B_TSSI_K_OFDM_RF1_P0}
2451 },
2452 };
2453
rtw8922a_set_txpwr_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2454 static void rtw8922a_set_txpwr_diff(struct rtw89_dev *rtwdev,
2455 const struct rtw89_chan *chan,
2456 enum rtw89_phy_idx phy_idx)
2457 {
2458 s16 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
2459 const struct rtw89_chip_info *chip = rtwdev->chip;
2460 static const u32 path_ofst[] = {0x0, 0x100};
2461 const struct rtw89_reg_def *txpwr_ref;
2462 static const s16 tssi_k_base = 0x12;
2463 s16 tssi_k_ofst = abs(pwr_ofst) + tssi_k_base;
2464 s16 ofst_dec[RF_PATH_NUM_8922A];
2465 s16 tssi_k[RF_PATH_NUM_8922A];
2466 s16 pwr_ref_ofst;
2467 s16 pwr_ref = 0;
2468 u8 i;
2469
2470 if (rtwdev->hal.cv == CHIP_CAV)
2471 pwr_ref = 16;
2472
2473 pwr_ref <<= chip->txpwr_factor_rf;
2474 pwr_ref_ofst = pwr_ref - rtw89_phy_txpwr_bb_to_rf(rtwdev, abs(pwr_ofst));
2475
2476 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst;
2477 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref;
2478 tssi_k[RF_PATH_A] = pwr_ofst > 0 ? tssi_k_base : tssi_k_ofst;
2479 tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : tssi_k_base;
2480
2481 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
2482 txpwr_ref = rtw8922a_txpwr_ref[phy_idx];
2483
2484 rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i],
2485 txpwr_ref[0].mask, ofst_dec[i]);
2486 rtw89_phy_write32_mask(rtwdev, txpwr_ref[1].addr + path_ofst[i],
2487 txpwr_ref[1].mask, ofst_dec[i]);
2488 rtw89_phy_write32_mask(rtwdev, txpwr_ref[2].addr + path_ofst[i],
2489 txpwr_ref[2].mask, tssi_k[i]);
2490 }
2491 }
2492
rtw8922a_bb_tx_triangular(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2493 static void rtw8922a_bb_tx_triangular(struct rtw89_dev *rtwdev, bool en,
2494 enum rtw89_phy_idx phy_idx)
2495 {
2496 u8 ctrl = en ? 0x1 : 0x0;
2497
2498 rtw89_phy_write32_idx(rtwdev, R_BEDGE3, B_BEDGE_CFG, ctrl, phy_idx);
2499 }
2500
rtw8922a_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2501 static void rtw8922a_set_tx_shape(struct rtw89_dev *rtwdev,
2502 const struct rtw89_chan *chan,
2503 enum rtw89_phy_idx phy_idx)
2504 {
2505 u8 band = chan->band_type;
2506 u8 tx_shape_idx;
2507
2508 tx_shape_idx = rtw89_get_tx_shape_idx(rtwdev, band, RTW89_RS_OFDM);
2509 if (tx_shape_idx == 0)
2510 rtw8922a_bb_tx_triangular(rtwdev, false, phy_idx);
2511 else
2512 rtw8922a_bb_tx_triangular(rtwdev, true, phy_idx);
2513 }
2514
rtw8922a_set_txpwr_sar_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2515 static void rtw8922a_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
2516 const struct rtw89_chan *chan,
2517 enum rtw89_phy_idx phy_idx)
2518 {
2519 struct rtw89_sar_parm sar_parm = {
2520 .center_freq = chan->freq,
2521 .force_path = true,
2522 };
2523 s16 sar_rf;
2524 s8 sar_mac;
2525
2526 if (phy_idx != RTW89_PHY_0)
2527 return;
2528
2529 sar_parm.path = RF_PATH_A;
2530 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2531 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2532 rtw89_phy_write32_mask(rtwdev, R_P0_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
2533
2534 sar_parm.path = RF_PATH_B;
2535 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2536 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2537 rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
2538 }
2539
rtw8922a_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2540 static void rtw8922a_set_txpwr(struct rtw89_dev *rtwdev,
2541 const struct rtw89_chan *chan,
2542 enum rtw89_phy_idx phy_idx)
2543 {
2544 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2545 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2546 rtw8922a_set_tx_shape(rtwdev, chan, phy_idx);
2547 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2548 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2549 rtw8922a_set_txpwr_diff(rtwdev, chan, phy_idx);
2550 rtw8922a_set_txpwr_ref(rtwdev, phy_idx);
2551 rtw8922a_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
2552 }
2553
rtw8922a_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2554 static void rtw8922a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2555 enum rtw89_phy_idx phy_idx)
2556 {
2557 rtw8922a_set_txpwr_ref(rtwdev, phy_idx);
2558 }
2559
rtw8922a_ctrl_trx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,u8 tx_nss,enum rtw89_rf_path rx_path,u8 rx_nss)2560 static void rtw8922a_ctrl_trx_path(struct rtw89_dev *rtwdev,
2561 enum rtw89_rf_path tx_path, u8 tx_nss,
2562 enum rtw89_rf_path rx_path, u8 rx_nss)
2563 {
2564 enum rtw89_phy_idx phy_idx;
2565
2566 for (phy_idx = RTW89_PHY_0; phy_idx <= RTW89_PHY_1; phy_idx++) {
2567 rtw8922a_ctrl_tx_path_tmac(rtwdev, tx_path, phy_idx);
2568 rtw8922a_ctrl_rx_path_tmac(rtwdev, rx_path, phy_idx);
2569 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
2570 }
2571 }
2572
rtw8922a_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2573 static void rtw8922a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
2574 enum rtw89_phy_idx phy_idx)
2575 {
2576 if (en) {
2577 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx);
2578 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2579 0xf, phy_idx);
2580 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2581 0x0, phy_idx);
2582 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx);
2583 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx);
2584 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx);
2585 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx);
2586 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx);
2587 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx);
2588 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2589 0xf, phy_idx);
2590 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2591 0x0, phy_idx);
2592 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx);
2593 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx);
2594 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx);
2595 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx);
2596 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx);
2597 } else {
2598 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx);
2599 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2600 0x0, phy_idx);
2601 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2602 0x1, phy_idx);
2603 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx);
2604 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx);
2605 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx);
2606 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx);
2607 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx);
2608 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx);
2609 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2610 0x0, phy_idx);
2611 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2612 0x1, phy_idx);
2613 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx);
2614 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx);
2615 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx);
2616 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx);
2617 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx);
2618 }
2619 }
2620
rtw8922a_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)2621 static void rtw8922a_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2622 {
2623 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2624 enum rtw89_band band = chan->band_type;
2625 struct rtw89_hal *hal = &rtwdev->hal;
2626 u8 ntx_path = RF_PATH_AB;
2627 u8 nrx_path = RF_PATH_AB;
2628 u32 tx_en0, tx_en1;
2629 u8 rx_nss = 2;
2630
2631 if (hal->antenna_tx == RF_A)
2632 ntx_path = RF_PATH_A;
2633 else if (hal->antenna_tx == RF_B)
2634 ntx_path = RF_PATH_B;
2635
2636 if (hal->antenna_rx == RF_A)
2637 nrx_path = RF_PATH_A;
2638 else if (hal->antenna_rx == RF_B)
2639 nrx_path = RF_PATH_B;
2640
2641 if (nrx_path != RF_PATH_AB)
2642 rx_nss = 1;
2643
2644 rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, true);
2645 if (rtwdev->dbcc_en)
2646 rtw8922a_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2647 &tx_en1, true);
2648
2649 rtw8922a_ctrl_trx_path(rtwdev, ntx_path, 2, nrx_path, rx_nss);
2650
2651 rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, false);
2652 if (rtwdev->dbcc_en)
2653 rtw8922a_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2654 &tx_en1, false);
2655 }
2656
rtw8922a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)2657 static u8 rtw8922a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2658 {
2659 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
2660 struct rtw89_hal *hal = &rtwdev->hal;
2661 int th;
2662
2663 /* read thermal only if debugging or thermal protection enabled */
2664 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_CFO | RTW89_DBG_RFK_TRACK) &&
2665 !hal->thermal_prot_th)
2666 return 80;
2667
2668 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2669 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2670 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2671
2672 fsleep(200);
2673
2674 th = rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL_V1);
2675 th += (s8)info->thermal_trim[rf_path];
2676
2677 return clamp_t(int, th, 0, U8_MAX);
2678 }
2679
rtw8922a_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2680 static u32 rtw8922a_chan_to_rf18_val(struct rtw89_dev *rtwdev,
2681 const struct rtw89_chan *chan)
2682 {
2683 u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
2684
2685 switch (chan->band_type) {
2686 case RTW89_BAND_2G:
2687 default:
2688 break;
2689 case RTW89_BAND_5G:
2690 val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
2691 u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
2692 break;
2693 case RTW89_BAND_6G:
2694 val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
2695 u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
2696 break;
2697 }
2698
2699 switch (chan->band_width) {
2700 case RTW89_CHANNEL_WIDTH_5:
2701 case RTW89_CHANNEL_WIDTH_10:
2702 case RTW89_CHANNEL_WIDTH_20:
2703 default:
2704 break;
2705 case RTW89_CHANNEL_WIDTH_40:
2706 val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
2707 break;
2708 case RTW89_CHANNEL_WIDTH_80:
2709 val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
2710 break;
2711 case RTW89_CHANNEL_WIDTH_160:
2712 val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
2713 break;
2714 case RTW89_CHANNEL_WIDTH_320:
2715 val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
2716 break;
2717 }
2718
2719 return val;
2720 }
2721
rtw8922a_btc_set_rfe(struct rtw89_dev * rtwdev)2722 static void rtw8922a_btc_set_rfe(struct rtw89_dev *rtwdev)
2723 {
2724 struct rtw89_btc *btc = &rtwdev->btc;
2725 struct rtw89_btc_module *md = &btc->mdinfo;
2726 u8 i, j;
2727 u8 tx_path_pos, rx_path_pos;
2728
2729 md->rfe_type = rtwdev->efuse.rfe_type;
2730 md->kt_ver = rtwdev->hal.cv;
2731 md->kt_ver_adie = rtwdev->hal.acv;
2732 md->wa_type = 0;
2733
2734 md->ant.num = 2;
2735 md->ant.single_pos = BTC_RF_S0;
2736
2737 if (md->kt_ver <= 1)
2738 md->wa_type |= BTC_WA_HFP_ZB;
2739
2740 btc->cx.bt0.ant_iso_to_wl = md->ant.isolation;
2741 btc->cx.bt1.ant_iso_to_wl = md->ant.isolation;
2742
2743 md->ant.stream_cnt = 2;
2744 md->ant.btg_pos = RF_PATH_B;
2745 md->ant.single_pos = RF_PATH_A;
2746
2747 btc->cx.bt0.band_56G_support = 0;
2748 btc->cx.bt1.band_56G_support = 0;
2749 btc->cx.bt0.func_type = BTC_BTF_BT;
2750 btc->cx.bt1.func_type = BTC_BTF_NONE;
2751
2752 if (md->rfe_type == 0) {
2753 rtwdev->btc.dm.error.map.rfe_type0 = true;
2754 return;
2755 }
2756
2757 md->ant.num = (md->rfe_type % 2) ? 2 : 3;
2758 if (md->kt_ver == 0)
2759 md->ant.num = 2;
2760
2761 memset(btc->dm.ant_xmap, 0, sizeof(btc->dm.ant_xmap));
2762
2763 switch (md->ant.num) {
2764 case 1:
2765 md->ant.type = BTC_ANT_SHARED;
2766 md->bt0_pos = BTC_BT_BTG;
2767 md->bt0_sw_type = BTC_SWITCH_V1_INTERNAL;
2768 md->ant.btg_pos = BTC_RF_S0;
2769 btc->dm.ant_xmap[BTC_RF_S0][BTC_BT_1ST] = 1;
2770 md->ant.func[0] = BTC_EFMAP_BT0;
2771 break;
2772 case 2: /* 2-Ant */
2773 default:
2774 md->ant.type = BTC_ANT_SHARED;
2775 md->bt0_pos = BTC_BT_BTG;
2776 md->bt0_sw_type = BTC_SWITCH_V1_INTERNAL;
2777 btc->dm.wl_trx_nss_en = 1;
2778 btc->dm.ant_xmap[BTC_RF_S1][BTC_BT_1ST] = 1;
2779 md->ant.func[1] = BTC_EFMAP_BT0;
2780 break;
2781 case 3: /* 3-Ant, 3 different BT-configuration */
2782 /* WL-S0 + WL-S1 + BT0-S0 */
2783 md->ant.type = BTC_ANT_DEDICATED;
2784 md->bt0_pos = BTC_BT_ALONE;
2785 md->bt0_sw_type = BTC_SWITCH_V1_NONE;
2786 md->ant.func[2] = BTC_EFMAP_BT0;
2787 }
2788
2789 tx_path_pos = _btc_get_rf_path_from_ant_num(btc, rtwdev->hal.tx_nss);
2790 rx_path_pos = _btc_get_rf_path_from_ant_num(btc, rtwdev->hal.rx_nss);
2791 /* Combine TX[7:4] and RX[3:0] into path_pos byte */
2792 md->ant.path_pos = ((tx_path_pos << BTC_ANT_SHIFT) & BTC_ANT_TX_MASK) |
2793 (rx_path_pos & BTC_ANT_RX_MASK);
2794
2795 switch (btc->cx.bt_ext.chip_id) {
2796 default:
2797 case BTC_ESOC_NONE:
2798 memset(&btc->cx.bt_ext, 0, sizeof(struct rtw89_btc_extsoc_info));
2799 btc->cx.bt_ext.max_tx_pwr = RTW89_BTC_BT_DEF_LE_TX_PWR_1;
2800 btc->cx.bt_ext.ant_iso_to_wl = RTW89_BTC_DEFAULT_ANISO;
2801 break;
2802 case BTC_ESOC_8771:
2803 btc->cx.bt_ext.func_type = BTC_BTF_THREAD;
2804 btc->cx.bt_ext.hw_coex = BTC_EXTSOC_INTF_PTA;
2805 btc->cx.bt_ext.rf_band_map = 0x1; /* 2.4G only */
2806 btc->cx.bt_ext.link_weight[BTC_BT_B2G] = 10;
2807 btc->cx.bt_ext.profile_map[BTC_BT_B2G] |= BTC_BT_THREAD;
2808 /* use GPIO 12~15 for Ext-4-wire-PTA */
2809 btc->cx.bt_ext.hpta_cfg = BIT(12) | BIT(13) | BIT(14) | BIT(15);
2810 md->ant.func[2] = BTC_EFMAP_ZB;
2811 break;
2812 }
2813
2814 btc->dm.ant_xmap[BTC_RF_S0][BTC_BT_EXT] = 0;
2815 btc->dm.ant_xmap[BTC_RF_S1][BTC_BT_EXT] = 0;
2816
2817 for (i = BTC_RF_S0; i <= BTC_RF_S1; i++)
2818 for (j = BTC_BT_1ST; j <= BTC_BT_EXT; j++)
2819 md->ant.ant_xmap[i][j] = btc->dm.ant_xmap[i][j];
2820
2821 rtwdev->btc.btg_pos = md->ant.btg_pos;
2822 rtwdev->btc.ant_type = md->ant.type;
2823 }
2824
2825 static
rtw8922a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)2826 void rtw8922a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2827 {
2828 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2829 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2830 }
2831
rtw8922a_btc_init_cfg(struct rtw89_dev * rtwdev)2832 static void rtw8922a_btc_init_cfg(struct rtw89_dev *rtwdev)
2833 {
2834 struct rtw89_btc *btc = &rtwdev->btc;
2835 struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2836 u32 wl_pri, path_min, path_max;
2837 u8 path;
2838
2839 /* for 1-Ant && 1-ss case: only 1-path */
2840 if (ant->num == 1) {
2841 path_min = ant->single_pos;
2842 path_max = path_min;
2843 } else {
2844 path_min = RF_PATH_A;
2845 path_max = RF_PATH_B;
2846 }
2847
2848 path = path_min;
2849
2850 for (path = path_min; path <= path_max; path++) {
2851 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2852 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2853
2854 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2855 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2856
2857 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2858 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2859
2860 /* if GNT_WL = 0 && BT = Tx_group -->
2861 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2862 */
2863 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path)
2864 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2865 else
2866 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2867
2868 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2869 }
2870
2871 /* set WL PTA Hi-Pri: Ack-Tx, beacon-tx, Trig-frame-Tx, Null-Tx*/
2872 wl_pri = B_BTC_RSP_ACK_HI | B_BTC_TX_BCN_HI | B_BTC_TX_TRI_HI |
2873 B_BTC_TX_NULL_HI;
2874 rtw89_write32(rtwdev, R_BTC_COEX_WL_REQ_BE, wl_pri);
2875
2876 /* set PTA break table */
2877 rtw89_write32(rtwdev, R_BE_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2878
2879 /* ZB coex table init for HFP PTA req-cmd bit-4 define issue COEX-900*/
2880 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a);
2881
2882 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a);
2883
2884 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff);
2885 }
2886
2887 static void
rtw8922a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2888 rtw8922a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2889 {
2890 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
2891 u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
2892
2893 switch (ctrl_all_time) {
2894 case 0xffff:
2895 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2896 B_BE_FORCE_PWR_BY_RATE_EN, 0x0);
2897 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2898 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0);
2899 break;
2900 default:
2901 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2902 B_BE_FORCE_PWR_BY_RATE_VAL, ctrl_all_time);
2903 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2904 B_BE_FORCE_PWR_BY_RATE_EN, 0x1);
2905 break;
2906 }
2907
2908 switch (ctrl_gnt_bt) {
2909 case 0xffff:
2910 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2911 B_BE_PWR_BT_EN, 0x0);
2912 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2913 B_BE_PWR_BT_VAL, 0x0);
2914 break;
2915 default:
2916 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2917 B_BE_PWR_BT_VAL, ctrl_gnt_bt);
2918 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2919 B_BE_PWR_BT_EN, 0x1);
2920 break;
2921 }
2922 }
2923
2924 static
rtw8922a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2925 s8 rtw8922a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2926 {
2927 return clamp_t(s8, val, -100, 0) + 100;
2928 }
2929
2930 static const struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8922a_rf_ul_v0[] = {
2931 {255, 0, 0, 7}, /* 0 -> original */
2932 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2933 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2934 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2935 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2936 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2937 {6, 1, 0, 7},
2938 {13, 1, 0, 7},
2939 {13, 1, 0, 7}
2940 };
2941
2942 static const struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8922a_rf_dl_v0[] = {
2943 {255, 0, 0, 7}, /* 0 -> original */
2944 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2945 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2946 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2947 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2948 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2949 {255, 1, 0, 7},
2950 {255, 1, 0, 7},
2951 {255, 1, 0, 7}
2952 };
2953
2954 static const u8 rtw89_btc_8922a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2955 static const u8 rtw89_btc_8922a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
2956
2957 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8922a_mon_reg[] = {
2958 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2959 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2960 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2961 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2962 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2963 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2964 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2965 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2966 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2967 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2968 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2969 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2970 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2971 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2972 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2973 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2974 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2975 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2976 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2977 };
2978
2979 static
rtw8922a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2980 void rtw8922a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2981 {
2982 /* Feature move to firmware */
2983 }
2984
2985 static
rtw8922a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2986 void rtw8922a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2987 {
2988 if (!state) {
2989 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2990 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2991 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110);
2992 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018);
2993 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000);
2994
2995 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
2996 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1);
2997 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110);
2998 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018);
2999 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
3000 } else {
3001 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
3002 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
3003 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110);
3004 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018);
3005 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000);
3006
3007 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
3008 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1);
3009 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110);
3010 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018);
3011 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
3012 }
3013 }
3014
rtw8922a_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)3015 static void rtw8922a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
3016 {
3017 }
3018
rtw8922a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)3019 static void rtw8922a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
3020 struct rtw89_rx_phy_ppdu *phy_ppdu,
3021 struct ieee80211_rx_status *status)
3022 {
3023 u8 chan_idx = phy_ppdu->chan_idx;
3024 enum nl80211_band band;
3025 u8 ch;
3026
3027 if (chan_idx == 0)
3028 return;
3029
3030 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
3031 status->freq = ieee80211_channel_to_frequency(ch, band);
3032 status->band = band;
3033 }
3034
rtw8922a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)3035 static void rtw8922a_query_ppdu(struct rtw89_dev *rtwdev,
3036 struct rtw89_rx_phy_ppdu *phy_ppdu,
3037 struct ieee80211_rx_status *status)
3038 {
3039 u8 path;
3040 u8 *rx_power = phy_ppdu->rssi;
3041
3042 if (!status->signal)
3043 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
3044 rx_power[RF_PATH_B]));
3045
3046 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
3047 status->chains |= BIT(path);
3048 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
3049 }
3050 if (phy_ppdu->valid)
3051 rtw8922a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
3052 }
3053
rtw8922a_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)3054 static void rtw8922a_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
3055 struct rtw89_rx_phy_ppdu *phy_ppdu)
3056 {
3057 /* Mapping to BW: 5, 10, 20, 40, 80, 160, 80_80 */
3058 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0};
3059 u8 *rssi = phy_ppdu->rssi;
3060 u8 compensate = 0;
3061 u16 rpl_tmp;
3062 u8 i;
3063
3064 if (phy_ppdu->bw_idx < ARRAY_SIZE(bw_compensate))
3065 compensate = bw_compensate[phy_ppdu->bw_idx];
3066
3067 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
3068 if (!(phy_ppdu->rx_path_en & BIT(i))) {
3069 rssi[i] = 0;
3070 phy_ppdu->rpl_path[i] = 0;
3071 phy_ppdu->rpl_fd[i] = 0;
3072 }
3073 if (phy_ppdu->rate >= RTW89_HW_RATE_OFDM6) {
3074 rpl_tmp = phy_ppdu->rpl_fd[i];
3075 if (rpl_tmp)
3076 rpl_tmp += compensate;
3077
3078 phy_ppdu->rpl_path[i] = rpl_tmp;
3079 }
3080 rssi[i] = phy_ppdu->rpl_path[i];
3081 }
3082
3083 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg;
3084 }
3085
rtw8922a_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3086 static void rtw8922a_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
3087 struct rtw89_rx_desc_info *desc_info,
3088 struct ieee80211_rx_status *rx_status)
3089 {
3090 if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI)
3091 return;
3092
3093 rx_status->signal = (desc_info->rssi >> 2) - MAX_RSSI;
3094 }
3095
rtw8922a_mac_enable_bb_rf(struct rtw89_dev * rtwdev)3096 static int rtw8922a_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3097 {
3098 rtw89_write8_set(rtwdev, R_BE_FEN_RST_ENABLE,
3099 B_BE_FEN_BBPLAT_RSTB | B_BE_FEN_BB_IP_RSTN);
3100 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9);
3101
3102 return 0;
3103 }
3104
rtw8922a_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3105 static int rtw8922a_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3106 {
3107 rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE,
3108 B_BE_FEN_BBPLAT_RSTB | B_BE_FEN_BB_IP_RSTN);
3109
3110 return 0;
3111 }
3112
3113 static const struct rtw89_chanctx_listener rtw8922a_chanctx_listener = {
3114 .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb,
3115 };
3116
3117 #ifdef CONFIG_PM
3118 static const struct wiphy_wowlan_support rtw_wowlan_stub_8922a = {
3119 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
3120 WIPHY_WOWLAN_NET_DETECT,
3121 .n_patterns = RTW89_MAX_PATTERN_NUM,
3122 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
3123 .pattern_min_len = 1,
3124 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
3125 };
3126 #endif
3127
3128 static const struct rtw89_chip_ops rtw8922a_chip_ops = {
3129 .enable_bb_rf = rtw8922a_mac_enable_bb_rf,
3130 .disable_bb_rf = rtw8922a_mac_disable_bb_rf,
3131 .bb_preinit = rtw8922a_bb_preinit,
3132 .bb_postinit = rtw8922a_bb_postinit,
3133 .bb_reset = rtw8922a_bb_reset,
3134 .bb_sethw = rtw8922a_bb_sethw,
3135 .read_rf = rtw89_phy_read_rf_v2,
3136 .write_rf = rtw89_phy_write_rf_v2,
3137 .set_channel = rtw8922a_set_channel,
3138 .set_channel_help = rtw8922a_set_channel_help,
3139 .read_efuse = rtw8922a_read_efuse,
3140 .read_phycap = rtw8922a_read_phycap,
3141 .fem_setup = NULL,
3142 .data_setup = NULL,
3143 .rfe_gpio = NULL,
3144 .rfk_hw_init = rtw8922a_rfk_hw_init,
3145 .rfk_init = rtw8922a_rfk_init,
3146 .rfk_init_late = rtw8922a_rfk_init_late,
3147 .rfk_channel = rtw8922a_rfk_channel,
3148 .rfk_band_changed = rtw8922a_rfk_band_changed,
3149 .rfk_scan = rtw8922a_rfk_scan,
3150 .rfk_track = rtw8922a_rfk_track,
3151 .power_trim = rtw8922a_power_trim,
3152 .set_txpwr = rtw8922a_set_txpwr,
3153 .set_txpwr_ctrl = rtw8922a_set_txpwr_ctrl,
3154 .init_txpwr_unit = NULL,
3155 .get_thermal = rtw8922a_get_thermal,
3156 .chan_to_rf18_val = rtw8922a_chan_to_rf18_val,
3157 .ctrl_btg_bt_rx = rtw8922a_ctrl_btg_bt_rx,
3158 .query_ppdu = rtw8922a_query_ppdu,
3159 .convert_rpl_to_rssi = rtw8922a_convert_rpl_to_rssi,
3160 .phy_rpt_to_rssi = rtw8922a_phy_rpt_to_rssi,
3161 .ctrl_nbtg_bt_tx = rtw8922a_ctrl_nbtg_bt_tx,
3162 .cfg_txrx_path = rtw8922a_bb_cfg_txrx_path,
3163 .set_txpwr_ul_tb_offset = NULL,
3164 .digital_pwr_comp = rtw8922a_digital_pwr_comp,
3165 .calc_rx_gain_normal = NULL,
3166 .path_diff_update = NULL,
3167 .pwr_on_func = rtw8922a_pwr_on_func,
3168 .pwr_off_func = rtw8922a_pwr_off_func,
3169 .query_rxdesc = rtw89_core_query_rxdesc_v2,
3170 .fill_txdesc = rtw89_core_fill_txdesc_v2,
3171 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2,
3172 .get_ch_dma = {rtw89_core_get_ch_dma,
3173 rtw89_core_get_ch_dma_v2,
3174 NULL,},
3175 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2,
3176 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v2,
3177 .stop_sch_tx = rtw89_mac_stop_sch_tx_v2,
3178 .resume_sch_tx = rtw89_mac_resume_sch_tx_v2,
3179 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v2,
3180 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl_g7,
3181 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl_g7,
3182 .h2c_ampdu_cmac_tbl = rtw89_fw_h2c_ampdu_cmac_tbl_g7,
3183 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl_g7,
3184 .h2c_punctured_cmac_tbl = rtw89_fw_h2c_punctured_cmac_tbl_g7,
3185 .h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v2,
3186 .h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
3187 .h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
3188 .h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
3189
3190 .btc_set_rfe = rtw8922a_btc_set_rfe,
3191 .btc_init_cfg = rtw8922a_btc_init_cfg,
3192 .btc_set_wl_pri = NULL,
3193 .btc_set_wl_txpwr_ctrl = rtw8922a_btc_set_wl_txpwr_ctrl,
3194 .btc_get_bt_rssi = rtw8922a_btc_get_bt_rssi,
3195 .btc_update_bt_cnt = rtw8922a_btc_update_bt_cnt,
3196 .btc_wl_s1_standby = rtw8922a_btc_wl_s1_standby,
3197 .btc_set_wl_rx_gain = rtw8922a_btc_set_wl_rx_gain,
3198 .btc_set_policy = rtw89_btc_set_policy_v1,
3199 };
3200
3201 const struct rtw89_chip_info rtw8922a_chip_info = {
3202 .chip_id = RTL8922A,
3203 .chip_gen = RTW89_CHIP_BE,
3204 .ops = &rtw8922a_chip_ops,
3205 .mac_def = &rtw89_mac_gen_be,
3206 .phy_def = &rtw89_phy_gen_be,
3207 .fw_def = {
3208 .fw_basename = RTW8922A_FW_BASENAME,
3209 .fw_format_max = RTW8922A_FW_FORMAT_MAX,
3210 .fw_b_aid = 0,
3211 },
3212 .try_ce_fw = false,
3213 .bbmcu_nr = 1,
3214 .needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS,
3215 .fw_blacklist = &rtw89_fw_blacklist_default,
3216 .fifo_size = 589824,
3217 .small_fifo_size = false,
3218 .dle_scc_rsvd_size = 0,
3219 .max_amsdu_limit = 8000,
3220 .max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
3221 .max_eht_mpdu_cap = IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
3222 .max_tx_agg_num = 128,
3223 .max_rx_agg_num = 64,
3224 .dis_2g_40m_ul_ofdma = false,
3225 .rsvd_ple_ofst = 0x8f800,
3226 .qta_def = {
3227 .hfc_param_ini = {rtw8922a_hfc_param_ini_pcie,
3228 rtw8922a_hfc_param_ini_usb2,
3229 rtw8922a_hfc_param_ini_usb3,
3230 NULL},
3231 .dle_mem = {rtw8922a_dle_mem_pcie,
3232 rtw8922a_dle_mem_usb2,
3233 rtw8922a_dle_mem_usb3,
3234 NULL},
3235 },
3236 .wde_qempty_acq_grpnum = 4,
3237 .wde_qempty_mgq_grpsel = 4,
3238 .rf_base_addr = {0xe000, 0xf000},
3239 .thermal_th = {0xad, 0xb4},
3240 .pwr_on_seq = NULL,
3241 .pwr_off_seq = NULL,
3242 .bb_table = NULL,
3243 .bb_gain_table = NULL,
3244 .rf_table = {},
3245 .nctl_table = NULL,
3246 .nctl_post_table = NULL,
3247 .dflt_parms = NULL, /* load parm from fw */
3248 .rfe_parms_conf = NULL, /* load parm from fw */
3249 .chanctx_listener = &rtw8922a_chanctx_listener,
3250 .txpwr_factor_bb = 3,
3251 .txpwr_factor_rf = 2,
3252 .txpwr_factor_mac = 1,
3253 .dig_table = NULL,
3254 .dig_regs = &rtw8922a_dig_regs,
3255 .tssi_dbw_table = NULL,
3256 .support_macid_num = 32,
3257 .support_link_num = 2,
3258 .support_chanctx_num = 2,
3259 .support_rnr = true,
3260 .support_bands = BIT(NL80211_BAND_2GHZ) |
3261 BIT(NL80211_BAND_5GHZ) |
3262 BIT(NL80211_BAND_6GHZ),
3263 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
3264 BIT(NL80211_CHAN_WIDTH_40) |
3265 BIT(NL80211_CHAN_WIDTH_80) |
3266 BIT(NL80211_CHAN_WIDTH_160),
3267 .support_unii4 = true,
3268 .support_ant_gain = true,
3269 .support_tas = true,
3270 .support_sar_by_ant = true,
3271 .support_noise = false,
3272 .support_fw_cmd_ofld = false,
3273 .ul_tb_waveform_ctrl = false,
3274 .ul_tb_pwr_diff = false,
3275 .rx_freq_from_ie = false,
3276 .hw_sec_hdr = true,
3277 .hw_mgmt_tx_encrypt = true,
3278 .hw_tkip_crypto = true,
3279 .hw_mlo_bmc_crypto = false,
3280 .rf_path_num = 2,
3281 .tx_nss = 2,
3282 .rx_nss = 2,
3283 .acam_num = 128,
3284 .bcam_num = 20,
3285 .scam_num = 32,
3286 .bacam_num = 24,
3287 .bacam_dynamic_num = 8,
3288 .bacam_ver = RTW89_BACAM_V1,
3289 .addrcam_ver = 0,
3290 .ppdu_max_usr = 16,
3291 .sec_ctrl_efuse_size = 4,
3292 .physical_efuse_size = 0x1300,
3293 .logical_efuse_size = 0x70000,
3294 .limit_efuse_size = 0x40000,
3295 .dav_phy_efuse_size = 0,
3296 .dav_log_efuse_size = 0,
3297 .efuse_blocks = rtw8922a_efuse_blocks,
3298 .phycap_addr = 0x1700,
3299 .phycap_size = 0x38,
3300 .para_ver = 0xf,
3301 .wlcx_desired = 0x07110000,
3302 .scbd = 0x1,
3303 .mailbox = 0x1,
3304
3305 .afh_guard_ch = 6,
3306 .fdd_iso_freq = 1000,
3307 .wl_rssi_thres = rtw89_btc_8922a_wl_rssi_thres,
3308 .bt_rssi_thres = rtw89_btc_8922a_bt_rssi_thres,
3309 .rssi_tol = 2,
3310 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8922a_mon_reg),
3311 .mon_reg = rtw89_btc_8922a_mon_reg,
3312 .rf_para_ulink_v0 = rtw89_btc_8922a_rf_ul_v0,
3313 .rf_para_dlink_v0 = rtw89_btc_8922a_rf_dl_v0,
3314 .rf_para_ulink_num_v0 = ARRAY_SIZE(rtw89_btc_8922a_rf_ul_v0),
3315 .rf_para_dlink_num_v0 = ARRAY_SIZE(rtw89_btc_8922a_rf_dl_v0),
3316 .rf_para_ulink_v9 = NULL,
3317 .rf_para_dlink_v9 = NULL,
3318 .rf_para_ulink_num_v9 = 0,
3319 .rf_para_dlink_num_v9 = 0,
3320 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3321 BIT(RTW89_PS_MODE_CLK_GATED) |
3322 BIT(RTW89_PS_MODE_PWR_GATED),
3323 .low_power_hci_modes = 0,
3324 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_G7,
3325 .hci_func_en_addr = R_BE_HCI_FUNC_EN,
3326 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short_v2),
3327 .txwd_body_size = sizeof(struct rtw89_txwd_body_v2),
3328 .txwd_info_size = sizeof(struct rtw89_txwd_info_v2),
3329 .h2c_ctrl_reg = R_BE_H2CREG_CTRL,
3330 .h2c_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3331 .h2c_regs = rtw8922a_h2c_regs,
3332 .c2h_ctrl_reg = R_BE_C2HREG_CTRL,
3333 .c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3334 .c2h_regs = rtw8922a_c2h_regs,
3335 .page_regs = &rtw8922a_page_regs,
3336 .wow_reason_reg = rtw8922a_wow_wakeup_regs,
3337 .cfo_src_fd = true,
3338 .cfo_hw_comp = true,
3339 .dcfo_comp = NULL,
3340 .dcfo_comp_sft = 0,
3341 .nhm_report = NULL,
3342 .nhm_th = NULL,
3343 .imr_info = NULL,
3344 .imr_dmac_table = &rtw8922a_imr_dmac_table,
3345 .imr_cmac_table = &rtw8922a_imr_cmac_table,
3346 .rrsr_cfgs = &rtw8922a_rrsr_cfgs,
3347 .bss_clr_vld = {R_BSS_CLR_VLD_V2, B_BSS_CLR_VLD0_V2},
3348 .bss_clr_map_reg = R_BSS_CLR_MAP_V2,
3349 .rfkill_init = &rtw8922a_rfkill_regs,
3350 .rfkill_get = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
3351 .btc_sb = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
3352 .dma_ch_mask = 0,
3353 .edcca_regs = &rtw8922a_edcca_regs,
3354 .pmac_regs = &rtw8922a_pmac_regs,
3355 #ifdef CONFIG_PM
3356 .wowlan_stub = &rtw_wowlan_stub_8922a,
3357 #endif
3358 .xtal_info = NULL,
3359 .default_quirks = 0,
3360 .txtime_limit_2ghz = 0,
3361 };
3362 EXPORT_SYMBOL(rtw8922a_chip_info);
3363
3364 const struct rtw89_chip_variant rtw8922ae_vs_variant = {
3365 .no_mcs_12_13 = true,
3366 .fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),
3367 .fw_def_override = NULL,
3368 .qta_def_override = NULL,
3369 };
3370 EXPORT_SYMBOL(rtw8922ae_vs_variant);
3371
3372 MODULE_FIRMWARE(RTW8922A_MODULE_FIRMWARE);
3373 MODULE_AUTHOR("Realtek Corporation");
3374 MODULE_DESCRIPTION("Realtek 802.11be wireless 8922A driver");
3375 MODULE_LICENSE("Dual BSD/GPL");
3376