1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2025 Raspberry Pi Ltd.
4 *
5 * All rights reserved.
6 */
7
8 #include <linux/err.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/module.h>
14 #include <linux/msi.h>
15 #include <linux/of_platform.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18
19 #define RP1_HW_IRQ_MASK GENMASK(5, 0)
20
21 #define REG_SET 0x800
22 #define REG_CLR 0xc00
23
24 /* MSI-X CFG registers start at 0x8 */
25 #define MSIX_CFG(x) (0x8 + (4 * (x)))
26
27 #define MSIX_CFG_IACK_EN BIT(3)
28 #define MSIX_CFG_IACK BIT(2)
29 #define MSIX_CFG_ENABLE BIT(0)
30
31 /* Address map */
32 #define RP1_PCIE_APBS_BASE 0x108000
33
34 /* Interrupts */
35 #define RP1_INT_END 61
36
37 struct rp1_dev {
38 struct pci_dev *pdev;
39 struct irq_domain *domain;
40 struct irq_data *pcie_irqds[64];
41 void __iomem *bar1;
42 bool level_triggered_irq[RP1_INT_END];
43 };
44
msix_cfg_set(struct rp1_dev * rp1,unsigned int hwirq,u32 value)45 static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
46 {
47 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq));
48 }
49
msix_cfg_clr(struct rp1_dev * rp1,unsigned int hwirq,u32 value)50 static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value)
51 {
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq));
53 }
54
rp1_mask_irq(struct irq_data * irqd)55 static void rp1_mask_irq(struct irq_data *irqd)
56 {
57 struct rp1_dev *rp1 = irqd->domain->host_data;
58 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
59
60 pci_msi_mask_irq(pcie_irqd);
61 }
62
rp1_unmask_irq(struct irq_data * irqd)63 static void rp1_unmask_irq(struct irq_data *irqd)
64 {
65 struct rp1_dev *rp1 = irqd->domain->host_data;
66 struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq];
67
68 pci_msi_unmask_irq(pcie_irqd);
69 }
70
rp1_irq_set_type(struct irq_data * irqd,unsigned int type)71 static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type)
72 {
73 struct rp1_dev *rp1 = irqd->domain->host_data;
74 unsigned int hwirq = (unsigned int)irqd->hwirq;
75
76 switch (type) {
77 case IRQ_TYPE_LEVEL_HIGH:
78 dev_dbg(&rp1->pdev->dev, "MSIX IACK EN for IRQ %u\n", hwirq);
79 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN);
80 rp1->level_triggered_irq[hwirq] = true;
81 break;
82 case IRQ_TYPE_EDGE_RISING:
83 msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN);
84 rp1->level_triggered_irq[hwirq] = false;
85 break;
86 default:
87 return -EINVAL;
88 }
89
90 return 0;
91 }
92
93 static struct irq_chip rp1_irq_chip = {
94 .name = "rp1_irq_chip",
95 .irq_mask = rp1_mask_irq,
96 .irq_unmask = rp1_unmask_irq,
97 .irq_set_type = rp1_irq_set_type,
98 };
99
rp1_chained_handle_irq(struct irq_desc * desc)100 static void rp1_chained_handle_irq(struct irq_desc *desc)
101 {
102 unsigned int hwirq = desc->irq_data.hwirq & RP1_HW_IRQ_MASK;
103 struct rp1_dev *rp1 = irq_desc_get_handler_data(desc);
104 struct irq_chip *chip = irq_desc_get_chip(desc);
105 unsigned int virq;
106
107 chained_irq_enter(chip, desc);
108
109 virq = irq_find_mapping(rp1->domain, hwirq);
110 generic_handle_irq(virq);
111 if (rp1->level_triggered_irq[hwirq])
112 msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK);
113
114 chained_irq_exit(chip, desc);
115 }
116
rp1_irq_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)117 static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node,
118 const u32 *intspec, unsigned int intsize,
119 unsigned long *out_hwirq, unsigned int *out_type)
120 {
121 struct rp1_dev *rp1 = d->host_data;
122 struct irq_data *pcie_irqd;
123 unsigned long hwirq;
124 int pcie_irq;
125 int ret;
126
127 ret = irq_domain_xlate_twocell(d, node, intspec, intsize,
128 &hwirq, out_type);
129 if (ret)
130 return ret;
131
132 pcie_irq = pci_irq_vector(rp1->pdev, hwirq);
133 pcie_irqd = irq_get_irq_data(pcie_irq);
134 rp1->pcie_irqds[hwirq] = pcie_irqd;
135 *out_hwirq = hwirq;
136
137 return 0;
138 }
139
rp1_irq_activate(struct irq_domain * d,struct irq_data * irqd,bool reserve)140 static int rp1_irq_activate(struct irq_domain *d, struct irq_data *irqd,
141 bool reserve)
142 {
143 struct rp1_dev *rp1 = d->host_data;
144
145 msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
146 msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_IACK);
147
148 return 0;
149 }
150
rp1_irq_deactivate(struct irq_domain * d,struct irq_data * irqd)151 static void rp1_irq_deactivate(struct irq_domain *d, struct irq_data *irqd)
152 {
153 struct rp1_dev *rp1 = d->host_data;
154
155 msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE);
156 }
157
158 static const struct irq_domain_ops rp1_domain_ops = {
159 .xlate = rp1_irq_xlate,
160 .activate = rp1_irq_activate,
161 .deactivate = rp1_irq_deactivate,
162 };
163
rp1_unregister_interrupts(struct pci_dev * pdev)164 static void rp1_unregister_interrupts(struct pci_dev *pdev)
165 {
166 struct rp1_dev *rp1 = pci_get_drvdata(pdev);
167 int irq, i;
168
169 if (rp1->domain) {
170 for (i = 0; i < RP1_INT_END; i++) {
171 irq = irq_find_mapping(rp1->domain, i);
172 irq_dispose_mapping(irq);
173 }
174
175 irq_domain_remove(rp1->domain);
176 }
177
178 pci_free_irq_vectors(pdev);
179 }
180
rp1_probe(struct pci_dev * pdev,const struct pci_device_id * id)181 static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
182 {
183 struct device *dev = &pdev->dev;
184 struct device_node *rp1_node;
185 struct rp1_dev *rp1;
186 int err = 0;
187 int i;
188
189 rp1_node = dev_of_node(dev);
190
191 if (!rp1_node) {
192 dev_err(dev, "Missing of_node for device\n");
193 err = -EINVAL;
194 goto err_put_node;
195 }
196
197 rp1 = devm_kzalloc(&pdev->dev, sizeof(*rp1), GFP_KERNEL);
198 if (!rp1) {
199 err = -ENOMEM;
200 goto err_put_node;
201 }
202
203 rp1->pdev = pdev;
204
205 if (pci_resource_len(pdev, 1) <= 0x10000) {
206 dev_err(&pdev->dev,
207 "Not initialized - is the firmware running?\n");
208 err = -EINVAL;
209 goto err_put_node;
210 }
211
212 err = pcim_enable_device(pdev);
213 if (err < 0) {
214 err = dev_err_probe(&pdev->dev, err,
215 "Enabling PCI device has failed");
216 goto err_put_node;
217 }
218
219 rp1->bar1 = pcim_iomap(pdev, 1, 0);
220 if (!rp1->bar1) {
221 dev_err(&pdev->dev, "Cannot map PCI BAR\n");
222 err = -EIO;
223 goto err_put_node;
224 }
225
226 pci_set_master(pdev);
227
228 err = pci_alloc_irq_vectors(pdev, RP1_INT_END, RP1_INT_END,
229 PCI_IRQ_MSIX);
230 if (err < 0) {
231 err = dev_err_probe(&pdev->dev, err,
232 "Failed to allocate MSI-X vectors\n");
233 goto err_put_node;
234 } else if (err != RP1_INT_END) {
235 dev_err(&pdev->dev, "Cannot allocate enough interrupts\n");
236 err = -EINVAL;
237 goto err_put_node;
238 }
239
240 pci_set_drvdata(pdev, rp1);
241 rp1->domain = irq_domain_add_linear(rp1_node, RP1_INT_END,
242 &rp1_domain_ops, rp1);
243 if (!rp1->domain) {
244 dev_err(&pdev->dev, "Error creating IRQ domain\n");
245 err = -ENOMEM;
246 goto err_unregister_interrupts;
247 }
248
249 for (i = 0; i < RP1_INT_END; i++) {
250 unsigned int irq = irq_create_mapping(rp1->domain, i);
251
252 if (!irq) {
253 dev_err(&pdev->dev, "Failed to create IRQ mapping\n");
254 err = -EINVAL;
255 goto err_unregister_interrupts;
256 }
257
258 irq_set_chip_and_handler(irq, &rp1_irq_chip, handle_level_irq);
259 irq_set_probe(irq);
260 irq_set_chained_handler_and_data(pci_irq_vector(pdev, i),
261 rp1_chained_handle_irq, rp1);
262 }
263
264 err = of_platform_default_populate(rp1_node, NULL, dev);
265 if (err) {
266 dev_err_probe(&pdev->dev, err, "Error populating devicetree\n");
267 goto err_unregister_interrupts;
268 }
269
270 of_node_put(rp1_node);
271
272 return 0;
273
274 err_unregister_interrupts:
275 rp1_unregister_interrupts(pdev);
276 err_put_node:
277 of_node_put(rp1_node);
278
279 return err;
280 }
281
rp1_remove(struct pci_dev * pdev)282 static void rp1_remove(struct pci_dev *pdev)
283 {
284 struct device *dev = &pdev->dev;
285
286 of_platform_depopulate(dev);
287 rp1_unregister_interrupts(pdev);
288 }
289
290 static const struct pci_device_id dev_id_table[] = {
291 { PCI_DEVICE(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0), },
292 { }
293 };
294 MODULE_DEVICE_TABLE(pci, dev_id_table);
295
296 static struct pci_driver rp1_driver = {
297 .name = KBUILD_MODNAME,
298 .id_table = dev_id_table,
299 .probe = rp1_probe,
300 .remove = rp1_remove,
301 };
302
303 module_pci_driver(rp1_driver);
304
305 MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.com>");
306 MODULE_AUTHOR("Andrea della Porta <andrea.porta@suse.com>");
307 MODULE_DESCRIPTION("RaspberryPi RP1 misc device");
308 MODULE_LICENSE("GPL");
309