1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx7ulp-clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12#include "imx7ulp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 gpio0 = &gpio_ptc; 22 gpio1 = &gpio_ptd; 23 gpio2 = &gpio_pte; 24 gpio3 = &gpio_ptf; 25 i2c0 = &lpi2c6; 26 i2c1 = &lpi2c7; 27 mmc0 = &usdhc0; 28 mmc1 = &usdhc1; 29 serial0 = &lpuart4; 30 serial1 = &lpuart5; 31 serial2 = &lpuart6; 32 serial3 = &lpuart7; 33 usbphy0 = &usbphy1; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@f00 { 41 compatible = "arm,cortex-a7"; 42 device_type = "cpu"; 43 reg = <0xf00>; 44 clocks = <&smc1 IMX7ULP_CLK_ARM>, 45 <&scg1 IMX7ULP_CLK_CORE>, 46 <&scg1 IMX7ULP_CLK_SYS_SEL>, 47 <&scg1 IMX7ULP_CLK_HSRUN_CORE>, 48 <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>, 49 <&scg1 IMX7ULP_CLK_FIRC>; 50 clock-names = "arm", "core", "scs_sel", 51 "hsrun_core", "hsrun_scs_sel", 52 "firc"; 53 operating-points-v2 = <&cpu0_opp_table>; 54 }; 55 }; 56 57 cpu0_opp_table: opp-table { 58 compatible = "operating-points-v2"; 59 opp-shared; 60 61 opp-500210000 { 62 opp-hz = /bits/ 64 <500210000>; 63 opp-microvolt = <1025000>; 64 clock-latency-ns = <150000>; 65 opp-suspend; 66 }; 67 68 opp-720000000 { 69 opp-hz = /bits/ 64 <720000000>; 70 opp-microvolt = <1125000>; 71 clock-latency-ns = <150000>; 72 }; 73 }; 74 75 intc: interrupt-controller@40021000 { 76 compatible = "arm,cortex-a7-gic"; 77 #interrupt-cells = <3>; 78 interrupt-controller; 79 reg = <0x40021000 0x1000>, 80 <0x40022000 0x1000>; 81 }; 82 83 rosc: clock-rosc { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 clock-output-names = "rosc"; 87 #clock-cells = <0>; 88 }; 89 90 sosc: clock-sosc { 91 compatible = "fixed-clock"; 92 clock-frequency = <24000000>; 93 clock-output-names = "sosc"; 94 #clock-cells = <0>; 95 }; 96 97 sirc: clock-sirc { 98 compatible = "fixed-clock"; 99 clock-frequency = <16000000>; 100 clock-output-names = "sirc"; 101 #clock-cells = <0>; 102 }; 103 104 firc: clock-firc { 105 compatible = "fixed-clock"; 106 clock-frequency = <48000000>; 107 clock-output-names = "firc"; 108 #clock-cells = <0>; 109 }; 110 111 upll: clock-upll { 112 compatible = "fixed-clock"; 113 clock-frequency = <480000000>; 114 clock-output-names = "upll"; 115 #clock-cells = <0>; 116 }; 117 118 ahbbridge0: bus@40000000 { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 reg = <0x40000000 0x800000>; 123 ranges; 124 125 edma1: dma-controller@40080000 { 126 #dma-cells = <2>; 127 compatible = "fsl,imx7ulp-edma"; 128 reg = <0x40080000 0x2000>, 129 <0x40210000 0x1000>; 130 dma-channels = <32>; 131 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 148 clock-names = "dma", "dmamux0"; 149 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, 150 <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 151 }; 152 153 crypto: crypto@40240000 { 154 compatible = "fsl,sec-v4.0"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 reg = <0x40240000 0x10000>; 158 ranges = <0 0x40240000 0x10000>; 159 clocks = <&pcc2 IMX7ULP_CLK_CAAM>, 160 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; 161 clock-names = "aclk", "ipg"; 162 163 sec_jr0: jr@1000 { 164 compatible = "fsl,sec-v4.0-job-ring"; 165 reg = <0x1000 0x1000>; 166 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 167 }; 168 169 sec_jr1: jr@2000 { 170 compatible = "fsl,sec-v4.0-job-ring"; 171 reg = <0x2000 0x1000>; 172 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 }; 175 176 lpuart4: serial@402d0000 { 177 compatible = "fsl,imx7ulp-lpuart"; 178 reg = <0x402d0000 0x1000>; 179 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; 181 clock-names = "ipg"; 182 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; 183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 184 assigned-clock-rates = <24000000>; 185 status = "disabled"; 186 }; 187 188 lpuart5: serial@402e0000 { 189 compatible = "fsl,imx7ulp-lpuart"; 190 reg = <0x402e0000 0x1000>; 191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; 193 clock-names = "ipg"; 194 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; 195 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 196 assigned-clock-rates = <48000000>; 197 status = "disabled"; 198 }; 199 200 tpm4: pwm@40250000 { 201 compatible = "fsl,imx7ulp-pwm"; 202 reg = <0x40250000 0x1000>; 203 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 204 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 205 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 206 #pwm-cells = <3>; 207 status = "disabled"; 208 }; 209 210 tpm5: tpm@40260000 { 211 compatible = "fsl,imx7ulp-tpm"; 212 reg = <0x40260000 0x1000>; 213 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 215 <&pcc2 IMX7ULP_CLK_LPTPM5>; 216 clock-names = "ipg", "per"; 217 }; 218 219 usbotg1: usb@40330000 { 220 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; 221 reg = <0x40330000 0x200>; 222 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&pcc2 IMX7ULP_CLK_USB0>; 224 phys = <&usbphy1>; 225 fsl,usbmisc = <&usbmisc1 0>; 226 ahb-burst-config = <0x0>; 227 tx-burst-size-dword = <0x8>; 228 rx-burst-size-dword = <0x8>; 229 status = "disabled"; 230 }; 231 232 usbmisc1: usbmisc@40330200 { 233 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", 234 "fsl,imx6q-usbmisc"; 235 #index-cells = <1>; 236 reg = <0x40330200 0x200>; 237 }; 238 239 usbphy1: usb-phy@40350000 { 240 compatible = "fsl,imx7ulp-usbphy"; 241 reg = <0x40350000 0x1000>; 242 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; 244 #phy-cells = <0>; 245 nxp,sim = <&sim>; 246 }; 247 248 usdhc0: mmc@40370000 { 249 compatible = "fsl,imx7ulp-usdhc"; 250 reg = <0x40370000 0x10000>; 251 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 253 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 254 <&pcc2 IMX7ULP_CLK_USDHC0>; 255 clock-names = "ipg", "ahb", "per"; 256 bus-width = <4>; 257 fsl,tuning-start-tap = <20>; 258 fsl,tuning-step = <2>; 259 status = "disabled"; 260 }; 261 262 usdhc1: mmc@40380000 { 263 compatible = "fsl,imx7ulp-usdhc"; 264 reg = <0x40380000 0x10000>; 265 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 267 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 268 <&pcc2 IMX7ULP_CLK_USDHC1>; 269 clock-names = "ipg", "ahb", "per"; 270 bus-width = <4>; 271 fsl,tuning-start-tap = <20>; 272 fsl,tuning-step = <2>; 273 status = "disabled"; 274 }; 275 276 scg1: clock-controller@403e0000 { 277 compatible = "fsl,imx7ulp-scg1"; 278 reg = <0x403e0000 0x10000>; 279 clocks = <&rosc>, <&sosc>, <&sirc>, 280 <&firc>, <&upll>; 281 clock-names = "rosc", "sosc", "sirc", 282 "firc", "upll"; 283 #clock-cells = <1>; 284 }; 285 286 wdog1: watchdog@403d0000 { 287 compatible = "fsl,imx7ulp-wdt"; 288 reg = <0x403d0000 0x10000>; 289 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 291 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 292 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; 293 timeout-sec = <40>; 294 }; 295 296 pcc2: clock-controller@403f0000 { 297 compatible = "fsl,imx7ulp-pcc2"; 298 reg = <0x403f0000 0x10000>; 299 #clock-cells = <1>; 300 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 301 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 302 <&scg1 IMX7ULP_CLK_DDR_DIV>, 303 <&scg1 IMX7ULP_CLK_APLL_PFD2>, 304 <&scg1 IMX7ULP_CLK_APLL_PFD1>, 305 <&scg1 IMX7ULP_CLK_APLL_PFD0>, 306 <&scg1 IMX7ULP_CLK_UPLL>, 307 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 308 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 309 <&scg1 IMX7ULP_CLK_ROSC>, 310 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 311 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 312 "apll_pfd2", "apll_pfd1", "apll_pfd0", 313 "upll", "sosc_bus_clk", 314 "firc_bus_clk", "rosc", "spll_bus_clk"; 315 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; 316 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 317 }; 318 319 smc1: clock-controller@40410000 { 320 compatible = "fsl,imx7ulp-smc1"; 321 reg = <0x40410000 0x1000>; 322 #clock-cells = <1>; 323 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, 324 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; 325 clock-names = "divcore", "hsrun_divcore"; 326 }; 327 328 pcc3: clock-controller@40b30000 { 329 compatible = "fsl,imx7ulp-pcc3"; 330 reg = <0x40b30000 0x10000>; 331 #clock-cells = <1>; 332 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 333 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 334 <&scg1 IMX7ULP_CLK_DDR_DIV>, 335 <&scg1 IMX7ULP_CLK_APLL_PFD2>, 336 <&scg1 IMX7ULP_CLK_APLL_PFD1>, 337 <&scg1 IMX7ULP_CLK_APLL_PFD0>, 338 <&scg1 IMX7ULP_CLK_UPLL>, 339 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 340 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 341 <&scg1 IMX7ULP_CLK_ROSC>, 342 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 343 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 344 "apll_pfd2", "apll_pfd1", "apll_pfd0", 345 "upll", "sosc_bus_clk", 346 "firc_bus_clk", "rosc", "spll_bus_clk"; 347 }; 348 }; 349 350 ahbbridge1: bus@40800000 { 351 compatible = "simple-bus"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 reg = <0x40800000 0x800000>; 355 ranges; 356 357 lpi2c6: i2c@40a40000 { 358 compatible = "fsl,imx7ulp-lpi2c"; 359 reg = <0x40a40000 0x10000>; 360 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, 362 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; 363 clock-names = "per", "ipg"; 364 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; 365 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 366 assigned-clock-rates = <48000000>; 367 status = "disabled"; 368 }; 369 370 lpi2c7: i2c@40a50000 { 371 compatible = "fsl,imx7ulp-lpi2c"; 372 reg = <0x40a50000 0x10000>; 373 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, 375 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; 376 clock-names = "per", "ipg"; 377 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; 378 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 379 assigned-clock-rates = <48000000>; 380 status = "disabled"; 381 }; 382 383 lpuart6: serial@40a60000 { 384 compatible = "fsl,imx7ulp-lpuart"; 385 reg = <0x40a60000 0x1000>; 386 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; 388 clock-names = "ipg"; 389 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; 390 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 391 assigned-clock-rates = <48000000>; 392 status = "disabled"; 393 }; 394 395 lpuart7: serial@40a70000 { 396 compatible = "fsl,imx7ulp-lpuart"; 397 reg = <0x40a70000 0x1000>; 398 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; 400 clock-names = "ipg"; 401 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; 402 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; 403 assigned-clock-rates = <48000000>; 404 status = "disabled"; 405 }; 406 407 memory-controller@40ab0000 { 408 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; 409 reg = <0x40ab0000 0x1000>; 410 clocks = <&pcc3 IMX7ULP_CLK_MMDC>; 411 }; 412 413 iomuxc1: pinctrl@40ac0000 { 414 compatible = "fsl,imx7ulp-iomuxc1"; 415 reg = <0x40ac0000 0x1000>; 416 }; 417 418 gpio_ptc: gpio@40ae0000 { 419 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; 420 reg = <0x40ae0000 0x1000 0x400f0000 0x40>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, 427 <&pcc3 IMX7ULP_CLK_PCTLC>; 428 clock-names = "gpio", "port"; 429 gpio-ranges = <&iomuxc1 0 0 20>; 430 ngpios = <20>; 431 }; 432 433 gpio_ptd: gpio@40af0000 { 434 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; 435 reg = <0x40af0000 0x1000 0x400f0040 0x40>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, 442 <&pcc3 IMX7ULP_CLK_PCTLD>; 443 clock-names = "gpio", "port"; 444 gpio-ranges = <&iomuxc1 0 32 12>; 445 ngpios = <12>; 446 }; 447 448 gpio_pte: gpio@40b00000 { 449 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; 450 reg = <0x40b00000 0x1000 0x400f0080 0x40>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, 457 <&pcc3 IMX7ULP_CLK_PCTLE>; 458 clock-names = "gpio", "port"; 459 gpio-ranges = <&iomuxc1 0 64 16>; 460 ngpios = <16>; 461 }; 462 463 gpio_ptf: gpio@40b10000 { 464 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; 465 reg = <0x40b10000 0x1000 0x400f00c0 0x40>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, 472 <&pcc3 IMX7ULP_CLK_PCTLF>; 473 clock-names = "gpio", "port"; 474 gpio-ranges = <&iomuxc1 0 96 20>; 475 ngpios = <20>; 476 }; 477 }; 478 479 m4aips1: bus@41080000 { 480 compatible = "simple-bus"; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 reg = <0x41080000 0x80000>; 484 ranges; 485 486 sim: sim@410a3000 { 487 compatible = "fsl,imx7ulp-sim", "syscon"; 488 reg = <0x410a3000 0x1000>; 489 }; 490 491 ocotp: efuse@410a6000 { 492 compatible = "fsl,imx7ulp-ocotp", "syscon"; 493 reg = <0x410a6000 0x4000>; 494 clocks = <&scg1 IMX7ULP_CLK_DUMMY>; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 }; 498 }; 499}; 500