1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip Video Decoder HEVC backend
4 *
5 * Copyright (C) 2023 Collabora, Ltd.
6 * Sebastian Fricke <sebastian.fricke@collabora.com>
7 *
8 * Copyright (C) 2019 Collabora, Ltd.
9 * Boris Brezillon <boris.brezillon@collabora.com>
10 *
11 * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
12 * Jeffy Chen <jeffy.chen@rock-chips.com>
13 */
14
15 #include <media/v4l2-hevc.h>
16 #include <media/v4l2-mem2mem.h>
17
18 #include "rkvdec.h"
19 #include "rkvdec-regs.h"
20 #include "rkvdec-cabac.h"
21 #include "rkvdec-hevc-common.h"
22 #include "rkvdec-bitwriter.h"
23
24 /* Size in u8/u32 units. */
25 #define RKV_SCALING_LIST_SIZE 1360
26 #define RKV_PPS_SIZE (80 / 4)
27 #define RKV_PPS_LEN 64
28 #define RKV_RPS_SIZE (32 / 4)
29 #define RKV_RPS_LEN 600
30
31 struct rkvdec_sps_pps_packet {
32 u32 info[RKV_PPS_SIZE];
33 };
34
35 struct rkvdec_rps_packet {
36 u32 info[RKV_RPS_SIZE];
37 };
38
39 /* SPS */
40 #define VIDEO_PARAMETER_SET_ID BW_FIELD(0, 4)
41 #define SEQ_PARAMETER_SET_ID BW_FIELD(4, 4)
42 #define CHROMA_FORMAT_IDC BW_FIELD(8, 2)
43 #define PIC_WIDTH_IN_LUMA_SAMPLES BW_FIELD(10, 13)
44 #define PIC_HEIGHT_IN_LUMA_SAMPLES BW_FIELD(23, 13)
45 #define BIT_DEPTH_LUMA BW_FIELD(36, 4)
46 #define BIT_DEPTH_CHROMA BW_FIELD(40, 4)
47 #define LOG2_MAX_PIC_ORDER_CNT_LSB BW_FIELD(44, 5)
48 #define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(49, 2)
49 #define LOG2_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(51, 3)
50 #define LOG2_MIN_TRANSFORM_BLOCK_SIZE BW_FIELD(54, 3)
51 #define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE BW_FIELD(57, 2)
52 #define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER BW_FIELD(59, 3)
53 #define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA BW_FIELD(62, 3)
54 #define SCALING_LIST_ENABLED_FLAG BW_FIELD(65, 1)
55 #define AMP_ENABLED_FLAG BW_FIELD(66, 1)
56 #define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG BW_FIELD(67, 1)
57 #define PCM_ENABLED_FLAG BW_FIELD(68, 1)
58 #define PCM_SAMPLE_BIT_DEPTH_LUMA BW_FIELD(69, 4)
59 #define PCM_SAMPLE_BIT_DEPTH_CHROMA BW_FIELD(73, 4)
60 #define PCM_LOOP_FILTER_DISABLED_FLAG BW_FIELD(77, 1)
61 #define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(78, 3)
62 #define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(81, 3)
63 #define NUM_SHORT_TERM_REF_PIC_SETS BW_FIELD(84, 7)
64 #define LONG_TERM_REF_PICS_PRESENT_FLAG BW_FIELD(91, 1)
65 #define NUM_LONG_TERM_REF_PICS_SPS BW_FIELD(92, 6)
66 #define SPS_TEMPORAL_MVP_ENABLED_FLAG BW_FIELD(98, 1)
67 #define STRONG_INTRA_SMOOTHING_ENABLED_FLAG BW_FIELD(99, 1)
68 /* PPS */
69 #define PIC_PARAMETER_SET_ID BW_FIELD(128, 6)
70 #define PPS_SEQ_PARAMETER_SET_ID BW_FIELD(134, 4)
71 #define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG BW_FIELD(138, 1)
72 #define OUTPUT_FLAG_PRESENT_FLAG BW_FIELD(139, 1)
73 #define NUM_EXTRA_SLICE_HEADER_BITS BW_FIELD(140, 13)
74 #define SIGN_DATA_HIDING_ENABLED_FLAG BW_FIELD(153, 1)
75 #define CABAC_INIT_PRESENT_FLAG BW_FIELD(154, 1)
76 #define NUM_REF_IDX_L0_DEFAULT_ACTIVE BW_FIELD(155, 4)
77 #define NUM_REF_IDX_L1_DEFAULT_ACTIVE BW_FIELD(159, 4)
78 #define INIT_QP_MINUS26 BW_FIELD(163, 7)
79 #define CONSTRAINED_INTRA_PRED_FLAG BW_FIELD(170, 1)
80 #define TRANSFORM_SKIP_ENABLED_FLAG BW_FIELD(171, 1)
81 #define CU_QP_DELTA_ENABLED_FLAG BW_FIELD(172, 1)
82 #define LOG2_MIN_CU_QP_DELTA_SIZE BW_FIELD(173, 3)
83 #define PPS_CB_QP_OFFSET BW_FIELD(176, 5)
84 #define PPS_CR_QP_OFFSET BW_FIELD(181, 5)
85 #define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG BW_FIELD(186, 1)
86 #define WEIGHTED_PRED_FLAG BW_FIELD(187, 1)
87 #define WEIGHTED_BIPRED_FLAG BW_FIELD(188, 1)
88 #define TRANSQUANT_BYPASS_ENABLED_FLAG BW_FIELD(189, 1)
89 #define TILES_ENABLED_FLAG BW_FIELD(190, 1)
90 #define ENTROPY_CODING_SYNC_ENABLED_FLAG BW_FIELD(191, 1)
91 #define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG BW_FIELD(192, 1)
92 #define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG BW_FIELD(193, 1)
93 #define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG BW_FIELD(194, 1)
94 #define PPS_DEBLOCKING_FILTER_DISABLED_FLAG BW_FIELD(195, 1)
95 #define PPS_BETA_OFFSET_DIV2 BW_FIELD(196, 4)
96 #define PPS_TC_OFFSET_DIV2 BW_FIELD(200, 4)
97 #define LISTS_MODIFICATION_PRESENT_FLAG BW_FIELD(204, 1)
98 #define LOG2_PARALLEL_MERGE_LEVEL BW_FIELD(205, 3)
99 #define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG BW_FIELD(208, 1)
100 #define NUM_TILE_COLUMNS BW_FIELD(212, 5)
101 #define NUM_TILE_ROWS BW_FIELD(217, 5)
102 #define COLUMN_WIDTH(i) BW_FIELD(256 + ((i) * 8), 8)
103 #define ROW_HEIGHT(i) BW_FIELD(416 + ((i) * 8), 8)
104 #define SCALING_LIST_ADDRESS BW_FIELD(592, 32)
105
106 /* Data structure describing auxiliary buffer format. */
107 struct rkvdec_hevc_priv_tbl {
108 u8 cabac_table[RKV_HEVC_CABAC_TABLE_SIZE];
109 struct scaling_factor scaling_list;
110 struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
111 struct rkvdec_rps_packet rps[RKV_RPS_LEN];
112 };
113
114 struct rkvdec_hevc_ctx {
115 struct rkvdec_aux_buf priv_tbl;
116 struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
117 struct rkvdec_regs regs;
118 };
119
assemble_hw_pps(struct rkvdec_ctx * ctx,struct rkvdec_hevc_run * run)120 static void assemble_hw_pps(struct rkvdec_ctx *ctx,
121 struct rkvdec_hevc_run *run)
122 {
123 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
124 const struct v4l2_ctrl_hevc_sps *sps = run->sps;
125 const struct v4l2_ctrl_hevc_pps *pps = run->pps;
126 struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
127 struct rkvdec_sps_pps_packet *hw_ps;
128 u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
129 u32 log2_min_cu_qp_delta_size, scaling_distance;
130 dma_addr_t scaling_list_address;
131 int i;
132
133 /*
134 * HW read the SPS/PPS information from PPS packet index by PPS id.
135 * offset from the base can be calculated by PPS_id * 80 (size per PPS
136 * packet unit). so the driver copy SPS/PPS information to the exact PPS
137 * packet unit for HW accessing.
138 */
139 if (pps->pic_parameter_set_id >= ARRAY_SIZE(priv_tbl->param_set))
140 return;
141 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
142 memset(hw_ps, 0, sizeof(*hw_ps));
143
144 #define WRITE_PPS(value, field) rkvdec_set_bw_field(hw_ps->info, field, value)
145 /* write sps */
146 WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
147 WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
148 WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
149 WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
150 WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
151 WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
152 WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
153 WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
154 LOG2_MAX_PIC_ORDER_CNT_LSB);
155 WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
156 LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
157 WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
158 LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
159 WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
160 LOG2_MIN_TRANSFORM_BLOCK_SIZE);
161 WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
162 LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
163 WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
164 MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
165 WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
166 MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
167 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
168 SCALING_LIST_ENABLED_FLAG);
169 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
170 AMP_ENABLED_FLAG);
171 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
172 SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
173 if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
174 WRITE_PPS(1, PCM_ENABLED_FLAG);
175 WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
176 PCM_SAMPLE_BIT_DEPTH_LUMA);
177 WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
178 PCM_SAMPLE_BIT_DEPTH_CHROMA);
179 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
180 PCM_LOOP_FILTER_DISABLED_FLAG);
181 WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
182 LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
183 WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
184 LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
185 }
186 WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
187 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
188 LONG_TERM_REF_PICS_PRESENT_FLAG);
189 WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
190 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
191 SPS_TEMPORAL_MVP_ENABLED_FLAG);
192 WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
193 STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
194
195 /* write pps */
196 WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
197 WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
198 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
199 DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
200 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
201 OUTPUT_FLAG_PRESENT_FLAG);
202 WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
203 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
204 SIGN_DATA_HIDING_ENABLED_FLAG);
205 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
206 CABAC_INIT_PRESENT_FLAG);
207 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
208 NUM_REF_IDX_L0_DEFAULT_ACTIVE);
209 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
210 NUM_REF_IDX_L1_DEFAULT_ACTIVE);
211 WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
212 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
213 CONSTRAINED_INTRA_PRED_FLAG);
214 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
215 TRANSFORM_SKIP_ENABLED_FLAG);
216 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
217 CU_QP_DELTA_ENABLED_FLAG);
218
219 min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
220 ctb_log2_size_y = min_cb_log2_size_y +
221 sps->log2_diff_max_min_luma_coding_block_size;
222 ctb_size_y = 1 << ctb_log2_size_y;
223 log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
224 WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
225 WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
226 WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
227 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
228 PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
229 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
230 WEIGHTED_PRED_FLAG);
231 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
232 WEIGHTED_BIPRED_FLAG);
233 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
234 TRANSQUANT_BYPASS_ENABLED_FLAG);
235 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
236 TILES_ENABLED_FLAG);
237 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
238 ENTROPY_CODING_SYNC_ENABLED_FLAG);
239 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
240 PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
241 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
242 LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
243 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
244 DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
245 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
246 PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
247 WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
248 WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
249 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
250 LISTS_MODIFICATION_PRESENT_FLAG);
251 WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
252 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
253 SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
254 WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
255 WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
256
257 if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
258 /* Userspace also provide column width and row height for uniform spacing */
259 for (i = 0; i < v4l2_hevc_pps_num_tile_columns(pps); i++)
260 WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
261 for (i = 0; i < v4l2_hevc_pps_num_tile_rows(pps); i++)
262 WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
263 } else {
264 WRITE_PPS(DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_y) - 1,
265 COLUMN_WIDTH(0));
266 WRITE_PPS(DIV_ROUND_UP(sps->pic_height_in_luma_samples, ctb_size_y) - 1,
267 ROW_HEIGHT(0));
268 }
269
270 scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
271 scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
272 WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
273 }
274
275 /*
276 * Creation of the Reference Picture Set memory blob for the hardware.
277 * The layout looks like this:
278 * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
279 * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
280 * + 4 bits of the 13th reference)
281 * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
282 * 21 bits for L1 (4 references + first bit of 5)
283 * [3] 32 bits of padding with 0s
284 * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
285 * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
286 * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
287 * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
288 * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
289 * [7] 32 bits of padding with 0s
290 *
291 * Thus we have to set up padding in between reference 5 of the L1 list.
292 */
assemble_sw_rps(struct rkvdec_ctx * ctx,struct rkvdec_hevc_run * run)293 static void assemble_sw_rps(struct rkvdec_ctx *ctx,
294 struct rkvdec_hevc_run *run)
295 {
296 const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
297 const struct v4l2_ctrl_hevc_sps *sps = run->sps;
298 const struct v4l2_ctrl_hevc_slice_params *sl_params;
299 const struct v4l2_hevc_dpb_entry *dpb;
300 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
301 struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
302 struct rkvdec_rps_packet *hw_ps;
303 int i, j;
304 unsigned int lowdelay;
305
306 #define WRITE_RPS(value, field) rkvdec_set_bw_field(hw_ps->info, field, value)
307
308 #define REF_PIC_LONG_TERM_L0(n) BW_FIELD((n) * 5, 1)
309 #define REF_PIC_IDX_L0(n) BW_FIELD(1 + ((n) * 5), 4)
310 #define REF_PIC_LONG_TERM_L1(n) BW_FIELD(((n) < 5 ? 75 : 132) + ((n) * 5), 1)
311 #define REF_PIC_IDX_L1(n) BW_FIELD(((n) < 4 ? 76 : 128) + ((n) * 5), 4)
312
313 #define LOWDELAY BW_FIELD(182, 1)
314 #define LONG_TERM_RPS_BIT_OFFSET BW_FIELD(183, 10)
315 #define SHORT_TERM_RPS_BIT_OFFSET BW_FIELD(193, 9)
316 #define NUM_RPS_POC BW_FIELD(202, 4)
317
318 for (j = 0; j < run->num_slices; j++) {
319 uint st_bit_offset = 0;
320 uint num_l0_refs = 0;
321 uint num_l1_refs = 0;
322
323 sl_params = &run->slices_params[j];
324 dpb = decode_params->dpb;
325
326 if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
327 num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
328
329 if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
330 num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
331
332 lowdelay = 1;
333 } else {
334 lowdelay = 0;
335 }
336
337 hw_ps = &priv_tbl->rps[j];
338 memset(hw_ps, 0, sizeof(*hw_ps));
339
340 for (i = 0; i < num_l0_refs; i++) {
341 const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
342
343 WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
344 REF_PIC_LONG_TERM_L0(i));
345 WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
346
347 if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
348 lowdelay = 0;
349 }
350
351 for (i = 0; i < num_l1_refs; i++) {
352 const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
353 int is_long_term =
354 !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
355
356 WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
357 WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
358
359 if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
360 lowdelay = 0;
361 }
362
363 WRITE_RPS(lowdelay, LOWDELAY);
364
365 if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
366 if (sl_params->short_term_ref_pic_set_size)
367 st_bit_offset = sl_params->short_term_ref_pic_set_size;
368 else if (sps->num_short_term_ref_pic_sets > 1)
369 st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
370 }
371
372 WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
373 LONG_TERM_RPS_BIT_OFFSET);
374 WRITE_RPS(sl_params->short_term_ref_pic_set_size,
375 SHORT_TERM_RPS_BIT_OFFSET);
376
377 WRITE_RPS(decode_params->num_poc_st_curr_before +
378 decode_params->num_poc_st_curr_after +
379 decode_params->num_poc_lt_curr,
380 NUM_RPS_POC);
381 }
382 }
383
config_registers(struct rkvdec_ctx * ctx,struct rkvdec_hevc_run * run)384 static void config_registers(struct rkvdec_ctx *ctx,
385 struct rkvdec_hevc_run *run)
386 {
387 struct rkvdec_dev *rkvdec = ctx->dev;
388 const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
389 const struct v4l2_ctrl_hevc_sps *sps = run->sps;
390 const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
391 const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
392 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
393 struct rkvdec_regs *regs = &hevc_ctx->regs;
394 dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
395 const struct v4l2_pix_format_mplane *dst_fmt;
396 struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
397 struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
398 const struct v4l2_format *f;
399 dma_addr_t rlc_addr;
400 dma_addr_t refer_addr;
401 u32 rlc_len;
402 u32 hor_virstride;
403 u32 ver_virstride;
404 u32 y_virstride;
405 u32 yuv_virstride = 0;
406 u32 offset;
407 dma_addr_t dst_addr;
408 u32 reg, i;
409
410 memset(regs, 0, sizeof(*regs));
411
412 regs->common.reg02.dec_mode = RKVDEC_MODE_HEVC;
413
414 f = &ctx->decoded_fmt;
415 dst_fmt = &f->fmt.pix_mp;
416 hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
417 ver_virstride = dst_fmt->height;
418 y_virstride = hor_virstride * ver_virstride;
419
420 if (sps->chroma_format_idc == 0)
421 yuv_virstride = y_virstride;
422 else if (sps->chroma_format_idc == 1)
423 yuv_virstride = y_virstride + y_virstride / 2;
424 else if (sps->chroma_format_idc == 2)
425 yuv_virstride = 2 * y_virstride;
426
427 regs->common.reg03.slice_num_lowbits = run->num_slices;
428 regs->common.reg03.uv_hor_virstride = hor_virstride / 16;
429 regs->common.reg03.y_hor_virstride = hor_virstride / 16;
430
431 /* config rlc base address */
432 rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
433 regs->common.strm_rlc_base = rlc_addr;
434
435 rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
436 regs->common.stream_len = round_up(rlc_len, 16) + 64;
437
438 /* config cabac table */
439 offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
440 regs->common.cabactbl_base = priv_start_addr + offset;
441
442 /* config output base address */
443 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
444 regs->common.decout_base = dst_addr;
445
446 regs->common.reg08.y_virstride = y_virstride / 16;
447 regs->common.reg09.yuv_virstride = yuv_virstride / 16;
448
449 /* config ref pic address */
450 for (i = 0; i < 15; i++) {
451 struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
452
453 if (i < 4 && decode_params->num_active_dpb_entries) {
454 reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
455 reg = (reg >> (i * 4)) & 0xf;
456 } else {
457 reg = 0;
458 }
459
460 refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
461
462 regs->h26x.ref0_14_base[i].base_addr = refer_addr >> 4;
463 regs->h26x.ref0_14_base[i].field_ref = !!(reg & 1);
464 regs->h26x.ref0_14_base[i].topfield_used_ref = !!(reg & 2);
465 regs->h26x.ref0_14_base[i].botfield_used_ref = !!(reg & 4);
466 regs->h26x.ref0_14_base[i].colmv_use_flag_ref = !!(reg & 8);
467
468 regs->h26x.ref0_14_poc[i] = i < decode_params->num_active_dpb_entries
469 ? dpb[i].pic_order_cnt_val
470 : 0;
471 }
472
473 regs->h26x.cur_poc = sl_params->slice_pic_order_cnt;
474
475 /* config hw pps address */
476 offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
477 regs->h26x.pps_base = priv_start_addr + offset;
478
479 /* config hw rps address */
480 offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
481 regs->h26x.rps_base = priv_start_addr + offset;
482
483 rkvdec_memcpy_toio(rkvdec->regs, regs,
484 MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs));
485 }
486
rkvdec_hevc_validate_sps(struct rkvdec_ctx * ctx,const struct v4l2_ctrl_hevc_sps * sps)487 static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
488 const struct v4l2_ctrl_hevc_sps *sps)
489 {
490 if (sps->chroma_format_idc > 1)
491 /* Only 4:0:0 and 4:2:0 are supported */
492 return -EINVAL;
493 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
494 /* Luma and chroma bit depth mismatch */
495 return -EINVAL;
496 if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
497 /* Only 8-bit and 10-bit are supported */
498 return -EINVAL;
499
500 if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
501 sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
502 return -EINVAL;
503
504 return 0;
505 }
506
rkvdec_hevc_start(struct rkvdec_ctx * ctx)507 static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
508 {
509 struct rkvdec_dev *rkvdec = ctx->dev;
510 struct rkvdec_hevc_priv_tbl *priv_tbl;
511 struct rkvdec_hevc_ctx *hevc_ctx;
512
513 hevc_ctx = kzalloc_obj(*hevc_ctx);
514 if (!hevc_ctx)
515 return -ENOMEM;
516
517 priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
518 &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
519 if (!priv_tbl) {
520 kfree(hevc_ctx);
521 return -ENOMEM;
522 }
523
524 hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
525 hevc_ctx->priv_tbl.cpu = priv_tbl;
526 memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
527 sizeof(rkvdec_hevc_cabac_table));
528
529 ctx->priv = hevc_ctx;
530 return 0;
531 }
532
rkvdec_hevc_stop(struct rkvdec_ctx * ctx)533 static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
534 {
535 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
536 struct rkvdec_dev *rkvdec = ctx->dev;
537
538 dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
539 hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
540 kfree(hevc_ctx);
541 }
542
rkvdec_hevc_run(struct rkvdec_ctx * ctx)543 static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
544 {
545 struct rkvdec_dev *rkvdec = ctx->dev;
546 struct rkvdec_hevc_run run;
547 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
548 struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
549 u32 reg;
550
551 rkvdec_hevc_run_preamble(ctx, &run);
552
553 rkvdec_hevc_assemble_hw_scaling_list(ctx, &run, &tbl->scaling_list,
554 &hevc_ctx->scaling_matrix_cache);
555 assemble_hw_pps(ctx, &run);
556 assemble_sw_rps(ctx, &run);
557 config_registers(ctx, &run);
558
559 rkvdec_run_postamble(ctx, &run.base);
560
561 schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
562
563 writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
564 writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
565
566 if (rkvdec->variant->quirks & RKVDEC_QUIRK_DISABLE_QOS)
567 rkvdec_quirks_disable_qos(ctx);
568
569 /* Start decoding! */
570 reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ?
571 0 : RKVDEC_WR_DDR_ALIGN_EN;
572 writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
573 RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E | reg,
574 rkvdec->regs + RKVDEC_REG_INTERRUPT);
575
576 return 0;
577 }
578
rkvdec_hevc_try_ctrl(struct rkvdec_ctx * ctx,struct v4l2_ctrl * ctrl)579 static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
580 {
581 if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
582 return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
583
584 return 0;
585 }
586
587 const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
588 .adjust_fmt = rkvdec_hevc_adjust_fmt,
589 .start = rkvdec_hevc_start,
590 .stop = rkvdec_hevc_stop,
591 .run = rkvdec_hevc_run,
592 .try_ctrl = rkvdec_hevc_try_ctrl,
593 .get_image_fmt = rkvdec_hevc_get_image_fmt,
594 };
595