1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 /*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8 */
9
10 #include "dl2k.h"
11 #include <linux/dma-mapping.h>
12
13 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
14 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
15 #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
16 #define dr32(reg) ioread32(ioaddr + (reg))
17 #define dr16(reg) ioread16(ioaddr + (reg))
18 #define dr8(reg) ioread8(ioaddr + (reg))
19
20 #define MAX_UNITS 8
21 static int mtu[MAX_UNITS];
22 static int vlan[MAX_UNITS];
23 static int jumbo[MAX_UNITS];
24 static char *media[MAX_UNITS];
25 static int tx_flow=-1;
26 static int rx_flow=-1;
27 static int copy_thresh;
28 static int rx_coalesce=10; /* Rx frame count each interrupt */
29 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
30 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
31
32
33 MODULE_AUTHOR ("Edward Peng");
34 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
35 MODULE_LICENSE("GPL");
36 module_param_array(mtu, int, NULL, 0);
37 module_param_array(media, charp, NULL, 0);
38 module_param_array(vlan, int, NULL, 0);
39 module_param_array(jumbo, int, NULL, 0);
40 module_param(tx_flow, int, 0);
41 module_param(rx_flow, int, 0);
42 module_param(copy_thresh, int, 0);
43 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
46
47
48 /* Enable the default interrupts */
49 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
50 UpdateStats | LinkEvent)
51
dl2k_enable_int(struct netdev_private * np)52 static void dl2k_enable_int(struct netdev_private *np)
53 {
54 void __iomem *ioaddr = np->ioaddr;
55
56 dw16(IntEnable, DEFAULT_INTR);
57 }
58
59 static const int max_intrloop = 50;
60 static const int multicast_filter_limit = 0x40;
61
62 static int rio_open (struct net_device *dev);
63 static void rio_timer (struct timer_list *t);
64 static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
65 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
66 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
67 static void rio_free_tx (struct net_device *dev, int irq);
68 static void tx_error (struct net_device *dev, int tx_status);
69 static int receive_packet (struct net_device *dev);
70 static void rio_error (struct net_device *dev, int int_status);
71 static void set_multicast (struct net_device *dev);
72 static struct net_device_stats *get_stats (struct net_device *dev);
73 static int clear_stats (struct net_device *dev);
74 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
75 static int rio_close (struct net_device *dev);
76 static int find_miiphy (struct net_device *dev);
77 static int parse_eeprom (struct net_device *dev);
78 static int read_eeprom (struct netdev_private *, int eep_addr);
79 static int mii_wait_link (struct net_device *dev, int wait);
80 static int mii_set_media (struct net_device *dev);
81 static int mii_get_media (struct net_device *dev);
82 static int mii_set_media_pcs (struct net_device *dev);
83 static int mii_get_media_pcs (struct net_device *dev);
84 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
85 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
86 u16 data);
87
88 static const struct ethtool_ops ethtool_ops;
89
90 static const struct net_device_ops netdev_ops = {
91 .ndo_open = rio_open,
92 .ndo_start_xmit = start_xmit,
93 .ndo_stop = rio_close,
94 .ndo_get_stats = get_stats,
95 .ndo_validate_addr = eth_validate_addr,
96 .ndo_set_mac_address = eth_mac_addr,
97 .ndo_set_rx_mode = set_multicast,
98 .ndo_eth_ioctl = rio_ioctl,
99 .ndo_tx_timeout = rio_tx_timeout,
100 };
101
is_support_rmon_mmio(struct pci_dev * pdev)102 static bool is_support_rmon_mmio(struct pci_dev *pdev)
103 {
104 return pdev->vendor == PCI_VENDOR_ID_DLINK &&
105 pdev->device == 0x4000 &&
106 pdev->revision == 0x0c;
107 }
108
109 static int
rio_probe1(struct pci_dev * pdev,const struct pci_device_id * ent)110 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
111 {
112 struct net_device *dev;
113 struct netdev_private *np;
114 static int card_idx;
115 int chip_idx = ent->driver_data;
116 int err, irq;
117 void __iomem *ioaddr;
118 void *ring_space;
119 dma_addr_t ring_dma;
120
121 err = pci_enable_device (pdev);
122 if (err)
123 return err;
124
125 irq = pdev->irq;
126 err = pci_request_regions (pdev, "dl2k");
127 if (err)
128 goto err_out_disable;
129
130 pci_set_master (pdev);
131
132 err = -ENOMEM;
133
134 dev = alloc_etherdev (sizeof (*np));
135 if (!dev)
136 goto err_out_res;
137 SET_NETDEV_DEV(dev, &pdev->dev);
138
139 np = netdev_priv(dev);
140
141 if (is_support_rmon_mmio(pdev))
142 np->rmon_enable = true;
143
144 /* IO registers range. */
145 ioaddr = pci_iomap(pdev, 0, 0);
146 if (!ioaddr)
147 goto err_out_dev;
148 np->eeprom_addr = ioaddr;
149
150 if (np->rmon_enable) {
151 /* MM registers range. */
152 ioaddr = pci_iomap(pdev, 1, 0);
153 if (!ioaddr)
154 goto err_out_iounmap;
155 }
156
157 np->ioaddr = ioaddr;
158 np->chip_id = chip_idx;
159 np->pdev = pdev;
160
161 spin_lock_init(&np->stats_lock);
162 spin_lock_init (&np->tx_lock);
163 spin_lock_init (&np->rx_lock);
164
165 /* Parse manual configuration */
166 np->an_enable = 1;
167 np->tx_coalesce = 1;
168 if (card_idx < MAX_UNITS) {
169 if (media[card_idx] != NULL) {
170 np->an_enable = 0;
171 if (strcmp (media[card_idx], "auto") == 0 ||
172 strcmp (media[card_idx], "autosense") == 0 ||
173 strcmp (media[card_idx], "0") == 0 ) {
174 np->an_enable = 2;
175 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
176 strcmp (media[card_idx], "4") == 0) {
177 np->speed = 100;
178 np->full_duplex = 1;
179 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
180 strcmp (media[card_idx], "3") == 0) {
181 np->speed = 100;
182 np->full_duplex = 0;
183 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
184 strcmp (media[card_idx], "2") == 0) {
185 np->speed = 10;
186 np->full_duplex = 1;
187 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
188 strcmp (media[card_idx], "1") == 0) {
189 np->speed = 10;
190 np->full_duplex = 0;
191 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
192 strcmp (media[card_idx], "6") == 0) {
193 np->speed=1000;
194 np->full_duplex=1;
195 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
196 strcmp (media[card_idx], "5") == 0) {
197 np->speed = 1000;
198 np->full_duplex = 0;
199 } else {
200 np->an_enable = 1;
201 }
202 }
203 if (jumbo[card_idx] != 0) {
204 np->jumbo = 1;
205 dev->mtu = MAX_JUMBO;
206 } else {
207 np->jumbo = 0;
208 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
209 dev->mtu = mtu[card_idx];
210 }
211 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
212 vlan[card_idx] : 0;
213 if (rx_coalesce > 0 && rx_timeout > 0) {
214 np->rx_coalesce = rx_coalesce;
215 np->rx_timeout = rx_timeout;
216 np->coalesce = 1;
217 }
218 np->tx_flow = (tx_flow == 0) ? 0 : 1;
219 np->rx_flow = (rx_flow == 0) ? 0 : 1;
220
221 if (tx_coalesce < 1)
222 tx_coalesce = 1;
223 else if (tx_coalesce > TX_RING_SIZE-1)
224 tx_coalesce = TX_RING_SIZE - 1;
225 }
226 dev->netdev_ops = &netdev_ops;
227 dev->watchdog_timeo = TX_TIMEOUT;
228 dev->ethtool_ops = ðtool_ops;
229 #if 0
230 dev->features = NETIF_F_IP_CSUM;
231 #endif
232 /* MTU range: 68 - 1536 or 8000 */
233 dev->min_mtu = ETH_MIN_MTU;
234 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
235
236 pci_set_drvdata (pdev, dev);
237
238 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
239 GFP_KERNEL);
240 if (!ring_space)
241 goto err_out_iounmap;
242 np->tx_ring = ring_space;
243 np->tx_ring_dma = ring_dma;
244
245 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
246 GFP_KERNEL);
247 if (!ring_space)
248 goto err_out_unmap_tx;
249 np->rx_ring = ring_space;
250 np->rx_ring_dma = ring_dma;
251
252 /* Parse eeprom data */
253 parse_eeprom (dev);
254
255 /* Find PHY address */
256 err = find_miiphy (dev);
257 if (err)
258 goto err_out_unmap_rx;
259
260 /* Fiber device? */
261 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
262 np->link_status = 0;
263 /* Set media and reset PHY */
264 if (np->phy_media) {
265 /* default Auto-Negotiation for fiber deivices */
266 if (np->an_enable == 2) {
267 np->an_enable = 1;
268 }
269 } else {
270 /* Auto-Negotiation is mandatory for 1000BASE-T,
271 IEEE 802.3ab Annex 28D page 14 */
272 if (np->speed == 1000)
273 np->an_enable = 1;
274 }
275
276 err = register_netdev (dev);
277 if (err)
278 goto err_out_unmap_rx;
279
280 card_idx++;
281
282 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
283 dev->name, np->name, dev->dev_addr, irq);
284 if (tx_coalesce > 1)
285 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
286 tx_coalesce);
287 if (np->coalesce)
288 printk(KERN_INFO
289 "rx_coalesce:\t%d packets\n"
290 "rx_timeout: \t%d ns\n",
291 np->rx_coalesce, np->rx_timeout*640);
292 if (np->vlan)
293 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
294 return 0;
295
296 err_out_unmap_rx:
297 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
298 np->rx_ring_dma);
299 err_out_unmap_tx:
300 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
301 np->tx_ring_dma);
302 err_out_iounmap:
303 if (np->rmon_enable)
304 pci_iounmap(pdev, np->ioaddr);
305 pci_iounmap(pdev, np->eeprom_addr);
306 err_out_dev:
307 free_netdev (dev);
308 err_out_res:
309 pci_release_regions (pdev);
310 err_out_disable:
311 pci_disable_device (pdev);
312 return err;
313 }
314
315 static int
find_miiphy(struct net_device * dev)316 find_miiphy (struct net_device *dev)
317 {
318 struct netdev_private *np = netdev_priv(dev);
319 int i, phy_found = 0;
320
321 np->phy_addr = 1;
322
323 for (i = 31; i >= 0; i--) {
324 int mii_status = mii_read (dev, i, 1);
325 if (mii_status != 0xffff && mii_status != 0x0000) {
326 np->phy_addr = i;
327 phy_found++;
328 }
329 }
330 if (!phy_found) {
331 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
332 return -ENODEV;
333 }
334 return 0;
335 }
336
337 static int
parse_eeprom(struct net_device * dev)338 parse_eeprom (struct net_device *dev)
339 {
340 struct netdev_private *np = netdev_priv(dev);
341 void __iomem *ioaddr = np->ioaddr;
342 int i, j;
343 u8 sromdata[256];
344 u8 *psib;
345 u32 crc;
346 PSROM_t psrom = (PSROM_t) sromdata;
347
348 int cid, next;
349
350 for (i = 0; i < 128; i++)
351 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
352
353 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
354 /* Check CRC */
355 crc = ~ether_crc_le (256 - 4, sromdata);
356 if (psrom->crc != cpu_to_le32(crc)) {
357 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
358 dev->name);
359 return -1;
360 }
361 }
362
363 /* Set MAC address */
364 eth_hw_addr_set(dev, psrom->mac_addr);
365
366 if (np->chip_id == CHIP_IP1000A) {
367 np->led_mode = le16_to_cpu(psrom->led_mode);
368 return 0;
369 }
370
371 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
372 return 0;
373 }
374
375 /* Parse Software Information Block */
376 i = 0x30;
377 psib = (u8 *) sromdata;
378 do {
379 cid = psib[i++];
380 next = psib[i++];
381 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
382 printk (KERN_ERR "Cell data error\n");
383 return -1;
384 }
385 switch (cid) {
386 case 0: /* Format version */
387 break;
388 case 1: /* End of cell */
389 return 0;
390 case 2: /* Duplex Polarity */
391 np->duplex_polarity = psib[i];
392 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
393 break;
394 case 3: /* Wake Polarity */
395 np->wake_polarity = psib[i];
396 break;
397 case 9: /* Adapter description */
398 j = (next - i > 255) ? 255 : next - i;
399 memcpy (np->name, &(psib[i]), j);
400 break;
401 case 4:
402 case 5:
403 case 6:
404 case 7:
405 case 8: /* Reversed */
406 break;
407 default: /* Unknown cell */
408 return -1;
409 }
410 i = next;
411 } while (1);
412
413 return 0;
414 }
415
rio_set_led_mode(struct net_device * dev)416 static void rio_set_led_mode(struct net_device *dev)
417 {
418 struct netdev_private *np = netdev_priv(dev);
419 void __iomem *ioaddr = np->ioaddr;
420 u32 mode;
421
422 if (np->chip_id != CHIP_IP1000A)
423 return;
424
425 mode = dr32(ASICCtrl);
426 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
427
428 if (np->led_mode & 0x01)
429 mode |= IPG_AC_LED_MODE;
430 if (np->led_mode & 0x02)
431 mode |= IPG_AC_LED_MODE_BIT_1;
432 if (np->led_mode & 0x08)
433 mode |= IPG_AC_LED_SPEED;
434
435 dw32(ASICCtrl, mode);
436 }
437
desc_to_dma(struct netdev_desc * desc)438 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
439 {
440 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
441 }
442
free_list(struct net_device * dev)443 static void free_list(struct net_device *dev)
444 {
445 struct netdev_private *np = netdev_priv(dev);
446 struct sk_buff *skb;
447 int i;
448
449 /* Free all the skbuffs in the queue. */
450 for (i = 0; i < RX_RING_SIZE; i++) {
451 skb = np->rx_skbuff[i];
452 if (skb) {
453 dma_unmap_single(&np->pdev->dev,
454 desc_to_dma(&np->rx_ring[i]),
455 skb->len, DMA_FROM_DEVICE);
456 dev_kfree_skb(skb);
457 np->rx_skbuff[i] = NULL;
458 }
459 np->rx_ring[i].status = 0;
460 np->rx_ring[i].fraginfo = 0;
461 }
462 for (i = 0; i < TX_RING_SIZE; i++) {
463 skb = np->tx_skbuff[i];
464 if (skb) {
465 dma_unmap_single(&np->pdev->dev,
466 desc_to_dma(&np->tx_ring[i]),
467 skb->len, DMA_TO_DEVICE);
468 dev_kfree_skb(skb);
469 np->tx_skbuff[i] = NULL;
470 }
471 }
472 }
473
rio_reset_ring(struct netdev_private * np)474 static void rio_reset_ring(struct netdev_private *np)
475 {
476 int i;
477
478 np->cur_rx = 0;
479 np->cur_tx = 0;
480 np->old_rx = 0;
481 np->old_tx = 0;
482
483 for (i = 0; i < TX_RING_SIZE; i++)
484 np->tx_ring[i].status = cpu_to_le64(TFDDone);
485
486 for (i = 0; i < RX_RING_SIZE; i++)
487 np->rx_ring[i].status = 0;
488 }
489
490 /* allocate and initialize Tx and Rx descriptors */
alloc_list(struct net_device * dev)491 static int alloc_list(struct net_device *dev)
492 {
493 struct netdev_private *np = netdev_priv(dev);
494 int i;
495
496 rio_reset_ring(np);
497 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
498
499 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
500 for (i = 0; i < TX_RING_SIZE; i++) {
501 np->tx_skbuff[i] = NULL;
502 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
503 ((i + 1) % TX_RING_SIZE) *
504 sizeof(struct netdev_desc));
505 }
506
507 /* Initialize Rx descriptors & allocate buffers */
508 for (i = 0; i < RX_RING_SIZE; i++) {
509 /* Allocated fixed size of skbuff */
510 struct sk_buff *skb;
511
512 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
513 np->rx_skbuff[i] = skb;
514 if (!skb) {
515 free_list(dev);
516 return -ENOMEM;
517 }
518
519 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
520 ((i + 1) % RX_RING_SIZE) *
521 sizeof(struct netdev_desc));
522 /* Rubicon now supports 40 bits of addressing space. */
523 np->rx_ring[i].fraginfo =
524 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
525 np->rx_buf_sz, DMA_FROM_DEVICE));
526 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
527 }
528
529 return 0;
530 }
531
rio_hw_init(struct net_device * dev)532 static void rio_hw_init(struct net_device *dev)
533 {
534 struct netdev_private *np = netdev_priv(dev);
535 void __iomem *ioaddr = np->ioaddr;
536 int i;
537 u16 macctrl;
538
539 /* Reset all logic functions */
540 dw16(ASICCtrl + 2,
541 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
542 mdelay(10);
543
544 rio_set_led_mode(dev);
545
546 /* DebugCtrl bit 4, 5, 9 must set */
547 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
548
549 if (np->chip_id == CHIP_IP1000A &&
550 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
551 /* PHY magic taken from ipg driver, undocumented registers */
552 mii_write(dev, np->phy_addr, 31, 0x0001);
553 mii_write(dev, np->phy_addr, 27, 0x01e0);
554 mii_write(dev, np->phy_addr, 31, 0x0002);
555 mii_write(dev, np->phy_addr, 27, 0xeb8e);
556 mii_write(dev, np->phy_addr, 31, 0x0000);
557 mii_write(dev, np->phy_addr, 30, 0x005e);
558 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
559 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
560 }
561
562 if (np->phy_media)
563 mii_set_media_pcs(dev);
564 else
565 mii_set_media(dev);
566
567 /* Jumbo frame */
568 if (np->jumbo != 0)
569 dw16(MaxFrameSize, MAX_JUMBO+14);
570
571 /* Set RFDListPtr */
572 dw32(RFDListPtr0, np->rx_ring_dma);
573 dw32(RFDListPtr1, 0);
574
575 /* Set station address */
576 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
577 * too. However, it doesn't work on IP1000A so we use 16-bit access.
578 */
579 for (i = 0; i < 3; i++)
580 dw16(StationAddr0 + 2 * i, get_unaligned_le16(&dev->dev_addr[2 * i]));
581
582 set_multicast (dev);
583 if (np->coalesce) {
584 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
585 }
586 /* Set RIO to poll every N*320nsec. */
587 dw8(RxDMAPollPeriod, 0x20);
588 dw8(TxDMAPollPeriod, 0xff);
589 dw8(RxDMABurstThresh, 0x30);
590 dw8(RxDMAUrgentThresh, 0x30);
591 if (!np->rmon_enable)
592 dw32(RmonStatMask, 0x0007ffff);
593 /* clear statistics */
594 clear_stats (dev);
595
596 /* VLAN supported */
597 if (np->vlan) {
598 /* priority field in RxDMAIntCtrl */
599 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
600 /* VLANId */
601 dw16(VLANId, np->vlan);
602 /* Length/Type should be 0x8100 */
603 dw32(VLANTag, 0x8100 << 16 | np->vlan);
604 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
605 VLAN information tagged by TFC' VID, CFI fields. */
606 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
607 }
608
609 /* Start Tx/Rx */
610 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
611
612 macctrl = 0;
613 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
614 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
615 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
616 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
617 dw16(MACCtrl, macctrl);
618 }
619
rio_hw_stop(struct net_device * dev)620 static void rio_hw_stop(struct net_device *dev)
621 {
622 struct netdev_private *np = netdev_priv(dev);
623 void __iomem *ioaddr = np->ioaddr;
624
625 /* Disable interrupts */
626 dw16(IntEnable, 0);
627
628 /* Stop Tx and Rx logics */
629 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
630 }
631
rio_open(struct net_device * dev)632 static int rio_open(struct net_device *dev)
633 {
634 struct netdev_private *np = netdev_priv(dev);
635 const int irq = np->pdev->irq;
636 int i;
637
638 i = alloc_list(dev);
639 if (i)
640 return i;
641
642 rio_hw_init(dev);
643
644 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
645 if (i) {
646 rio_hw_stop(dev);
647 free_list(dev);
648 return i;
649 }
650
651 timer_setup(&np->timer, rio_timer, 0);
652 np->timer.expires = jiffies + 1 * HZ;
653 add_timer(&np->timer);
654
655 netif_start_queue (dev);
656
657 dl2k_enable_int(np);
658 return 0;
659 }
660
661 static void
rio_timer(struct timer_list * t)662 rio_timer (struct timer_list *t)
663 {
664 struct netdev_private *np = timer_container_of(np, t, timer);
665 struct net_device *dev = pci_get_drvdata(np->pdev);
666 unsigned int entry;
667 int next_tick = 1*HZ;
668 unsigned long flags;
669
670 spin_lock_irqsave(&np->rx_lock, flags);
671 /* Recover rx ring exhausted error */
672 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
673 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
674 /* Re-allocate skbuffs to fill the descriptor ring */
675 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
676 struct sk_buff *skb;
677 entry = np->old_rx % RX_RING_SIZE;
678 /* Dropped packets don't need to re-allocate */
679 if (np->rx_skbuff[entry] == NULL) {
680 skb = netdev_alloc_skb_ip_align(dev,
681 np->rx_buf_sz);
682 if (skb == NULL) {
683 np->rx_ring[entry].fraginfo = 0;
684 printk (KERN_INFO
685 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
686 dev->name, entry);
687 break;
688 }
689 np->rx_skbuff[entry] = skb;
690 np->rx_ring[entry].fraginfo =
691 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
692 np->rx_buf_sz, DMA_FROM_DEVICE));
693 }
694 np->rx_ring[entry].fraginfo |=
695 cpu_to_le64((u64)np->rx_buf_sz << 48);
696 np->rx_ring[entry].status = 0;
697 } /* end for */
698 } /* end if */
699 spin_unlock_irqrestore (&np->rx_lock, flags);
700 np->timer.expires = jiffies + next_tick;
701 add_timer(&np->timer);
702 }
703
704 static void
rio_tx_timeout(struct net_device * dev,unsigned int txqueue)705 rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
706 {
707 struct netdev_private *np = netdev_priv(dev);
708 void __iomem *ioaddr = np->ioaddr;
709
710 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
711 dev->name, dr32(TxStatus));
712 rio_free_tx(dev, 0);
713 dev->if_port = 0;
714 netif_trans_update(dev); /* prevent tx timeout */
715 }
716
717 static netdev_tx_t
start_xmit(struct sk_buff * skb,struct net_device * dev)718 start_xmit (struct sk_buff *skb, struct net_device *dev)
719 {
720 struct netdev_private *np = netdev_priv(dev);
721 void __iomem *ioaddr = np->ioaddr;
722 struct netdev_desc *txdesc;
723 unsigned entry;
724 u64 tfc_vlan_tag = 0;
725
726 if (np->link_status == 0) { /* Link Down */
727 dev_kfree_skb(skb);
728 return NETDEV_TX_OK;
729 }
730 entry = np->cur_tx % TX_RING_SIZE;
731 np->tx_skbuff[entry] = skb;
732 txdesc = &np->tx_ring[entry];
733
734 #if 0
735 if (skb->ip_summed == CHECKSUM_PARTIAL) {
736 txdesc->status |=
737 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
738 IPChecksumEnable);
739 }
740 #endif
741 if (np->vlan) {
742 tfc_vlan_tag = VLANTagInsert |
743 ((u64)np->vlan << 32) |
744 ((u64)skb->priority << 45);
745 }
746 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
747 skb->len, DMA_TO_DEVICE));
748 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
749
750 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
751 * Work around: Always use 1 descriptor in 10Mbps mode */
752 if (entry % np->tx_coalesce == 0 || np->speed == 10)
753 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
754 WordAlignDisable |
755 TxDMAIndicate |
756 (1 << FragCountShift));
757 else
758 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
759 WordAlignDisable |
760 (1 << FragCountShift));
761
762 /* TxDMAPollNow */
763 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
764 /* Schedule ISR */
765 dw32(CountDown, 10000);
766 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
767 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
768 < TX_QUEUE_LEN - 1 && np->speed != 10) {
769 /* do nothing */
770 } else if (!netif_queue_stopped(dev)) {
771 netif_stop_queue (dev);
772 }
773
774 /* The first TFDListPtr */
775 if (!dr32(TFDListPtr0)) {
776 dw32(TFDListPtr0, np->tx_ring_dma +
777 entry * sizeof (struct netdev_desc));
778 dw32(TFDListPtr1, 0);
779 }
780
781 return NETDEV_TX_OK;
782 }
783
784 static irqreturn_t
rio_interrupt(int irq,void * dev_instance)785 rio_interrupt (int irq, void *dev_instance)
786 {
787 struct net_device *dev = dev_instance;
788 struct netdev_private *np = netdev_priv(dev);
789 void __iomem *ioaddr = np->ioaddr;
790 unsigned int_status;
791 int cnt = max_intrloop;
792 int handled = 0;
793
794 while (1) {
795 int_status = dr16(IntStatus);
796 dw16(IntStatus, int_status);
797 int_status &= DEFAULT_INTR;
798 if (int_status == 0 || --cnt < 0)
799 break;
800 handled = 1;
801 /* Processing received packets */
802 if (int_status & RxDMAComplete)
803 receive_packet (dev);
804 /* TxDMAComplete interrupt */
805 if ((int_status & (TxDMAComplete|IntRequested))) {
806 int tx_status;
807 tx_status = dr32(TxStatus);
808 if (tx_status & 0x01)
809 tx_error (dev, tx_status);
810 /* Free used tx skbuffs */
811 rio_free_tx (dev, 1);
812 }
813
814 /* Handle uncommon events */
815 if (int_status &
816 (HostError | LinkEvent | UpdateStats))
817 rio_error (dev, int_status);
818 }
819 if (np->cur_tx != np->old_tx)
820 dw32(CountDown, 100);
821 return IRQ_RETVAL(handled);
822 }
823
824 static void
rio_free_tx(struct net_device * dev,int irq)825 rio_free_tx (struct net_device *dev, int irq)
826 {
827 struct netdev_private *np = netdev_priv(dev);
828 int entry = np->old_tx % TX_RING_SIZE;
829 unsigned long flag = 0;
830
831 if (irq)
832 spin_lock(&np->tx_lock);
833 else
834 spin_lock_irqsave(&np->tx_lock, flag);
835
836 /* Free used tx skbuffs */
837 while (entry != np->cur_tx) {
838 struct sk_buff *skb;
839
840 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
841 break;
842 skb = np->tx_skbuff[entry];
843 dma_unmap_single(&np->pdev->dev,
844 desc_to_dma(&np->tx_ring[entry]), skb->len,
845 DMA_TO_DEVICE);
846 if (irq)
847 dev_consume_skb_irq(skb);
848 else
849 dev_kfree_skb(skb);
850
851 np->tx_skbuff[entry] = NULL;
852 entry = (entry + 1) % TX_RING_SIZE;
853 }
854 if (irq)
855 spin_unlock(&np->tx_lock);
856 else
857 spin_unlock_irqrestore(&np->tx_lock, flag);
858 np->old_tx = entry;
859
860 /* If the ring is no longer full, clear tx_full and
861 call netif_wake_queue() */
862
863 if (netif_queue_stopped(dev) &&
864 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
865 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
866 netif_wake_queue (dev);
867 }
868 }
869
870 static void
tx_error(struct net_device * dev,int tx_status)871 tx_error (struct net_device *dev, int tx_status)
872 {
873 struct netdev_private *np = netdev_priv(dev);
874 void __iomem *ioaddr = np->ioaddr;
875 int frame_id;
876 int i;
877
878 frame_id = (tx_status & 0xffff0000);
879 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
880 dev->name, tx_status, frame_id);
881 /* Ttransmit Underrun */
882 if (tx_status & 0x10) {
883 dev->stats.tx_fifo_errors++;
884 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
885 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
886 dw16(ASICCtrl + 2,
887 TxReset | DMAReset | FIFOReset | NetworkReset);
888 /* Wait for ResetBusy bit clear */
889 for (i = 50; i > 0; i--) {
890 if (!(dr16(ASICCtrl + 2) & ResetBusy))
891 break;
892 mdelay (1);
893 }
894 rio_set_led_mode(dev);
895 rio_free_tx (dev, 1);
896 /* Reset TFDListPtr */
897 dw32(TFDListPtr0, np->tx_ring_dma +
898 np->old_tx * sizeof (struct netdev_desc));
899 dw32(TFDListPtr1, 0);
900
901 /* Let TxStartThresh stay default value */
902 }
903 /* Late Collision */
904 if (tx_status & 0x04) {
905 dev->stats.tx_fifo_errors++;
906 /* TxReset and clear FIFO */
907 dw16(ASICCtrl + 2, TxReset | FIFOReset);
908 /* Wait reset done */
909 for (i = 50; i > 0; i--) {
910 if (!(dr16(ASICCtrl + 2) & ResetBusy))
911 break;
912 mdelay (1);
913 }
914 rio_set_led_mode(dev);
915 /* Let TxStartThresh stay default value */
916 }
917
918 spin_lock(&np->stats_lock);
919 /* Maximum Collisions */
920 if (tx_status & 0x08)
921 dev->stats.collisions++;
922
923 dev->stats.tx_errors++;
924 spin_unlock(&np->stats_lock);
925
926 /* Restart the Tx */
927 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
928 }
929
930 static int
receive_packet(struct net_device * dev)931 receive_packet (struct net_device *dev)
932 {
933 struct netdev_private *np = netdev_priv(dev);
934 int entry = np->cur_rx % RX_RING_SIZE;
935 int cnt = 30;
936
937 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
938 while (1) {
939 struct netdev_desc *desc = &np->rx_ring[entry];
940 int pkt_len;
941 u64 frame_status;
942
943 if (!(desc->status & cpu_to_le64(RFDDone)) ||
944 !(desc->status & cpu_to_le64(FrameStart)) ||
945 !(desc->status & cpu_to_le64(FrameEnd)))
946 break;
947
948 /* Chip omits the CRC. */
949 frame_status = le64_to_cpu(desc->status);
950 pkt_len = frame_status & 0xffff;
951 if (--cnt < 0)
952 break;
953 /* Update rx error statistics, drop packet. */
954 if (frame_status & RFS_Errors) {
955 dev->stats.rx_errors++;
956 if (frame_status & (RxRuntFrame | RxLengthError))
957 dev->stats.rx_length_errors++;
958 if (frame_status & RxFCSError)
959 dev->stats.rx_crc_errors++;
960 if (frame_status & RxAlignmentError && np->speed != 1000)
961 dev->stats.rx_frame_errors++;
962 if (frame_status & RxFIFOOverrun)
963 dev->stats.rx_fifo_errors++;
964 } else {
965 struct sk_buff *skb;
966
967 skb = NULL;
968 /* Small skbuffs for short packets */
969 if (pkt_len <= copy_thresh)
970 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
971 if (!skb) {
972 dma_unmap_single(&np->pdev->dev,
973 desc_to_dma(desc),
974 np->rx_buf_sz,
975 DMA_FROM_DEVICE);
976 skb_put (skb = np->rx_skbuff[entry], pkt_len);
977 np->rx_skbuff[entry] = NULL;
978 } else {
979 dma_sync_single_for_cpu(&np->pdev->dev,
980 desc_to_dma(desc),
981 np->rx_buf_sz,
982 DMA_FROM_DEVICE);
983 skb_copy_to_linear_data (skb,
984 np->rx_skbuff[entry]->data,
985 pkt_len);
986 skb_put (skb, pkt_len);
987 dma_sync_single_for_device(&np->pdev->dev,
988 desc_to_dma(desc),
989 np->rx_buf_sz,
990 DMA_FROM_DEVICE);
991 }
992 skb->protocol = eth_type_trans (skb, dev);
993 #if 0
994 /* Checksum done by hw, but csum value unavailable. */
995 if (np->pdev->pci_rev_id >= 0x0c &&
996 !(frame_status & (TCPError | UDPError | IPError))) {
997 skb->ip_summed = CHECKSUM_UNNECESSARY;
998 }
999 #endif
1000 netif_rx (skb);
1001 }
1002 entry = (entry + 1) % RX_RING_SIZE;
1003 }
1004 spin_lock(&np->rx_lock);
1005 np->cur_rx = entry;
1006 /* Re-allocate skbuffs to fill the descriptor ring */
1007 entry = np->old_rx;
1008 while (entry != np->cur_rx) {
1009 struct sk_buff *skb;
1010 /* Dropped packets don't need to re-allocate */
1011 if (np->rx_skbuff[entry] == NULL) {
1012 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
1013 if (skb == NULL) {
1014 np->rx_ring[entry].fraginfo = 0;
1015 printk (KERN_INFO
1016 "%s: receive_packet: "
1017 "Unable to re-allocate Rx skbuff.#%d\n",
1018 dev->name, entry);
1019 break;
1020 }
1021 np->rx_skbuff[entry] = skb;
1022 np->rx_ring[entry].fraginfo =
1023 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
1024 np->rx_buf_sz, DMA_FROM_DEVICE));
1025 }
1026 np->rx_ring[entry].fraginfo |=
1027 cpu_to_le64((u64)np->rx_buf_sz << 48);
1028 np->rx_ring[entry].status = 0;
1029 entry = (entry + 1) % RX_RING_SIZE;
1030 }
1031 np->old_rx = entry;
1032 spin_unlock(&np->rx_lock);
1033 return 0;
1034 }
1035
1036 static void
rio_error(struct net_device * dev,int int_status)1037 rio_error (struct net_device *dev, int int_status)
1038 {
1039 struct netdev_private *np = netdev_priv(dev);
1040 void __iomem *ioaddr = np->ioaddr;
1041 u16 macctrl;
1042
1043 /* Link change event */
1044 if (int_status & LinkEvent) {
1045 if (mii_wait_link (dev, 10) == 0) {
1046 printk (KERN_INFO "%s: Link up\n", dev->name);
1047 if (np->phy_media)
1048 mii_get_media_pcs (dev);
1049 else
1050 mii_get_media (dev);
1051 if (np->speed == 1000)
1052 np->tx_coalesce = tx_coalesce;
1053 else
1054 np->tx_coalesce = 1;
1055 macctrl = 0;
1056 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1057 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1058 macctrl |= (np->tx_flow) ?
1059 TxFlowControlEnable : 0;
1060 macctrl |= (np->rx_flow) ?
1061 RxFlowControlEnable : 0;
1062 dw16(MACCtrl, macctrl);
1063 np->link_status = 1;
1064 netif_carrier_on(dev);
1065 } else {
1066 printk (KERN_INFO "%s: Link off\n", dev->name);
1067 np->link_status = 0;
1068 netif_carrier_off(dev);
1069 }
1070 }
1071
1072 /* UpdateStats statistics registers */
1073 if (int_status & UpdateStats) {
1074 get_stats (dev);
1075 }
1076
1077 /* PCI Error, a catastronphic error related to the bus interface
1078 occurs, set GlobalReset and HostReset to reset. */
1079 if (int_status & HostError) {
1080 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1081 dev->name, int_status);
1082 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1083 mdelay (500);
1084 rio_set_led_mode(dev);
1085 }
1086 }
1087
1088 static struct net_device_stats *
get_stats(struct net_device * dev)1089 get_stats (struct net_device *dev)
1090 {
1091 struct netdev_private *np = netdev_priv(dev);
1092 void __iomem *ioaddr = np->ioaddr;
1093 unsigned int stat_reg;
1094 unsigned long flags;
1095
1096 spin_lock_irqsave(&np->stats_lock, flags);
1097 /* All statistics registers need to be acknowledged,
1098 else statistic overflow could cause problems */
1099
1100 dev->stats.rx_packets += dr32(FramesRcvOk);
1101 dev->stats.tx_packets += dr32(FramesXmtOk);
1102 dev->stats.rx_bytes += dr32(OctetRcvOk);
1103 dev->stats.tx_bytes += dr32(OctetXmtOk);
1104
1105 dev->stats.multicast += dr32(McstFramesRcvdOk);
1106 dev->stats.collisions += dr32(SingleColFrames)
1107 + dr32(MultiColFrames);
1108
1109 /* detailed tx errors */
1110 stat_reg = dr16(FramesAbortXSColls);
1111 dev->stats.tx_aborted_errors += stat_reg;
1112 dev->stats.tx_errors += stat_reg;
1113
1114 stat_reg = dr16(CarrierSenseErrors);
1115 dev->stats.tx_carrier_errors += stat_reg;
1116 dev->stats.tx_errors += stat_reg;
1117
1118 /* Clear all other statistic register. */
1119 dr32(McstOctetXmtOk);
1120 dr16(BcstFramesXmtdOk);
1121 dr32(McstFramesXmtdOk);
1122 dr16(BcstFramesRcvdOk);
1123 dr16(MacControlFramesRcvd);
1124 dr16(FrameTooLongErrors);
1125 dr16(InRangeLengthErrors);
1126 dr16(FramesCheckSeqErrors);
1127 dr16(FramesLostRxErrors);
1128 dr32(McstOctetXmtOk);
1129 dr32(BcstOctetXmtOk);
1130 dr32(McstFramesXmtdOk);
1131 dr32(FramesWDeferredXmt);
1132 dr32(LateCollisions);
1133 dr16(BcstFramesXmtdOk);
1134 dr16(MacControlFramesXmtd);
1135 dr16(FramesWEXDeferal);
1136
1137 if (np->rmon_enable)
1138 for (int i = 0x100; i <= 0x150; i += 4)
1139 dr32(i);
1140
1141 dr16(TxJumboFrames);
1142 dr16(RxJumboFrames);
1143 dr16(TCPCheckSumErrors);
1144 dr16(UDPCheckSumErrors);
1145 dr16(IPCheckSumErrors);
1146
1147 spin_unlock_irqrestore(&np->stats_lock, flags);
1148
1149 return &dev->stats;
1150 }
1151
1152 static int
clear_stats(struct net_device * dev)1153 clear_stats (struct net_device *dev)
1154 {
1155 struct netdev_private *np = netdev_priv(dev);
1156 void __iomem *ioaddr = np->ioaddr;
1157
1158 /* All statistics registers need to be acknowledged,
1159 else statistic overflow could cause problems */
1160 dr32(FramesRcvOk);
1161 dr32(FramesXmtOk);
1162 dr32(OctetRcvOk);
1163 dr32(OctetXmtOk);
1164
1165 dr32(McstFramesRcvdOk);
1166 dr32(SingleColFrames);
1167 dr32(MultiColFrames);
1168 dr32(LateCollisions);
1169 /* detailed rx errors */
1170 dr16(FrameTooLongErrors);
1171 dr16(InRangeLengthErrors);
1172 dr16(FramesCheckSeqErrors);
1173 dr16(FramesLostRxErrors);
1174
1175 /* detailed tx errors */
1176 dr16(FramesAbortXSColls);
1177 dr16(CarrierSenseErrors);
1178
1179 /* Clear all other statistic register. */
1180 dr32(McstOctetXmtOk);
1181 dr16(BcstFramesXmtdOk);
1182 dr32(McstFramesXmtdOk);
1183 dr16(BcstFramesRcvdOk);
1184 dr16(MacControlFramesRcvd);
1185 dr32(McstOctetXmtOk);
1186 dr32(BcstOctetXmtOk);
1187 dr32(McstFramesXmtdOk);
1188 dr32(FramesWDeferredXmt);
1189 dr16(BcstFramesXmtdOk);
1190 dr16(MacControlFramesXmtd);
1191 dr16(FramesWEXDeferal);
1192 if (np->rmon_enable)
1193 for (int i = 0x100; i <= 0x150; i += 4)
1194 dr32(i);
1195 dr16(TxJumboFrames);
1196 dr16(RxJumboFrames);
1197 dr16(TCPCheckSumErrors);
1198 dr16(UDPCheckSumErrors);
1199 dr16(IPCheckSumErrors);
1200 return 0;
1201 }
1202
1203 static void
set_multicast(struct net_device * dev)1204 set_multicast (struct net_device *dev)
1205 {
1206 struct netdev_private *np = netdev_priv(dev);
1207 void __iomem *ioaddr = np->ioaddr;
1208 u32 hash_table[2];
1209 u16 rx_mode = 0;
1210
1211 hash_table[0] = hash_table[1] = 0;
1212 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1213 hash_table[1] |= 0x02000000;
1214 if (dev->flags & IFF_PROMISC) {
1215 /* Receive all frames promiscuously. */
1216 rx_mode = ReceiveAllFrames;
1217 } else if ((dev->flags & IFF_ALLMULTI) ||
1218 (netdev_mc_count(dev) > multicast_filter_limit)) {
1219 /* Receive broadcast and multicast frames */
1220 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1221 } else if (!netdev_mc_empty(dev)) {
1222 struct netdev_hw_addr *ha;
1223 /* Receive broadcast frames and multicast frames filtering
1224 by Hashtable */
1225 rx_mode =
1226 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1227 netdev_for_each_mc_addr(ha, dev) {
1228 int bit, index = 0;
1229 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1230 /* The inverted high significant 6 bits of CRC are
1231 used as an index to hashtable */
1232 for (bit = 0; bit < 6; bit++)
1233 if (crc & (1 << (31 - bit)))
1234 index |= (1 << bit);
1235 hash_table[index / 32] |= (1 << (index % 32));
1236 }
1237 } else {
1238 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1239 }
1240 if (np->vlan) {
1241 /* ReceiveVLANMatch field in ReceiveMode */
1242 rx_mode |= ReceiveVLANMatch;
1243 }
1244
1245 dw32(HashTable0, hash_table[0]);
1246 dw32(HashTable1, hash_table[1]);
1247 dw16(ReceiveMode, rx_mode);
1248 }
1249
rio_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1250 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1251 {
1252 struct netdev_private *np = netdev_priv(dev);
1253
1254 strscpy(info->driver, "dl2k", sizeof(info->driver));
1255 strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1256 }
1257
rio_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1258 static int rio_get_link_ksettings(struct net_device *dev,
1259 struct ethtool_link_ksettings *cmd)
1260 {
1261 struct netdev_private *np = netdev_priv(dev);
1262 u32 supported, advertising;
1263
1264 if (np->phy_media) {
1265 /* fiber device */
1266 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1267 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1268 cmd->base.port = PORT_FIBRE;
1269 } else {
1270 /* copper device */
1271 supported = SUPPORTED_10baseT_Half |
1272 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1273 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1274 SUPPORTED_Autoneg | SUPPORTED_MII;
1275 advertising = ADVERTISED_10baseT_Half |
1276 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1277 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1278 ADVERTISED_Autoneg | ADVERTISED_MII;
1279 cmd->base.port = PORT_MII;
1280 }
1281 if (np->link_status) {
1282 cmd->base.speed = np->speed;
1283 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1284 } else {
1285 cmd->base.speed = SPEED_UNKNOWN;
1286 cmd->base.duplex = DUPLEX_UNKNOWN;
1287 }
1288 if (np->an_enable)
1289 cmd->base.autoneg = AUTONEG_ENABLE;
1290 else
1291 cmd->base.autoneg = AUTONEG_DISABLE;
1292
1293 cmd->base.phy_address = np->phy_addr;
1294
1295 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1296 supported);
1297 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1298 advertising);
1299
1300 return 0;
1301 }
1302
rio_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1303 static int rio_set_link_ksettings(struct net_device *dev,
1304 const struct ethtool_link_ksettings *cmd)
1305 {
1306 struct netdev_private *np = netdev_priv(dev);
1307 u32 speed = cmd->base.speed;
1308 u8 duplex = cmd->base.duplex;
1309
1310 netif_carrier_off(dev);
1311 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1312 if (np->an_enable) {
1313 return 0;
1314 } else {
1315 np->an_enable = 1;
1316 mii_set_media(dev);
1317 return 0;
1318 }
1319 } else {
1320 np->an_enable = 0;
1321 if (np->speed == 1000) {
1322 speed = SPEED_100;
1323 duplex = DUPLEX_FULL;
1324 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1325 }
1326 switch (speed) {
1327 case SPEED_10:
1328 np->speed = 10;
1329 np->full_duplex = (duplex == DUPLEX_FULL);
1330 break;
1331 case SPEED_100:
1332 np->speed = 100;
1333 np->full_duplex = (duplex == DUPLEX_FULL);
1334 break;
1335 case SPEED_1000: /* not supported */
1336 default:
1337 return -EINVAL;
1338 }
1339 mii_set_media(dev);
1340 }
1341 return 0;
1342 }
1343
rio_get_link(struct net_device * dev)1344 static u32 rio_get_link(struct net_device *dev)
1345 {
1346 struct netdev_private *np = netdev_priv(dev);
1347 return np->link_status;
1348 }
1349
1350 static const struct ethtool_ops ethtool_ops = {
1351 .get_drvinfo = rio_get_drvinfo,
1352 .get_link = rio_get_link,
1353 .get_link_ksettings = rio_get_link_ksettings,
1354 .set_link_ksettings = rio_set_link_ksettings,
1355 };
1356
1357 static int
rio_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1358 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1359 {
1360 int phy_addr;
1361 struct netdev_private *np = netdev_priv(dev);
1362 struct mii_ioctl_data *miidata = if_mii(rq);
1363
1364 phy_addr = np->phy_addr;
1365 switch (cmd) {
1366 case SIOCGMIIPHY:
1367 miidata->phy_id = phy_addr;
1368 break;
1369 case SIOCGMIIREG:
1370 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1371 break;
1372 case SIOCSMIIREG:
1373 if (!capable(CAP_NET_ADMIN))
1374 return -EPERM;
1375 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1376 break;
1377 default:
1378 return -EOPNOTSUPP;
1379 }
1380 return 0;
1381 }
1382
1383 #define EEP_READ 0x0200
1384 #define EEP_BUSY 0x8000
1385 /* Read the EEPROM word */
1386 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
read_eeprom(struct netdev_private * np,int eep_addr)1387 static int read_eeprom(struct netdev_private *np, int eep_addr)
1388 {
1389 void __iomem *ioaddr = np->eeprom_addr;
1390 int i = 1000;
1391
1392 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1393 while (i-- > 0) {
1394 if (!(dr16(EepromCtrl) & EEP_BUSY))
1395 return dr16(EepromData);
1396 }
1397 return 0;
1398 }
1399
1400 enum phy_ctrl_bits {
1401 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1402 MII_DUPLEX = 0x08,
1403 };
1404
1405 #define mii_delay() dr8(PhyCtrl)
1406 static void
mii_sendbit(struct net_device * dev,u32 data)1407 mii_sendbit (struct net_device *dev, u32 data)
1408 {
1409 struct netdev_private *np = netdev_priv(dev);
1410 void __iomem *ioaddr = np->ioaddr;
1411
1412 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1413 dw8(PhyCtrl, data);
1414 mii_delay ();
1415 dw8(PhyCtrl, data | MII_CLK);
1416 mii_delay ();
1417 }
1418
1419 static int
mii_getbit(struct net_device * dev)1420 mii_getbit (struct net_device *dev)
1421 {
1422 struct netdev_private *np = netdev_priv(dev);
1423 void __iomem *ioaddr = np->ioaddr;
1424 u8 data;
1425
1426 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1427 dw8(PhyCtrl, data);
1428 mii_delay ();
1429 dw8(PhyCtrl, data | MII_CLK);
1430 mii_delay ();
1431 return (dr8(PhyCtrl) >> 1) & 1;
1432 }
1433
1434 static void
mii_send_bits(struct net_device * dev,u32 data,int len)1435 mii_send_bits (struct net_device *dev, u32 data, int len)
1436 {
1437 int i;
1438
1439 for (i = len - 1; i >= 0; i--) {
1440 mii_sendbit (dev, data & (1 << i));
1441 }
1442 }
1443
1444 static int
mii_read(struct net_device * dev,int phy_addr,int reg_num)1445 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1446 {
1447 u32 cmd;
1448 int i;
1449 u32 retval = 0;
1450
1451 /* Preamble */
1452 mii_send_bits (dev, 0xffffffff, 32);
1453 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1454 /* ST,OP = 0110'b for read operation */
1455 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1456 mii_send_bits (dev, cmd, 14);
1457 /* Turnaround */
1458 if (mii_getbit (dev))
1459 goto err_out;
1460 /* Read data */
1461 for (i = 0; i < 16; i++) {
1462 retval |= mii_getbit (dev);
1463 retval <<= 1;
1464 }
1465 /* End cycle */
1466 mii_getbit (dev);
1467 return (retval >> 1) & 0xffff;
1468
1469 err_out:
1470 return 0;
1471 }
1472 static int
mii_write(struct net_device * dev,int phy_addr,int reg_num,u16 data)1473 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1474 {
1475 u32 cmd;
1476
1477 /* Preamble */
1478 mii_send_bits (dev, 0xffffffff, 32);
1479 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1480 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1481 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1482 mii_send_bits (dev, cmd, 32);
1483 /* End cycle */
1484 mii_getbit (dev);
1485 return 0;
1486 }
1487 static int
mii_wait_link(struct net_device * dev,int wait)1488 mii_wait_link (struct net_device *dev, int wait)
1489 {
1490 __u16 bmsr;
1491 int phy_addr;
1492 struct netdev_private *np;
1493
1494 np = netdev_priv(dev);
1495 phy_addr = np->phy_addr;
1496
1497 do {
1498 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1499 if (bmsr & BMSR_LSTATUS)
1500 return 0;
1501 mdelay (1);
1502 } while (--wait > 0);
1503 return -1;
1504 }
1505 static int
mii_get_media(struct net_device * dev)1506 mii_get_media (struct net_device *dev)
1507 {
1508 __u16 negotiate;
1509 __u16 bmsr;
1510 __u16 mscr;
1511 __u16 mssr;
1512 int phy_addr;
1513 struct netdev_private *np;
1514
1515 np = netdev_priv(dev);
1516 phy_addr = np->phy_addr;
1517
1518 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1519 if (np->an_enable) {
1520 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1521 /* Auto-Negotiation not completed */
1522 return -1;
1523 }
1524 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1525 mii_read (dev, phy_addr, MII_LPA);
1526 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1527 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1528 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1529 np->speed = 1000;
1530 np->full_duplex = 1;
1531 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1532 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1533 np->speed = 1000;
1534 np->full_duplex = 0;
1535 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1536 } else if (negotiate & ADVERTISE_100FULL) {
1537 np->speed = 100;
1538 np->full_duplex = 1;
1539 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1540 } else if (negotiate & ADVERTISE_100HALF) {
1541 np->speed = 100;
1542 np->full_duplex = 0;
1543 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1544 } else if (negotiate & ADVERTISE_10FULL) {
1545 np->speed = 10;
1546 np->full_duplex = 1;
1547 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1548 } else if (negotiate & ADVERTISE_10HALF) {
1549 np->speed = 10;
1550 np->full_duplex = 0;
1551 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1552 }
1553 if (negotiate & ADVERTISE_PAUSE_CAP) {
1554 np->tx_flow &= 1;
1555 np->rx_flow &= 1;
1556 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1557 np->tx_flow = 0;
1558 np->rx_flow &= 1;
1559 }
1560 /* else tx_flow, rx_flow = user select */
1561 } else {
1562 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1563 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1564 case BMCR_SPEED1000:
1565 printk (KERN_INFO "Operating at 1000 Mbps, ");
1566 break;
1567 case BMCR_SPEED100:
1568 printk (KERN_INFO "Operating at 100 Mbps, ");
1569 break;
1570 case 0:
1571 printk (KERN_INFO "Operating at 10 Mbps, ");
1572 }
1573 if (bmcr & BMCR_FULLDPLX) {
1574 printk (KERN_CONT "Full duplex\n");
1575 } else {
1576 printk (KERN_CONT "Half duplex\n");
1577 }
1578 }
1579 if (np->tx_flow)
1580 printk(KERN_INFO "Enable Tx Flow Control\n");
1581 else
1582 printk(KERN_INFO "Disable Tx Flow Control\n");
1583 if (np->rx_flow)
1584 printk(KERN_INFO "Enable Rx Flow Control\n");
1585 else
1586 printk(KERN_INFO "Disable Rx Flow Control\n");
1587
1588 return 0;
1589 }
1590
1591 static int
mii_set_media(struct net_device * dev)1592 mii_set_media (struct net_device *dev)
1593 {
1594 __u16 pscr;
1595 __u16 bmcr;
1596 __u16 bmsr;
1597 __u16 anar;
1598 int phy_addr;
1599 struct netdev_private *np;
1600 np = netdev_priv(dev);
1601 phy_addr = np->phy_addr;
1602
1603 /* Does user set speed? */
1604 if (np->an_enable) {
1605 /* Advertise capabilities */
1606 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1607 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1608 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1609 ADVERTISE_100HALF | ADVERTISE_10HALF |
1610 ADVERTISE_100BASE4);
1611 if (bmsr & BMSR_100FULL)
1612 anar |= ADVERTISE_100FULL;
1613 if (bmsr & BMSR_100HALF)
1614 anar |= ADVERTISE_100HALF;
1615 if (bmsr & BMSR_100BASE4)
1616 anar |= ADVERTISE_100BASE4;
1617 if (bmsr & BMSR_10FULL)
1618 anar |= ADVERTISE_10FULL;
1619 if (bmsr & BMSR_10HALF)
1620 anar |= ADVERTISE_10HALF;
1621 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1622 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1623
1624 /* Enable Auto crossover */
1625 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1626 pscr |= 3 << 5; /* 11'b */
1627 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1628
1629 /* Soft reset PHY */
1630 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1631 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1632 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1633 mdelay(1);
1634 } else {
1635 /* Force speed setting */
1636 /* 1) Disable Auto crossover */
1637 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1638 pscr &= ~(3 << 5);
1639 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1640
1641 /* 2) PHY Reset */
1642 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1643 bmcr |= BMCR_RESET;
1644 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1645
1646 /* 3) Power Down */
1647 bmcr = 0x1940; /* must be 0x1940 */
1648 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1649 mdelay (100); /* wait a certain time */
1650
1651 /* 4) Advertise nothing */
1652 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1653
1654 /* 5) Set media and Power Up */
1655 bmcr = BMCR_PDOWN;
1656 if (np->speed == 100) {
1657 bmcr |= BMCR_SPEED100;
1658 printk (KERN_INFO "Manual 100 Mbps, ");
1659 } else if (np->speed == 10) {
1660 printk (KERN_INFO "Manual 10 Mbps, ");
1661 }
1662 if (np->full_duplex) {
1663 bmcr |= BMCR_FULLDPLX;
1664 printk (KERN_CONT "Full duplex\n");
1665 } else {
1666 printk (KERN_CONT "Half duplex\n");
1667 }
1668 #if 0
1669 /* Set 1000BaseT Master/Slave setting */
1670 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1671 mscr |= MII_MSCR_CFG_ENABLE;
1672 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1673 #endif
1674 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1675 mdelay(10);
1676 }
1677 return 0;
1678 }
1679
1680 static int
mii_get_media_pcs(struct net_device * dev)1681 mii_get_media_pcs (struct net_device *dev)
1682 {
1683 __u16 negotiate;
1684 __u16 bmsr;
1685 int phy_addr;
1686 struct netdev_private *np;
1687
1688 np = netdev_priv(dev);
1689 phy_addr = np->phy_addr;
1690
1691 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1692 if (np->an_enable) {
1693 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1694 /* Auto-Negotiation not completed */
1695 return -1;
1696 }
1697 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1698 mii_read (dev, phy_addr, PCS_ANLPAR);
1699 np->speed = 1000;
1700 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1701 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1702 np->full_duplex = 1;
1703 } else {
1704 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1705 np->full_duplex = 0;
1706 }
1707 if (negotiate & PCS_ANAR_PAUSE) {
1708 np->tx_flow &= 1;
1709 np->rx_flow &= 1;
1710 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1711 np->tx_flow = 0;
1712 np->rx_flow &= 1;
1713 }
1714 /* else tx_flow, rx_flow = user select */
1715 } else {
1716 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1717 printk (KERN_INFO "Operating at 1000 Mbps, ");
1718 if (bmcr & BMCR_FULLDPLX) {
1719 printk (KERN_CONT "Full duplex\n");
1720 } else {
1721 printk (KERN_CONT "Half duplex\n");
1722 }
1723 }
1724 if (np->tx_flow)
1725 printk(KERN_INFO "Enable Tx Flow Control\n");
1726 else
1727 printk(KERN_INFO "Disable Tx Flow Control\n");
1728 if (np->rx_flow)
1729 printk(KERN_INFO "Enable Rx Flow Control\n");
1730 else
1731 printk(KERN_INFO "Disable Rx Flow Control\n");
1732
1733 return 0;
1734 }
1735
1736 static int
mii_set_media_pcs(struct net_device * dev)1737 mii_set_media_pcs (struct net_device *dev)
1738 {
1739 __u16 bmcr;
1740 __u16 esr;
1741 __u16 anar;
1742 int phy_addr;
1743 struct netdev_private *np;
1744 np = netdev_priv(dev);
1745 phy_addr = np->phy_addr;
1746
1747 /* Auto-Negotiation? */
1748 if (np->an_enable) {
1749 /* Advertise capabilities */
1750 esr = mii_read (dev, phy_addr, PCS_ESR);
1751 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1752 ~PCS_ANAR_HALF_DUPLEX &
1753 ~PCS_ANAR_FULL_DUPLEX;
1754 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1755 anar |= PCS_ANAR_HALF_DUPLEX;
1756 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1757 anar |= PCS_ANAR_FULL_DUPLEX;
1758 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1759 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1760
1761 /* Soft reset PHY */
1762 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1763 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1764 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1765 mdelay(1);
1766 } else {
1767 /* Force speed setting */
1768 /* PHY Reset */
1769 bmcr = BMCR_RESET;
1770 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1771 mdelay(10);
1772 if (np->full_duplex) {
1773 bmcr = BMCR_FULLDPLX;
1774 printk (KERN_INFO "Manual full duplex\n");
1775 } else {
1776 bmcr = 0;
1777 printk (KERN_INFO "Manual half duplex\n");
1778 }
1779 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1780 mdelay(10);
1781
1782 /* Advertise nothing */
1783 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1784 }
1785 return 0;
1786 }
1787
1788
1789 static int
rio_close(struct net_device * dev)1790 rio_close (struct net_device *dev)
1791 {
1792 struct netdev_private *np = netdev_priv(dev);
1793 struct pci_dev *pdev = np->pdev;
1794
1795 netif_stop_queue (dev);
1796
1797 rio_hw_stop(dev);
1798
1799 free_irq(pdev->irq, dev);
1800 timer_delete_sync(&np->timer);
1801
1802 free_list(dev);
1803
1804 return 0;
1805 }
1806
1807 static void
rio_remove1(struct pci_dev * pdev)1808 rio_remove1 (struct pci_dev *pdev)
1809 {
1810 struct net_device *dev = pci_get_drvdata (pdev);
1811
1812 if (dev) {
1813 struct netdev_private *np = netdev_priv(dev);
1814
1815 unregister_netdev (dev);
1816 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1817 np->rx_ring_dma);
1818 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1819 np->tx_ring_dma);
1820 if (np->rmon_enable)
1821 pci_iounmap(pdev, np->ioaddr);
1822 pci_iounmap(pdev, np->eeprom_addr);
1823 free_netdev (dev);
1824 pci_release_regions (pdev);
1825 pci_disable_device (pdev);
1826 }
1827 }
1828
1829 #ifdef CONFIG_PM_SLEEP
rio_suspend(struct device * device)1830 static int rio_suspend(struct device *device)
1831 {
1832 struct net_device *dev = dev_get_drvdata(device);
1833 struct netdev_private *np = netdev_priv(dev);
1834
1835 if (!netif_running(dev))
1836 return 0;
1837
1838 netif_device_detach(dev);
1839 timer_delete_sync(&np->timer);
1840 rio_hw_stop(dev);
1841
1842 return 0;
1843 }
1844
rio_resume(struct device * device)1845 static int rio_resume(struct device *device)
1846 {
1847 struct net_device *dev = dev_get_drvdata(device);
1848 struct netdev_private *np = netdev_priv(dev);
1849
1850 if (!netif_running(dev))
1851 return 0;
1852
1853 rio_reset_ring(np);
1854 rio_hw_init(dev);
1855 np->timer.expires = jiffies + 1 * HZ;
1856 add_timer(&np->timer);
1857 netif_device_attach(dev);
1858 dl2k_enable_int(np);
1859
1860 return 0;
1861 }
1862
1863 static DEFINE_SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1864 #define RIO_PM_OPS (&rio_pm_ops)
1865
1866 #else
1867
1868 #define RIO_PM_OPS NULL
1869
1870 #endif /* CONFIG_PM_SLEEP */
1871
1872 static struct pci_driver rio_driver = {
1873 .name = "dl2k",
1874 .id_table = rio_pci_tbl,
1875 .probe = rio_probe1,
1876 .remove = rio_remove1,
1877 .driver.pm = RIO_PM_OPS,
1878 };
1879
1880 module_pci_driver(rio_driver);
1881
1882 /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */
1883