1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Authors:
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
7 */
8
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_platform.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/reset.h>
22
23 #include <ufs/ufshcd.h>
24 #include "ufshcd-pltfrm.h"
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/unipro.h>
27
28 #include "ufs-mediatek.h"
29 #include "ufs-mediatek-sip.h"
30
31 static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
32 static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
33
34 #define CREATE_TRACE_POINTS
35 #include "ufs-mediatek-trace.h"
36 #undef CREATE_TRACE_POINTS
37
38 #define MAX_SUPP_MAC 64
39 #define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200)
40
41 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
42 { .wmanufacturerid = UFS_ANY_VENDOR,
43 .model = UFS_ANY_MODEL,
44 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
45 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
46 .model = "H9HQ21AFAMZDAR",
47 .quirk = UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES },
48 {}
49 };
50
51 static const struct of_device_id ufs_mtk_of_match[] = {
52 { .compatible = "mediatek,mt8183-ufshci" },
53 { .compatible = "mediatek,mt8195-ufshci" },
54 {},
55 };
56 MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
57
58 /*
59 * Details of UIC Errors
60 */
61 static const char *const ufs_uic_err_str[] = {
62 "PHY Adapter Layer",
63 "Data Link Layer",
64 "Network Link Layer",
65 "Transport Link Layer",
66 "DME"
67 };
68
69 static const char *const ufs_uic_pa_err_str[] = {
70 "PHY error on Lane 0",
71 "PHY error on Lane 1",
72 "PHY error on Lane 2",
73 "PHY error on Lane 3",
74 "Generic PHY Adapter Error. This should be the LINERESET indication"
75 };
76
77 static const char *const ufs_uic_dl_err_str[] = {
78 "NAC_RECEIVED",
79 "TCx_REPLAY_TIMER_EXPIRED",
80 "AFCx_REQUEST_TIMER_EXPIRED",
81 "FCx_PROTECTION_TIMER_EXPIRED",
82 "CRC_ERROR",
83 "RX_BUFFER_OVERFLOW",
84 "MAX_FRAME_LENGTH_EXCEEDED",
85 "WRONG_SEQUENCE_NUMBER",
86 "AFC_FRAME_SYNTAX_ERROR",
87 "NAC_FRAME_SYNTAX_ERROR",
88 "EOF_SYNTAX_ERROR",
89 "FRAME_SYNTAX_ERROR",
90 "BAD_CTRL_SYMBOL_TYPE",
91 "PA_INIT_ERROR",
92 "PA_ERROR_IND_RECEIVED",
93 "PA_INIT"
94 };
95
ufs_mtk_is_boost_crypt_enabled(struct ufs_hba * hba)96 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
97 {
98 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
99
100 return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
101 }
102
ufs_mtk_is_va09_supported(struct ufs_hba * hba)103 static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
104 {
105 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
106
107 return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL;
108 }
109
ufs_mtk_is_broken_vcc(struct ufs_hba * hba)110 static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
111 {
112 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
113
114 return host->caps & UFS_MTK_CAP_BROKEN_VCC;
115 }
116
ufs_mtk_is_pmc_via_fastauto(struct ufs_hba * hba)117 static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
118 {
119 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
120
121 return host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO;
122 }
123
ufs_mtk_is_tx_skew_fix(struct ufs_hba * hba)124 static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
125 {
126 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
127
128 return host->caps & UFS_MTK_CAP_TX_SKEW_FIX;
129 }
130
ufs_mtk_is_rtff_mtcmos(struct ufs_hba * hba)131 static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
132 {
133 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
134
135 return host->caps & UFS_MTK_CAP_RTFF_MTCMOS;
136 }
137
ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba * hba)138 static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
139 {
140 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
141
142 return host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM;
143 }
144
ufs_mtk_is_clk_scale_ready(struct ufs_hba * hba)145 static bool ufs_mtk_is_clk_scale_ready(struct ufs_hba *hba)
146 {
147 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
148 struct ufs_mtk_clk *mclk = &host->mclk;
149
150 return mclk->ufs_sel_clki &&
151 mclk->ufs_sel_max_clki &&
152 mclk->ufs_sel_min_clki;
153 }
154
ufs_mtk_cfg_unipro_cg(struct ufs_hba * hba,bool enable)155 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
156 {
157 u32 tmp;
158
159 if (enable) {
160 ufshcd_dme_get(hba,
161 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
162 tmp = tmp |
163 (1 << RX_SYMBOL_CLK_GATE_EN) |
164 (1 << SYS_CLK_GATE_EN) |
165 (1 << TX_CLK_GATE_EN);
166 ufshcd_dme_set(hba,
167 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
168
169 ufshcd_dme_get(hba,
170 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
171 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
172 ufshcd_dme_set(hba,
173 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
174 } else {
175 ufshcd_dme_get(hba,
176 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
177 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
178 (1 << SYS_CLK_GATE_EN) |
179 (1 << TX_CLK_GATE_EN));
180 ufshcd_dme_set(hba,
181 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
182
183 ufshcd_dme_get(hba,
184 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
185 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
186 ufshcd_dme_set(hba,
187 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
188 }
189 }
190
ufs_mtk_crypto_enable(struct ufs_hba * hba)191 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
192 {
193 struct arm_smccc_res res;
194
195 ufs_mtk_crypto_ctrl(res, 1);
196 if (res.a0) {
197 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
198 __func__, res.a0);
199 hba->caps &= ~UFSHCD_CAP_CRYPTO;
200 }
201 }
202
ufs_mtk_host_reset(struct ufs_hba * hba)203 static void ufs_mtk_host_reset(struct ufs_hba *hba)
204 {
205 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
206 struct arm_smccc_res res;
207
208 reset_control_assert(host->hci_reset);
209 reset_control_assert(host->crypto_reset);
210 reset_control_assert(host->unipro_reset);
211 reset_control_assert(host->mphy_reset);
212
213 usleep_range(100, 110);
214
215 reset_control_deassert(host->unipro_reset);
216 reset_control_deassert(host->crypto_reset);
217 reset_control_deassert(host->hci_reset);
218 reset_control_deassert(host->mphy_reset);
219
220 /* restore mphy setting aftre mphy reset */
221 if (host->mphy_reset)
222 ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
223 }
224
ufs_mtk_init_reset_control(struct ufs_hba * hba,struct reset_control ** rc,char * str)225 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
226 struct reset_control **rc,
227 char *str)
228 {
229 *rc = devm_reset_control_get(hba->dev, str);
230 if (IS_ERR(*rc)) {
231 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
232 str, PTR_ERR(*rc));
233 *rc = NULL;
234 }
235 }
236
ufs_mtk_init_reset(struct ufs_hba * hba)237 static void ufs_mtk_init_reset(struct ufs_hba *hba)
238 {
239 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
240
241 ufs_mtk_init_reset_control(hba, &host->hci_reset,
242 "hci_rst");
243 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
244 "unipro_rst");
245 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
246 "crypto_rst");
247 ufs_mtk_init_reset_control(hba, &host->mphy_reset,
248 "mphy_rst");
249 }
250
ufs_mtk_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)251 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
252 enum ufs_notify_change_status status)
253 {
254 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
255
256 if (status == PRE_CHANGE) {
257 if (host->unipro_lpm) {
258 hba->vps->hba_enable_delay_us = 0;
259 } else {
260 hba->vps->hba_enable_delay_us = 600;
261 ufs_mtk_host_reset(hba);
262 }
263
264 if (hba->caps & UFSHCD_CAP_CRYPTO)
265 ufs_mtk_crypto_enable(hba);
266
267 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) {
268 ufshcd_writel(hba, 0,
269 REG_AUTO_HIBERNATE_IDLE_TIMER);
270 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
271 hba->ahit = 0;
272 }
273
274 /*
275 * Turn on CLK_CG early to bypass abnormal ERR_CHK signal
276 * to prevent host hang issue
277 */
278 ufshcd_writel(hba,
279 ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
280 REG_UFS_XOUFS_CTRL);
281
282 if (host->legacy_ip_ver)
283 return 0;
284
285 /* DDR_EN setting */
286 if (host->ip_ver >= IP_VER_MT6989) {
287 ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),
288 0x453000, REG_UFS_MMIO_OPT_CTRL_0);
289 }
290
291 if (host->ip_ver >= IP_VER_MT6991_A0) {
292 /* Enable multi-rtt */
293 ufshcd_rmwl(hba, MRTT_EN, MRTT_EN, REG_UFS_MMIO_OPT_CTRL_0);
294 /* Enable random performance improvement */
295 ufshcd_rmwl(hba, RDN_PFM_IMPV_DIS, 0, REG_UFS_MMIO_OPT_CTRL_0);
296 }
297 }
298
299 return 0;
300 }
301
ufs_mtk_bind_mphy(struct ufs_hba * hba)302 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
303 {
304 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
305 struct device *dev = hba->dev;
306 struct device_node *np = dev->of_node;
307 int err = 0;
308
309 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
310
311 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
312 /*
313 * UFS driver might be probed before the phy driver does.
314 * In that case we would like to return EPROBE_DEFER code.
315 */
316 err = -EPROBE_DEFER;
317 dev_info(dev,
318 "%s: required phy hasn't probed yet. err = %d\n",
319 __func__, err);
320 } else if (IS_ERR(host->mphy)) {
321 err = PTR_ERR(host->mphy);
322 if (err != -ENODEV) {
323 dev_info(dev, "%s: PHY get failed %d\n", __func__,
324 err);
325 }
326 }
327
328 if (err)
329 host->mphy = NULL;
330 /*
331 * Allow unbound mphy because not every platform needs specific
332 * mphy control.
333 */
334 if (err == -ENODEV)
335 err = 0;
336
337 return err;
338 }
339
ufs_mtk_setup_ref_clk(struct ufs_hba * hba,bool on)340 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
341 {
342 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
343 struct arm_smccc_res res;
344 ktime_t timeout, time_checked;
345 u32 value;
346
347 if (host->ref_clk_enabled == on)
348 return 0;
349
350 ufs_mtk_ref_clk_notify(on, PRE_CHANGE, res);
351
352 if (on) {
353 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
354 } else {
355 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
356 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
357 }
358
359 /* Wait for ack */
360 timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
361 do {
362 time_checked = ktime_get();
363 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
364
365 /* Wait until ack bit equals to req bit */
366 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
367 goto out;
368
369 usleep_range(100, 200);
370 } while (ktime_before(time_checked, timeout));
371
372 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
373
374 /*
375 * If clock on timeout, assume clock is off, notify tfa do clock
376 * off setting.(keep DIFN disable, release resource)
377 * If clock off timeout, assume clock will off finally,
378 * set ref_clk_enabled directly.(keep DIFN disable, keep resource)
379 */
380 if (on)
381 ufs_mtk_ref_clk_notify(false, POST_CHANGE, res);
382 else
383 host->ref_clk_enabled = false;
384
385 return -ETIMEDOUT;
386
387 out:
388 host->ref_clk_enabled = on;
389 if (on)
390 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
391
392 ufs_mtk_ref_clk_notify(on, POST_CHANGE, res);
393
394 return 0;
395 }
396
ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba * hba,u16 gating_us)397 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
398 u16 gating_us)
399 {
400 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
401
402 if (hba->dev_info.clk_gating_wait_us) {
403 host->ref_clk_gating_wait_us =
404 hba->dev_info.clk_gating_wait_us;
405 } else {
406 host->ref_clk_gating_wait_us = gating_us;
407 }
408
409 host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US;
410 }
411
ufs_mtk_dbg_sel(struct ufs_hba * hba)412 static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
413 {
414 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
415
416 if (!host->legacy_ip_ver && host->ip_ver >= IP_VER_MT6983) {
417 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
418 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
419 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
420 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
421 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
422 } else {
423 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
424 }
425 }
426
ufs_mtk_wait_idle_state(struct ufs_hba * hba,unsigned long retry_ms)427 static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
428 unsigned long retry_ms)
429 {
430 u64 timeout, time_checked;
431 u32 val, sm;
432 bool wait_idle;
433 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
434
435 /* cannot use plain ktime_get() in suspend */
436 timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
437
438 /* wait a specific time after check base */
439 udelay(10);
440 wait_idle = false;
441
442 do {
443 time_checked = ktime_get_mono_fast_ns();
444 if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
445 ufs_mtk_dbg_sel(hba);
446 val = ufshcd_readl(hba, REG_UFS_PROBE);
447 } else {
448 val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
449 val = val >> 16;
450 }
451
452 sm = val & 0x1f;
453
454 /*
455 * if state is in H8 enter and H8 enter confirm
456 * wait until return to idle state.
457 */
458 if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
459 wait_idle = true;
460 udelay(50);
461 continue;
462 } else if (!wait_idle)
463 break;
464
465 if (wait_idle && (sm == VS_HCE_BASE))
466 break;
467 } while (time_checked < timeout);
468
469 if (wait_idle && sm != VS_HCE_BASE) {
470 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
471 return -ETIMEDOUT;
472 }
473
474 return 0;
475 }
476
ufs_mtk_wait_link_state(struct ufs_hba * hba,u32 state,unsigned long max_wait_ms)477 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
478 unsigned long max_wait_ms)
479 {
480 ktime_t timeout, time_checked;
481 u32 val;
482 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
483
484 timeout = ktime_add_ms(ktime_get(), max_wait_ms);
485 do {
486 time_checked = ktime_get();
487
488 if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
489 ufs_mtk_dbg_sel(hba);
490 val = ufshcd_readl(hba, REG_UFS_PROBE);
491 val = val >> 28;
492 } else {
493 val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
494 val = val >> 24;
495 }
496
497 if (val == state)
498 return 0;
499
500 /* Sleep for max. 200us */
501 usleep_range(100, 200);
502 } while (ktime_before(time_checked, timeout));
503
504 return -ETIMEDOUT;
505 }
506
ufs_mtk_mphy_power_on(struct ufs_hba * hba,bool on)507 static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
508 {
509 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
510 struct phy *mphy = host->mphy;
511 struct arm_smccc_res res;
512 int err;
513 int ret = 0;
514
515 if (!mphy || !(on ^ host->mphy_powered_on))
516 return 0;
517
518 if (on) {
519 if (ufs_mtk_is_va09_supported(hba)) {
520 ret = regulator_enable(host->reg_va09);
521 if (ret < 0)
522 goto out;
523 /* wait 200 us to stablize VA09 */
524 usleep_range(200, 210);
525 ufs_mtk_va09_pwr_ctrl(res, 1);
526 }
527 ret = phy_power_on(mphy);
528 if (ret) {
529 if (ufs_mtk_is_va09_supported(hba)) {
530 ufs_mtk_va09_pwr_ctrl(res, 0);
531 err = regulator_disable(host->reg_va09);
532 if (err)
533 dev_err(hba->dev,
534 "failed to unwind va09: %d\n", err);
535 }
536 dev_err(hba->dev, "failed to enable mphy: %d\n", ret);
537 return ret;
538 }
539 } else {
540 phy_power_off(mphy);
541 if (ufs_mtk_is_va09_supported(hba)) {
542 ufs_mtk_va09_pwr_ctrl(res, 0);
543 ret = regulator_disable(host->reg_va09);
544 }
545 }
546 out:
547 if (ret) {
548 dev_info(hba->dev,
549 "failed to %s va09: %d\n",
550 on ? "enable" : "disable",
551 ret);
552 } else {
553 host->mphy_powered_on = on;
554 }
555
556 return ret;
557 }
558
ufs_mtk_get_host_clk(struct device * dev,const char * name,struct clk ** clk_out)559 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
560 struct clk **clk_out)
561 {
562 struct clk *clk;
563 int err = 0;
564
565 clk = devm_clk_get(dev, name);
566 if (IS_ERR(clk))
567 err = PTR_ERR(clk);
568 else
569 *clk_out = clk;
570
571 return err;
572 }
573
ufs_mtk_boost_crypt(struct ufs_hba * hba,bool boost)574 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
575 {
576 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
577 struct ufs_mtk_crypt_cfg *cfg;
578 struct regulator *reg;
579 int volt, ret;
580
581 if (!ufs_mtk_is_boost_crypt_enabled(hba))
582 return;
583
584 cfg = host->crypt;
585 volt = cfg->vcore_volt;
586 reg = cfg->reg_vcore;
587
588 ret = clk_prepare_enable(cfg->clk_crypt_mux);
589 if (ret) {
590 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
591 ret);
592 return;
593 }
594
595 if (boost) {
596 ret = regulator_set_voltage(reg, volt, INT_MAX);
597 if (ret) {
598 dev_info(hba->dev,
599 "failed to set vcore to %d\n", volt);
600 goto out;
601 }
602
603 ret = clk_set_parent(cfg->clk_crypt_mux,
604 cfg->clk_crypt_perf);
605 if (ret) {
606 dev_info(hba->dev,
607 "failed to set clk_crypt_perf\n");
608 regulator_set_voltage(reg, 0, INT_MAX);
609 goto out;
610 }
611 } else {
612 ret = clk_set_parent(cfg->clk_crypt_mux,
613 cfg->clk_crypt_lp);
614 if (ret) {
615 dev_info(hba->dev,
616 "failed to set clk_crypt_lp\n");
617 goto out;
618 }
619
620 ret = regulator_set_voltage(reg, 0, INT_MAX);
621 if (ret) {
622 dev_info(hba->dev,
623 "failed to set vcore to MIN\n");
624 }
625 }
626 out:
627 clk_disable_unprepare(cfg->clk_crypt_mux);
628 }
629
ufs_mtk_init_host_clk(struct ufs_hba * hba,const char * name,struct clk ** clk)630 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
631 struct clk **clk)
632 {
633 int ret;
634
635 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
636 if (ret) {
637 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
638 name, ret);
639 }
640
641 return ret;
642 }
643
ufs_mtk_init_boost_crypt(struct ufs_hba * hba)644 static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
645 {
646 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
647 struct ufs_mtk_crypt_cfg *cfg;
648 struct device *dev = hba->dev;
649 struct regulator *reg;
650 u32 volt;
651
652 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
653 GFP_KERNEL);
654 if (!host->crypt)
655 goto disable_caps;
656
657 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
658 if (IS_ERR(reg)) {
659 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
660 PTR_ERR(reg));
661 goto disable_caps;
662 }
663
664 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
665 &volt)) {
666 dev_info(dev, "failed to get boost-crypt-vcore-min");
667 goto disable_caps;
668 }
669
670 cfg = host->crypt;
671 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
672 &cfg->clk_crypt_mux))
673 goto disable_caps;
674
675 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
676 &cfg->clk_crypt_lp))
677 goto disable_caps;
678
679 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
680 &cfg->clk_crypt_perf))
681 goto disable_caps;
682
683 cfg->reg_vcore = reg;
684 cfg->vcore_volt = volt;
685 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
686
687 disable_caps:
688 return;
689 }
690
ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba * hba)691 static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
692 {
693 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
694
695 host->reg_va09 = regulator_get(hba->dev, "va09");
696 if (IS_ERR(host->reg_va09))
697 dev_info(hba->dev, "failed to get va09");
698 else
699 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
700 }
701
ufs_mtk_init_host_caps(struct ufs_hba * hba)702 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
703 {
704 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
705 struct device_node *np = hba->dev->of_node;
706
707 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
708 ufs_mtk_init_boost_crypt(hba);
709
710 if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
711 ufs_mtk_init_va09_pwr_ctrl(hba);
712
713 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
714 host->caps |= UFS_MTK_CAP_DISABLE_AH8;
715
716 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
717 host->caps |= UFS_MTK_CAP_BROKEN_VCC;
718
719 if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
720 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
721
722 if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
723 host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
724
725 if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
726 host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
727
728 if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
729 host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
730
731 if (of_property_read_bool(np, "mediatek,ufs-broken-rtc"))
732 host->caps |= UFS_MTK_CAP_MCQ_BROKEN_RTC;
733
734 dev_info(hba->dev, "caps: 0x%x", host->caps);
735 }
736
ufs_mtk_scale_perf(struct ufs_hba * hba,bool scale_up)737 static void ufs_mtk_scale_perf(struct ufs_hba *hba, bool scale_up)
738 {
739 ufs_mtk_boost_crypt(hba, scale_up);
740 }
741
ufs_mtk_pwr_ctrl(struct ufs_hba * hba,bool on)742 static void ufs_mtk_pwr_ctrl(struct ufs_hba *hba, bool on)
743 {
744 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
745
746 if (on) {
747 phy_power_on(host->mphy);
748 ufs_mtk_setup_ref_clk(hba, on);
749 if (!ufshcd_is_clkscaling_supported(hba))
750 ufs_mtk_scale_perf(hba, on);
751 } else {
752 if (!ufshcd_is_clkscaling_supported(hba))
753 ufs_mtk_scale_perf(hba, on);
754 ufs_mtk_setup_ref_clk(hba, on);
755 phy_power_off(host->mphy);
756 }
757 }
758
ufs_mtk_mcq_disable_irq(struct ufs_hba * hba)759 static void ufs_mtk_mcq_disable_irq(struct ufs_hba *hba)
760 {
761 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
762 u32 irq, i;
763
764 if (!hba->mcq_enabled)
765 return;
766
767 if (host->mcq_nr_intr == 0)
768 return;
769
770 for (i = 0; i < host->mcq_nr_intr; i++) {
771 irq = host->mcq_intr_info[i].irq;
772 disable_irq(irq);
773 }
774 host->is_mcq_intr_enabled = false;
775 }
776
ufs_mtk_mcq_enable_irq(struct ufs_hba * hba)777 static void ufs_mtk_mcq_enable_irq(struct ufs_hba *hba)
778 {
779 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
780 u32 irq, i;
781
782 if (!hba->mcq_enabled)
783 return;
784
785 if (host->mcq_nr_intr == 0)
786 return;
787
788 if (host->is_mcq_intr_enabled == true)
789 return;
790
791 for (i = 0; i < host->mcq_nr_intr; i++) {
792 irq = host->mcq_intr_info[i].irq;
793 enable_irq(irq);
794 }
795 host->is_mcq_intr_enabled = true;
796 }
797
798 /**
799 * ufs_mtk_setup_clocks - enables/disable clocks
800 * @hba: host controller instance
801 * @on: If true, enable clocks else disable them.
802 * @status: PRE_CHANGE or POST_CHANGE notify
803 *
804 * Return: 0 on success, non-zero on failure.
805 */
ufs_mtk_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)806 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
807 enum ufs_notify_change_status status)
808 {
809 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
810 bool clk_pwr_off = false;
811 int ret = 0;
812
813 /*
814 * In case ufs_mtk_init() is not yet done, simply ignore.
815 * This ufs_mtk_setup_clocks() shall be called from
816 * ufs_mtk_init() after init is done.
817 */
818 if (!host)
819 return 0;
820
821 if (!on && status == PRE_CHANGE) {
822 if (ufshcd_is_link_off(hba)) {
823 clk_pwr_off = true;
824 } else if (ufshcd_is_link_hibern8(hba) ||
825 (!ufshcd_can_hibern8_during_gating(hba) &&
826 ufshcd_is_auto_hibern8_enabled(hba))) {
827 /*
828 * Gate ref-clk and poweroff mphy if link state is in
829 * OFF or Hibern8 by either Auto-Hibern8 or
830 * ufshcd_link_state_transition().
831 */
832 ret = ufs_mtk_wait_link_state(hba,
833 VS_LINK_HIBERN8,
834 15);
835 if (!ret)
836 clk_pwr_off = true;
837 }
838
839 if (clk_pwr_off) {
840 ufs_mtk_pwr_ctrl(hba, false);
841 } else {
842 dev_warn(hba->dev, "Clock is not turned off, hba->ahit = 0x%x, AHIT = 0x%x\n",
843 hba->ahit,
844 ufshcd_readl(hba,
845 REG_AUTO_HIBERNATE_IDLE_TIMER));
846 }
847 ufs_mtk_mcq_disable_irq(hba);
848 } else if (on && status == POST_CHANGE) {
849 ufs_mtk_pwr_ctrl(hba, true);
850 ufs_mtk_mcq_enable_irq(hba);
851 }
852
853 return ret;
854 }
855
ufs_mtk_mcq_get_irq(struct ufs_hba * hba,unsigned int cpu)856 static u32 ufs_mtk_mcq_get_irq(struct ufs_hba *hba, unsigned int cpu)
857 {
858 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
859 struct blk_mq_tag_set *tag_set = &hba->host->tag_set;
860 struct blk_mq_queue_map *map = &tag_set->map[HCTX_TYPE_DEFAULT];
861 unsigned int nr = map->nr_queues;
862 unsigned int q_index;
863
864 q_index = map->mq_map[cpu];
865 if (q_index >= nr) {
866 dev_err(hba->dev, "hwq index %d exceed %d\n",
867 q_index, nr);
868 return MTK_MCQ_INVALID_IRQ;
869 }
870
871 return host->mcq_intr_info[q_index].irq;
872 }
873
ufs_mtk_mcq_set_irq_affinity(struct ufs_hba * hba,unsigned int cpu)874 static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
875 {
876 unsigned int irq, _cpu;
877 int ret;
878
879 irq = ufs_mtk_mcq_get_irq(hba, cpu);
880 if (irq == MTK_MCQ_INVALID_IRQ) {
881 dev_err(hba->dev, "invalid irq. unable to bind irq to cpu%d", cpu);
882 return;
883 }
884
885 /* force migrate irq of cpu0 to cpu3 */
886 _cpu = (cpu == 0) ? 3 : cpu;
887 ret = irq_set_affinity(irq, cpumask_of(_cpu));
888 if (ret) {
889 dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n",
890 irq, _cpu);
891 return;
892 }
893 dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
894 }
895
ufs_mtk_is_legacy_chipset(struct ufs_hba * hba,u32 hw_ip_ver)896 static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
897 {
898 bool is_legacy = false;
899
900 switch (hw_ip_ver) {
901 case IP_LEGACY_VER_MT6893:
902 case IP_LEGACY_VER_MT6781:
903 /* can add other legacy chipset ID here accordingly */
904 is_legacy = true;
905 break;
906 default:
907 break;
908 }
909 dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy);
910
911 return is_legacy;
912 }
913
914 /*
915 * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since
916 * project MT6878. In order to perform correct version comparison,
917 * version number is changed by SW for the following projects.
918 * IP_VER_MT6983 0x00360000 to 0x10360000
919 * IP_VER_MT6897 0x01440000 to 0x10440000
920 * IP_VER_MT6989 0x01450000 to 0x10450000
921 * IP_VER_MT6991 0x01460000 to 0x10460000
922 */
ufs_mtk_get_hw_ip_version(struct ufs_hba * hba)923 static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
924 {
925 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
926 u32 hw_ip_ver;
927
928 hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
929
930 if (((hw_ip_ver & (0xFF << 24)) == (0x1 << 24)) ||
931 ((hw_ip_ver & (0xFF << 24)) == 0)) {
932 hw_ip_ver &= ~(0xFF << 24);
933 hw_ip_ver |= (0x1 << 28);
934 }
935
936 host->ip_ver = hw_ip_ver;
937
938 host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver);
939 }
940
ufs_mtk_get_controller_version(struct ufs_hba * hba)941 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
942 {
943 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
944 int ret, ver = 0;
945
946 if (host->hw_ver.major)
947 return;
948
949 /* Set default (minimum) version anyway */
950 host->hw_ver.major = 2;
951
952 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);
953 if (!ret) {
954 if (ver >= UFS_UNIPRO_VER_1_8) {
955 host->hw_ver.major = 3;
956 /*
957 * Fix HCI version for some platforms with
958 * incorrect version
959 */
960 if (hba->ufs_version < ufshci_version(3, 0))
961 hba->ufs_version = ufshci_version(3, 0);
962 }
963 }
964 }
965
ufs_mtk_get_ufs_hci_version(struct ufs_hba * hba)966 static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba *hba)
967 {
968 return hba->ufs_version;
969 }
970
971 /**
972 * ufs_mtk_init_clocks - Init mtk driver private clocks
973 *
974 * @hba: per adapter instance
975 */
ufs_mtk_init_clocks(struct ufs_hba * hba)976 static void ufs_mtk_init_clocks(struct ufs_hba *hba)
977 {
978 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
979 struct list_head *head = &hba->clk_list_head;
980 struct ufs_clk_info *clki, *clki_tmp;
981 struct device *dev = hba->dev;
982 struct regulator *reg;
983 u32 volt;
984
985 /*
986 * Find private clocks and store them in struct ufs_mtk_clk.
987 * Remove "ufs_sel_min_src" and "ufs_sel_min_src" from list to avoid
988 * being switched on/off in clock gating.
989 */
990 list_for_each_entry_safe(clki, clki_tmp, head, list) {
991 if (!strcmp(clki->name, "ufs_sel")) {
992 host->mclk.ufs_sel_clki = clki;
993 } else if (!strcmp(clki->name, "ufs_sel_max_src")) {
994 host->mclk.ufs_sel_max_clki = clki;
995 clk_disable_unprepare(clki->clk);
996 list_del(&clki->list);
997 } else if (!strcmp(clki->name, "ufs_sel_min_src")) {
998 host->mclk.ufs_sel_min_clki = clki;
999 clk_disable_unprepare(clki->clk);
1000 list_del(&clki->list);
1001 } else if (!strcmp(clki->name, "ufs_fde")) {
1002 host->mclk.ufs_fde_clki = clki;
1003 } else if (!strcmp(clki->name, "ufs_fde_max_src")) {
1004 host->mclk.ufs_fde_max_clki = clki;
1005 clk_disable_unprepare(clki->clk);
1006 list_del(&clki->list);
1007 } else if (!strcmp(clki->name, "ufs_fde_min_src")) {
1008 host->mclk.ufs_fde_min_clki = clki;
1009 clk_disable_unprepare(clki->clk);
1010 list_del(&clki->list);
1011 }
1012 }
1013
1014 list_for_each_entry(clki, head, list) {
1015 dev_info(hba->dev, "clk \"%s\" present", clki->name);
1016 }
1017
1018 if (!ufs_mtk_is_clk_scale_ready(hba)) {
1019 hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
1020 dev_info(hba->dev,
1021 "%s: Clk-scaling not ready. Feature disabled.",
1022 __func__);
1023 return;
1024 }
1025
1026 /*
1027 * Default get vcore if dts have these settings.
1028 * No matter clock scaling support or not. (may disable by customer)
1029 */
1030 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
1031 if (IS_ERR(reg)) {
1032 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
1033 PTR_ERR(reg));
1034 return;
1035 }
1036
1037 if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
1038 &volt)) {
1039 dev_info(dev, "failed to get clk-scale-up-vcore-min");
1040 return;
1041 }
1042
1043 host->mclk.reg_vcore = reg;
1044 host->mclk.vcore_volt = volt;
1045
1046 /* If default boot is max gear, request vcore */
1047 if (reg && volt && host->clk_scale_up) {
1048 if (regulator_set_voltage(reg, volt, INT_MAX)) {
1049 dev_info(hba->dev,
1050 "Failed to set vcore to %d\n", volt);
1051 }
1052 }
1053 }
1054
1055 #define MAX_VCC_NAME 30
ufs_mtk_vreg_fix_vcc(struct ufs_hba * hba)1056 static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
1057 {
1058 struct ufs_vreg_info *info = &hba->vreg_info;
1059 struct device_node *np = hba->dev->of_node;
1060 struct device *dev = hba->dev;
1061 char vcc_name[MAX_VCC_NAME];
1062 struct arm_smccc_res res;
1063 int err, ver;
1064
1065 if (info->vcc)
1066 return 0;
1067
1068 if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
1069 ufs_mtk_get_vcc_num(res);
1070 if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
1071 snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1);
1072 else
1073 return -ENODEV;
1074 } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
1075 ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
1076 snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
1077 } else {
1078 return 0;
1079 }
1080
1081 err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false);
1082 if (err)
1083 return err;
1084
1085 err = ufshcd_get_vreg(dev, info->vcc);
1086 if (err)
1087 return err;
1088
1089 err = regulator_enable(info->vcc->reg);
1090 if (!err) {
1091 info->vcc->enabled = true;
1092 dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
1093 }
1094
1095 return err;
1096 }
1097
ufs_mtk_vreg_fix_vccqx(struct ufs_hba * hba)1098 static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
1099 {
1100 struct ufs_vreg_info *info = &hba->vreg_info;
1101 struct ufs_vreg **vreg_on, **vreg_off;
1102
1103 if (hba->dev_info.wspecversion >= 0x0300) {
1104 vreg_on = &info->vccq;
1105 vreg_off = &info->vccq2;
1106 } else {
1107 vreg_on = &info->vccq2;
1108 vreg_off = &info->vccq;
1109 }
1110
1111 if (*vreg_on)
1112 (*vreg_on)->always_on = true;
1113
1114 if (*vreg_off) {
1115 regulator_disable((*vreg_off)->reg);
1116 devm_kfree(hba->dev, (*vreg_off)->name);
1117 devm_kfree(hba->dev, *vreg_off);
1118 *vreg_off = NULL;
1119 }
1120 }
1121
ufs_mtk_setup_clk_gating(struct ufs_hba * hba)1122 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
1123 {
1124 unsigned long flags;
1125 u32 ah_ms = 10;
1126 u32 ah_scale, ah_timer;
1127 static const u32 scale_us[] = {1, 10, 100, 1000, 10000, 100000};
1128
1129 if (ufshcd_is_clkgating_allowed(hba)) {
1130 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) {
1131 ah_scale = FIELD_GET(UFSHCI_AHIBERN8_SCALE_MASK,
1132 hba->ahit);
1133 ah_timer = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
1134 hba->ahit);
1135 if (ah_scale <= 5)
1136 ah_ms = ah_timer * scale_us[ah_scale] / 1000;
1137 }
1138
1139 spin_lock_irqsave(hba->host->host_lock, flags);
1140 hba->clk_gating.delay_ms = max(ah_ms, 10U);
1141 spin_unlock_irqrestore(hba->host->host_lock, flags);
1142 }
1143 }
1144
ufs_mtk_fix_ahit(struct ufs_hba * hba)1145 static void ufs_mtk_fix_ahit(struct ufs_hba *hba)
1146 {
1147 unsigned int us;
1148
1149 if (ufshcd_is_auto_hibern8_supported(hba)) {
1150 switch (hba->dev_info.wmanufacturerid) {
1151 case UFS_VENDOR_SAMSUNG:
1152 /* configure auto-hibern8 timer to 3.5 ms */
1153 us = 3500;
1154 break;
1155
1156 case UFS_VENDOR_MICRON:
1157 /* configure auto-hibern8 timer to 2 ms */
1158 us = 2000;
1159 break;
1160
1161 default:
1162 /* configure auto-hibern8 timer to 1 ms */
1163 us = 1000;
1164 break;
1165 }
1166
1167 hba->ahit = ufshcd_us_to_ahit(us);
1168 }
1169
1170 ufs_mtk_setup_clk_gating(hba);
1171 }
1172
ufs_mtk_fix_clock_scaling(struct ufs_hba * hba)1173 static void ufs_mtk_fix_clock_scaling(struct ufs_hba *hba)
1174 {
1175 /* UFS version is below 4.0, clock scaling is not necessary */
1176 if ((hba->dev_info.wspecversion < 0x0400) &&
1177 ufs_mtk_is_clk_scale_ready(hba)) {
1178 hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
1179
1180 _ufs_mtk_clk_scale(hba, false);
1181 }
1182 }
1183
ufs_mtk_init_mcq_irq(struct ufs_hba * hba)1184 static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
1185 {
1186 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1187 struct platform_device *pdev;
1188 int i;
1189 int irq;
1190
1191 host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
1192 pdev = container_of(hba->dev, struct platform_device, dev);
1193
1194 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
1195 goto failed;
1196
1197 for (i = 0; i < host->mcq_nr_intr; i++) {
1198 /* irq index 0 is legacy irq, sq/cq irq start from index 1 */
1199 irq = platform_get_irq(pdev, i + 1);
1200 if (irq < 0) {
1201 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ;
1202 goto failed;
1203 }
1204 host->mcq_intr_info[i].hba = hba;
1205 host->mcq_intr_info[i].irq = irq;
1206 dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
1207 }
1208
1209 return;
1210 failed:
1211 /* invalidate irq info */
1212 for (i = 0; i < host->mcq_nr_intr; i++)
1213 host->mcq_intr_info[i].irq = MTK_MCQ_INVALID_IRQ;
1214
1215 host->mcq_nr_intr = 0;
1216 }
1217
1218 /**
1219 * ufs_mtk_init - find other essential mmio bases
1220 * @hba: host controller instance
1221 *
1222 * Binds PHY with controller and powers up PHY enabling clocks
1223 * and regulators.
1224 *
1225 * Return: -EPROBE_DEFER if binding fails, returns negative error
1226 * on phy power up failure and returns zero on success.
1227 */
ufs_mtk_init(struct ufs_hba * hba)1228 static int ufs_mtk_init(struct ufs_hba *hba)
1229 {
1230 const struct of_device_id *id;
1231 struct device *dev = hba->dev;
1232 struct ufs_mtk_host *host;
1233 struct Scsi_Host *shost = hba->host;
1234 int err = 0;
1235 struct arm_smccc_res res;
1236
1237 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1238 if (!host) {
1239 err = -ENOMEM;
1240 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
1241 goto out;
1242 }
1243
1244 host->hba = hba;
1245 ufshcd_set_variant(hba, host);
1246
1247 id = of_match_device(ufs_mtk_of_match, dev);
1248 if (!id) {
1249 err = -EINVAL;
1250 goto out;
1251 }
1252
1253 /* Initialize host capability */
1254 ufs_mtk_init_host_caps(hba);
1255
1256 ufs_mtk_init_mcq_irq(hba);
1257
1258 err = ufs_mtk_bind_mphy(hba);
1259 if (err)
1260 goto out_variant_clear;
1261
1262 ufs_mtk_init_reset(hba);
1263
1264 /* backup mphy setting if mphy can reset */
1265 if (host->mphy_reset)
1266 ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
1267
1268 /* Enable runtime autosuspend */
1269 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
1270
1271 /* Enable clock-gating */
1272 hba->caps |= UFSHCD_CAP_CLK_GATING;
1273
1274 /* Enable inline encryption */
1275 hba->caps |= UFSHCD_CAP_CRYPTO;
1276
1277 /* Enable WriteBooster */
1278 hba->caps |= UFSHCD_CAP_WB_EN;
1279
1280 /* Enable clk scaling*/
1281 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1282 host->clk_scale_up = true; /* default is max freq */
1283
1284 /* Set runtime pm delay to replace default */
1285 shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS;
1286
1287 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
1288
1289 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR;
1290 if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC)
1291 hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
1292
1293 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
1294
1295 if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
1296 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1297
1298 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
1299 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP;
1300
1301 ufs_mtk_init_clocks(hba);
1302
1303 /*
1304 * ufshcd_vops_init() is invoked after
1305 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
1306 * phy clock setup is skipped.
1307 *
1308 * Enable phy clocks specifically here.
1309 */
1310 err = ufs_mtk_mphy_power_on(hba, true);
1311 if (err)
1312 goto out_variant_clear;
1313
1314 if (ufs_mtk_is_rtff_mtcmos(hba)) {
1315 /* First Restore here, to avoid backup unexpected value */
1316 ufs_mtk_mtcmos_ctrl(false, res);
1317
1318 /* Power on to init */
1319 ufs_mtk_mtcmos_ctrl(true, res);
1320 }
1321
1322 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
1323
1324 ufs_mtk_get_hw_ip_version(hba);
1325
1326 goto out;
1327
1328 out_variant_clear:
1329 ufshcd_set_variant(hba, NULL);
1330 out:
1331 return err;
1332 }
1333
ufs_mtk_negotiate_pwr_mode(struct ufs_hba * hba,const struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1334 static int ufs_mtk_negotiate_pwr_mode(struct ufs_hba *hba,
1335 const struct ufs_pa_layer_attr *dev_max_params,
1336 struct ufs_pa_layer_attr *dev_req_params)
1337 {
1338 struct ufs_host_params host_params;
1339
1340 ufshcd_init_host_params(&host_params);
1341 host_params.hs_rx_gear = UFS_HS_G5;
1342 host_params.hs_tx_gear = UFS_HS_G5;
1343
1344 if (dev_max_params->pwr_rx == SLOW_MODE ||
1345 dev_max_params->pwr_tx == SLOW_MODE)
1346 host_params.desired_working_mode = UFS_PWM_MODE;
1347
1348 return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
1349 }
1350
ufs_mtk_pmc_via_fastauto(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_req_params)1351 static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba,
1352 struct ufs_pa_layer_attr *dev_req_params)
1353 {
1354 if (!ufs_mtk_is_pmc_via_fastauto(hba))
1355 return false;
1356
1357 if (dev_req_params->hs_rate == hba->pwr_info.hs_rate)
1358 return false;
1359
1360 if (dev_req_params->pwr_tx != FAST_MODE &&
1361 dev_req_params->gear_tx < UFS_HS_G4)
1362 return false;
1363
1364 if (dev_req_params->pwr_rx != FAST_MODE &&
1365 dev_req_params->gear_rx < UFS_HS_G4)
1366 return false;
1367
1368 if (dev_req_params->pwr_tx == SLOW_MODE ||
1369 dev_req_params->pwr_rx == SLOW_MODE)
1370 return false;
1371
1372 return true;
1373 }
1374
ufs_mtk_adjust_sync_length(struct ufs_hba * hba)1375 static void ufs_mtk_adjust_sync_length(struct ufs_hba *hba)
1376 {
1377 int i;
1378 u32 value;
1379 u32 cnt, att, min;
1380 struct attr_min {
1381 u32 attr;
1382 u32 min_value;
1383 } pa_min_sync_length[] = {
1384 {PA_TXHSG1SYNCLENGTH, 0x48},
1385 {PA_TXHSG2SYNCLENGTH, 0x48},
1386 {PA_TXHSG3SYNCLENGTH, 0x48},
1387 {PA_TXHSG4SYNCLENGTH, 0x48},
1388 {PA_TXHSG5SYNCLENGTH, 0x48}
1389 };
1390
1391 cnt = sizeof(pa_min_sync_length) / sizeof(struct attr_min);
1392 for (i = 0; i < cnt; i++) {
1393 att = pa_min_sync_length[i].attr;
1394 min = pa_min_sync_length[i].min_value;
1395 ufshcd_dme_get(hba, UIC_ARG_MIB(att), &value);
1396 if (value < min)
1397 ufshcd_dme_set(hba, UIC_ARG_MIB(att), min);
1398
1399 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(att), &value);
1400 if (value < min)
1401 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(att), min);
1402 }
1403 }
1404
ufs_mtk_pre_pwr_change(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_req_params)1405 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
1406 struct ufs_pa_layer_attr *dev_req_params)
1407 {
1408 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1409 int ret = 0;
1410
1411 if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) {
1412 ufs_mtk_adjust_sync_length(hba);
1413
1414 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
1415 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1);
1416
1417 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
1418 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1);
1419
1420 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
1421 dev_req_params->lane_tx);
1422 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
1423 dev_req_params->lane_rx);
1424 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
1425 dev_req_params->hs_rate);
1426
1427 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),
1428 PA_NO_ADAPT);
1429
1430 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
1431 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
1432 DL_FC0ProtectionTimeOutVal_Default);
1433 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
1434 DL_TC0ReplayTimeOutVal_Default);
1435 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
1436 DL_AFC0ReqTimeOutVal_Default);
1437 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
1438 DL_FC1ProtectionTimeOutVal_Default);
1439 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
1440 DL_TC1ReplayTimeOutVal_Default);
1441 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
1442 DL_AFC1ReqTimeOutVal_Default);
1443
1444 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
1445 DL_FC0ProtectionTimeOutVal_Default);
1446 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
1447 DL_TC0ReplayTimeOutVal_Default);
1448 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
1449 DL_AFC0ReqTimeOutVal_Default);
1450 }
1451
1452 ret = ufshcd_uic_change_pwr_mode(hba,
1453 FASTAUTO_MODE << 4 | FASTAUTO_MODE);
1454
1455 if (ret) {
1456 dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n",
1457 __func__, ret);
1458 }
1459 }
1460
1461 /* if already configured to the requested pwr_mode, skip adapt */
1462 if (dev_req_params->gear_rx == hba->pwr_info.gear_rx &&
1463 dev_req_params->gear_tx == hba->pwr_info.gear_tx &&
1464 dev_req_params->lane_rx == hba->pwr_info.lane_rx &&
1465 dev_req_params->lane_tx == hba->pwr_info.lane_tx &&
1466 dev_req_params->pwr_rx == hba->pwr_info.pwr_rx &&
1467 dev_req_params->pwr_tx == hba->pwr_info.pwr_tx &&
1468 dev_req_params->hs_rate == hba->pwr_info.hs_rate) {
1469 return ret;
1470 }
1471
1472 if (dev_req_params->pwr_rx == FAST_MODE ||
1473 dev_req_params->pwr_rx == FASTAUTO_MODE) {
1474 if (host->hw_ver.major >= 3) {
1475 ret = ufshcd_dme_configure_adapt(hba,
1476 dev_req_params->gear_tx,
1477 PA_INITIAL_ADAPT);
1478 } else {
1479 ret = ufshcd_dme_configure_adapt(hba,
1480 dev_req_params->gear_tx,
1481 PA_NO_ADAPT);
1482 }
1483 } else {
1484 ret = ufshcd_dme_configure_adapt(hba,
1485 dev_req_params->gear_tx,
1486 PA_NO_ADAPT);
1487 }
1488
1489 return ret;
1490 }
1491
ufs_mtk_auto_hibern8_disable(struct ufs_hba * hba)1492 static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
1493 {
1494 int ret;
1495
1496 /* disable auto-hibern8 */
1497 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
1498
1499 /* wait host return to idle state when auto-hibern8 off */
1500 ret = ufs_mtk_wait_idle_state(hba, 5);
1501 if (ret)
1502 goto out;
1503
1504 ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1505
1506 out:
1507 if (ret) {
1508 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1509
1510 ufshcd_force_error_recovery(hba);
1511
1512 /* trigger error handler and break suspend */
1513 ret = -EBUSY;
1514 }
1515
1516 return ret;
1517 }
1518
ufs_mtk_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status stage,struct ufs_pa_layer_attr * dev_req_params)1519 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
1520 enum ufs_notify_change_status stage,
1521 struct ufs_pa_layer_attr *dev_req_params)
1522 {
1523 int ret = 0;
1524 static u32 reg;
1525
1526 switch (stage) {
1527 case PRE_CHANGE:
1528 if (ufshcd_is_auto_hibern8_supported(hba)) {
1529 reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
1530 ufs_mtk_auto_hibern8_disable(hba);
1531 }
1532 ret = ufs_mtk_pre_pwr_change(hba, dev_req_params);
1533 break;
1534 case POST_CHANGE:
1535 if (ufshcd_is_auto_hibern8_supported(hba))
1536 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
1537 break;
1538 default:
1539 ret = -EINVAL;
1540 break;
1541 }
1542
1543 return ret;
1544 }
1545
ufs_mtk_unipro_set_lpm(struct ufs_hba * hba,bool lpm)1546 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
1547 {
1548 int ret;
1549 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1550
1551 ret = ufshcd_dme_set(hba,
1552 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
1553 lpm ? 1 : 0);
1554 if (!ret || !lpm) {
1555 /*
1556 * Forcibly set as non-LPM mode if UIC commands is failed
1557 * to use default hba_enable_delay_us value for re-enabling
1558 * the host.
1559 */
1560 host->unipro_lpm = lpm;
1561 }
1562
1563 return ret;
1564 }
1565
ufs_mtk_pre_link(struct ufs_hba * hba)1566 static int ufs_mtk_pre_link(struct ufs_hba *hba)
1567 {
1568 int ret;
1569 u32 tmp;
1570 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1571
1572 ufs_mtk_get_controller_version(hba);
1573
1574 ret = ufs_mtk_unipro_set_lpm(hba, false);
1575 if (ret)
1576 return ret;
1577
1578 /*
1579 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
1580 * to make sure that both host and device TX LCC are disabled
1581 * once link startup is completed.
1582 */
1583 ret = ufshcd_disable_host_tx_lcc(hba);
1584 if (ret)
1585 return ret;
1586
1587 /* disable deep stall */
1588 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
1589 if (ret)
1590 return ret;
1591
1592 tmp &= ~(1 << 6);
1593
1594 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
1595
1596 /* Enable the 1144 functions setting */
1597 if (host->ip_ver == IP_VER_MT6989) {
1598 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGOMC), &tmp);
1599 if (ret)
1600 return ret;
1601
1602 tmp |= 0x10;
1603 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), tmp);
1604 }
1605
1606 return ret;
1607 }
1608
ufs_mtk_post_link(struct ufs_hba * hba)1609 static void ufs_mtk_post_link(struct ufs_hba *hba)
1610 {
1611 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1612 u32 tmp;
1613
1614 /* fix device PA_INIT no adapt */
1615 if (host->ip_ver >= IP_VER_MT6899) {
1616 ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGOMC), &tmp);
1617 tmp |= 0x100;
1618 ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), tmp);
1619 }
1620
1621 /* enable unipro clock gating feature */
1622 ufs_mtk_cfg_unipro_cg(hba, true);
1623 }
1624
ufs_mtk_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status stage)1625 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
1626 enum ufs_notify_change_status stage)
1627 {
1628 int ret = 0;
1629
1630 switch (stage) {
1631 case PRE_CHANGE:
1632 ret = ufs_mtk_pre_link(hba);
1633 break;
1634 case POST_CHANGE:
1635 ufs_mtk_post_link(hba);
1636 break;
1637 default:
1638 ret = -EINVAL;
1639 break;
1640 }
1641
1642 return ret;
1643 }
1644
ufs_mtk_device_reset(struct ufs_hba * hba)1645 static int ufs_mtk_device_reset(struct ufs_hba *hba)
1646 {
1647 struct arm_smccc_res res;
1648
1649 ufs_mtk_device_reset_ctrl(0, res);
1650
1651 /* disable hba in middle of device reset */
1652 ufshcd_hba_stop(hba);
1653
1654 /*
1655 * The reset signal is active low. UFS devices shall detect
1656 * more than or equal to 1us of positive or negative RST_n
1657 * pulse width.
1658 *
1659 * To be on safe side, keep the reset low for at least 10us.
1660 */
1661 usleep_range(10, 15);
1662
1663 ufs_mtk_device_reset_ctrl(1, res);
1664
1665 /* Some devices may need time to respond to rst_n */
1666 usleep_range(10000, 15000);
1667
1668 dev_info(hba->dev, "device reset done\n");
1669
1670 return 0;
1671 }
1672
ufs_mtk_link_set_hpm(struct ufs_hba * hba)1673 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
1674 {
1675 int err;
1676 u32 val;
1677 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1678
1679 err = ufshcd_hba_enable(hba);
1680 if (err)
1681 return err;
1682
1683 err = ufs_mtk_unipro_set_lpm(hba, false);
1684 if (err) {
1685 if (host->ip_ver < IP_VER_MT6899) {
1686 ufs_mtk_dbg_sel(hba);
1687 val = ufshcd_readl(hba, REG_UFS_PROBE);
1688 } else {
1689 val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
1690 }
1691 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val);
1692 val = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
1693 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val);
1694 return err;
1695 }
1696
1697 err = ufshcd_uic_hibern8_exit(hba);
1698 if (err)
1699 return err;
1700
1701 /* Check link state to make sure exit h8 success */
1702 err = ufs_mtk_wait_idle_state(hba, 5);
1703 if (err) {
1704 dev_warn(hba->dev, "wait idle fail, err=%d\n", err);
1705 return err;
1706 }
1707 err = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1708 if (err) {
1709 dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err);
1710 return err;
1711 }
1712 ufshcd_set_link_active(hba);
1713
1714 err = ufshcd_make_hba_operational(hba);
1715 if (err)
1716 return err;
1717
1718 if (hba->mcq_enabled) {
1719 ufs_mtk_config_mcq(hba, false);
1720 ufshcd_mcq_make_queues_operational(hba);
1721 ufshcd_mcq_config_mac(hba, hba->nutrs);
1722 ufshcd_mcq_enable(hba);
1723 }
1724
1725 return 0;
1726 }
1727
ufs_mtk_link_set_lpm(struct ufs_hba * hba)1728 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
1729 {
1730 int err;
1731
1732 /* Disable reset confirm feature by UniPro */
1733 ufshcd_writel(hba,
1734 (ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) & ~0x100),
1735 REG_UFS_XOUFS_CTRL);
1736
1737 err = ufs_mtk_unipro_set_lpm(hba, true);
1738 if (err) {
1739 /* Resume UniPro state for following error recovery */
1740 ufs_mtk_unipro_set_lpm(hba, false);
1741 return err;
1742 }
1743
1744 return 0;
1745 }
1746
ufs_mtk_vccqx_set_lpm(struct ufs_hba * hba,bool lpm)1747 static void ufs_mtk_vccqx_set_lpm(struct ufs_hba *hba, bool lpm)
1748 {
1749 struct ufs_vreg *vccqx = NULL;
1750
1751 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
1752 return;
1753
1754 if (hba->vreg_info.vccq)
1755 vccqx = hba->vreg_info.vccq;
1756 else
1757 vccqx = hba->vreg_info.vccq2;
1758
1759 regulator_set_mode(vccqx->reg,
1760 lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL);
1761 }
1762
ufs_mtk_vsx_set_lpm(struct ufs_hba * hba,bool lpm)1763 static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm)
1764 {
1765 struct arm_smccc_res res;
1766
1767 ufs_mtk_device_pwr_ctrl(!lpm,
1768 (unsigned long)hba->dev_info.wspecversion,
1769 res);
1770 }
1771
ufs_mtk_dev_vreg_set_lpm(struct ufs_hba * hba,bool lpm)1772 static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
1773 {
1774 bool skip_vccqx = false;
1775
1776 /* Prevent entering LPM when device is still active */
1777 if (lpm && ufshcd_is_ufs_dev_active(hba))
1778 return;
1779
1780 /* Skip vccqx lpm control and control vsx only */
1781 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
1782 skip_vccqx = true;
1783
1784 /* VCC is always-on, control vsx only */
1785 if (!hba->vreg_info.vcc)
1786 skip_vccqx = true;
1787
1788 /* Broken vcc keep vcc always on, most case control vsx only */
1789 if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) {
1790 /* Some device vccqx/vsx can enter lpm */
1791 if (ufs_mtk_is_allow_vccqx_lpm(hba))
1792 skip_vccqx = false;
1793 else /* control vsx only */
1794 skip_vccqx = true;
1795 }
1796
1797 if (lpm) {
1798 if (!skip_vccqx)
1799 ufs_mtk_vccqx_set_lpm(hba, lpm);
1800 ufs_mtk_vsx_set_lpm(hba, lpm);
1801 } else {
1802 ufs_mtk_vsx_set_lpm(hba, lpm);
1803 if (!skip_vccqx)
1804 ufs_mtk_vccqx_set_lpm(hba, lpm);
1805 }
1806 }
1807
ufs_mtk_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)1808 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1809 enum ufs_notify_change_status status)
1810 {
1811 int err;
1812 struct arm_smccc_res res;
1813 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1814
1815 if (status == PRE_CHANGE) {
1816 if (ufshcd_is_auto_hibern8_supported(hba))
1817 return ufs_mtk_auto_hibern8_disable(hba);
1818 return 0;
1819 }
1820
1821 if (ufshcd_is_link_hibern8(hba)) {
1822 err = ufs_mtk_link_set_lpm(hba);
1823 if (err)
1824 goto fail;
1825 }
1826
1827 if (!ufshcd_is_link_active(hba)) {
1828 /*
1829 * Make sure no error will be returned to prevent
1830 * ufshcd_suspend() re-enabling regulators while vreg is still
1831 * in low-power mode.
1832 */
1833 err = ufs_mtk_mphy_power_on(hba, false);
1834 if (err)
1835 goto fail;
1836 }
1837
1838 if (ufshcd_is_link_off(hba))
1839 ufs_mtk_device_reset_ctrl(0, res);
1840
1841 ufs_mtk_sram_pwr_ctrl(false, res);
1842
1843 /* Release pm_qos/clk if in scale-up mode during suspend */
1844 if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) {
1845 ufshcd_pm_qos_update(hba, false);
1846 _ufs_mtk_clk_scale(hba, false);
1847 } else if ((!ufshcd_is_clkscaling_supported(hba) &&
1848 hba->pwr_info.gear_rx >= UFS_HS_G5)) {
1849 _ufs_mtk_clk_scale(hba, false);
1850 }
1851
1852 return 0;
1853 fail:
1854 /*
1855 * Set link as off state enforcedly to trigger
1856 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
1857 * for completed host reset.
1858 */
1859 ufshcd_set_link_off(hba);
1860 return -EAGAIN;
1861 }
1862
ufs_mtk_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1863 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1864 {
1865 int err;
1866 struct arm_smccc_res res;
1867 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1868
1869 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
1870 ufs_mtk_dev_vreg_set_lpm(hba, false);
1871
1872 ufs_mtk_sram_pwr_ctrl(true, res);
1873
1874 err = ufs_mtk_mphy_power_on(hba, true);
1875 if (err)
1876 goto fail;
1877
1878 /* Request pm_qos/clk if in scale-up mode after resume */
1879 if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) {
1880 ufshcd_pm_qos_update(hba, true);
1881 _ufs_mtk_clk_scale(hba, true);
1882 } else if ((!ufshcd_is_clkscaling_supported(hba) &&
1883 hba->pwr_info.gear_rx >= UFS_HS_G5)) {
1884 _ufs_mtk_clk_scale(hba, true);
1885 }
1886
1887 if (ufshcd_is_link_hibern8(hba)) {
1888 err = ufs_mtk_link_set_hpm(hba);
1889 if (err)
1890 goto fail;
1891 }
1892
1893 return 0;
1894
1895 fail:
1896 /*
1897 * Check if the platform (parent) device has resumed, and ensure that
1898 * power, clock, and MTCMOS are all turned on.
1899 */
1900 err = ufshcd_link_recovery(hba);
1901 if (err) {
1902 dev_err(hba->dev, "Device PM: req=%d, status:%d, err:%d\n",
1903 hba->dev->power.request,
1904 hba->dev->power.runtime_status,
1905 hba->dev->power.runtime_error);
1906 }
1907
1908 return 0; /* Cannot return a failure, otherwise, the I/O will hang. */
1909 }
1910
ufs_mtk_dbg_register_dump(struct ufs_hba * hba)1911 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
1912 {
1913 /* Dump ufshci register 0x140 ~ 0x14C */
1914 ufshcd_dump_regs(hba, REG_UFS_XOUFS_CTRL, 0x10,
1915 "XOUFS Ctrl (0x140): ");
1916
1917 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
1918
1919 /* Dump ufshci register 0x2200 ~ 0x22AC */
1920 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
1921 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
1922 "MPHY Ctrl (0x2200): ");
1923
1924 /* Direct debugging information to REG_MTK_PROBE */
1925 ufs_mtk_dbg_sel(hba);
1926 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
1927 }
1928
ufs_mtk_apply_dev_quirks(struct ufs_hba * hba)1929 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
1930 {
1931 struct ufs_dev_info *dev_info = &hba->dev_info;
1932 u16 mid = dev_info->wmanufacturerid;
1933 unsigned int cpu;
1934
1935 if (hba->mcq_enabled) {
1936 /* Iterate all cpus to set affinity for mcq irqs */
1937 for (cpu = 0; cpu < nr_cpu_ids; cpu++)
1938 ufs_mtk_mcq_set_irq_affinity(hba, cpu);
1939 }
1940
1941 if (mid == UFS_VENDOR_SAMSUNG) {
1942 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
1943 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
1944 } else if (mid == UFS_VENDOR_MICRON) {
1945 /* Only for the host which have TX skew issue */
1946 if (ufs_mtk_is_tx_skew_fix(hba) &&
1947 (STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||
1948 STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||
1949 STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||
1950 STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||
1951 STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||
1952 STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {
1953 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);
1954 }
1955 }
1956
1957 /*
1958 * Decide waiting time before gating reference clock and
1959 * after ungating reference clock according to vendors'
1960 * requirements.
1961 */
1962 if (mid == UFS_VENDOR_SAMSUNG)
1963 ufs_mtk_setup_ref_clk_wait_us(hba, 1);
1964 else if (mid == UFS_VENDOR_SKHYNIX)
1965 ufs_mtk_setup_ref_clk_wait_us(hba, 30);
1966 else if (mid == UFS_VENDOR_TOSHIBA)
1967 ufs_mtk_setup_ref_clk_wait_us(hba, 100);
1968 else
1969 ufs_mtk_setup_ref_clk_wait_us(hba,
1970 REFCLK_DEFAULT_WAIT_US);
1971 return 0;
1972 }
1973
ufs_mtk_fixup_dev_quirks(struct ufs_hba * hba)1974 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1975 {
1976 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
1977
1978 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
1979
1980 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc) {
1981 hba->vreg_info.vcc->always_on = true;
1982 /*
1983 * VCC will be kept always-on thus we don't
1984 * need any delay before putting device's VCC in LPM mode.
1985 */
1986 hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM;
1987 }
1988
1989 /*
1990 * Add a delay after enabling UFS5 VCC to ensure the voltage
1991 * is stable before the refclk is enabled.
1992 */
1993 if (hba->dev_info.wspecversion >= 0x0500 &&
1994 (host->ip_ver == IP_VER_MT6995_A0 ||
1995 host->ip_ver == IP_VER_MT6995_B0))
1996 hba->quirks |= UFSHCD_QUIRK_VCC_ON_DELAY;
1997
1998 ufs_mtk_vreg_fix_vcc(hba);
1999 ufs_mtk_vreg_fix_vccqx(hba);
2000 ufs_mtk_fix_ahit(hba);
2001 ufs_mtk_fix_clock_scaling(hba);
2002 }
2003
ufs_mtk_event_notify(struct ufs_hba * hba,enum ufs_event_type evt,void * data)2004 static void ufs_mtk_event_notify(struct ufs_hba *hba,
2005 enum ufs_event_type evt, void *data)
2006 {
2007 unsigned int val = *(u32 *)data;
2008 unsigned long reg;
2009 u8 bit;
2010
2011 trace_ufs_mtk_event(evt, val);
2012
2013 /* Print details of UIC Errors */
2014 if (evt <= UFS_EVT_DME_ERR) {
2015 dev_info(hba->dev,
2016 "Host UIC Error Code (%s): %08x\n",
2017 ufs_uic_err_str[evt], val);
2018 reg = val;
2019 }
2020
2021 if (evt == UFS_EVT_PA_ERR) {
2022 for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str))
2023 dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]);
2024 }
2025
2026 if (evt == UFS_EVT_DL_ERR) {
2027 for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str))
2028 dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]);
2029 }
2030 }
2031
ufs_mtk_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * profile,struct devfreq_simple_ondemand_data * data)2032 static void ufs_mtk_config_scaling_param(struct ufs_hba *hba,
2033 struct devfreq_dev_profile *profile,
2034 struct devfreq_simple_ondemand_data *data)
2035 {
2036 /* Customize min gear in clk scaling */
2037 hba->clk_scaling.min_gear = UFS_HS_G4;
2038
2039 hba->vps->devfreq_profile.polling_ms = 200;
2040 hba->vps->ondemand_data.upthreshold = 50;
2041 hba->vps->ondemand_data.downdifferential = 20;
2042 }
2043
_ufs_mtk_clk_scale(struct ufs_hba * hba,bool scale_up)2044 static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
2045 {
2046 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2047 struct ufs_mtk_clk *mclk = &host->mclk;
2048 struct ufs_clk_info *clki = mclk->ufs_sel_clki;
2049 struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki;
2050 struct regulator *reg;
2051 int volt, ret = 0;
2052 bool clk_bind_vcore = false;
2053 bool clk_fde_scale = false;
2054
2055 if (!hba->clk_scaling.is_initialized)
2056 return;
2057
2058 if (!clki || !fde_clki)
2059 return;
2060
2061 reg = host->mclk.reg_vcore;
2062 volt = host->mclk.vcore_volt;
2063 if (reg && volt != 0)
2064 clk_bind_vcore = true;
2065
2066 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki)
2067 clk_fde_scale = true;
2068
2069 ret = clk_prepare_enable(clki->clk);
2070 if (ret) {
2071 dev_info(hba->dev,
2072 "clk_prepare_enable() fail, ret: %d\n", ret);
2073 return;
2074 }
2075
2076 if (clk_fde_scale) {
2077 ret = clk_prepare_enable(fde_clki->clk);
2078 if (ret) {
2079 dev_info(hba->dev,
2080 "fde clk_prepare_enable() fail, ret: %d\n", ret);
2081 return;
2082 }
2083 }
2084
2085 if (scale_up) {
2086 if (clk_bind_vcore) {
2087 ret = regulator_set_voltage(reg, volt, INT_MAX);
2088 if (ret) {
2089 dev_info(hba->dev,
2090 "Failed to set vcore to %d\n", volt);
2091 goto out;
2092 }
2093 }
2094
2095 ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk);
2096 if (ret) {
2097 dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
2098 ret);
2099 }
2100
2101 if (clk_fde_scale) {
2102 ret = clk_set_parent(fde_clki->clk,
2103 mclk->ufs_fde_max_clki->clk);
2104 if (ret) {
2105 dev_info(hba->dev,
2106 "Failed to set fde clk mux, ret = %d\n",
2107 ret);
2108 }
2109 }
2110 } else {
2111 if (clk_fde_scale) {
2112 ret = clk_set_parent(fde_clki->clk,
2113 mclk->ufs_fde_min_clki->clk);
2114 if (ret) {
2115 dev_info(hba->dev,
2116 "Failed to set fde clk mux, ret = %d\n",
2117 ret);
2118 goto out;
2119 }
2120 }
2121
2122 ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
2123 if (ret) {
2124 dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
2125 ret);
2126 goto out;
2127 }
2128
2129 if (clk_bind_vcore) {
2130 ret = regulator_set_voltage(reg, 0, INT_MAX);
2131 if (ret) {
2132 dev_info(hba->dev,
2133 "failed to set vcore to MIN\n");
2134 }
2135 }
2136 }
2137
2138 out:
2139 clk_disable_unprepare(clki->clk);
2140
2141 if (clk_fde_scale)
2142 clk_disable_unprepare(fde_clki->clk);
2143 }
2144
2145 /**
2146 * ufs_mtk_clk_scale - Internal clk scaling operation
2147 *
2148 * MTK platform supports clk scaling by switching parent of ufs_sel(mux).
2149 * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware.
2150 * Max and min clocks rate of ufs_sel defined in dts should match rate of
2151 * "ufs_sel_max_src" and "ufs_sel_min_src" respectively.
2152 * This prevent changing rate of pll clock that is shared between modules.
2153 *
2154 * @hba: per adapter instance
2155 * @scale_up: True for scaling up and false for scaling down
2156 */
ufs_mtk_clk_scale(struct ufs_hba * hba,bool scale_up)2157 static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
2158 {
2159 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2160 struct ufs_mtk_clk *mclk = &host->mclk;
2161 struct ufs_clk_info *clki = mclk->ufs_sel_clki;
2162
2163 if (host->clk_scale_up == scale_up)
2164 goto out;
2165
2166 if (scale_up)
2167 _ufs_mtk_clk_scale(hba, true);
2168 else
2169 _ufs_mtk_clk_scale(hba, false);
2170
2171 host->clk_scale_up = scale_up;
2172
2173 /* Must always set before clk_set_rate() */
2174 if (scale_up)
2175 clki->curr_freq = clki->max_freq;
2176 else
2177 clki->curr_freq = clki->min_freq;
2178 out:
2179 trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk));
2180 }
2181
ufs_mtk_clk_scale_notify(struct ufs_hba * hba,bool scale_up,unsigned long target_freq,enum ufs_notify_change_status status)2182 static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
2183 unsigned long target_freq,
2184 enum ufs_notify_change_status status)
2185 {
2186 if (!ufshcd_is_clkscaling_supported(hba))
2187 return 0;
2188
2189 if (status == PRE_CHANGE) {
2190 /* Switch parent before clk_set_rate() */
2191 ufs_mtk_clk_scale(hba, scale_up);
2192 } else {
2193 /* Request interrupt latency QoS accordingly */
2194 ufs_mtk_scale_perf(hba, scale_up);
2195 }
2196
2197 return 0;
2198 }
2199
ufs_mtk_get_hba_nortt(struct ufs_hba * hba)2200 static int ufs_mtk_get_hba_nortt(struct ufs_hba *hba)
2201 {
2202 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2203
2204 if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6995_B0)
2205 return MTK_MAX_NUM_RTT_LEGACY;
2206
2207 return FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1;
2208 }
2209
ufs_mtk_get_hba_mac(struct ufs_hba * hba)2210 static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)
2211 {
2212 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2213
2214 /* MCQ operation not permitted */
2215 if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
2216 return -EPERM;
2217
2218 return MAX_SUPP_MAC;
2219 }
2220
ufs_mtk_op_runtime_config(struct ufs_hba * hba)2221 static int ufs_mtk_op_runtime_config(struct ufs_hba *hba)
2222 {
2223 struct ufshcd_mcq_opr_info_t *opr;
2224 int i;
2225
2226 hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD;
2227 hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS;
2228 hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD;
2229 hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS;
2230
2231 for (i = 0; i < OPR_MAX; i++) {
2232 opr = &hba->mcq_opr[i];
2233 opr->stride = REG_UFS_MCQ_STRIDE;
2234 opr->base = hba->mmio_base + opr->offset;
2235 }
2236
2237 return 0;
2238 }
2239
ufs_mtk_mcq_config_resource(struct ufs_hba * hba)2240 static int ufs_mtk_mcq_config_resource(struct ufs_hba *hba)
2241 {
2242 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2243
2244 /* fail mcq initialization if interrupt is not filled properly */
2245 if (!host->mcq_nr_intr) {
2246 dev_info(hba->dev, "IRQs not ready. MCQ disabled.");
2247 return -EINVAL;
2248 }
2249
2250 hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities);
2251 return 0;
2252 }
2253
ufs_mtk_mcq_intr(int irq,void * __intr_info)2254 static irqreturn_t ufs_mtk_mcq_intr(int irq, void *__intr_info)
2255 {
2256 struct ufs_mtk_mcq_intr_info *mcq_intr_info = __intr_info;
2257 struct ufs_hba *hba = mcq_intr_info->hba;
2258 struct ufs_hw_queue *hwq;
2259 u32 events;
2260 int qid = mcq_intr_info->qid;
2261
2262 hwq = &hba->uhq[qid];
2263
2264 events = ufshcd_mcq_read_cqis(hba, qid);
2265 if (events)
2266 ufshcd_mcq_write_cqis(hba, events, qid);
2267
2268 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
2269 ufshcd_mcq_poll_cqe_lock(hba, hwq);
2270
2271 return IRQ_HANDLED;
2272 }
2273
ufs_mtk_config_mcq_irq(struct ufs_hba * hba)2274 static int ufs_mtk_config_mcq_irq(struct ufs_hba *hba)
2275 {
2276 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2277 u32 irq, i;
2278 int ret;
2279
2280 for (i = 0; i < host->mcq_nr_intr; i++) {
2281 irq = host->mcq_intr_info[i].irq;
2282 if (irq == MTK_MCQ_INVALID_IRQ) {
2283 dev_err(hba->dev, "invalid irq. %d\n", i);
2284 return -ENOPARAM;
2285 }
2286
2287 host->mcq_intr_info[i].qid = i;
2288 ret = devm_request_irq(hba->dev, irq, ufs_mtk_mcq_intr, 0, UFSHCD,
2289 &host->mcq_intr_info[i]);
2290
2291 dev_dbg(hba->dev, "request irq %d intr %s\n", irq, ret ? "failed" : "");
2292
2293 if (ret)
2294 return ret;
2295 }
2296 host->is_mcq_intr_enabled = true;
2297
2298 return 0;
2299 }
2300
ufs_mtk_config_mcq(struct ufs_hba * hba,bool irq)2301 static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq)
2302 {
2303 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2304 int ret = 0;
2305
2306 if (!host->mcq_set_intr) {
2307 /* Disable irq option register */
2308 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0);
2309
2310 if (irq) {
2311 ret = ufs_mtk_config_mcq_irq(hba);
2312 if (ret)
2313 return ret;
2314 }
2315
2316 host->mcq_set_intr = true;
2317 }
2318
2319 ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0);
2320 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0);
2321
2322 return 0;
2323 }
2324
ufs_mtk_config_esi(struct ufs_hba * hba)2325 static int ufs_mtk_config_esi(struct ufs_hba *hba)
2326 {
2327 return ufs_mtk_config_mcq(hba, true);
2328 }
2329
ufs_mtk_config_scsi_dev(struct scsi_device * sdev)2330 static void ufs_mtk_config_scsi_dev(struct scsi_device *sdev)
2331 {
2332 struct ufs_hba *hba = shost_priv(sdev->host);
2333
2334 dev_dbg(hba->dev, "lu %llu scsi device configured", sdev->lun);
2335 if (sdev->lun == 2)
2336 blk_queue_flag_set(QUEUE_FLAG_SAME_FORCE, sdev->request_queue);
2337 }
2338
2339 /*
2340 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
2341 *
2342 * The variant operations configure the necessary controller and PHY
2343 * handshake during initialization.
2344 */
2345 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
2346 .name = "mediatek.ufshci",
2347 .init = ufs_mtk_init,
2348 .get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
2349 .setup_clocks = ufs_mtk_setup_clocks,
2350 .hce_enable_notify = ufs_mtk_hce_enable_notify,
2351 .link_startup_notify = ufs_mtk_link_startup_notify,
2352 .negotiate_pwr_mode = ufs_mtk_negotiate_pwr_mode,
2353 .pwr_change_notify = ufs_mtk_pwr_change_notify,
2354 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
2355 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
2356 .suspend = ufs_mtk_suspend,
2357 .resume = ufs_mtk_resume,
2358 .dbg_register_dump = ufs_mtk_dbg_register_dump,
2359 .device_reset = ufs_mtk_device_reset,
2360 .event_notify = ufs_mtk_event_notify,
2361 .config_scaling_param = ufs_mtk_config_scaling_param,
2362 .clk_scale_notify = ufs_mtk_clk_scale_notify,
2363 .get_hba_nortt = ufs_mtk_get_hba_nortt,
2364 /* mcq vops */
2365 .get_hba_mac = ufs_mtk_get_hba_mac,
2366 .op_runtime_config = ufs_mtk_op_runtime_config,
2367 .mcq_config_resource = ufs_mtk_mcq_config_resource,
2368 .config_esi = ufs_mtk_config_esi,
2369 .config_scsi_dev = ufs_mtk_config_scsi_dev,
2370 };
2371
2372 /**
2373 * ufs_mtk_probe - probe routine of the driver
2374 * @pdev: pointer to Platform device handle
2375 *
2376 * Return: zero for success and non-zero for failure.
2377 */
ufs_mtk_probe(struct platform_device * pdev)2378 static int ufs_mtk_probe(struct platform_device *pdev)
2379 {
2380 int err;
2381 struct device *dev = &pdev->dev, *phy_dev = NULL;
2382 struct device_node *reset_node, *phy_node = NULL;
2383 struct platform_device *reset_pdev, *phy_pdev = NULL;
2384 struct device_link *link;
2385 struct ufs_hba *hba;
2386 struct ufs_mtk_host *host;
2387
2388 reset_node = of_find_compatible_node(NULL, NULL,
2389 "ti,syscon-reset");
2390 if (!reset_node) {
2391 dev_notice(dev, "find ti,syscon-reset fail\n");
2392 goto skip_reset;
2393 }
2394 reset_pdev = of_find_device_by_node(reset_node);
2395 if (!reset_pdev) {
2396 dev_notice(dev, "find reset_pdev fail\n");
2397 goto skip_reset;
2398 }
2399 link = device_link_add(dev, &reset_pdev->dev,
2400 DL_FLAG_AUTOPROBE_CONSUMER);
2401 put_device(&reset_pdev->dev);
2402 if (!link) {
2403 dev_notice(dev, "add reset device_link fail\n");
2404 goto skip_reset;
2405 }
2406 /* supplier is not probed */
2407 if (link->status == DL_STATE_DORMANT) {
2408 err = -EPROBE_DEFER;
2409 goto out;
2410 }
2411
2412 skip_reset:
2413 /* find phy node */
2414 phy_node = of_parse_phandle(dev->of_node, "phys", 0);
2415
2416 if (phy_node) {
2417 phy_pdev = of_find_device_by_node(phy_node);
2418 if (!phy_pdev)
2419 goto skip_phy;
2420 phy_dev = &phy_pdev->dev;
2421
2422 pm_runtime_set_active(phy_dev);
2423 pm_runtime_enable(phy_dev);
2424 pm_runtime_get_sync(phy_dev);
2425
2426 put_device(phy_dev);
2427 dev_info(dev, "phys node found\n");
2428 } else {
2429 dev_notice(dev, "phys node not found\n");
2430 }
2431
2432 skip_phy:
2433 /* perform generic probe */
2434 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
2435 if (err) {
2436 dev_err(dev, "probe failed %d\n", err);
2437 goto out;
2438 }
2439
2440 hba = platform_get_drvdata(pdev);
2441 if (!hba)
2442 goto out;
2443
2444 if (phy_node && phy_dev) {
2445 host = ufshcd_get_variant(hba);
2446 host->phy_dev = phy_dev;
2447 }
2448
2449 /*
2450 * Because the default power setting of VSx (the upper layer of
2451 * VCCQ/VCCQ2) is HWLP, we need to prevent VCCQ/VCCQ2 from
2452 * entering LPM.
2453 */
2454 ufs_mtk_dev_vreg_set_lpm(hba, false);
2455
2456 out:
2457 of_node_put(phy_node);
2458 of_node_put(reset_node);
2459 return err;
2460 }
2461
2462 /**
2463 * ufs_mtk_remove - set driver_data of the device to NULL
2464 * @pdev: pointer to platform device handle
2465 *
2466 * Always return 0
2467 */
ufs_mtk_remove(struct platform_device * pdev)2468 static void ufs_mtk_remove(struct platform_device *pdev)
2469 {
2470 ufshcd_pltfrm_remove(pdev);
2471 }
2472
ufs_mtk_system_suspend(struct device * dev)2473 static int ufs_mtk_system_suspend(struct device *dev)
2474 {
2475 struct ufs_hba *hba = dev_get_drvdata(dev);
2476 struct arm_smccc_res res;
2477 int ret;
2478
2479 if (hba->shutting_down) {
2480 ret = -EBUSY;
2481 goto out;
2482 }
2483
2484 ret = ufshcd_system_suspend(dev);
2485 if (ret)
2486 goto out;
2487
2488 if (pm_runtime_suspended(hba->dev))
2489 goto out;
2490
2491 ufs_mtk_dev_vreg_set_lpm(hba, true);
2492
2493 if (ufs_mtk_is_rtff_mtcmos(hba))
2494 ufs_mtk_mtcmos_ctrl(false, res);
2495
2496 out:
2497 return ret;
2498 }
2499
ufs_mtk_system_resume(struct device * dev)2500 static int ufs_mtk_system_resume(struct device *dev)
2501 {
2502 int ret = 0;
2503 struct ufs_hba *hba = dev_get_drvdata(dev);
2504 struct arm_smccc_res res;
2505
2506 if (pm_runtime_suspended(hba->dev))
2507 goto out;
2508
2509 if (ufs_mtk_is_rtff_mtcmos(hba))
2510 ufs_mtk_mtcmos_ctrl(true, res);
2511
2512 ufs_mtk_dev_vreg_set_lpm(hba, false);
2513
2514 out:
2515 ret = ufshcd_system_resume(dev);
2516
2517 return ret;
2518 }
2519
ufs_mtk_runtime_suspend(struct device * dev)2520 static int ufs_mtk_runtime_suspend(struct device *dev)
2521 {
2522 struct ufs_hba *hba = dev_get_drvdata(dev);
2523 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2524 struct arm_smccc_res res;
2525 int ret = 0;
2526
2527 ret = ufshcd_runtime_suspend(dev);
2528 if (ret)
2529 return ret;
2530
2531 ufs_mtk_dev_vreg_set_lpm(hba, true);
2532
2533 if (ufs_mtk_is_rtff_mtcmos(hba))
2534 ufs_mtk_mtcmos_ctrl(false, res);
2535
2536 if (host->phy_dev)
2537 pm_runtime_put_sync(host->phy_dev);
2538
2539 return 0;
2540 }
2541
ufs_mtk_runtime_resume(struct device * dev)2542 static int ufs_mtk_runtime_resume(struct device *dev)
2543 {
2544 struct ufs_hba *hba = dev_get_drvdata(dev);
2545 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
2546 struct arm_smccc_res res;
2547
2548 if (ufs_mtk_is_rtff_mtcmos(hba))
2549 ufs_mtk_mtcmos_ctrl(true, res);
2550
2551 if (host->phy_dev)
2552 pm_runtime_get_sync(host->phy_dev);
2553
2554 ufs_mtk_dev_vreg_set_lpm(hba, false);
2555
2556 return ufshcd_runtime_resume(dev);
2557 }
2558
2559 static const struct dev_pm_ops ufs_mtk_pm_ops = {
2560 SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend, ufs_mtk_system_resume)
2561 RUNTIME_PM_OPS(ufs_mtk_runtime_suspend, ufs_mtk_runtime_resume, NULL)
2562 .prepare = ufshcd_suspend_prepare,
2563 .complete = ufshcd_resume_complete,
2564 };
2565
2566 static struct platform_driver ufs_mtk_pltform = {
2567 .probe = ufs_mtk_probe,
2568 .remove = ufs_mtk_remove,
2569 .driver = {
2570 .name = "ufshcd-mtk",
2571 .pm = pm_ptr(&ufs_mtk_pm_ops),
2572 .of_match_table = ufs_mtk_of_match,
2573 },
2574 };
2575
2576 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
2577 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
2578 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
2579 MODULE_LICENSE("GPL v2");
2580
2581 module_platform_driver(ufs_mtk_pltform);
2582