1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: Main component of the bnxt_re driver
37 */
38
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57 #include <linux/hashtable.h>
58 #include <linux/bnxt/ulp.h>
59
60 #include "roce_hsi.h"
61 #include "qplib_res.h"
62 #include "qplib_sp.h"
63 #include "qplib_fp.h"
64 #include "qplib_rcfw.h"
65 #include "bnxt_re.h"
66 #include "ib_verbs.h"
67 #include <rdma/bnxt_re-abi.h>
68 #include "bnxt.h"
69 #include "hw_counters.h"
70 #include "debugfs.h"
71
72 static char version[] =
73 BNXT_RE_DESC "\n";
74
75 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
76 MODULE_DESCRIPTION(BNXT_RE_DESC);
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 /* globals */
80 static DEFINE_MUTEX(bnxt_re_mutex);
81
82 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev);
83 static int bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev);
84
85 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
86 u32 *offset);
87 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
88 u8 port_num, enum ib_event_type event);
bnxt_re_set_db_offset(struct bnxt_re_dev * rdev)89 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
90 {
91 struct bnxt_qplib_chip_ctx *cctx;
92 struct bnxt_en_dev *en_dev;
93 struct bnxt_qplib_res *res;
94 u32 l2db_len = 0;
95 u32 offset = 0;
96 u32 barlen;
97 int rc;
98
99 res = &rdev->qplib_res;
100 en_dev = rdev->en_dev;
101 cctx = rdev->chip_ctx;
102
103 /* Issue qcfg */
104 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset);
105 if (rc)
106 dev_info(rdev_to_dev(rdev),
107 "Couldn't get DB bar size, Low latency framework is disabled\n");
108 /* set register offsets for both UC and WC */
109 if (bnxt_qplib_is_chip_gen_p7(cctx)) {
110 res->dpi_tbl.ucreg.offset = offset;
111 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
112 } else {
113 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
114 BNXT_QPLIB_DBR_PF_DB_OFFSET;
115 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
116 }
117
118 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
119 * is equal to the DB-Bar actual size. This indicates that L2
120 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping
121 * in such cases and DB-push will be disabled.
122 */
123 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION);
124 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) {
125 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size;
126 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n");
127 }
128 }
129
bnxt_re_set_drv_mode(struct bnxt_re_dev * rdev)130 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev)
131 {
132 struct bnxt_qplib_chip_ctx *cctx;
133
134 cctx = rdev->chip_ctx;
135 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ?
136 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC;
137 if (bnxt_re_hwrm_qcaps(rdev))
138 dev_err(rdev_to_dev(rdev),
139 "Failed to query hwrm qcaps\n");
140 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) {
141 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;
142 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT;
143 }
144 }
145
bnxt_re_destroy_chip_ctx(struct bnxt_re_dev * rdev)146 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
147 {
148 struct bnxt_qplib_chip_ctx *chip_ctx;
149
150 if (!rdev->chip_ctx)
151 return;
152
153 kfree(rdev->dev_attr);
154 rdev->dev_attr = NULL;
155
156 chip_ctx = rdev->chip_ctx;
157 rdev->chip_ctx = NULL;
158 rdev->rcfw.res = NULL;
159 rdev->qplib_res.cctx = NULL;
160 rdev->qplib_res.pdev = NULL;
161 rdev->qplib_res.netdev = NULL;
162 kfree(chip_ctx);
163 }
164
bnxt_re_setup_chip_ctx(struct bnxt_re_dev * rdev)165 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev)
166 {
167 struct bnxt_qplib_chip_ctx *chip_ctx;
168 struct bnxt_en_dev *en_dev;
169 int rc = -ENOMEM;
170
171 en_dev = rdev->en_dev;
172
173 rdev->qplib_res.pdev = en_dev->pdev;
174 chip_ctx = kzalloc_obj(*chip_ctx);
175 if (!chip_ctx)
176 return -ENOMEM;
177 chip_ctx->chip_num = en_dev->chip_num;
178 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
179
180 rdev->chip_ctx = chip_ctx;
181 /* rest members to follow eventually */
182
183 rdev->qplib_res.cctx = rdev->chip_ctx;
184 rdev->rcfw.res = &rdev->qplib_res;
185 rdev->dev_attr = kzalloc_obj(*rdev->dev_attr);
186 if (!rdev->dev_attr)
187 goto free_chip_ctx;
188 rdev->qplib_res.dattr = rdev->dev_attr;
189 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
190 rdev->qplib_res.en_dev = en_dev;
191
192 rc = bnxt_re_query_hwrm_intf_version(rdev);
193 if (rc)
194 goto free_dev_attr;
195
196 bnxt_re_set_drv_mode(rdev);
197
198 bnxt_re_set_db_offset(rdev);
199 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res);
200 if (rc)
201 goto free_dev_attr;
202
203 if (bnxt_qplib_determine_atomics(en_dev->pdev))
204 ibdev_info(&rdev->ibdev,
205 "platform doesn't support global atomics.");
206 return 0;
207 free_dev_attr:
208 kfree(rdev->dev_attr);
209 rdev->dev_attr = NULL;
210 free_chip_ctx:
211 kfree(rdev->chip_ctx);
212 rdev->chip_ctx = NULL;
213 return rc;
214 }
215
216 /* SR-IOV helper functions */
217
bnxt_re_get_sriov_func_type(struct bnxt_re_dev * rdev)218 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
219 {
220 if (BNXT_EN_VF(rdev->en_dev))
221 rdev->is_virtfn = 1;
222 }
223
224 /* Set the maximum number of each resource that the driver actually wants
225 * to allocate. This may be up to the maximum number the firmware has
226 * reserved for the function. The driver may choose to allocate fewer
227 * resources than the firmware maximum.
228 */
bnxt_re_limit_pf_res(struct bnxt_re_dev * rdev)229 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
230 {
231 struct bnxt_qplib_dev_attr *attr;
232 struct bnxt_qplib_ctx *ctx;
233 int i;
234
235 attr = rdev->dev_attr;
236 ctx = &rdev->qplib_ctx;
237
238 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
239 attr->max_qp);
240 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
241 /* Use max_mr from fw since max_mrw does not get set */
242 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
243 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
244 attr->max_srq);
245 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
246 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
247 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
248 rdev->qplib_ctx.tqm_ctx.qcount[i] =
249 rdev->dev_attr->tqm_alloc_reqs[i];
250 }
251
bnxt_re_limit_vf_res(struct bnxt_qplib_ctx * qplib_ctx,u32 num_vf)252 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
253 {
254 struct bnxt_qplib_vf_res *vf_res;
255 u32 mrws = 0;
256 u32 vf_pct;
257 u32 nvfs;
258
259 vf_res = &qplib_ctx->vf_res;
260 /*
261 * Reserve a set of resources for the PF. Divide the remaining
262 * resources among the VFs
263 */
264 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
265 nvfs = num_vf;
266 num_vf = 100 * num_vf;
267 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
268 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
269 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
270 /*
271 * The driver allows many more MRs than other resources. If the
272 * firmware does also, then reserve a fixed amount for the PF and
273 * divide the rest among VFs. VFs may use many MRs for NFS
274 * mounts, ISER, NVME applications, etc. If the firmware severely
275 * restricts the number of MRs, then let PF have half and divide
276 * the rest among VFs, as for the other resource types.
277 */
278 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
279 mrws = qplib_ctx->mrw_count * vf_pct;
280 nvfs = num_vf;
281 } else {
282 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
283 }
284 vf_res->max_mrw_per_vf = (mrws / nvfs);
285 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
286 }
287
bnxt_re_set_resource_limits(struct bnxt_re_dev * rdev)288 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
289 {
290 u32 num_vfs;
291
292 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
293 bnxt_re_limit_pf_res(rdev);
294
295 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
296 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
297 if (num_vfs)
298 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
299 }
300
bnxt_re_vf_res_config(struct bnxt_re_dev * rdev)301 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
302 {
303 /*
304 * Use the total VF count since the actual VF count may not be
305 * available at this point.
306 */
307 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
308 if (!rdev->num_vfs)
309 return;
310
311 bnxt_re_set_resource_limits(rdev);
312 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
313 &rdev->qplib_ctx);
314 }
315
316 struct bnxt_re_dcb_work {
317 struct work_struct work;
318 struct bnxt_re_dev *rdev;
319 struct hwrm_async_event_cmpl cmpl;
320 };
321
bnxt_re_is_qp1_qp(struct bnxt_re_qp * qp)322 static bool bnxt_re_is_qp1_qp(struct bnxt_re_qp *qp)
323 {
324 return qp->ib_qp.qp_type == IB_QPT_GSI;
325 }
326
bnxt_re_get_qp1_qp(struct bnxt_re_dev * rdev)327 static struct bnxt_re_qp *bnxt_re_get_qp1_qp(struct bnxt_re_dev *rdev)
328 {
329 struct bnxt_re_qp *qp;
330
331 mutex_lock(&rdev->qp_lock);
332 list_for_each_entry(qp, &rdev->qp_list, list) {
333 if (bnxt_re_is_qp1_qp(qp)) {
334 mutex_unlock(&rdev->qp_lock);
335 return qp;
336 }
337 }
338 mutex_unlock(&rdev->qp_lock);
339 return NULL;
340 }
341
bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev * rdev)342 static int bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev *rdev)
343 {
344 struct bnxt_re_qp *qp;
345
346 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
347 return 0;
348
349 qp = bnxt_re_get_qp1_qp(rdev);
350 if (!qp)
351 return 0;
352
353 qp->qplib_qp.modify_flags = CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP;
354 qp->qplib_qp.tos_dscp = rdev->cc_param.qp1_tos_dscp;
355
356 return bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
357 }
358
bnxt_re_init_dcb_wq(struct bnxt_re_dev * rdev)359 static int bnxt_re_init_dcb_wq(struct bnxt_re_dev *rdev)
360 {
361 rdev->dcb_wq = create_singlethread_workqueue("bnxt_re_dcb_wq");
362 if (!rdev->dcb_wq)
363 return -ENOMEM;
364
365 return 0;
366 }
367
bnxt_re_uninit_dcb_wq(struct bnxt_re_dev * rdev)368 static void bnxt_re_uninit_dcb_wq(struct bnxt_re_dev *rdev)
369 {
370 if (!rdev->dcb_wq)
371 return;
372 destroy_workqueue(rdev->dcb_wq);
373 }
374
bnxt_re_dcb_wq_task(struct work_struct * work)375 static void bnxt_re_dcb_wq_task(struct work_struct *work)
376 {
377 struct bnxt_re_dcb_work *dcb_work =
378 container_of(work, struct bnxt_re_dcb_work, work);
379 struct bnxt_re_dev *rdev = dcb_work->rdev;
380 struct bnxt_qplib_cc_param *cc_param;
381 int rc;
382
383 if (!rdev)
384 goto free_dcb;
385
386 cc_param = &rdev->cc_param;
387 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, cc_param);
388 if (rc) {
389 ibdev_dbg(&rdev->ibdev, "Failed to query ccparam rc:%d", rc);
390 goto free_dcb;
391 }
392 if (cc_param->qp1_tos_dscp != cc_param->tos_dscp) {
393 cc_param->qp1_tos_dscp = cc_param->tos_dscp;
394 rc = bnxt_re_update_qp1_tos_dscp(rdev);
395 if (rc) {
396 ibdev_dbg(&rdev->ibdev, "%s: Failed to modify QP1 rc:%d",
397 __func__, rc);
398 goto free_dcb;
399 }
400 }
401
402 free_dcb:
403 kfree(dcb_work);
404 }
405
bnxt_re_async_notifier(void * handle,struct hwrm_async_event_cmpl * cmpl)406 static void bnxt_re_async_notifier(void *handle, struct hwrm_async_event_cmpl *cmpl)
407 {
408 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
409 struct bnxt_re_dcb_work *dcb_work;
410 struct bnxt_re_dev *rdev;
411 u32 data1, data2;
412 u16 event_id;
413
414 rdev = en_info->rdev;
415 if (!rdev)
416 return;
417
418 event_id = le16_to_cpu(cmpl->event_id);
419 data1 = le32_to_cpu(cmpl->event_data1);
420 data2 = le32_to_cpu(cmpl->event_data2);
421
422 ibdev_dbg(&rdev->ibdev, "Async event_id = %d data1 = %d data2 = %d",
423 event_id, data1, data2);
424
425 switch (event_id) {
426 case ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE:
427 dcb_work = kzalloc_obj(*dcb_work, GFP_ATOMIC);
428 if (!dcb_work)
429 break;
430
431 dcb_work->rdev = rdev;
432 memcpy(&dcb_work->cmpl, cmpl, sizeof(*cmpl));
433 INIT_WORK(&dcb_work->work, bnxt_re_dcb_wq_task);
434 queue_work(rdev->dcb_wq, &dcb_work->work);
435 break;
436 default:
437 break;
438 }
439 }
440
bnxt_re_stop_irq(void * handle,bool reset)441 static void bnxt_re_stop_irq(void *handle, bool reset)
442 {
443 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
444 struct bnxt_qplib_rcfw *rcfw;
445 struct bnxt_re_dev *rdev;
446 struct bnxt_qplib_nq *nq;
447 int indx;
448
449 rdev = en_info->rdev;
450 if (!rdev)
451 return;
452 rcfw = &rdev->rcfw;
453
454 if (reset) {
455 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
456 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
457 wake_up_all(&rdev->rcfw.cmdq.waitq);
458 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
459 IB_EVENT_DEVICE_FATAL);
460 }
461
462 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) {
463 nq = &rdev->nqr->nq[indx - 1];
464 bnxt_qplib_nq_stop_irq(nq, false);
465 }
466
467 bnxt_qplib_rcfw_stop_irq(rcfw, false);
468 }
469
bnxt_re_start_irq(void * handle,struct bnxt_msix_entry * ent)470 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
471 {
472 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle);
473 struct bnxt_msix_entry *msix_ent;
474 struct bnxt_qplib_rcfw *rcfw;
475 struct bnxt_re_dev *rdev;
476 struct bnxt_qplib_nq *nq;
477 int indx, rc;
478
479 rdev = en_info->rdev;
480 if (!rdev)
481 return;
482 msix_ent = rdev->nqr->msix_entries;
483 rcfw = &rdev->rcfw;
484 if (!ent) {
485 /* Not setting the f/w timeout bit in rcfw.
486 * During the driver unload the first command
487 * to f/w will timeout and that will set the
488 * timeout bit.
489 */
490 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
491 return;
492 }
493
494 /* Vectors may change after restart, so update with new vectors
495 * in device sctructure.
496 */
497 for (indx = 0; indx < rdev->nqr->num_msix; indx++)
498 rdev->nqr->msix_entries[indx].vector = ent[indx].vector;
499
500 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
501 false);
502 if (rc) {
503 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n");
504 return;
505 }
506 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->nqr->num_msix; indx++) {
507 nq = &rdev->nqr->nq[indx - 1];
508 rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
509 msix_ent[indx].vector, false);
510 if (rc) {
511 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
512 indx - 1);
513 return;
514 }
515 }
516 }
517
518 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
519 .ulp_async_notifier = bnxt_re_async_notifier,
520 .ulp_irq_stop = bnxt_re_stop_irq,
521 .ulp_irq_restart = bnxt_re_start_irq
522 };
523
524 /* RoCE -> Net driver */
525
bnxt_re_register_netdev(struct bnxt_re_dev * rdev)526 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
527 {
528 struct bnxt_en_dev *en_dev;
529
530 en_dev = rdev->en_dev;
531 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev);
532 }
533
bnxt_re_init_hwrm_hdr(struct input * hdr,u16 opcd)534 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd)
535 {
536 hdr->req_type = cpu_to_le16(opcd);
537 hdr->cmpl_ring = cpu_to_le16(-1);
538 hdr->target_id = cpu_to_le16(-1);
539 }
540
bnxt_re_fill_fw_msg(struct bnxt_fw_msg * fw_msg,void * msg,int msg_len,void * resp,int resp_max_len,int timeout)541 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
542 int msg_len, void *resp, int resp_max_len,
543 int timeout)
544 {
545 fw_msg->msg = msg;
546 fw_msg->msg_len = msg_len;
547 fw_msg->resp = resp;
548 fw_msg->resp_max_len = resp_max_len;
549 fw_msg->timeout = timeout;
550 }
551
bnxt_re_hwrm_free_vnic(struct bnxt_re_dev * rdev)552 void bnxt_re_hwrm_free_vnic(struct bnxt_re_dev *rdev)
553 {
554 struct bnxt_en_dev *en_dev = rdev->en_dev;
555 struct hwrm_vnic_free_input req = {};
556 struct bnxt_fw_msg fw_msg = {};
557 int rc;
558
559 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VNIC_FREE);
560
561 req.vnic_id = cpu_to_le32(rdev->mirror_vnic_id);
562 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), NULL,
563 0, BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
564 rc = bnxt_send_msg(en_dev, &fw_msg);
565 if (rc)
566 ibdev_dbg(&rdev->ibdev,
567 "Failed to free vnic, rc = %d\n", rc);
568 }
569
bnxt_re_hwrm_alloc_vnic(struct bnxt_re_dev * rdev)570 int bnxt_re_hwrm_alloc_vnic(struct bnxt_re_dev *rdev)
571 {
572 struct bnxt_en_dev *en_dev = rdev->en_dev;
573 struct hwrm_vnic_alloc_output resp = {};
574 struct hwrm_vnic_alloc_input req = {};
575 struct bnxt_fw_msg fw_msg = {};
576 int rc;
577
578 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VNIC_ALLOC);
579
580 req.vnic_id = cpu_to_le16(rdev->mirror_vnic_id);
581 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID);
582 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
583 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
584 rc = bnxt_send_msg(en_dev, &fw_msg);
585 if (rc)
586 ibdev_dbg(&rdev->ibdev,
587 "Failed to alloc vnic, rc = %d\n", rc);
588
589 return rc;
590 }
591
bnxt_re_hwrm_cfg_vnic(struct bnxt_re_dev * rdev,u32 qp_id)592 int bnxt_re_hwrm_cfg_vnic(struct bnxt_re_dev *rdev, u32 qp_id)
593 {
594 struct bnxt_en_dev *en_dev = rdev->en_dev;
595 struct hwrm_vnic_cfg_input req = {};
596 struct bnxt_fw_msg fw_msg = {};
597 int rc;
598
599 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VNIC_CFG);
600
601 req.flags = cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE);
602 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_QP_ID |
603 VNIC_CFG_REQ_ENABLES_MRU);
604 req.vnic_id = cpu_to_le16(rdev->mirror_vnic_id);
605 req.qp_id = cpu_to_le32(qp_id);
606 req.mru = cpu_to_le16(rdev->netdev->mtu + VLAN_ETH_HLEN);
607
608 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), NULL,
609 0, BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
610 rc = bnxt_send_msg(en_dev, &fw_msg);
611 if (rc)
612 ibdev_dbg(&rdev->ibdev,
613 "Failed to cfg vnic, rc = %d\n", rc);
614
615 return rc;
616 }
617
618 /* Query device config using common hwrm */
bnxt_re_hwrm_qcfg(struct bnxt_re_dev * rdev,u32 * db_len,u32 * offset)619 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len,
620 u32 *offset)
621 {
622 struct bnxt_en_dev *en_dev = rdev->en_dev;
623 struct hwrm_func_qcfg_output resp = {0};
624 struct hwrm_func_qcfg_input req = {0};
625 struct bnxt_fw_msg fw_msg = {};
626 int rc;
627
628 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG);
629 req.fid = cpu_to_le16(0xffff);
630 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
631 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
632 rc = bnxt_send_msg(en_dev, &fw_msg);
633 if (!rc) {
634 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024);
635 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024);
636 rdev->mirror_vnic_id = le16_to_cpu(resp.mirror_vnic_id);
637 }
638 return rc;
639 }
640
641 /* Query function capabilities using common hwrm */
bnxt_re_hwrm_qcaps(struct bnxt_re_dev * rdev)642 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev)
643 {
644 struct bnxt_en_dev *en_dev = rdev->en_dev;
645 struct hwrm_func_qcaps_output resp = {};
646 struct hwrm_func_qcaps_input req = {};
647 struct bnxt_qplib_chip_ctx *cctx;
648 struct bnxt_fw_msg fw_msg = {};
649 u32 flags_ext2;
650 int rc;
651
652 cctx = rdev->chip_ctx;
653 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS);
654 req.fid = cpu_to_le16(0xffff);
655 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
656 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
657
658 rc = bnxt_send_msg(en_dev, &fw_msg);
659 if (rc)
660 return rc;
661 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE;
662
663 flags_ext2 = le32_to_cpu(resp.flags_ext2);
664 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED ||
665 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED;
666 cctx->modes.roce_mirror = !!(le32_to_cpu(resp.flags_ext3) &
667 FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED);
668 return 0;
669 }
670
bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev * rdev)671 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev)
672 {
673 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
674 struct hwrm_func_dbr_pacing_qcfg_output resp = {};
675 struct hwrm_func_dbr_pacing_qcfg_input req = {};
676 struct bnxt_en_dev *en_dev = rdev->en_dev;
677 struct bnxt_qplib_chip_ctx *cctx;
678 struct bnxt_fw_msg fw_msg = {};
679 int rc;
680
681 cctx = rdev->chip_ctx;
682 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG);
683 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
684 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
685 rc = bnxt_send_msg(en_dev, &fw_msg);
686 if (rc)
687 return rc;
688
689 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
690 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) ==
691 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC)
692 cctx->dbr_stat_db_fifo =
693 le32_to_cpu(resp.dbr_stat_db_fifo_reg) &
694 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK;
695
696 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth);
697 if (!pacing_data->fifo_max_depth)
698 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx);
699 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask);
700 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift;
701
702 return 0;
703 }
704
705 /* Update the pacing tunable parameters to the default values */
bnxt_re_set_default_pacing_data(struct bnxt_re_dev * rdev)706 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev)
707 {
708 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
709
710 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing;
711 pacing_data->pacing_th = rdev->pacing.pacing_algo_th;
712 pacing_data->alarm_th =
713 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
714 }
715
__get_fifo_occupancy(struct bnxt_re_dev * rdev)716 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev)
717 {
718 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
719 u32 read_val, fifo_occup;
720
721 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off);
722 fifo_occup = pacing_data->fifo_max_depth -
723 ((read_val & pacing_data->fifo_room_mask) >>
724 pacing_data->fifo_room_shift);
725 return fifo_occup;
726 }
727
is_dbr_fifo_full(struct bnxt_re_dev * rdev)728 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev)
729 {
730 u32 max_occup, fifo_occup;
731
732 fifo_occup = __get_fifo_occupancy(rdev);
733 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1;
734 if (fifo_occup == max_occup)
735 return true;
736
737 return false;
738 }
739
__wait_for_fifo_occupancy_below_th(struct bnxt_re_dev * rdev)740 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev)
741 {
742 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data;
743 u32 retry_fifo_check = 1000;
744 u32 fifo_occup;
745
746 /* loop shouldn't run infintely as the occupancy usually goes
747 * below pacing algo threshold as soon as pacing kicks in.
748 */
749 while (1) {
750 fifo_occup = __get_fifo_occupancy(rdev);
751 /* Fifo occupancy cannot be greater the MAX FIFO depth */
752 if (fifo_occup > pacing_data->fifo_max_depth)
753 break;
754
755 if (fifo_occup < pacing_data->pacing_th)
756 break;
757 if (!retry_fifo_check--) {
758 dev_info_once(rdev_to_dev(rdev),
759 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n",
760 __func__, fifo_occup, pacing_data->fifo_max_depth,
761 pacing_data->pacing_th);
762 break;
763 }
764
765 }
766 }
767
bnxt_re_db_fifo_check(struct work_struct * work)768 static void bnxt_re_db_fifo_check(struct work_struct *work)
769 {
770 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
771 dbq_fifo_check_work);
772 struct bnxt_qplib_db_pacing_data *pacing_data;
773 u32 pacing_save;
774
775 if (!mutex_trylock(&rdev->pacing.dbq_lock))
776 return;
777 pacing_data = rdev->qplib_res.pacing_data;
778 pacing_save = rdev->pacing.do_pacing_save;
779 __wait_for_fifo_occupancy_below_th(rdev);
780 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
781 if (pacing_save > rdev->pacing.dbr_def_do_pacing) {
782 /* Double the do_pacing value during the congestion */
783 pacing_save = pacing_save << 1;
784 } else {
785 /*
786 * when a new congestion is detected increase the do_pacing
787 * by 8 times. And also increase the pacing_th by 4 times. The
788 * reason to increase pacing_th is to give more space for the
789 * queue to oscillate down without getting empty, but also more
790 * room for the queue to increase without causing another alarm.
791 */
792 pacing_save = pacing_save << 3;
793 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4;
794 }
795
796 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING)
797 pacing_save = BNXT_RE_MAX_DBR_DO_PACING;
798
799 pacing_data->do_pacing = pacing_save;
800 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
801 pacing_data->alarm_th =
802 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE;
803 schedule_delayed_work(&rdev->dbq_pacing_work,
804 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
805 rdev->stats.pacing.alerts++;
806 mutex_unlock(&rdev->pacing.dbq_lock);
807 }
808
bnxt_re_pacing_timer_exp(struct work_struct * work)809 static void bnxt_re_pacing_timer_exp(struct work_struct *work)
810 {
811 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
812 dbq_pacing_work.work);
813 struct bnxt_qplib_db_pacing_data *pacing_data;
814 u32 fifo_occup;
815
816 if (!mutex_trylock(&rdev->pacing.dbq_lock))
817 return;
818
819 pacing_data = rdev->qplib_res.pacing_data;
820 fifo_occup = __get_fifo_occupancy(rdev);
821
822 if (fifo_occup > pacing_data->pacing_th)
823 goto restart_timer;
824
825 /*
826 * Instead of immediately going back to the default do_pacing
827 * reduce it by 1/8 times and restart the timer.
828 */
829 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3);
830 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing);
831 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) {
832 bnxt_re_set_default_pacing_data(rdev);
833 rdev->stats.pacing.complete++;
834 goto dbq_unlock;
835 }
836
837 restart_timer:
838 schedule_delayed_work(&rdev->dbq_pacing_work,
839 msecs_to_jiffies(rdev->pacing.dbq_pacing_time));
840 rdev->stats.pacing.resched++;
841 dbq_unlock:
842 rdev->pacing.do_pacing_save = pacing_data->do_pacing;
843 mutex_unlock(&rdev->pacing.dbq_lock);
844 }
845
bnxt_re_pacing_alert(struct bnxt_re_dev * rdev)846 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev)
847 {
848 struct bnxt_qplib_db_pacing_data *pacing_data;
849
850 if (!rdev->pacing.dbr_pacing)
851 return;
852 mutex_lock(&rdev->pacing.dbq_lock);
853 pacing_data = rdev->qplib_res.pacing_data;
854
855 /*
856 * Increase the alarm_th to max so that other user lib instances do not
857 * keep alerting the driver.
858 */
859 pacing_data->alarm_th = pacing_data->fifo_max_depth;
860 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING;
861 cancel_work_sync(&rdev->dbq_fifo_check_work);
862 schedule_work(&rdev->dbq_fifo_check_work);
863 mutex_unlock(&rdev->pacing.dbq_lock);
864 }
865
bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev * rdev)866 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev)
867 {
868 /* Allocate a page for app use */
869 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL);
870 if (!rdev->pacing.dbr_page)
871 return -ENOMEM;
872
873 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE);
874 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page;
875
876 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) {
877 free_page((u64)rdev->pacing.dbr_page);
878 rdev->pacing.dbr_page = NULL;
879 return -EIO;
880 }
881
882 /* MAP HW window 2 for reading db fifo depth */
883 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
884 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
885 rdev->pacing.dbr_db_fifo_reg_off =
886 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) +
887 BNXT_RE_GRC_FIFO_REG_BASE;
888 rdev->pacing.dbr_bar_addr =
889 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off;
890
891 if (is_dbr_fifo_full(rdev)) {
892 free_page((u64)rdev->pacing.dbr_page);
893 rdev->pacing.dbr_page = NULL;
894 return -EIO;
895 }
896
897 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD;
898 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME;
899 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION;
900 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing;
901 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off;
902 bnxt_re_set_default_pacing_data(rdev);
903 /* Initialize worker for DBR Pacing */
904 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check);
905 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp);
906 return 0;
907 }
908
bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev * rdev)909 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev)
910 {
911 cancel_work_sync(&rdev->dbq_fifo_check_work);
912 cancel_delayed_work_sync(&rdev->dbq_pacing_work);
913 if (rdev->pacing.dbr_page)
914 free_page((u64)rdev->pacing.dbr_page);
915
916 rdev->pacing.dbr_page = NULL;
917 rdev->pacing.dbr_pacing = false;
918 }
919
bnxt_re_net_ring_free(struct bnxt_re_dev * rdev,u16 fw_ring_id,int type)920 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
921 u16 fw_ring_id, int type)
922 {
923 struct bnxt_en_dev *en_dev = rdev->en_dev;
924 struct hwrm_ring_free_input req = {};
925 struct hwrm_ring_free_output resp;
926 struct bnxt_fw_msg fw_msg = {};
927 int rc = -EINVAL;
928
929 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
930 return 0;
931
932 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE);
933 req.ring_type = type;
934 req.ring_id = cpu_to_le16(fw_ring_id);
935 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
936 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
937 rc = bnxt_send_msg(en_dev, &fw_msg);
938 if (rc)
939 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
940 req.ring_id, rc);
941 return rc;
942 }
943
bnxt_re_net_ring_alloc(struct bnxt_re_dev * rdev,struct bnxt_re_ring_attr * ring_attr,u16 * fw_ring_id)944 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
945 struct bnxt_re_ring_attr *ring_attr,
946 u16 *fw_ring_id)
947 {
948 struct bnxt_en_dev *en_dev = rdev->en_dev;
949 struct hwrm_ring_alloc_input req = {};
950 struct hwrm_ring_alloc_output resp;
951 struct bnxt_fw_msg fw_msg = {};
952 int rc = -EINVAL;
953
954 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC);
955 req.enables = 0;
956 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]);
957 if (ring_attr->pages > 1) {
958 /* Page size is in log2 units */
959 req.page_size = BNXT_PAGE_SHIFT;
960 req.page_tbl_depth = 1;
961 }
962 req.fbo = 0;
963 /* Association of ring index with doorbell index and MSIX number */
964 req.logical_id = cpu_to_le16(ring_attr->lrid);
965 req.length = cpu_to_le32(ring_attr->depth + 1);
966 req.ring_type = ring_attr->type;
967 req.int_mode = ring_attr->mode;
968 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
969 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
970 rc = bnxt_send_msg(en_dev, &fw_msg);
971 if (!rc)
972 *fw_ring_id = le16_to_cpu(resp.ring_id);
973
974 return rc;
975 }
976
bnxt_re_net_stats_ctx_free(struct bnxt_re_dev * rdev,u32 fw_stats_ctx_id)977 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
978 u32 fw_stats_ctx_id)
979 {
980 struct bnxt_en_dev *en_dev = rdev->en_dev;
981 struct hwrm_stat_ctx_free_input req = {};
982 struct hwrm_stat_ctx_free_output resp = {};
983 struct bnxt_fw_msg fw_msg = {};
984 int rc = -EINVAL;
985
986 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
987 return 0;
988
989 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE);
990 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
991 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
992 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
993 rc = bnxt_send_msg(en_dev, &fw_msg);
994 if (rc)
995 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
996 rc);
997
998 return rc;
999 }
1000
bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev * rdev,struct bnxt_qplib_stats * stats)1001 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
1002 struct bnxt_qplib_stats *stats)
1003 {
1004 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
1005 struct hwrm_stat_ctx_alloc_output resp = {};
1006 struct hwrm_stat_ctx_alloc_input req = {};
1007 struct bnxt_en_dev *en_dev = rdev->en_dev;
1008 struct bnxt_fw_msg fw_msg = {};
1009 int rc = -EINVAL;
1010
1011 stats->fw_id = INVALID_STATS_CTX_ID;
1012
1013 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC);
1014 req.update_period_ms = cpu_to_le32(1000);
1015 req.stats_dma_addr = cpu_to_le64(stats->dma_map);
1016 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
1017 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
1018 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1019 sizeof(resp), BNXT_RE_HWRM_CMD_TIMEOUT(rdev));
1020 rc = bnxt_send_msg(en_dev, &fw_msg);
1021 if (!rc)
1022 stats->fw_id = le32_to_cpu(resp.stat_ctx_id);
1023
1024 return rc;
1025 }
1026
bnxt_re_disassociate_ucontext(struct ib_ucontext * ibcontext)1027 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext)
1028 {
1029 }
1030
1031 /* Device */
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)1032 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
1033 char *buf)
1034 {
1035 struct bnxt_re_dev *rdev =
1036 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
1037
1038 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->revision);
1039 }
1040 static DEVICE_ATTR_RO(hw_rev);
1041
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)1042 static ssize_t hca_type_show(struct device *device,
1043 struct device_attribute *attr, char *buf)
1044 {
1045 struct bnxt_re_dev *rdev =
1046 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
1047
1048 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->device);
1049 }
1050 static DEVICE_ATTR_RO(hca_type);
1051
board_id_show(struct device * device,struct device_attribute * attr,char * buf)1052 static ssize_t board_id_show(struct device *device, struct device_attribute *attr,
1053 char *buf)
1054 {
1055 struct bnxt_re_dev *rdev = rdma_device_to_drv_device(device,
1056 struct bnxt_re_dev, ibdev);
1057 char buffer[BNXT_VPD_FLD_LEN] = {};
1058
1059 if (!rdev->is_virtfn)
1060 memcpy(buffer, rdev->board_partno, BNXT_VPD_FLD_LEN - 1);
1061 else
1062 scnprintf(buffer, BNXT_VPD_FLD_LEN, "0x%x-VF",
1063 rdev->en_dev->pdev->device);
1064
1065 return sysfs_emit(buf, "%s\n", buffer);
1066 }
1067 static DEVICE_ATTR_RO(board_id);
1068
1069 static struct attribute *bnxt_re_attributes[] = {
1070 &dev_attr_hw_rev.attr,
1071 &dev_attr_hca_type.attr,
1072 &dev_attr_board_id.attr,
1073 NULL
1074 };
1075
1076 static const struct attribute_group bnxt_re_dev_attr_group = {
1077 .attrs = bnxt_re_attributes,
1078 };
1079
bnxt_re_fill_res_mr_entry(struct sk_buff * msg,struct ib_mr * ib_mr)1080 static int bnxt_re_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr)
1081 {
1082 struct bnxt_qplib_hwq *mr_hwq;
1083 struct nlattr *table_attr;
1084 struct bnxt_re_mr *mr;
1085
1086 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1087 if (!table_attr)
1088 return -EMSGSIZE;
1089
1090 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
1091 mr_hwq = &mr->qplib_mr.hwq;
1092
1093 if (rdma_nl_put_driver_u32(msg, "page_size",
1094 mr_hwq->qe_ppg * mr_hwq->element_size))
1095 goto err;
1096 if (rdma_nl_put_driver_u32(msg, "max_elements", mr_hwq->max_elements))
1097 goto err;
1098 if (rdma_nl_put_driver_u32(msg, "element_size", mr_hwq->element_size))
1099 goto err;
1100 if (rdma_nl_put_driver_u64_hex(msg, "va", mr->qplib_mr.va))
1101 goto err;
1102
1103 nla_nest_end(msg, table_attr);
1104 return 0;
1105
1106 err:
1107 nla_nest_cancel(msg, table_attr);
1108 return -EMSGSIZE;
1109 }
1110
bnxt_re_fill_res_mr_entry_raw(struct sk_buff * msg,struct ib_mr * ib_mr)1111 static int bnxt_re_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr)
1112 {
1113 struct bnxt_re_dev *rdev;
1114 struct bnxt_re_mr *mr;
1115 int err, len;
1116 void *data;
1117
1118 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
1119 rdev = mr->rdev;
1120
1121 err = bnxt_re_read_context_allowed(rdev);
1122 if (err)
1123 return err;
1124
1125 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7 :
1126 BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5;
1127 data = kzalloc(len, GFP_KERNEL);
1128 if (!data)
1129 return -ENOMEM;
1130
1131 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_MRW,
1132 mr->qplib_mr.lkey, len, data);
1133 if (!err)
1134 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1135
1136 kfree(data);
1137 return err;
1138 }
1139
bnxt_re_fill_res_cq_entry(struct sk_buff * msg,struct ib_cq * ib_cq)1140 static int bnxt_re_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq)
1141 {
1142 struct bnxt_qplib_hwq *cq_hwq;
1143 struct nlattr *table_attr;
1144 struct bnxt_re_cq *cq;
1145
1146 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
1147 cq_hwq = &cq->qplib_cq.hwq;
1148
1149 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1150 if (!table_attr)
1151 return -EMSGSIZE;
1152
1153 if (rdma_nl_put_driver_u32(msg, "cq_depth", cq_hwq->depth))
1154 goto err;
1155 if (rdma_nl_put_driver_u32(msg, "max_elements", cq_hwq->max_elements))
1156 goto err;
1157 if (rdma_nl_put_driver_u32(msg, "element_size", cq_hwq->element_size))
1158 goto err;
1159 if (rdma_nl_put_driver_u32(msg, "max_wqe", cq->qplib_cq.max_wqe))
1160 goto err;
1161
1162 nla_nest_end(msg, table_attr);
1163 return 0;
1164
1165 err:
1166 nla_nest_cancel(msg, table_attr);
1167 return -EMSGSIZE;
1168 }
1169
bnxt_re_fill_res_cq_entry_raw(struct sk_buff * msg,struct ib_cq * ib_cq)1170 static int bnxt_re_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq)
1171 {
1172 struct bnxt_re_dev *rdev;
1173 struct bnxt_re_cq *cq;
1174 int err, len;
1175 void *data;
1176
1177 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
1178 rdev = cq->rdev;
1179
1180 err = bnxt_re_read_context_allowed(rdev);
1181 if (err)
1182 return err;
1183
1184 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7 :
1185 BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5;
1186 data = kzalloc(len, GFP_KERNEL);
1187 if (!data)
1188 return -ENOMEM;
1189
1190 err = bnxt_qplib_read_context(&rdev->rcfw,
1191 CMDQ_READ_CONTEXT_TYPE_CQ,
1192 cq->qplib_cq.id, len, data);
1193 if (!err)
1194 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1195
1196 kfree(data);
1197 return err;
1198 }
1199
bnxt_re_fill_res_qp_entry(struct sk_buff * msg,struct ib_qp * ib_qp)1200 static int bnxt_re_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp)
1201 {
1202 struct bnxt_qplib_qp *qplib_qp;
1203 struct nlattr *table_attr;
1204 struct bnxt_re_qp *qp;
1205
1206 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1207 if (!table_attr)
1208 return -EMSGSIZE;
1209
1210 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1211 qplib_qp = &qp->qplib_qp;
1212
1213 if (rdma_nl_put_driver_u32(msg, "sq_max_wqe", qplib_qp->sq.max_wqe))
1214 goto err;
1215 if (rdma_nl_put_driver_u32(msg, "sq_max_sge", qplib_qp->sq.max_sge))
1216 goto err;
1217 if (rdma_nl_put_driver_u32(msg, "sq_wqe_size", qplib_qp->sq.wqe_size))
1218 goto err;
1219 if (rdma_nl_put_driver_u32(msg, "sq_swq_start", qplib_qp->sq.swq_start))
1220 goto err;
1221 if (rdma_nl_put_driver_u32(msg, "sq_swq_last", qplib_qp->sq.swq_last))
1222 goto err;
1223 if (rdma_nl_put_driver_u32(msg, "rq_max_wqe", qplib_qp->rq.max_wqe))
1224 goto err;
1225 if (rdma_nl_put_driver_u32(msg, "rq_max_sge", qplib_qp->rq.max_sge))
1226 goto err;
1227 if (rdma_nl_put_driver_u32(msg, "rq_wqe_size", qplib_qp->rq.wqe_size))
1228 goto err;
1229 if (rdma_nl_put_driver_u32(msg, "rq_swq_start", qplib_qp->rq.swq_start))
1230 goto err;
1231 if (rdma_nl_put_driver_u32(msg, "rq_swq_last", qplib_qp->rq.swq_last))
1232 goto err;
1233 if (rdma_nl_put_driver_u32(msg, "timeout", qplib_qp->timeout))
1234 goto err;
1235
1236 nla_nest_end(msg, table_attr);
1237 return 0;
1238
1239 err:
1240 nla_nest_cancel(msg, table_attr);
1241 return -EMSGSIZE;
1242 }
1243
bnxt_re_fill_res_qp_entry_raw(struct sk_buff * msg,struct ib_qp * ibqp)1244 static int bnxt_re_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ibqp)
1245 {
1246 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibqp->device, ibdev);
1247 int err, len;
1248 void *data;
1249
1250 err = bnxt_re_read_context_allowed(rdev);
1251 if (err)
1252 return err;
1253
1254 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7 :
1255 BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5;
1256 data = kzalloc(len, GFP_KERNEL);
1257 if (!data)
1258 return -ENOMEM;
1259
1260 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_QPC,
1261 ibqp->qp_num, len, data);
1262 if (!err)
1263 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1264
1265 kfree(data);
1266 return err;
1267 }
1268
bnxt_re_fill_res_srq_entry(struct sk_buff * msg,struct ib_srq * ib_srq)1269 static int bnxt_re_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq)
1270 {
1271 struct nlattr *table_attr;
1272 struct bnxt_re_srq *srq;
1273
1274 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
1275 if (!table_attr)
1276 return -EMSGSIZE;
1277
1278 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1279
1280 if (rdma_nl_put_driver_u32_hex(msg, "wqe_size", srq->qplib_srq.wqe_size))
1281 goto err;
1282 if (rdma_nl_put_driver_u32_hex(msg, "max_wqe", srq->qplib_srq.max_wqe))
1283 goto err;
1284 if (rdma_nl_put_driver_u32_hex(msg, "max_sge", srq->qplib_srq.max_sge))
1285 goto err;
1286 if (rdma_nl_put_driver_u32_hex(msg, "srq_limit", srq->qplib_srq.threshold))
1287 goto err;
1288
1289 nla_nest_end(msg, table_attr);
1290 return 0;
1291
1292 err:
1293 nla_nest_cancel(msg, table_attr);
1294 return -EMSGSIZE;
1295 }
1296
bnxt_re_fill_res_srq_entry_raw(struct sk_buff * msg,struct ib_srq * ib_srq)1297 static int bnxt_re_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq)
1298 {
1299 struct bnxt_re_dev *rdev;
1300 struct bnxt_re_srq *srq;
1301 int err, len;
1302 void *data;
1303
1304 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1305 rdev = srq->rdev;
1306
1307 err = bnxt_re_read_context_allowed(rdev);
1308 if (err)
1309 return err;
1310
1311 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7 :
1312 BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5;
1313
1314 data = kzalloc(len, GFP_KERNEL);
1315 if (!data)
1316 return -ENOMEM;
1317
1318 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_SRQ,
1319 srq->qplib_srq.id, len, data);
1320 if (!err)
1321 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data);
1322
1323 kfree(data);
1324 return err;
1325 }
1326
1327 static const struct ib_device_ops bnxt_re_dev_ops = {
1328 .owner = THIS_MODULE,
1329 .driver_id = RDMA_DRIVER_BNXT_RE,
1330 .uverbs_abi_ver = BNXT_RE_ABI_VERSION,
1331 .uverbs_robust_udata = true,
1332
1333 .add_gid = bnxt_re_add_gid,
1334 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
1335 .alloc_mr = bnxt_re_alloc_mr,
1336 .alloc_pd = bnxt_re_alloc_pd,
1337 .alloc_ucontext = bnxt_re_alloc_ucontext,
1338 .create_ah = bnxt_re_create_ah,
1339 .create_cq = bnxt_re_create_cq,
1340 .create_user_cq = bnxt_re_create_user_cq,
1341 .create_qp = bnxt_re_create_qp,
1342 .create_srq = bnxt_re_create_srq,
1343 .create_user_ah = bnxt_re_create_ah,
1344 .dealloc_pd = bnxt_re_dealloc_pd,
1345 .dealloc_ucontext = bnxt_re_dealloc_ucontext,
1346 .del_gid = bnxt_re_del_gid,
1347 .dereg_mr = bnxt_re_dereg_mr,
1348 .destroy_ah = bnxt_re_destroy_ah,
1349 .destroy_cq = bnxt_re_destroy_cq,
1350 .destroy_qp = bnxt_re_destroy_qp,
1351 .destroy_srq = bnxt_re_destroy_srq,
1352 .device_group = &bnxt_re_dev_attr_group,
1353 .disassociate_ucontext = bnxt_re_disassociate_ucontext,
1354 .get_dev_fw_str = bnxt_re_query_fw_str,
1355 .get_dma_mr = bnxt_re_get_dma_mr,
1356 .get_hw_stats = bnxt_re_ib_get_hw_stats,
1357 .get_link_layer = bnxt_re_get_link_layer,
1358 .get_port_immutable = bnxt_re_get_port_immutable,
1359 .map_mr_sg = bnxt_re_map_mr_sg,
1360 .mmap = bnxt_re_mmap,
1361 .mmap_free = bnxt_re_mmap_free,
1362 .modify_qp = bnxt_re_modify_qp,
1363 .modify_srq = bnxt_re_modify_srq,
1364 .poll_cq = bnxt_re_poll_cq,
1365 .post_recv = bnxt_re_post_recv,
1366 .post_send = bnxt_re_post_send,
1367 .post_srq_recv = bnxt_re_post_srq_recv,
1368 .process_mad = bnxt_re_process_mad,
1369 .query_ah = bnxt_re_query_ah,
1370 .query_device = bnxt_re_query_device,
1371 .modify_device = bnxt_re_modify_device,
1372 .query_pkey = bnxt_re_query_pkey,
1373 .query_port = bnxt_re_query_port,
1374 .query_qp = bnxt_re_query_qp,
1375 .query_srq = bnxt_re_query_srq,
1376 .reg_user_mr = bnxt_re_reg_user_mr,
1377 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf,
1378 .req_notify_cq = bnxt_re_req_notify_cq,
1379 .resize_user_cq = bnxt_re_resize_cq,
1380 .create_flow = bnxt_re_create_flow,
1381 .destroy_flow = bnxt_re_destroy_flow,
1382 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
1383 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
1384 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
1385 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
1386 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
1387 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
1388 };
1389
1390 static const struct ib_device_ops restrack_ops = {
1391 .fill_res_cq_entry = bnxt_re_fill_res_cq_entry,
1392 .fill_res_cq_entry_raw = bnxt_re_fill_res_cq_entry_raw,
1393 .fill_res_qp_entry = bnxt_re_fill_res_qp_entry,
1394 .fill_res_qp_entry_raw = bnxt_re_fill_res_qp_entry_raw,
1395 .fill_res_mr_entry = bnxt_re_fill_res_mr_entry,
1396 .fill_res_mr_entry_raw = bnxt_re_fill_res_mr_entry_raw,
1397 .fill_res_srq_entry = bnxt_re_fill_res_srq_entry,
1398 .fill_res_srq_entry_raw = bnxt_re_fill_res_srq_entry_raw,
1399 };
1400
bnxt_re_register_ib(struct bnxt_re_dev * rdev)1401 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
1402 {
1403 struct ib_device *ibdev = &rdev->ibdev;
1404 int ret;
1405
1406 /* ib device init */
1407 ibdev->node_type = RDMA_NODE_IB_CA;
1408 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA");
1409 ibdev->phys_port_cnt = 1;
1410
1411 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
1412
1413 ibdev->num_comp_vectors = rdev->nqr->num_msix - 1;
1414 ibdev->dev.parent = &rdev->en_dev->pdev->dev;
1415 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
1416
1417 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
1418 ibdev->driver_def = bnxt_re_uapi_defs;
1419
1420 ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
1421 ib_set_device_ops(ibdev, &restrack_ops);
1422 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
1423 if (ret)
1424 return ret;
1425
1426 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
1427 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
1428 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
1429 }
1430
bnxt_re_dev_add(struct auxiliary_device * adev,struct bnxt_en_dev * en_dev)1431 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev,
1432 struct bnxt_en_dev *en_dev)
1433 {
1434 struct bnxt_re_dev *rdev;
1435
1436 /* Allocate bnxt_re_dev instance here */
1437 rdev = ib_alloc_device(bnxt_re_dev, ibdev);
1438 if (!rdev) {
1439 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
1440 ROCE_DRV_MODULE_NAME);
1441 return NULL;
1442 }
1443 /* Default values */
1444 rdev->netdev = en_dev->net;
1445 rdev->en_dev = en_dev;
1446 rdev->adev = adev;
1447 rdev->id = rdev->en_dev->pdev->devfn;
1448 INIT_LIST_HEAD(&rdev->qp_list);
1449 mutex_init(&rdev->qp_lock);
1450 mutex_init(&rdev->pacing.dbq_lock);
1451 atomic_set(&rdev->stats.res.qp_count, 0);
1452 atomic_set(&rdev->stats.res.cq_count, 0);
1453 atomic_set(&rdev->stats.res.srq_count, 0);
1454 atomic_set(&rdev->stats.res.mr_count, 0);
1455 atomic_set(&rdev->stats.res.mw_count, 0);
1456 atomic_set(&rdev->stats.res.ah_count, 0);
1457 atomic_set(&rdev->stats.res.pd_count, 0);
1458 rdev->cosq[0] = 0xFFFF;
1459 rdev->cosq[1] = 0xFFFF;
1460 rdev->cq_coalescing.enable = 1;
1461 rdev->cq_coalescing.buf_maxtime = BNXT_QPLIB_CQ_COAL_DEF_BUF_MAXTIME;
1462 if (bnxt_re_chip_gen_p7(en_dev->chip_num)) {
1463 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P7;
1464 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P7;
1465 } else {
1466 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P5;
1467 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P5;
1468 }
1469 rdev->cq_coalescing.en_ring_idle_mode = BNXT_QPLIB_CQ_COAL_DEF_EN_RING_IDLE_MODE;
1470
1471 return rdev;
1472 }
1473
bnxt_re_handle_unaffi_async_event(struct creq_func_event * unaffi_async)1474 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
1475 *unaffi_async)
1476 {
1477 switch (unaffi_async->event) {
1478 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
1479 break;
1480 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
1481 break;
1482 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
1483 break;
1484 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
1485 break;
1486 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
1487 break;
1488 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
1489 break;
1490 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
1491 break;
1492 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
1493 break;
1494 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
1495 break;
1496 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
1497 break;
1498 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
1499 break;
1500 default:
1501 return -EINVAL;
1502 }
1503 return 0;
1504 }
1505
bnxt_re_handle_qp_async_event(struct creq_qp_event * qp_event,struct bnxt_re_qp * qp)1506 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
1507 struct bnxt_re_qp *qp)
1508 {
1509 struct creq_qp_error_notification *err_event;
1510 struct bnxt_re_srq *srq = NULL;
1511 struct ib_event event = {};
1512 unsigned int flags;
1513
1514 if (qp->qplib_qp.srq)
1515 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq,
1516 qplib_srq);
1517
1518 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
1519 rdma_is_kernel_res(&qp->ib_qp.res)) {
1520 flags = bnxt_re_lock_cqs(qp);
1521 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1522 bnxt_re_unlock_cqs(qp, flags);
1523 }
1524
1525 event.device = &qp->rdev->ibdev;
1526 event.element.qp = &qp->ib_qp;
1527 event.event = IB_EVENT_QP_FATAL;
1528
1529 err_event = (struct creq_qp_error_notification *)qp_event;
1530
1531 switch (err_event->req_err_state_reason) {
1532 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR:
1533 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT:
1534 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT:
1535 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2:
1536 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3:
1537 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP:
1538 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND:
1539 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG:
1540 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE:
1541 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR:
1542 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR:
1543 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR:
1544 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR:
1545 event.event = IB_EVENT_QP_ACCESS_ERR;
1546 break;
1547 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1:
1548 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4:
1549 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH:
1550 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR:
1551 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR:
1552 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR:
1553 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR:
1554 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR:
1555 event.event = IB_EVENT_QP_REQ_ERR;
1556 break;
1557 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR:
1558 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR:
1559 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR:
1560 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR:
1561 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR:
1562 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR:
1563 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR:
1564 event.event = IB_EVENT_QP_FATAL;
1565 break;
1566
1567 default:
1568 break;
1569 }
1570
1571 switch (err_event->res_err_state_reason) {
1572 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX:
1573 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH:
1574 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT:
1575 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY:
1576 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR:
1577 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION:
1578 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR:
1579 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY:
1580 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR:
1581 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION:
1582 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR:
1583 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC:
1584 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND:
1585 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY:
1586 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR:
1587 event.event = IB_EVENT_QP_ACCESS_ERR;
1588 break;
1589 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE:
1590 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR:
1591 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE:
1592 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE:
1593 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR:
1594 event.event = IB_EVENT_QP_REQ_ERR;
1595 break;
1596 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW:
1597 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR:
1598 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR:
1599 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR:
1600 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR:
1601 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR:
1602 event.event = IB_EVENT_QP_FATAL;
1603 break;
1604 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR:
1605 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR:
1606 if (srq)
1607 event.event = IB_EVENT_SRQ_ERR;
1608 break;
1609 default:
1610 break;
1611 }
1612
1613 if (err_event->res_err_state_reason || err_event->req_err_state_reason) {
1614 ibdev_dbg(&qp->rdev->ibdev,
1615 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n",
1616 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user",
1617 qp->qplib_qp.id,
1618 err_event->sq_cons_idx,
1619 err_event->rq_cons_idx,
1620 err_event->req_slow_path_state,
1621 err_event->req_err_state_reason,
1622 err_event->res_slow_path_state,
1623 err_event->res_err_state_reason);
1624 } else {
1625 if (srq)
1626 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
1627 }
1628
1629 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) {
1630 (*srq->ib_srq.event_handler)(&event,
1631 srq->ib_srq.srq_context);
1632 } else if (event.device && qp->ib_qp.event_handler) {
1633 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
1634 }
1635
1636 return 0;
1637 }
1638
bnxt_re_handle_cq_async_error(void * event,struct bnxt_re_cq * cq)1639 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq)
1640 {
1641 struct creq_cq_error_notification *cqerr;
1642 struct ib_event ibevent = {};
1643
1644 cqerr = event;
1645 switch (cqerr->cq_err_reason) {
1646 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR:
1647 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR:
1648 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR:
1649 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR:
1650 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR:
1651 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR:
1652 ibevent.event = IB_EVENT_CQ_ERR;
1653 break;
1654 default:
1655 break;
1656 }
1657
1658 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) {
1659 ibevent.element.cq = &cq->ib_cq;
1660 ibevent.device = &cq->rdev->ibdev;
1661
1662 ibdev_dbg(&cq->rdev->ibdev,
1663 "%s err reason %d\n", __func__, cqerr->cq_err_reason);
1664 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context);
1665 }
1666
1667 return 0;
1668 }
1669
bnxt_re_handle_affi_async_event(struct creq_qp_event * affi_async,void * obj)1670 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
1671 void *obj)
1672 {
1673 struct bnxt_qplib_qp *lib_qp;
1674 struct bnxt_qplib_cq *lib_cq;
1675 struct bnxt_re_qp *qp;
1676 struct bnxt_re_cq *cq;
1677 int rc = 0;
1678 u8 event;
1679
1680 if (!obj)
1681 return rc; /* QP was already dead, still return success */
1682
1683 event = affi_async->event;
1684 switch (event) {
1685 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
1686 lib_qp = obj;
1687 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp);
1688 rc = bnxt_re_handle_qp_async_event(affi_async, qp);
1689 break;
1690 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION:
1691 lib_cq = obj;
1692 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq);
1693 rc = bnxt_re_handle_cq_async_error(affi_async, cq);
1694 break;
1695 default:
1696 rc = -EINVAL;
1697 }
1698 return rc;
1699 }
1700
bnxt_re_aeq_handler(struct bnxt_qplib_rcfw * rcfw,void * aeqe,void * obj)1701 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
1702 void *aeqe, void *obj)
1703 {
1704 struct creq_qp_event *affi_async;
1705 struct creq_func_event *unaffi_async;
1706 u8 type;
1707 int rc;
1708
1709 type = ((struct creq_base *)aeqe)->type;
1710 if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
1711 unaffi_async = aeqe;
1712 rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
1713 } else {
1714 affi_async = aeqe;
1715 rc = bnxt_re_handle_affi_async_event(affi_async, obj);
1716 }
1717
1718 return rc;
1719 }
1720
bnxt_re_srqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_srq * handle,u8 event)1721 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
1722 struct bnxt_qplib_srq *handle, u8 event)
1723 {
1724 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
1725 qplib_srq);
1726 struct ib_event ib_event;
1727
1728 ib_event.device = &srq->rdev->ibdev;
1729 ib_event.element.srq = &srq->ib_srq;
1730
1731 if (srq->ib_srq.event_handler) {
1732 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
1733 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
1734 (*srq->ib_srq.event_handler)(&ib_event,
1735 srq->ib_srq.srq_context);
1736 }
1737 return 0;
1738 }
1739
bnxt_re_cqn_handler(struct bnxt_qplib_nq * nq,struct bnxt_qplib_cq * handle)1740 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
1741 struct bnxt_qplib_cq *handle)
1742 {
1743 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
1744 qplib_cq);
1745
1746 if (cq->ib_cq.comp_handler)
1747 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
1748
1749 return 0;
1750 }
1751
bnxt_re_cleanup_res(struct bnxt_re_dev * rdev)1752 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
1753 {
1754 int i;
1755
1756 for (i = 1; i < rdev->nqr->num_msix; i++)
1757 bnxt_qplib_disable_nq(&rdev->nqr->nq[i - 1]);
1758
1759 if (rdev->qplib_res.rcfw)
1760 bnxt_qplib_cleanup_res(&rdev->qplib_res);
1761 }
1762
bnxt_re_init_res(struct bnxt_re_dev * rdev)1763 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
1764 {
1765 int num_vec_enabled = 0;
1766 int rc = 0, i;
1767 u32 db_offt;
1768
1769 bnxt_qplib_init_res(&rdev->qplib_res);
1770
1771 mutex_init(&rdev->nqr->load_lock);
1772
1773 for (i = 1; i < rdev->nqr->num_msix ; i++) {
1774 db_offt = rdev->nqr->msix_entries[i].db_offset;
1775 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nqr->nq[i - 1],
1776 i - 1, rdev->nqr->msix_entries[i].vector,
1777 db_offt, &bnxt_re_cqn_handler,
1778 &bnxt_re_srqn_handler);
1779 if (rc) {
1780 ibdev_err(&rdev->ibdev,
1781 "Failed to enable NQ with rc = 0x%x", rc);
1782 goto fail;
1783 }
1784 num_vec_enabled++;
1785 }
1786 return 0;
1787 fail:
1788 for (i = num_vec_enabled; i >= 0; i--)
1789 bnxt_qplib_disable_nq(&rdev->nqr->nq[i]);
1790 return rc;
1791 }
1792
bnxt_re_free_nq_res(struct bnxt_re_dev * rdev)1793 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
1794 {
1795 struct bnxt_qplib_nq *nq;
1796 u8 type;
1797 int i;
1798
1799 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1800 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1801 nq = &rdev->nqr->nq[i];
1802 bnxt_re_net_ring_free(rdev, nq->ring_id, type);
1803 bnxt_qplib_free_nq(nq);
1804 nq->res = NULL;
1805 }
1806 }
1807
bnxt_re_free_res(struct bnxt_re_dev * rdev)1808 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
1809 {
1810 bnxt_re_free_nq_res(rdev);
1811
1812 if (rdev->qplib_res.dpi_tbl.max) {
1813 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1814 &rdev->dpi_privileged);
1815 }
1816 if (rdev->qplib_res.rcfw) {
1817 bnxt_qplib_free_res(&rdev->qplib_res);
1818 rdev->qplib_res.rcfw = NULL;
1819 }
1820 }
1821
bnxt_re_alloc_res(struct bnxt_re_dev * rdev)1822 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
1823 {
1824 struct bnxt_re_ring_attr rattr = {};
1825 int num_vec_created = 0;
1826 int rc, i;
1827 u8 type;
1828
1829 /* Configure and allocate resources for qplib */
1830 rdev->qplib_res.rcfw = &rdev->rcfw;
1831 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
1832 if (rc)
1833 goto fail;
1834
1835 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev);
1836 if (rc)
1837 goto fail;
1838
1839 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res,
1840 &rdev->dpi_privileged,
1841 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL);
1842 if (rc)
1843 goto dealloc_res;
1844
1845 for (i = 0; i < rdev->nqr->num_msix - 1; i++) {
1846 struct bnxt_qplib_nq *nq;
1847
1848 nq = &rdev->nqr->nq[i];
1849 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
1850 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, nq);
1851 if (rc) {
1852 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
1853 i, rc);
1854 goto free_nq;
1855 }
1856 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1857 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1858 rattr.pages = nq->hwq.pbl[rdev->nqr->nq[i].hwq.level].pg_count;
1859 rattr.type = type;
1860 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1861 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
1862 rattr.lrid = rdev->nqr->msix_entries[i + 1].ring_idx;
1863 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
1864 if (rc) {
1865 ibdev_err(&rdev->ibdev,
1866 "Failed to allocate NQ fw id with rc = 0x%x",
1867 rc);
1868 bnxt_qplib_free_nq(nq);
1869 goto free_nq;
1870 }
1871 num_vec_created++;
1872 }
1873 return 0;
1874 free_nq:
1875 for (i = num_vec_created - 1; i >= 0; i--) {
1876 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1877 bnxt_re_net_ring_free(rdev, rdev->nqr->nq[i].ring_id, type);
1878 bnxt_qplib_free_nq(&rdev->nqr->nq[i]);
1879 }
1880 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
1881 &rdev->dpi_privileged);
1882 dealloc_res:
1883 bnxt_qplib_free_res(&rdev->qplib_res);
1884
1885 fail:
1886 rdev->qplib_res.rcfw = NULL;
1887 return rc;
1888 }
1889
bnxt_re_dispatch_event(struct ib_device * ibdev,struct ib_qp * qp,u8 port_num,enum ib_event_type event)1890 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
1891 u8 port_num, enum ib_event_type event)
1892 {
1893 struct ib_event ib_event;
1894
1895 ib_event.device = ibdev;
1896 if (qp) {
1897 ib_event.element.qp = qp;
1898 ib_event.event = event;
1899 if (qp->event_handler)
1900 qp->event_handler(&ib_event, qp->qp_context);
1901
1902 } else {
1903 ib_event.element.port_num = port_num;
1904 ib_event.event = event;
1905 ib_dispatch_event(&ib_event);
1906 }
1907 }
1908
bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp)1909 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
1910 struct bnxt_re_qp *qp)
1911 {
1912 return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
1913 (qp == rdev->gsi_ctx.gsi_sqp);
1914 }
1915
bnxt_re_dev_stop(struct bnxt_re_dev * rdev)1916 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
1917 {
1918 struct bnxt_re_qp *qp;
1919
1920 mutex_lock(&rdev->qp_lock);
1921 list_for_each_entry(qp, &rdev->qp_list, list) {
1922 /* Modify the state of all QPs except QP1/Shadow QP */
1923 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
1924 if (qp->qplib_qp.state !=
1925 CMDQ_MODIFY_QP_NEW_STATE_RESET &&
1926 qp->qplib_qp.state !=
1927 CMDQ_MODIFY_QP_NEW_STATE_ERR)
1928 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
1929 1, IB_EVENT_QP_FATAL);
1930 }
1931 }
1932 mutex_unlock(&rdev->qp_lock);
1933 }
1934
bnxt_re_net_unregister_async_event(struct bnxt_re_dev * rdev)1935 static void bnxt_re_net_unregister_async_event(struct bnxt_re_dev *rdev)
1936 {
1937 if (rdev->is_virtfn)
1938 return;
1939
1940 memset(&rdev->event_bitmap, 0, sizeof(rdev->event_bitmap));
1941 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap,
1942 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1943 }
1944
bnxt_re_net_register_async_event(struct bnxt_re_dev * rdev)1945 static void bnxt_re_net_register_async_event(struct bnxt_re_dev *rdev)
1946 {
1947 if (rdev->is_virtfn)
1948 return;
1949
1950 rdev->event_bitmap |= (1 << ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1951 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap,
1952 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE);
1953 }
1954
bnxt_re_read_vpd_info(struct bnxt_re_dev * rdev)1955 static void bnxt_re_read_vpd_info(struct bnxt_re_dev *rdev)
1956 {
1957 struct pci_dev *pdev = rdev->en_dev->pdev;
1958 unsigned int vpd_size, kw_len;
1959 int pos, size;
1960 u8 *vpd_data;
1961
1962 vpd_data = pci_vpd_alloc(pdev, &vpd_size);
1963 if (IS_ERR(vpd_data)) {
1964 pci_warn(pdev, "Unable to read VPD, err=%pe\n", vpd_data);
1965 return;
1966 }
1967
1968 pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
1969 PCI_VPD_RO_KEYWORD_PARTNO, &kw_len);
1970 if (pos < 0)
1971 goto free;
1972
1973 size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
1974 memcpy(rdev->board_partno, &vpd_data[pos], size);
1975 free:
1976 kfree(vpd_data);
1977 }
1978
bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev * rdev)1979 static int bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1980 {
1981 struct bnxt_en_dev *en_dev = rdev->en_dev;
1982 struct hwrm_ver_get_output resp = {};
1983 struct hwrm_ver_get_input req = {};
1984 struct bnxt_qplib_chip_ctx *cctx;
1985 struct bnxt_fw_msg fw_msg = {};
1986 int rc;
1987
1988 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET);
1989 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1990 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1991 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1992 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1993 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1994 rc = bnxt_send_msg(en_dev, &fw_msg);
1995 if (rc) {
1996 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1997 rc);
1998 return rc;
1999 }
2000
2001 cctx = rdev->chip_ctx;
2002 cctx->hwrm_intf_ver =
2003 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
2004 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
2005 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
2006 le16_to_cpu(resp.hwrm_intf_patch);
2007
2008 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout);
2009
2010 if (!cctx->hwrm_cmd_max_timeout)
2011 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT;
2012
2013 return 0;
2014 }
2015
bnxt_re_ib_init(struct bnxt_re_dev * rdev)2016 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
2017 {
2018 int rc;
2019 u32 event;
2020
2021 /* Register ib dev */
2022 rc = bnxt_re_register_ib(rdev);
2023 if (rc) {
2024 pr_err("Failed to register with IB: %#x\n", rc);
2025 return rc;
2026 }
2027 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
2028 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
2029
2030 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
2031 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2032
2033 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
2034
2035 return rc;
2036 }
2037
bnxt_re_alloc_nqr_mem(struct bnxt_re_dev * rdev)2038 static int bnxt_re_alloc_nqr_mem(struct bnxt_re_dev *rdev)
2039 {
2040 rdev->nqr = kzalloc_obj(*rdev->nqr);
2041 if (!rdev->nqr)
2042 return -ENOMEM;
2043
2044 return 0;
2045 }
2046
bnxt_re_free_nqr_mem(struct bnxt_re_dev * rdev)2047 static void bnxt_re_free_nqr_mem(struct bnxt_re_dev *rdev)
2048 {
2049 kfree(rdev->nqr);
2050 rdev->nqr = NULL;
2051 }
2052
2053 /* When DEL_GID fails, driver is not freeing GID ctx memory.
2054 * To avoid the memory leak, free the memory during unload
2055 */
bnxt_re_free_gid_ctx(struct bnxt_re_dev * rdev)2056 static void bnxt_re_free_gid_ctx(struct bnxt_re_dev *rdev)
2057 {
2058 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
2059 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
2060 int i;
2061
2062 if (!sgid_tbl->active)
2063 return;
2064
2065 ctx_tbl = sgid_tbl->ctx;
2066 for (i = 0; i < sgid_tbl->max; i++) {
2067 if (sgid_tbl->hw_id[i] == 0xFFFF)
2068 continue;
2069
2070 ctx = ctx_tbl[i];
2071 kfree(ctx);
2072 }
2073 }
2074
bnxt_re_get_stats_ctx(struct bnxt_re_dev * rdev)2075 static int bnxt_re_get_stats_ctx(struct bnxt_re_dev *rdev)
2076 {
2077 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx;
2078 struct bnxt_qplib_res *res = &rdev->qplib_res;
2079 int rc;
2080
2081 rc = bnxt_qplib_alloc_stats_ctx(res->pdev, res->cctx, &hctx->stats);
2082 if (rc)
2083 return rc;
2084
2085 rc = bnxt_re_net_stats_ctx_alloc(rdev, &hctx->stats);
2086 if (rc)
2087 goto free_stat_mem;
2088
2089 return 0;
2090 free_stat_mem:
2091 bnxt_qplib_free_stats_ctx(res->pdev, &hctx->stats);
2092
2093 return rc;
2094 }
2095
bnxt_re_get_stats3_ctx(struct bnxt_re_dev * rdev)2096 static int bnxt_re_get_stats3_ctx(struct bnxt_re_dev *rdev)
2097 {
2098 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx;
2099 struct bnxt_qplib_res *res = &rdev->qplib_res;
2100 int rc;
2101
2102 if (!rdev->rcfw.roce_mirror)
2103 return 0;
2104
2105 rc = bnxt_qplib_alloc_stats_ctx(res->pdev, res->cctx, &hctx->stats3);
2106 if (rc)
2107 return rc;
2108
2109 rc = bnxt_re_net_stats_ctx_alloc(rdev, &hctx->stats3);
2110 if (rc)
2111 goto free_stat_mem;
2112
2113 return 0;
2114 free_stat_mem:
2115 bnxt_qplib_free_stats_ctx(res->pdev, &hctx->stats3);
2116
2117 return rc;
2118 }
2119
bnxt_re_put_stats3_ctx(struct bnxt_re_dev * rdev)2120 static void bnxt_re_put_stats3_ctx(struct bnxt_re_dev *rdev)
2121 {
2122 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx;
2123 struct bnxt_qplib_res *res = &rdev->qplib_res;
2124
2125 if (!rdev->rcfw.roce_mirror)
2126 return;
2127
2128 bnxt_re_net_stats_ctx_free(rdev, hctx->stats3.fw_id);
2129 bnxt_qplib_free_stats_ctx(res->pdev, &hctx->stats3);
2130 }
2131
bnxt_re_put_stats_ctx(struct bnxt_re_dev * rdev)2132 static void bnxt_re_put_stats_ctx(struct bnxt_re_dev *rdev)
2133 {
2134 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx;
2135 struct bnxt_qplib_res *res = &rdev->qplib_res;
2136
2137 bnxt_re_net_stats_ctx_free(rdev, hctx->stats.fw_id);
2138 bnxt_qplib_free_stats_ctx(res->pdev, &hctx->stats);
2139 }
2140
bnxt_re_dev_uninit(struct bnxt_re_dev * rdev,u8 op_type)2141 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type)
2142 {
2143 u8 type;
2144 int rc;
2145
2146 bnxt_re_debugfs_rem_pdev(rdev);
2147
2148 bnxt_re_net_unregister_async_event(rdev);
2149 bnxt_re_uninit_dcb_wq(rdev);
2150
2151 bnxt_re_put_stats3_ctx(rdev);
2152
2153 bnxt_re_free_gid_ctx(rdev);
2154 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
2155 &rdev->flags))
2156 bnxt_re_cleanup_res(rdev);
2157 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
2158 bnxt_re_free_res(rdev);
2159
2160 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
2161 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
2162 if (rc)
2163 ibdev_warn(&rdev->ibdev,
2164 "Failed to deinitialize RCFW: %#x", rc);
2165 bnxt_re_put_stats_ctx(rdev);
2166 bnxt_qplib_free_hwctx(&rdev->qplib_res, &rdev->qplib_ctx);
2167 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
2168 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2169 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
2170 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
2171 }
2172
2173 rdev->nqr->num_msix = 0;
2174
2175 if (rdev->pacing.dbr_pacing)
2176 bnxt_re_deinitialize_dbr_pacing(rdev);
2177
2178 bnxt_re_free_nqr_mem(rdev);
2179 bnxt_re_destroy_chip_ctx(rdev);
2180 if (op_type == BNXT_RE_COMPLETE_REMOVE) {
2181 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
2182 bnxt_unregister_dev(rdev->en_dev);
2183 }
2184 }
2185
bnxt_re_dev_init(struct bnxt_re_dev * rdev,u8 op_type)2186 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type)
2187 {
2188 struct bnxt_re_ring_attr rattr = {};
2189 struct bnxt_qplib_creq_ctx *creq;
2190 u32 db_offt;
2191 int vid;
2192 u8 type;
2193 int rc;
2194
2195 if (op_type == BNXT_RE_COMPLETE_INIT) {
2196 /* Registered a new RoCE device instance to netdev */
2197 rc = bnxt_re_register_netdev(rdev);
2198 if (rc) {
2199 ibdev_err(&rdev->ibdev,
2200 "Failed to register with Ethernet driver, rc %d\n",
2201 rc);
2202 return rc;
2203 }
2204 }
2205 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2206
2207 if (rdev->en_dev->ulp_tbl->msix_requested < BNXT_RE_MIN_MSIX) {
2208 ibdev_err(&rdev->ibdev,
2209 "RoCE requires minimum 2 MSI-X vectors, but only %d reserved\n",
2210 rdev->en_dev->ulp_tbl->msix_requested);
2211 bnxt_unregister_dev(rdev->en_dev);
2212 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2213 return -EINVAL;
2214 }
2215 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
2216 rdev->en_dev->ulp_tbl->msix_requested);
2217
2218 rc = bnxt_re_setup_chip_ctx(rdev);
2219 if (rc) {
2220 bnxt_unregister_dev(rdev->en_dev);
2221 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2222 ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
2223 return -EINVAL;
2224 }
2225
2226 rc = bnxt_re_alloc_nqr_mem(rdev);
2227 if (rc) {
2228 bnxt_re_destroy_chip_ctx(rdev);
2229 bnxt_unregister_dev(rdev->en_dev);
2230 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
2231 return rc;
2232 }
2233 rdev->nqr->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
2234 memcpy(rdev->nqr->msix_entries, rdev->en_dev->msix_entries,
2235 sizeof(struct bnxt_msix_entry) * rdev->nqr->num_msix);
2236
2237 /* Check whether VF or PF */
2238 bnxt_re_get_sriov_func_type(rdev);
2239
2240 /* Establish RCFW Communication Channel to initialize the context
2241 * memory for the function and all child VFs
2242 */
2243 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
2244 &rdev->qplib_ctx);
2245 if (rc) {
2246 ibdev_err(&rdev->ibdev,
2247 "Failed to allocate RCFW Channel: %#x\n", rc);
2248 goto fail;
2249 }
2250
2251 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2252 creq = &rdev->rcfw.creq;
2253 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
2254 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
2255 rattr.type = type;
2256 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
2257 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
2258 rattr.lrid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
2259 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
2260 if (rc) {
2261 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
2262 goto free_rcfw;
2263 }
2264 db_offt = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
2265 vid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].vector;
2266 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
2267 vid, db_offt,
2268 &bnxt_re_aeq_handler);
2269 if (rc) {
2270 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
2271 rc);
2272 goto free_ring;
2273 }
2274
2275 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) {
2276 rc = bnxt_re_initialize_dbr_pacing(rdev);
2277 if (!rc) {
2278 rdev->pacing.dbr_pacing = true;
2279 } else {
2280 ibdev_err(&rdev->ibdev,
2281 "DBR pacing disabled with error : %d\n", rc);
2282 rdev->pacing.dbr_pacing = false;
2283 }
2284 }
2285 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw);
2286 if (rc)
2287 goto disable_rcfw;
2288
2289 bnxt_qplib_query_version(&rdev->rcfw);
2290 bnxt_re_set_resource_limits(rdev);
2291
2292 if (!rdev->is_virtfn &&
2293 !bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
2294 rc = bnxt_qplib_alloc_hwctx(&rdev->qplib_res, &rdev->qplib_ctx);
2295 if (rc) {
2296 ibdev_err(&rdev->ibdev,
2297 "Failed to allocate hw context: %#x\n", rc);
2298 goto disable_rcfw;
2299 }
2300 }
2301
2302 rc = bnxt_re_get_stats_ctx(rdev);
2303 if (rc) {
2304 ibdev_err(&rdev->ibdev,
2305 "Failed to allocate stats context: %#x\n", rc);
2306 goto free_ctx;
2307 }
2308
2309 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
2310 rdev->is_virtfn);
2311 if (rc) {
2312 ibdev_err(&rdev->ibdev,
2313 "Failed to initialize RCFW: %#x\n", rc);
2314 goto free_sctx;
2315 }
2316 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
2317
2318 /* Resources based on the 'new' device caps */
2319 rc = bnxt_re_alloc_res(rdev);
2320 if (rc) {
2321 ibdev_err(&rdev->ibdev,
2322 "Failed to allocate resources: %#x\n", rc);
2323 goto fail;
2324 }
2325 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
2326 rc = bnxt_re_init_res(rdev);
2327 if (rc) {
2328 ibdev_err(&rdev->ibdev,
2329 "Failed to initialize resources: %#x\n", rc);
2330 goto fail;
2331 }
2332
2333 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
2334
2335 if (!rdev->is_virtfn) {
2336 /* Query f/w defaults of CC params */
2337 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, &rdev->cc_param);
2338 if (rc)
2339 ibdev_warn(&rdev->ibdev, "Failed to query CC defaults\n");
2340
2341 if (!(rdev->qplib_res.en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT))
2342 bnxt_re_vf_res_config(rdev);
2343 }
2344 bnxt_re_debugfs_add_pdev(rdev);
2345
2346 rc = bnxt_re_init_dcb_wq(rdev);
2347 if (rc)
2348 goto fail;
2349 bnxt_re_net_register_async_event(rdev);
2350
2351 if (!rdev->is_virtfn)
2352 bnxt_re_read_vpd_info(rdev);
2353
2354 rc = bnxt_re_get_stats3_ctx(rdev);
2355 if (rc)
2356 goto fail;
2357
2358 return 0;
2359 free_sctx:
2360 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
2361 free_ctx:
2362 bnxt_qplib_free_hwctx(&rdev->qplib_res, &rdev->qplib_ctx);
2363 disable_rcfw:
2364 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
2365 free_ring:
2366 type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
2367 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
2368 free_rcfw:
2369 bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
2370 fail:
2371 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2372
2373 return rc;
2374 }
2375
bnxt_re_setup_cc(struct bnxt_re_dev * rdev,bool enable)2376 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)
2377 {
2378 struct bnxt_qplib_cc_param cc_param = {};
2379
2380 /* Do not enable congestion control on VFs */
2381 if (rdev->is_virtfn)
2382 return;
2383
2384 /* Currently enabling only for GenP5 adapters */
2385 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
2386 return;
2387
2388 if (enable) {
2389 cc_param.enable = 1;
2390 cc_param.tos_ecn = 1;
2391 }
2392
2393 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC |
2394 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN);
2395
2396 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param))
2397 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable);
2398 }
2399
bnxt_re_update_en_info_rdev(struct bnxt_re_dev * rdev,struct bnxt_re_en_dev_info * en_info,struct auxiliary_device * adev)2400 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev,
2401 struct bnxt_re_en_dev_info *en_info,
2402 struct auxiliary_device *adev)
2403 {
2404 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure,
2405 * take the rtnl lock to avoid accessing invalid rdev pointer from
2406 * L2 ULP callbacks. This is applicable in all the places where rdev
2407 * pointer is updated in bnxt_re_en_dev_info.
2408 */
2409 rtnl_lock();
2410 en_info->rdev = rdev;
2411 rtnl_unlock();
2412 }
2413
bnxt_re_add_device(struct auxiliary_device * adev,u8 op_type)2414 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type)
2415 {
2416 struct bnxt_aux_priv *aux_priv =
2417 container_of(adev, struct bnxt_aux_priv, aux_dev);
2418 struct bnxt_re_en_dev_info *en_info;
2419 struct bnxt_en_dev *en_dev;
2420 struct bnxt_re_dev *rdev;
2421 int rc;
2422
2423 en_info = auxiliary_get_drvdata(adev);
2424 en_dev = en_info->en_dev;
2425
2426
2427 rdev = bnxt_re_dev_add(adev, en_dev);
2428 if (!rdev || !rdev_to_dev(rdev)) {
2429 rc = -ENOMEM;
2430 goto exit;
2431 }
2432
2433 bnxt_re_update_en_info_rdev(rdev, en_info, adev);
2434
2435 rc = bnxt_re_dev_init(rdev, op_type);
2436 if (rc)
2437 goto re_dev_dealloc;
2438
2439 rc = bnxt_re_ib_init(rdev);
2440 if (rc) {
2441 pr_err("Failed to register with IB: %s",
2442 aux_priv->aux_dev.name);
2443 goto re_dev_uninit;
2444 }
2445
2446 bnxt_re_setup_cc(rdev, true);
2447
2448 return 0;
2449
2450 re_dev_uninit:
2451 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2452 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2453 re_dev_dealloc:
2454 ib_dealloc_device(&rdev->ibdev);
2455 exit:
2456 return rc;
2457 }
2458
2459 #define BNXT_ADEV_NAME "bnxt_en"
2460
bnxt_re_remove_device(struct bnxt_re_dev * rdev,u8 op_type,struct auxiliary_device * aux_dev)2461 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type,
2462 struct auxiliary_device *aux_dev)
2463 {
2464 bnxt_re_setup_cc(rdev, false);
2465 ib_unregister_device(&rdev->ibdev);
2466 bnxt_re_dev_uninit(rdev, op_type);
2467 ib_dealloc_device(&rdev->ibdev);
2468 }
2469
bnxt_re_remove(struct auxiliary_device * adev)2470 static void bnxt_re_remove(struct auxiliary_device *adev)
2471 {
2472 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2473 struct bnxt_re_dev *rdev;
2474
2475 mutex_lock(&bnxt_re_mutex);
2476 rdev = en_info->rdev;
2477
2478 if (rdev)
2479 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev);
2480 kfree(en_info);
2481 mutex_unlock(&bnxt_re_mutex);
2482 }
2483
bnxt_re_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)2484 static int bnxt_re_probe(struct auxiliary_device *adev,
2485 const struct auxiliary_device_id *id)
2486 {
2487 struct bnxt_aux_priv *aux_priv =
2488 container_of(adev, struct bnxt_aux_priv, aux_dev);
2489 struct bnxt_re_en_dev_info *en_info;
2490 struct bnxt_en_dev *en_dev;
2491 int rc;
2492
2493 en_dev = aux_priv->edev;
2494
2495 mutex_lock(&bnxt_re_mutex);
2496 en_info = kzalloc_obj(*en_info);
2497 if (!en_info) {
2498 mutex_unlock(&bnxt_re_mutex);
2499 return -ENOMEM;
2500 }
2501 en_info->en_dev = en_dev;
2502
2503 auxiliary_set_drvdata(adev, en_info);
2504
2505 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT);
2506 if (rc)
2507 kfree(en_info);
2508
2509 mutex_unlock(&bnxt_re_mutex);
2510
2511 return rc;
2512 }
2513
bnxt_re_suspend(struct auxiliary_device * adev,pm_message_t state)2514 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
2515 {
2516 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2517 struct bnxt_en_dev *en_dev;
2518 struct bnxt_re_dev *rdev;
2519
2520 rdev = en_info->rdev;
2521 en_dev = en_info->en_dev;
2522 mutex_lock(&bnxt_re_mutex);
2523
2524 ibdev_info(&rdev->ibdev, "Handle device suspend call");
2525 /* Check the current device state from bnxt_en_dev and move the
2526 * device to detached state if FW_FATAL_COND is set.
2527 * This prevents more commands to HW during clean-up,
2528 * in case the device is already in error.
2529 */
2530 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) {
2531 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
2532 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
2533 wake_up_all(&rdev->rcfw.cmdq.waitq);
2534 bnxt_re_dev_stop(rdev);
2535 }
2536
2537 if (rdev->pacing.dbr_pacing)
2538 bnxt_re_set_pacing_dev_state(rdev);
2539
2540 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx",
2541 __func__, en_dev->en_state);
2542 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev);
2543 bnxt_re_update_en_info_rdev(NULL, en_info, adev);
2544 mutex_unlock(&bnxt_re_mutex);
2545
2546 return 0;
2547 }
2548
bnxt_re_resume(struct auxiliary_device * adev)2549 static int bnxt_re_resume(struct auxiliary_device *adev)
2550 {
2551 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2552 struct bnxt_re_dev *rdev;
2553
2554 mutex_lock(&bnxt_re_mutex);
2555 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT);
2556 rdev = en_info->rdev;
2557 ibdev_info(&rdev->ibdev, "Device resume completed");
2558 mutex_unlock(&bnxt_re_mutex);
2559
2560 return 0;
2561 }
2562
bnxt_re_shutdown(struct auxiliary_device * adev)2563 static void bnxt_re_shutdown(struct auxiliary_device *adev)
2564 {
2565 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev);
2566 struct bnxt_re_dev *rdev;
2567
2568 rdev = en_info->rdev;
2569 ib_unregister_device(&rdev->ibdev);
2570 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE);
2571 }
2572
2573 static const struct auxiliary_device_id bnxt_re_id_table[] = {
2574 { .name = BNXT_ADEV_NAME ".rdma", },
2575 {},
2576 };
2577
2578 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
2579
2580 static struct auxiliary_driver bnxt_re_driver = {
2581 .name = "rdma",
2582 .probe = bnxt_re_probe,
2583 .remove = bnxt_re_remove,
2584 .shutdown = bnxt_re_shutdown,
2585 .suspend = bnxt_re_suspend,
2586 .resume = bnxt_re_resume,
2587 .id_table = bnxt_re_id_table,
2588 };
2589
bnxt_re_mod_init(void)2590 static int __init bnxt_re_mod_init(void)
2591 {
2592 int rc;
2593
2594 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
2595 bnxt_re_register_debugfs();
2596
2597 rc = auxiliary_driver_register(&bnxt_re_driver);
2598 if (rc) {
2599 pr_err("%s: Failed to register auxiliary driver\n",
2600 ROCE_DRV_MODULE_NAME);
2601 goto err_debug;
2602 }
2603 return 0;
2604 err_debug:
2605 bnxt_re_unregister_debugfs();
2606 return rc;
2607 }
2608
bnxt_re_mod_exit(void)2609 static void __exit bnxt_re_mod_exit(void)
2610 {
2611 auxiliary_driver_unregister(&bnxt_re_driver);
2612 bnxt_re_unregister_debugfs();
2613 }
2614
2615 module_init(bnxt_re_mod_init);
2616 module_exit(bnxt_re_mod_exit);
2617