1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2024 Nuvoton Technology Corp.
4 *
5 * Author: Shan-Chun Hung <shanchun1218@gmail.com>
6 */
7
8 #include <linux/align.h>
9 #include <linux/array_size.h>
10 #include <linux/bits.h>
11 #include <linux/build_bug.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dev_printk.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/math.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/minmax.h>
21 #include <linux/mmc/card.h>
22 #include <linux/mmc/host.h>
23 #include <linux/module.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/sizes.h>
29 #include <linux/types.h>
30
31 #include "sdhci-pltfm.h"
32 #include "sdhci.h"
33
34 #define MA35_SYS_MISCFCR0 0x070
35 #define MA35_SDHCI_MSHCCTL 0x508
36 #define MA35_SDHCI_MBIUCTL 0x510
37
38 #define MA35_SDHCI_CMD_CONFLICT_CHK BIT(0)
39 #define MA35_SDHCI_INCR_MSK GENMASK(3, 0)
40 #define MA35_SDHCI_INCR16 BIT(3)
41 #define MA35_SDHCI_INCR8 BIT(2)
42
43 struct ma35_priv {
44 struct reset_control *rst;
45 struct pinctrl *pinctrl;
46 struct pinctrl_state *pins_uhs;
47 struct pinctrl_state *pins_default;
48 };
49
50 struct ma35_restore_data {
51 u32 reg;
52 u32 width;
53 };
54
55 static const struct ma35_restore_data restore_data[] = {
56 { SDHCI_CLOCK_CONTROL, sizeof(u32)},
57 { SDHCI_BLOCK_SIZE, sizeof(u32)},
58 { SDHCI_INT_ENABLE, sizeof(u32)},
59 { SDHCI_SIGNAL_ENABLE, sizeof(u32)},
60 { SDHCI_AUTO_CMD_STATUS, sizeof(u32)},
61 { SDHCI_HOST_CONTROL, sizeof(u32)},
62 { SDHCI_TIMEOUT_CONTROL, sizeof(u8) },
63 { MA35_SDHCI_MSHCCTL, sizeof(u16)},
64 { MA35_SDHCI_MBIUCTL, sizeof(u16)},
65 };
66
67 /*
68 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
69 * so that each DMA transfer doesn't exceed the boundary.
70 */
ma35_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)71 static void ma35_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len,
72 unsigned int cmd)
73 {
74 int tmplen, offset;
75
76 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) {
77 sdhci_adma_write_desc(host, desc, addr, len, cmd);
78 return;
79 }
80
81 offset = addr & (SZ_128M - 1);
82 tmplen = SZ_128M - offset;
83 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
84
85 addr += tmplen;
86 len -= tmplen;
87 sdhci_adma_write_desc(host, desc, addr, len, cmd);
88 }
89
ma35_set_clock(struct sdhci_host * host,unsigned int clock)90 static void ma35_set_clock(struct sdhci_host *host, unsigned int clock)
91 {
92 u32 ctl;
93
94 /*
95 * If the clock frequency exceeds MMC_HIGH_52_MAX_DTR,
96 * disable command conflict check.
97 */
98 ctl = sdhci_readw(host, MA35_SDHCI_MSHCCTL);
99 if (clock > MMC_HIGH_52_MAX_DTR)
100 ctl &= ~MA35_SDHCI_CMD_CONFLICT_CHK;
101 else
102 ctl |= MA35_SDHCI_CMD_CONFLICT_CHK;
103 sdhci_writew(host, ctl, MA35_SDHCI_MSHCCTL);
104
105 sdhci_set_clock(host, clock);
106 }
107
ma35_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)108 static int ma35_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
109 {
110 struct sdhci_host *host = mmc_priv(mmc);
111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
112 struct ma35_priv *priv = sdhci_pltfm_priv(pltfm_host);
113
114 switch (ios->signal_voltage) {
115 case MMC_SIGNAL_VOLTAGE_180:
116 if (!IS_ERR(priv->pinctrl) && !IS_ERR(priv->pins_uhs))
117 pinctrl_select_state(priv->pinctrl, priv->pins_uhs);
118 break;
119 case MMC_SIGNAL_VOLTAGE_330:
120 if (!IS_ERR(priv->pinctrl) && !IS_ERR(priv->pins_default))
121 pinctrl_select_state(priv->pinctrl, priv->pins_default);
122 break;
123 default:
124 dev_err(mmc_dev(host->mmc), "Unsupported signal voltage!\n");
125 return -EINVAL;
126 }
127
128 return sdhci_start_signal_voltage_switch(mmc, ios);
129 }
130
ma35_voltage_switch(struct sdhci_host * host)131 static void ma35_voltage_switch(struct sdhci_host *host)
132 {
133 /* Wait for 5ms after set 1.8V signal enable bit */
134 fsleep(5000);
135 }
136
ma35_execute_tuning(struct mmc_host * mmc,u32 opcode)137 static int ma35_execute_tuning(struct mmc_host *mmc, u32 opcode)
138 {
139 struct sdhci_host *host = mmc_priv(mmc);
140 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
141 struct ma35_priv *priv = sdhci_pltfm_priv(pltfm_host);
142 int idx;
143 u32 regs[ARRAY_SIZE(restore_data)] = {};
144
145 /*
146 * Limitations require a reset of SD/eMMC before tuning and
147 * saving the registers before resetting, then restoring
148 * after the reset.
149 */
150 for (idx = 0; idx < ARRAY_SIZE(restore_data); idx++) {
151 if (restore_data[idx].width == sizeof(u32))
152 regs[idx] = sdhci_readl(host, restore_data[idx].reg);
153 else if (restore_data[idx].width == sizeof(u16))
154 regs[idx] = sdhci_readw(host, restore_data[idx].reg);
155 else if (restore_data[idx].width == sizeof(u8))
156 regs[idx] = sdhci_readb(host, restore_data[idx].reg);
157 }
158
159 reset_control_assert(priv->rst);
160 reset_control_deassert(priv->rst);
161
162 for (idx = 0; idx < ARRAY_SIZE(restore_data); idx++) {
163 if (restore_data[idx].width == sizeof(u32))
164 sdhci_writel(host, regs[idx], restore_data[idx].reg);
165 else if (restore_data[idx].width == sizeof(u16))
166 sdhci_writew(host, regs[idx], restore_data[idx].reg);
167 else if (restore_data[idx].width == sizeof(u8))
168 sdhci_writeb(host, regs[idx], restore_data[idx].reg);
169 }
170
171 return sdhci_execute_tuning(mmc, opcode);
172 }
173
174 static const struct sdhci_ops sdhci_ma35_ops = {
175 .set_clock = ma35_set_clock,
176 .set_bus_width = sdhci_set_bus_width,
177 .set_uhs_signaling = sdhci_set_uhs_signaling,
178 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
179 .reset = sdhci_reset,
180 .adma_write_desc = ma35_adma_write_desc,
181 .voltage_switch = ma35_voltage_switch,
182 };
183
184 static const struct sdhci_pltfm_data sdhci_ma35_pdata = {
185 .ops = &sdhci_ma35_ops,
186 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
187 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_BROKEN_DDR50 |
188 SDHCI_QUIRK2_ACMD23_BROKEN,
189 };
190
ma35_probe(struct platform_device * pdev)191 static int ma35_probe(struct platform_device *pdev)
192 {
193 struct device *dev = &pdev->dev;
194 struct sdhci_pltfm_host *pltfm_host;
195 struct sdhci_host *host;
196 struct ma35_priv *priv;
197 int err;
198 u32 extra, ctl;
199
200 host = sdhci_pltfm_init(pdev, &sdhci_ma35_pdata, sizeof(struct ma35_priv));
201 if (IS_ERR(host))
202 return PTR_ERR(host);
203
204 /* Extra adma table cnt for cross 128M boundary handling. */
205 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
206 extra = min(extra, SDHCI_MAX_SEGS);
207
208 host->adma_table_cnt += extra;
209 pltfm_host = sdhci_priv(host);
210 priv = sdhci_pltfm_priv(pltfm_host);
211
212 pltfm_host->clk = devm_clk_get_optional_enabled(dev, NULL);
213 if (IS_ERR(pltfm_host->clk))
214 return dev_err_probe(dev, PTR_ERR(pltfm_host->clk),
215 "failed to get clk\n");
216
217 err = mmc_of_parse(host->mmc);
218 if (err)
219 return err;
220
221 priv->rst = devm_reset_control_get_exclusive(dev, NULL);
222 if (IS_ERR(priv->rst))
223 return dev_err_probe(dev, PTR_ERR(priv->rst),
224 "failed to get reset control\n");
225
226 sdhci_get_of_property(pdev);
227
228 priv->pinctrl = devm_pinctrl_get(dev);
229 if (!IS_ERR(priv->pinctrl)) {
230 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default");
231 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, "state_uhs");
232 pinctrl_select_state(priv->pinctrl, priv->pins_default);
233 }
234
235 if (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)) {
236 struct regmap *regmap;
237 u32 reg;
238
239 regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys");
240 if (!IS_ERR(regmap)) {
241 /* Enable SDHCI voltage stable for 1.8V */
242 regmap_read(regmap, MA35_SYS_MISCFCR0, ®);
243 reg |= BIT(17);
244 regmap_write(regmap, MA35_SYS_MISCFCR0, reg);
245 }
246
247 host->mmc_host_ops.start_signal_voltage_switch =
248 ma35_start_signal_voltage_switch;
249 }
250
251 host->mmc_host_ops.execute_tuning = ma35_execute_tuning;
252
253 err = sdhci_add_host(host);
254 if (err)
255 return err;
256
257 /*
258 * Split data into chunks of 16 or 8 bytes for transmission.
259 * Each chunk transfer is guaranteed to be uninterrupted on the bus.
260 * This likely corresponds to the AHB bus DMA burst size.
261 */
262 ctl = sdhci_readw(host, MA35_SDHCI_MBIUCTL);
263 ctl &= ~MA35_SDHCI_INCR_MSK;
264 ctl |= MA35_SDHCI_INCR16 | MA35_SDHCI_INCR8;
265 sdhci_writew(host, ctl, MA35_SDHCI_MBIUCTL);
266
267 return 0;
268 }
269
ma35_disable_card_clk(struct sdhci_host * host)270 static void ma35_disable_card_clk(struct sdhci_host *host)
271 {
272 u16 ctrl;
273
274 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
275 if (ctrl & SDHCI_CLOCK_CARD_EN) {
276 ctrl &= ~SDHCI_CLOCK_CARD_EN;
277 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
278 }
279 }
280
ma35_remove(struct platform_device * pdev)281 static void ma35_remove(struct platform_device *pdev)
282 {
283 struct sdhci_host *host = platform_get_drvdata(pdev);
284
285 sdhci_remove_host(host, 0);
286 ma35_disable_card_clk(host);
287 }
288
289 static const struct of_device_id sdhci_ma35_dt_ids[] = {
290 { .compatible = "nuvoton,ma35d1-sdhci" },
291 {}
292 };
293 MODULE_DEVICE_TABLE(of, sdhci_ma35_dt_ids);
294
295 static struct platform_driver sdhci_ma35_driver = {
296 .driver = {
297 .name = "sdhci-ma35",
298 .of_match_table = sdhci_ma35_dt_ids,
299 },
300 .probe = ma35_probe,
301 .remove = ma35_remove,
302 };
303 module_platform_driver(sdhci_ma35_driver);
304
305 MODULE_DESCRIPTION("SDHCI platform driver for Nuvoton MA35");
306 MODULE_AUTHOR("Shan-Chun Hung <shanchun1218@gmail.com>");
307 MODULE_LICENSE("GPL");
308