1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale Vybrid vf610 ADC driver
4 *
5 * Copyright 2013 Freescale Semiconductor, Inc.
6 */
7
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/property.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/cleanup.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/err.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/sysfs.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29
30 /* Vybrid/IMX ADC registers */
31 #define VF610_REG_ADC_HC0 0x00
32 #define VF610_REG_ADC_HC1 0x04
33 #define VF610_REG_ADC_HS 0x08
34 #define VF610_REG_ADC_R0 0x0c
35 #define VF610_REG_ADC_R1 0x10
36 #define VF610_REG_ADC_CFG 0x14
37 #define VF610_REG_ADC_GC 0x18
38 #define VF610_REG_ADC_GS 0x1c
39 #define VF610_REG_ADC_CV 0x20
40 #define VF610_REG_ADC_OFS 0x24
41 #define VF610_REG_ADC_CAL 0x28
42 #define VF610_REG_ADC_PCTL 0x30
43
44 /* Configuration register field define */
45 #define VF610_ADC_MODE_BIT8 0x00
46 #define VF610_ADC_MODE_BIT10 0x04
47 #define VF610_ADC_MODE_BIT12 0x08
48 #define VF610_ADC_MODE_MASK 0x0c
49 #define VF610_ADC_BUSCLK2_SEL 0x01
50 #define VF610_ADC_ALTCLK_SEL 0x02
51 #define VF610_ADC_ADACK_SEL 0x03
52 #define VF610_ADC_ADCCLK_MASK 0x03
53 #define VF610_ADC_CLK_DIV2 0x20
54 #define VF610_ADC_CLK_DIV4 0x40
55 #define VF610_ADC_CLK_DIV8 0x60
56 #define VF610_ADC_CLK_MASK 0x60
57 #define VF610_ADC_ADLSMP_LONG 0x10
58 #define VF610_ADC_ADSTS_SHORT 0x100
59 #define VF610_ADC_ADSTS_NORMAL 0x200
60 #define VF610_ADC_ADSTS_LONG 0x300
61 #define VF610_ADC_ADSTS_MASK 0x300
62 #define VF610_ADC_ADLPC_EN 0x80
63 #define VF610_ADC_ADHSC_EN 0x400
64 #define VF610_ADC_REFSEL_VALT 0x800
65 #define VF610_ADC_REFSEL_VBG 0x1000
66 #define VF610_ADC_ADTRG_HARD 0x2000
67 #define VF610_ADC_AVGS_8 0x4000
68 #define VF610_ADC_AVGS_16 0x8000
69 #define VF610_ADC_AVGS_32 0xC000
70 #define VF610_ADC_AVGS_MASK 0xC000
71 #define VF610_ADC_OVWREN 0x10000
72
73 /* General control register field define */
74 #define VF610_ADC_ADACKEN 0x1
75 #define VF610_ADC_DMAEN 0x2
76 #define VF610_ADC_ACREN 0x4
77 #define VF610_ADC_ACFGT 0x8
78 #define VF610_ADC_ACFE 0x10
79 #define VF610_ADC_AVGEN 0x20
80 #define VF610_ADC_ADCON 0x40
81 #define VF610_ADC_CAL 0x80
82
83 /* Other field define */
84 #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
85 #define VF610_ADC_AIEN (0x1 << 7)
86 #define VF610_ADC_CONV_DISABLE 0x1F
87 #define VF610_ADC_HS_COCO0 0x1
88 #define VF610_ADC_CALF 0x2
89 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
90
91 #define DEFAULT_SAMPLE_TIME 1000
92
93 /* V at 25°C of 696 mV */
94 #define VF610_VTEMP25_3V0 950
95 /* V at 25°C of 699 mV */
96 #define VF610_VTEMP25_3V3 867
97 /* Typical sensor slope coefficient at all temperatures */
98 #define VF610_TEMP_SLOPE_COEFF 1840
99
100 enum clk_sel {
101 VF610_ADCIOC_BUSCLK_SET,
102 VF610_ADCIOC_ALTCLK_SET,
103 VF610_ADCIOC_ADACK_SET,
104 };
105
106 enum vol_ref {
107 VF610_ADCIOC_VR_VREF_SET,
108 VF610_ADCIOC_VR_VALT_SET,
109 VF610_ADCIOC_VR_VBG_SET,
110 };
111
112 enum average_sel {
113 VF610_ADC_SAMPLE_1,
114 VF610_ADC_SAMPLE_4,
115 VF610_ADC_SAMPLE_8,
116 VF610_ADC_SAMPLE_16,
117 VF610_ADC_SAMPLE_32,
118 };
119
120 enum conversion_mode_sel {
121 VF610_ADC_CONV_NORMAL,
122 VF610_ADC_CONV_HIGH_SPEED,
123 VF610_ADC_CONV_LOW_POWER,
124 };
125
126 enum lst_adder_sel {
127 VF610_ADCK_CYCLES_3,
128 VF610_ADCK_CYCLES_5,
129 VF610_ADCK_CYCLES_7,
130 VF610_ADCK_CYCLES_9,
131 VF610_ADCK_CYCLES_13,
132 VF610_ADCK_CYCLES_17,
133 VF610_ADCK_CYCLES_21,
134 VF610_ADCK_CYCLES_25,
135 };
136
137 struct vf610_adc_feature {
138 enum clk_sel clk_sel;
139 enum vol_ref vol_ref;
140 enum conversion_mode_sel conv_mode;
141
142 int clk_div;
143 int sample_rate;
144 int res_mode;
145 u32 lst_adder_index;
146 u32 default_sample_time;
147
148 bool calibration;
149 bool ovwren;
150 };
151
152 struct vf610_adc {
153 struct device *dev;
154 void __iomem *regs;
155 struct clk *clk;
156
157 /* lock to protect against multiple access to the device */
158 struct mutex lock;
159
160 u32 vref_uv;
161 u32 value;
162 struct regulator *vref;
163
164 u32 max_adck_rate[3];
165 struct vf610_adc_feature adc_feature;
166
167 u32 sample_freq_avail[5];
168
169 struct completion completion;
170 /* Ensure the timestamp is naturally aligned */
171 struct {
172 u16 chan;
173 aligned_s64 timestamp;
174 } scan;
175 };
176
177 struct vf610_chip_info {
178 u8 num_channels;
179 };
180
181 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
182 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
183
vf610_adc_calculate_rates(struct vf610_adc * info)184 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
185 {
186 struct vf610_adc_feature *adc_feature = &info->adc_feature;
187 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
188 u32 adck_period, lst_addr_min;
189 int divisor, i;
190
191 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
192
193 if (adck_rate) {
194 /* calculate clk divider which is within specification */
195 divisor = ipg_rate / adck_rate;
196 adc_feature->clk_div = 1 << fls(divisor + 1);
197 } else {
198 /* fall-back value using a safe divisor */
199 adc_feature->clk_div = 8;
200 }
201
202 adck_rate = ipg_rate / adc_feature->clk_div;
203
204 /*
205 * Determine the long sample time adder value to be used based
206 * on the default minimum sample time provided.
207 */
208 adck_period = NSEC_PER_SEC / adck_rate;
209 lst_addr_min = adc_feature->default_sample_time / adck_period;
210 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
211 if (vf610_lst_adder[i] > lst_addr_min) {
212 adc_feature->lst_adder_index = i;
213 break;
214 }
215 }
216
217 /*
218 * Calculate ADC sample frequencies
219 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
220 * which is the same as bus clock.
221 *
222 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
223 * SFCAdder: fixed to 6 ADCK cycles
224 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
225 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
226 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
227 */
228 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
229 info->sample_freq_avail[i] =
230 adck_rate / (6 + vf610_hw_avgs[i] *
231 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
232 }
233
vf610_adc_cfg_init(struct vf610_adc * info)234 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
235 {
236 struct vf610_adc_feature *adc_feature = &info->adc_feature;
237
238 /* set default Configuration for ADC controller */
239 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
240 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
241
242 adc_feature->calibration = true;
243 adc_feature->ovwren = true;
244
245 adc_feature->res_mode = 12;
246 adc_feature->sample_rate = 1;
247
248 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
249
250 vf610_adc_calculate_rates(info);
251 }
252
vf610_adc_cfg_post_set(struct vf610_adc * info)253 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
254 {
255 struct vf610_adc_feature *adc_feature = &info->adc_feature;
256 int cfg_data = 0;
257 int gc_data = 0;
258
259 switch (adc_feature->clk_sel) {
260 case VF610_ADCIOC_ALTCLK_SET:
261 cfg_data |= VF610_ADC_ALTCLK_SEL;
262 break;
263 case VF610_ADCIOC_ADACK_SET:
264 cfg_data |= VF610_ADC_ADACK_SEL;
265 break;
266 default:
267 break;
268 }
269
270 /* low power set for calibration */
271 cfg_data |= VF610_ADC_ADLPC_EN;
272
273 /* enable high speed for calibration */
274 cfg_data |= VF610_ADC_ADHSC_EN;
275
276 /* voltage reference */
277 switch (adc_feature->vol_ref) {
278 case VF610_ADCIOC_VR_VREF_SET:
279 break;
280 case VF610_ADCIOC_VR_VALT_SET:
281 cfg_data |= VF610_ADC_REFSEL_VALT;
282 break;
283 case VF610_ADCIOC_VR_VBG_SET:
284 cfg_data |= VF610_ADC_REFSEL_VBG;
285 break;
286 default:
287 dev_err(info->dev, "error voltage reference\n");
288 }
289
290 /* data overwrite enable */
291 if (adc_feature->ovwren)
292 cfg_data |= VF610_ADC_OVWREN;
293
294 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
295 writel(gc_data, info->regs + VF610_REG_ADC_GC);
296 }
297
vf610_adc_calibration(struct vf610_adc * info)298 static void vf610_adc_calibration(struct vf610_adc *info)
299 {
300 int adc_gc, hc_cfg;
301
302 if (!info->adc_feature.calibration)
303 return;
304
305 /* enable calibration interrupt */
306 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
307 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
308
309 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
310 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
311
312 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
313 dev_err(info->dev, "Timeout for adc calibration\n");
314
315 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
316 if (adc_gc & VF610_ADC_CALF)
317 dev_err(info->dev, "ADC calibration failed\n");
318
319 info->adc_feature.calibration = false;
320 }
321
vf610_adc_cfg_set(struct vf610_adc * info)322 static void vf610_adc_cfg_set(struct vf610_adc *info)
323 {
324 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
325 int cfg_data;
326
327 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
328
329 cfg_data &= ~VF610_ADC_ADLPC_EN;
330 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
331 cfg_data |= VF610_ADC_ADLPC_EN;
332
333 cfg_data &= ~VF610_ADC_ADHSC_EN;
334 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
335 cfg_data |= VF610_ADC_ADHSC_EN;
336
337 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
338 }
339
vf610_adc_sample_set(struct vf610_adc * info)340 static void vf610_adc_sample_set(struct vf610_adc *info)
341 {
342 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
343 int cfg_data, gc_data;
344
345 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
346 gc_data = readl(info->regs + VF610_REG_ADC_GC);
347
348 /* resolution mode */
349 cfg_data &= ~VF610_ADC_MODE_MASK;
350 switch (adc_feature->res_mode) {
351 case 8:
352 cfg_data |= VF610_ADC_MODE_BIT8;
353 break;
354 case 10:
355 cfg_data |= VF610_ADC_MODE_BIT10;
356 break;
357 case 12:
358 cfg_data |= VF610_ADC_MODE_BIT12;
359 break;
360 default:
361 dev_err(info->dev, "error resolution mode\n");
362 break;
363 }
364
365 /* clock select and clock divider */
366 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
367 switch (adc_feature->clk_div) {
368 case 1:
369 break;
370 case 2:
371 cfg_data |= VF610_ADC_CLK_DIV2;
372 break;
373 case 4:
374 cfg_data |= VF610_ADC_CLK_DIV4;
375 break;
376 case 8:
377 cfg_data |= VF610_ADC_CLK_DIV8;
378 break;
379 case 16:
380 switch (adc_feature->clk_sel) {
381 case VF610_ADCIOC_BUSCLK_SET:
382 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
383 break;
384 default:
385 dev_err(info->dev, "error clk divider\n");
386 break;
387 }
388 break;
389 }
390
391 /*
392 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
393 * determined.
394 */
395 switch (adc_feature->lst_adder_index) {
396 case VF610_ADCK_CYCLES_3:
397 break;
398 case VF610_ADCK_CYCLES_5:
399 cfg_data |= VF610_ADC_ADSTS_SHORT;
400 break;
401 case VF610_ADCK_CYCLES_7:
402 cfg_data |= VF610_ADC_ADSTS_NORMAL;
403 break;
404 case VF610_ADCK_CYCLES_9:
405 cfg_data |= VF610_ADC_ADSTS_LONG;
406 break;
407 case VF610_ADCK_CYCLES_13:
408 cfg_data |= VF610_ADC_ADLSMP_LONG;
409 break;
410 case VF610_ADCK_CYCLES_17:
411 cfg_data |= VF610_ADC_ADLSMP_LONG;
412 cfg_data |= VF610_ADC_ADSTS_SHORT;
413 break;
414 case VF610_ADCK_CYCLES_21:
415 cfg_data |= VF610_ADC_ADLSMP_LONG;
416 cfg_data |= VF610_ADC_ADSTS_NORMAL;
417 break;
418 case VF610_ADCK_CYCLES_25:
419 cfg_data |= VF610_ADC_ADLSMP_LONG;
420 cfg_data |= VF610_ADC_ADSTS_NORMAL;
421 break;
422 default:
423 dev_err(info->dev, "error in sample time select\n");
424 }
425
426 /* update hardware average selection */
427 cfg_data &= ~VF610_ADC_AVGS_MASK;
428 gc_data &= ~VF610_ADC_AVGEN;
429 switch (adc_feature->sample_rate) {
430 case VF610_ADC_SAMPLE_1:
431 break;
432 case VF610_ADC_SAMPLE_4:
433 gc_data |= VF610_ADC_AVGEN;
434 break;
435 case VF610_ADC_SAMPLE_8:
436 gc_data |= VF610_ADC_AVGEN;
437 cfg_data |= VF610_ADC_AVGS_8;
438 break;
439 case VF610_ADC_SAMPLE_16:
440 gc_data |= VF610_ADC_AVGEN;
441 cfg_data |= VF610_ADC_AVGS_16;
442 break;
443 case VF610_ADC_SAMPLE_32:
444 gc_data |= VF610_ADC_AVGEN;
445 cfg_data |= VF610_ADC_AVGS_32;
446 break;
447 default:
448 dev_err(info->dev,
449 "error hardware sample average select\n");
450 }
451
452 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
453 writel(gc_data, info->regs + VF610_REG_ADC_GC);
454 }
455
vf610_adc_hw_init(struct vf610_adc * info)456 static void vf610_adc_hw_init(struct vf610_adc *info)
457 {
458 /* CFG: Feature set */
459 vf610_adc_cfg_post_set(info);
460 vf610_adc_sample_set(info);
461
462 /* adc calibration */
463 vf610_adc_calibration(info);
464
465 /* CFG: power and speed set */
466 vf610_adc_cfg_set(info);
467 }
468
vf610_set_conversion_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)469 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
470 const struct iio_chan_spec *chan,
471 unsigned int mode)
472 {
473 struct vf610_adc *info = iio_priv(indio_dev);
474
475 mutex_lock(&info->lock);
476 info->adc_feature.conv_mode = mode;
477 vf610_adc_calculate_rates(info);
478 vf610_adc_hw_init(info);
479 mutex_unlock(&info->lock);
480
481 return 0;
482 }
483
vf610_get_conversion_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)484 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
485 const struct iio_chan_spec *chan)
486 {
487 struct vf610_adc *info = iio_priv(indio_dev);
488
489 return info->adc_feature.conv_mode;
490 }
491
492 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
493 "low-power" };
494
495 static const struct iio_enum vf610_conversion_mode = {
496 .items = vf610_conv_modes,
497 .num_items = ARRAY_SIZE(vf610_conv_modes),
498 .get = vf610_get_conversion_mode,
499 .set = vf610_set_conversion_mode,
500 };
501
502 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
503 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
504 { }
505 };
506
507 #define VF610_ADC_CHAN(_idx, _chan_type) { \
508 .type = (_chan_type), \
509 .indexed = 1, \
510 .channel = (_idx), \
511 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
512 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
513 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
514 .ext_info = vf610_ext_info, \
515 .scan_index = (_idx), \
516 .scan_type = { \
517 .sign = 'u', \
518 .realbits = 12, \
519 .storagebits = 16, \
520 }, \
521 }
522
523 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
524 .type = (_chan_type), \
525 .channel = (_idx), \
526 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
527 .scan_index = (_idx), \
528 .scan_type = { \
529 .sign = 'u', \
530 .realbits = 12, \
531 .storagebits = 16, \
532 }, \
533 }
534
535 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
536 VF610_ADC_CHAN(0, IIO_VOLTAGE),
537 VF610_ADC_CHAN(1, IIO_VOLTAGE),
538 VF610_ADC_CHAN(2, IIO_VOLTAGE),
539 VF610_ADC_CHAN(3, IIO_VOLTAGE),
540 VF610_ADC_CHAN(4, IIO_VOLTAGE),
541 VF610_ADC_CHAN(5, IIO_VOLTAGE),
542 VF610_ADC_CHAN(6, IIO_VOLTAGE),
543 VF610_ADC_CHAN(7, IIO_VOLTAGE),
544 VF610_ADC_CHAN(8, IIO_VOLTAGE),
545 VF610_ADC_CHAN(9, IIO_VOLTAGE),
546 VF610_ADC_CHAN(10, IIO_VOLTAGE),
547 VF610_ADC_CHAN(11, IIO_VOLTAGE),
548 VF610_ADC_CHAN(12, IIO_VOLTAGE),
549 VF610_ADC_CHAN(13, IIO_VOLTAGE),
550 VF610_ADC_CHAN(14, IIO_VOLTAGE),
551 VF610_ADC_CHAN(15, IIO_VOLTAGE),
552 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
553 IIO_CHAN_SOFT_TIMESTAMP(32),
554 /* sentinel */
555 };
556
vf610_adc_read_data(struct vf610_adc * info)557 static int vf610_adc_read_data(struct vf610_adc *info)
558 {
559 int result;
560
561 result = readl(info->regs + VF610_REG_ADC_R0);
562
563 switch (info->adc_feature.res_mode) {
564 case 8:
565 result &= 0xFF;
566 break;
567 case 10:
568 result &= 0x3FF;
569 break;
570 case 12:
571 result &= 0xFFF;
572 break;
573 default:
574 break;
575 }
576
577 return result;
578 }
579
vf610_adc_isr(int irq,void * dev_id)580 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
581 {
582 struct iio_dev *indio_dev = dev_id;
583 struct vf610_adc *info = iio_priv(indio_dev);
584 int coco;
585
586 coco = readl(info->regs + VF610_REG_ADC_HS);
587 if (coco & VF610_ADC_HS_COCO0) {
588 info->value = vf610_adc_read_data(info);
589 if (iio_buffer_enabled(indio_dev)) {
590 info->scan.chan = info->value;
591 iio_push_to_buffers_with_ts(indio_dev, &info->scan,
592 sizeof(info->scan),
593 iio_get_time_ns(indio_dev));
594 iio_trigger_notify_done(indio_dev->trig);
595 } else
596 complete(&info->completion);
597 }
598
599 return IRQ_HANDLED;
600 }
601
vf610_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)602 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
603 struct device_attribute *attr, char *buf)
604 {
605 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
606 size_t len = 0;
607 int i;
608
609 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
610 len += scnprintf(buf + len, PAGE_SIZE - len,
611 "%u ", info->sample_freq_avail[i]);
612
613 /* replace trailing space by newline */
614 buf[len - 1] = '\n';
615
616 return len;
617 }
618
619 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
620
621 static struct attribute *vf610_attributes[] = {
622 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
623 NULL
624 };
625
626 static const struct attribute_group vf610_attribute_group = {
627 .attrs = vf610_attributes,
628 };
629
vf610_read_sample(struct vf610_adc * info,struct iio_chan_spec const * chan,int * val)630 static int vf610_read_sample(struct vf610_adc *info,
631 struct iio_chan_spec const *chan, int *val)
632 {
633 unsigned int hc_cfg;
634 int ret;
635
636 guard(mutex)(&info->lock);
637 reinit_completion(&info->completion);
638 hc_cfg = VF610_ADC_ADCHC(chan->channel);
639 hc_cfg |= VF610_ADC_AIEN;
640 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
641 ret = wait_for_completion_interruptible_timeout(&info->completion,
642 VF610_ADC_TIMEOUT);
643 if (ret == 0)
644 return -ETIMEDOUT;
645
646 if (ret < 0)
647 return ret;
648
649 switch (chan->type) {
650 case IIO_VOLTAGE:
651 *val = info->value;
652 return 0;
653 case IIO_TEMP:
654 /*
655 * Calculate in degree Celsius times 1000
656 * Using the typical sensor slope of 1.84 mV/°C
657 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
658 */
659 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
660 1000000 / VF610_TEMP_SLOPE_COEFF;
661
662 return 0;
663 default:
664 return -EINVAL;
665 }
666 }
667
vf610_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)668 static int vf610_read_raw(struct iio_dev *indio_dev,
669 struct iio_chan_spec const *chan,
670 int *val,
671 int *val2,
672 long mask)
673 {
674 struct vf610_adc *info = iio_priv(indio_dev);
675 long ret;
676
677 switch (mask) {
678 case IIO_CHAN_INFO_RAW:
679 case IIO_CHAN_INFO_PROCESSED:
680 if (!iio_device_claim_direct(indio_dev))
681 return -EBUSY;
682 ret = vf610_read_sample(info, chan, val);
683 iio_device_release_direct(indio_dev);
684 if (ret < 0)
685 return ret;
686
687 return IIO_VAL_INT;
688
689 case IIO_CHAN_INFO_SCALE:
690 *val = info->vref_uv / 1000;
691 *val2 = info->adc_feature.res_mode;
692 return IIO_VAL_FRACTIONAL_LOG2;
693
694 case IIO_CHAN_INFO_SAMP_FREQ:
695 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
696 *val2 = 0;
697 return IIO_VAL_INT;
698
699 default:
700 break;
701 }
702
703 return -EINVAL;
704 }
705
vf610_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)706 static int vf610_write_raw(struct iio_dev *indio_dev,
707 struct iio_chan_spec const *chan,
708 int val,
709 int val2,
710 long mask)
711 {
712 struct vf610_adc *info = iio_priv(indio_dev);
713 int i;
714
715 switch (mask) {
716 case IIO_CHAN_INFO_SAMP_FREQ:
717 for (i = 0;
718 i < ARRAY_SIZE(info->sample_freq_avail);
719 i++)
720 if (val == info->sample_freq_avail[i]) {
721 info->adc_feature.sample_rate = i;
722 vf610_adc_sample_set(info);
723 return 0;
724 }
725 break;
726
727 default:
728 break;
729 }
730
731 return -EINVAL;
732 }
733
vf610_adc_buffer_postenable(struct iio_dev * indio_dev)734 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
735 {
736 struct vf610_adc *info = iio_priv(indio_dev);
737 unsigned int channel;
738 int val;
739
740 val = readl(info->regs + VF610_REG_ADC_GC);
741 val |= VF610_ADC_ADCON;
742 writel(val, info->regs + VF610_REG_ADC_GC);
743
744 channel = find_first_bit(indio_dev->active_scan_mask,
745 iio_get_masklength(indio_dev));
746
747 val = VF610_ADC_ADCHC(channel);
748 val |= VF610_ADC_AIEN;
749
750 writel(val, info->regs + VF610_REG_ADC_HC0);
751
752 return 0;
753 }
754
vf610_adc_buffer_predisable(struct iio_dev * indio_dev)755 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
756 {
757 struct vf610_adc *info = iio_priv(indio_dev);
758 unsigned int hc_cfg = 0;
759 int val;
760
761 val = readl(info->regs + VF610_REG_ADC_GC);
762 val &= ~VF610_ADC_ADCON;
763 writel(val, info->regs + VF610_REG_ADC_GC);
764
765 hc_cfg |= VF610_ADC_CONV_DISABLE;
766 hc_cfg &= ~VF610_ADC_AIEN;
767
768 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
769
770 return 0;
771 }
772
773 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
774 .postenable = &vf610_adc_buffer_postenable,
775 .predisable = &vf610_adc_buffer_predisable,
776 .validate_scan_mask = &iio_validate_scan_mask_onehot,
777 };
778
vf610_adc_reg_access(struct iio_dev * indio_dev,unsigned reg,unsigned writeval,unsigned * readval)779 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
780 unsigned reg, unsigned writeval,
781 unsigned *readval)
782 {
783 struct vf610_adc *info = iio_priv(indio_dev);
784
785 if ((readval == NULL) ||
786 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
787 return -EINVAL;
788
789 *readval = readl(info->regs + reg);
790
791 return 0;
792 }
793
794 static const struct iio_info vf610_adc_iio_info = {
795 .read_raw = &vf610_read_raw,
796 .write_raw = &vf610_write_raw,
797 .debugfs_reg_access = &vf610_adc_reg_access,
798 .attrs = &vf610_attribute_group,
799 };
800
801 static const struct vf610_chip_info vf610_chip_info = {
802 .num_channels = ARRAY_SIZE(vf610_adc_iio_channels),
803 };
804
805 static const struct vf610_chip_info imx6sx_chip_info = {
806 .num_channels = 4,
807 };
808
809 static const struct of_device_id vf610_adc_match[] = {
810 { .compatible = "fsl,imx6sx-adc", .data = &imx6sx_chip_info},
811 { .compatible = "fsl,vf610-adc", .data = &vf610_chip_info},
812 { }
813 };
814 MODULE_DEVICE_TABLE(of, vf610_adc_match);
815
vf610_adc_action_remove(void * d)816 static void vf610_adc_action_remove(void *d)
817 {
818 struct vf610_adc *info = d;
819
820 regulator_disable(info->vref);
821 }
822
vf610_adc_probe(struct platform_device * pdev)823 static int vf610_adc_probe(struct platform_device *pdev)
824 {
825 const struct vf610_chip_info *chip_info;
826 struct device *dev = &pdev->dev;
827 struct vf610_adc *info;
828 struct iio_dev *indio_dev;
829 int irq;
830 int ret;
831
832 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
833 if (!indio_dev)
834 return -ENOMEM;
835
836 info = iio_priv(indio_dev);
837 info->dev = &pdev->dev;
838
839 info->regs = devm_platform_ioremap_resource(pdev, 0);
840 if (IS_ERR(info->regs))
841 return PTR_ERR(info->regs);
842
843 chip_info = device_get_match_data(dev);
844
845 irq = platform_get_irq(pdev, 0);
846 if (irq < 0)
847 return irq;
848
849 ret = devm_request_irq(info->dev, irq,
850 vf610_adc_isr, 0,
851 dev_name(&pdev->dev), indio_dev);
852 if (ret < 0)
853 return dev_err_probe(&pdev->dev, ret, "failed requesting irq, irq = %d\n", irq);
854
855 info->clk = devm_clk_get_enabled(&pdev->dev, "adc");
856 if (IS_ERR(info->clk))
857 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed getting clock\n");
858
859 info->vref = devm_regulator_get(&pdev->dev, "vref");
860 if (IS_ERR(info->vref))
861 return PTR_ERR(info->vref);
862
863 ret = regulator_enable(info->vref);
864 if (ret)
865 return ret;
866
867 ret = devm_add_action_or_reset(&pdev->dev, vf610_adc_action_remove, info);
868 if (ret)
869 return ret;
870
871 info->vref_uv = regulator_get_voltage(info->vref);
872
873 device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3);
874
875 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
876 device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time);
877
878 platform_set_drvdata(pdev, indio_dev);
879
880 init_completion(&info->completion);
881
882 indio_dev->name = dev_name(&pdev->dev);
883 indio_dev->info = &vf610_adc_iio_info;
884 indio_dev->modes = INDIO_DIRECT_MODE;
885 indio_dev->channels = vf610_adc_iio_channels;
886 indio_dev->num_channels = chip_info->num_channels;
887
888 vf610_adc_cfg_init(info);
889 vf610_adc_hw_init(info);
890
891 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, &iio_pollfunc_store_time,
892 NULL, &iio_triggered_buffer_setup_ops);
893 if (ret < 0)
894 return dev_err_probe(&pdev->dev, ret, "Couldn't initialise the buffer\n");
895
896 mutex_init(&info->lock);
897
898 ret = devm_iio_device_register(&pdev->dev, indio_dev);
899 if (ret)
900 return dev_err_probe(&pdev->dev, ret, "Couldn't register the device.\n");
901
902 return 0;
903 }
904
vf610_adc_suspend(struct device * dev)905 static int vf610_adc_suspend(struct device *dev)
906 {
907 struct iio_dev *indio_dev = dev_get_drvdata(dev);
908 struct vf610_adc *info = iio_priv(indio_dev);
909 int hc_cfg;
910
911 /* ADC controller enters to stop mode */
912 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
913 hc_cfg |= VF610_ADC_CONV_DISABLE;
914 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
915
916 clk_disable_unprepare(info->clk);
917 regulator_disable(info->vref);
918
919 return 0;
920 }
921
vf610_adc_resume(struct device * dev)922 static int vf610_adc_resume(struct device *dev)
923 {
924 struct iio_dev *indio_dev = dev_get_drvdata(dev);
925 struct vf610_adc *info = iio_priv(indio_dev);
926 int ret;
927
928 ret = regulator_enable(info->vref);
929 if (ret)
930 return ret;
931
932 ret = clk_prepare_enable(info->clk);
933 if (ret)
934 goto disable_reg;
935
936 vf610_adc_hw_init(info);
937
938 return 0;
939
940 disable_reg:
941 regulator_disable(info->vref);
942 return ret;
943 }
944
945 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend,
946 vf610_adc_resume);
947
948 static struct platform_driver vf610_adc_driver = {
949 .probe = vf610_adc_probe,
950 .driver = {
951 .name = "vf610-adc",
952 .of_match_table = vf610_adc_match,
953 .pm = pm_sleep_ptr(&vf610_adc_pm_ops),
954 },
955 };
956
957 module_platform_driver(vf610_adc_driver);
958
959 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
960 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
961 MODULE_LICENSE("GPL v2");
962