1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
4 *
5 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
6 *
7 * Notes
8 * =====
9 * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured
10 * as a Pulse Width Modulator.
11 *
12 * SCT supports 16 outputs, 16 events and 16 registers. Each event will be
13 * triggered when its related register matches the SCT counter value, and it
14 * will set or clear a selected output.
15 *
16 * One of the events is preselected to generate the period, thus the maximum
17 * number of simultaneous channels is limited to 15. Notice that period is
18 * global to all the channels, thus PWM driver will refuse setting different
19 * values to it, unless there's only one channel requested.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pwm.h>
28
29 /* LPC18xx SCT registers */
30 #define LPC18XX_PWM_CONFIG 0x000
31 #define LPC18XX_PWM_CONFIG_UNIFY BIT(0)
32 #define LPC18XX_PWM_CONFIG_NORELOAD BIT(7)
33
34 #define LPC18XX_PWM_CTRL 0x004
35 #define LPC18XX_PWM_CTRL_HALT BIT(2)
36 #define LPC18XX_PWM_BIDIR BIT(4)
37 #define LPC18XX_PWM_PRE_SHIFT 5
38 #define LPC18XX_PWM_PRE_MASK (0xff << LPC18XX_PWM_PRE_SHIFT)
39 #define LPC18XX_PWM_PRE(x) (x << LPC18XX_PWM_PRE_SHIFT)
40
41 #define LPC18XX_PWM_LIMIT 0x008
42
43 #define LPC18XX_PWM_RES_BASE 0x058
44 #define LPC18XX_PWM_RES_SHIFT(_ch) (_ch * 2)
45 #define LPC18XX_PWM_RES(_ch, _action) (_action << LPC18XX_PWM_RES_SHIFT(_ch))
46 #define LPC18XX_PWM_RES_MASK(_ch) (0x3 << LPC18XX_PWM_RES_SHIFT(_ch))
47
48 #define LPC18XX_PWM_MATCH_BASE 0x100
49 #define LPC18XX_PWM_MATCH(_ch) (LPC18XX_PWM_MATCH_BASE + _ch * 4)
50
51 #define LPC18XX_PWM_MATCHREL_BASE 0x200
52 #define LPC18XX_PWM_MATCHREL(_ch) (LPC18XX_PWM_MATCHREL_BASE + _ch * 4)
53
54 #define LPC18XX_PWM_EVSTATEMSK_BASE 0x300
55 #define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8)
56 #define LPC18XX_PWM_EVSTATEMSK_ALL 0xffffffff
57
58 #define LPC18XX_PWM_EVCTRL_BASE 0x304
59 #define LPC18XX_PWM_EVCTRL(_ev) (LPC18XX_PWM_EVCTRL_BASE + _ev * 8)
60
61 #define LPC18XX_PWM_EVCTRL_MATCH(_ch) _ch
62
63 #define LPC18XX_PWM_EVCTRL_COMB_SHIFT 12
64 #define LPC18XX_PWM_EVCTRL_COMB_MATCH (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT)
65
66 #define LPC18XX_PWM_OUTPUTSET_BASE 0x500
67 #define LPC18XX_PWM_OUTPUTSET(_ch) (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8)
68
69 #define LPC18XX_PWM_OUTPUTCL_BASE 0x504
70 #define LPC18XX_PWM_OUTPUTCL(_ch) (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8)
71
72 /* LPC18xx SCT unified counter */
73 #define LPC18XX_PWM_TIMER_MAX 0xffffffff
74
75 /* LPC18xx SCT events */
76 #define LPC18XX_PWM_EVENT_PERIOD 0
77 #define LPC18XX_PWM_EVENT_MAX 16
78
79 #define LPC18XX_NUM_PWMS 16
80
81 /* SCT conflict resolution */
82 enum lpc18xx_pwm_res_action {
83 LPC18XX_PWM_RES_NONE,
84 LPC18XX_PWM_RES_SET,
85 LPC18XX_PWM_RES_CLEAR,
86 LPC18XX_PWM_RES_TOGGLE,
87 };
88
89 struct lpc18xx_pwm_data {
90 unsigned int duty_event;
91 };
92
93 struct lpc18xx_pwm_chip {
94 void __iomem *base;
95 struct clk *pwm_clk;
96 unsigned long clk_rate;
97 unsigned int period_ns;
98 unsigned int min_period_ns;
99 u64 max_period_ns;
100 unsigned int period_event;
101 unsigned long event_map;
102 struct lpc18xx_pwm_data channeldata[LPC18XX_NUM_PWMS];
103 };
104
105 static inline struct lpc18xx_pwm_chip *
to_lpc18xx_pwm_chip(struct pwm_chip * chip)106 to_lpc18xx_pwm_chip(struct pwm_chip *chip)
107 {
108 return pwmchip_get_drvdata(chip);
109 }
110
lpc18xx_pwm_writel(struct lpc18xx_pwm_chip * lpc18xx_pwm,u32 reg,u32 val)111 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
112 u32 reg, u32 val)
113 {
114 writel(val, lpc18xx_pwm->base + reg);
115 }
116
lpc18xx_pwm_readl(struct lpc18xx_pwm_chip * lpc18xx_pwm,u32 reg)117 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
118 u32 reg)
119 {
120 return readl(lpc18xx_pwm->base + reg);
121 }
122
lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip * lpc18xx_pwm,struct pwm_device * pwm,enum lpc18xx_pwm_res_action action)123 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
124 struct pwm_device *pwm,
125 enum lpc18xx_pwm_res_action action)
126 {
127 u32 val;
128
129 /*
130 * Simultaneous set and clear may happen on an output, that is the case
131 * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict
132 * resolution action to be taken in such a case.
133 */
134 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
135 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
136 val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
137 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
138 }
139
lpc18xx_pwm_config_period(struct pwm_chip * chip,u64 period_ns)140 static void lpc18xx_pwm_config_period(struct pwm_chip *chip, u64 period_ns)
141 {
142 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
143 u32 val;
144
145 /*
146 * With clk_rate < NSEC_PER_SEC this cannot overflow.
147 * With period_ns < max_period_ns this also fits into an u32.
148 * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
149 * we have val >= 1.
150 */
151 val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
152
153 lpc18xx_pwm_writel(lpc18xx_pwm,
154 LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
155 val - 1);
156
157 lpc18xx_pwm_writel(lpc18xx_pwm,
158 LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
159 val - 1);
160 }
161
lpc18xx_pwm_config_duty(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns)162 static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
163 struct pwm_device *pwm, u64 duty_ns)
164 {
165 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
166 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
167 u32 val;
168
169 /*
170 * With clk_rate <= NSEC_PER_SEC this cannot overflow.
171 * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
172 */
173 val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
174
175 lpc18xx_pwm_writel(lpc18xx_pwm,
176 LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
177 val);
178
179 lpc18xx_pwm_writel(lpc18xx_pwm,
180 LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event),
181 val);
182 }
183
lpc18xx_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)184 static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
185 int duty_ns, int period_ns)
186 {
187 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
188 int requested_events;
189
190 if (period_ns < lpc18xx_pwm->min_period_ns ||
191 period_ns > lpc18xx_pwm->max_period_ns) {
192 dev_err(pwmchip_parent(chip), "period %d not in range\n", period_ns);
193 return -ERANGE;
194 }
195
196 requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
197 LPC18XX_PWM_EVENT_MAX);
198
199 /*
200 * The PWM supports only a single period for all PWM channels.
201 * Once the period is set, it can only be changed if no more than one
202 * channel is requested at that moment.
203 */
204 if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
205 lpc18xx_pwm->period_ns) {
206 dev_err(pwmchip_parent(chip), "conflicting period requested for PWM %u\n",
207 pwm->hwpwm);
208 return -EBUSY;
209 }
210
211 if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
212 !lpc18xx_pwm->period_ns) {
213 lpc18xx_pwm->period_ns = period_ns;
214 lpc18xx_pwm_config_period(chip, period_ns);
215 }
216
217 lpc18xx_pwm_config_duty(chip, pwm, duty_ns);
218
219 return 0;
220 }
221
lpc18xx_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)222 static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
223 {
224 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
225 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
226 enum lpc18xx_pwm_res_action res_action;
227 unsigned int set_event, clear_event;
228
229 lpc18xx_pwm_writel(lpc18xx_pwm,
230 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event),
231 LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) |
232 LPC18XX_PWM_EVCTRL_COMB_MATCH);
233
234 lpc18xx_pwm_writel(lpc18xx_pwm,
235 LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event),
236 LPC18XX_PWM_EVSTATEMSK_ALL);
237
238 if (polarity == PWM_POLARITY_NORMAL) {
239 set_event = lpc18xx_pwm->period_event;
240 clear_event = lpc18xx_data->duty_event;
241 res_action = LPC18XX_PWM_RES_SET;
242 } else {
243 set_event = lpc18xx_data->duty_event;
244 clear_event = lpc18xx_pwm->period_event;
245 res_action = LPC18XX_PWM_RES_CLEAR;
246 }
247
248 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
249 BIT(set_event));
250 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
251 BIT(clear_event));
252 lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
253
254 return 0;
255 }
256
lpc18xx_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)257 static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
258 {
259 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
260 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
261
262 lpc18xx_pwm_writel(lpc18xx_pwm,
263 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0);
264 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
265 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
266 }
267
lpc18xx_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)268 static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
269 {
270 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
271 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
272 unsigned long event;
273
274 event = find_first_zero_bit(&lpc18xx_pwm->event_map,
275 LPC18XX_PWM_EVENT_MAX);
276
277 if (event >= LPC18XX_PWM_EVENT_MAX) {
278 dev_err(pwmchip_parent(chip),
279 "maximum number of simultaneous channels reached\n");
280 return -EBUSY;
281 }
282
283 set_bit(event, &lpc18xx_pwm->event_map);
284 lpc18xx_data->duty_event = event;
285
286 return 0;
287 }
288
lpc18xx_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)289 static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
290 {
291 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
292 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
293
294 clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
295 }
296
lpc18xx_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)297 static int lpc18xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
298 const struct pwm_state *state)
299 {
300 int err;
301 bool enabled = pwm->state.enabled;
302
303 if (state->polarity != pwm->state.polarity && pwm->state.enabled) {
304 lpc18xx_pwm_disable(chip, pwm);
305 enabled = false;
306 }
307
308 if (!state->enabled) {
309 if (enabled)
310 lpc18xx_pwm_disable(chip, pwm);
311
312 return 0;
313 }
314
315 err = lpc18xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
316 if (err)
317 return err;
318
319 if (!enabled)
320 err = lpc18xx_pwm_enable(chip, pwm, state->polarity);
321
322 return err;
323 }
324 static const struct pwm_ops lpc18xx_pwm_ops = {
325 .apply = lpc18xx_pwm_apply,
326 .request = lpc18xx_pwm_request,
327 .free = lpc18xx_pwm_free,
328 };
329
330 static const struct of_device_id lpc18xx_pwm_of_match[] = {
331 { .compatible = "nxp,lpc1850-sct-pwm" },
332 { }
333 };
334 MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match);
335
lpc18xx_pwm_probe(struct platform_device * pdev)336 static int lpc18xx_pwm_probe(struct platform_device *pdev)
337 {
338 struct pwm_chip *chip;
339 struct lpc18xx_pwm_chip *lpc18xx_pwm;
340 int ret;
341 u64 val;
342
343 chip = devm_pwmchip_alloc(&pdev->dev, LPC18XX_NUM_PWMS, sizeof(*lpc18xx_pwm));
344 if (IS_ERR(chip))
345 return PTR_ERR(chip);
346 lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
347
348 lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
349 if (IS_ERR(lpc18xx_pwm->base))
350 return PTR_ERR(lpc18xx_pwm->base);
351
352 lpc18xx_pwm->pwm_clk = devm_clk_get_enabled(&pdev->dev, "pwm");
353 if (IS_ERR(lpc18xx_pwm->pwm_clk))
354 return dev_err_probe(&pdev->dev, PTR_ERR(lpc18xx_pwm->pwm_clk),
355 "failed to get pwm clock\n");
356
357 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
358 if (!lpc18xx_pwm->clk_rate)
359 return dev_err_probe(&pdev->dev,
360 -EINVAL, "pwm clock has no frequency\n");
361
362 /*
363 * If clkrate is too fast, the calculations in .apply() might overflow.
364 */
365 if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC)
366 return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
367
368 lpc18xx_pwm->max_period_ns =
369 mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);
370
371 lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
372 lpc18xx_pwm->clk_rate);
373
374 chip->ops = &lpc18xx_pwm_ops;
375
376 /* SCT counter must be in unify (32 bit) mode */
377 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
378 LPC18XX_PWM_CONFIG_UNIFY);
379
380 /*
381 * Everytime the timer counter reaches the period value, the related
382 * event will be triggered and the counter reset to 0.
383 */
384 set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
385 lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
386
387 lpc18xx_pwm_writel(lpc18xx_pwm,
388 LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
389 LPC18XX_PWM_EVSTATEMSK_ALL);
390
391 val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
392 LPC18XX_PWM_EVCTRL_COMB_MATCH;
393 lpc18xx_pwm_writel(lpc18xx_pwm,
394 LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
395
396 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
397 BIT(lpc18xx_pwm->period_event));
398
399 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
400 val &= ~LPC18XX_PWM_BIDIR;
401 val &= ~LPC18XX_PWM_CTRL_HALT;
402 val &= ~LPC18XX_PWM_PRE_MASK;
403 val |= LPC18XX_PWM_PRE(0);
404 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
405
406 ret = pwmchip_add(chip);
407 if (ret < 0)
408 return dev_err_probe(&pdev->dev, ret, "pwmchip_add failed\n");
409
410 platform_set_drvdata(pdev, chip);
411
412 return 0;
413 }
414
lpc18xx_pwm_remove(struct platform_device * pdev)415 static void lpc18xx_pwm_remove(struct platform_device *pdev)
416 {
417 struct pwm_chip *chip = platform_get_drvdata(pdev);
418 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
419 u32 val;
420
421 pwmchip_remove(chip);
422
423 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
424 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,
425 val | LPC18XX_PWM_CTRL_HALT);
426 }
427
428 static struct platform_driver lpc18xx_pwm_driver = {
429 .driver = {
430 .name = "lpc18xx-sct-pwm",
431 .of_match_table = lpc18xx_pwm_of_match,
432 },
433 .probe = lpc18xx_pwm_probe,
434 .remove = lpc18xx_pwm_remove,
435 };
436 module_platform_driver(lpc18xx_pwm_driver);
437
438 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
439 MODULE_DESCRIPTION("NXP LPC18xx PWM driver");
440 MODULE_LICENSE("GPL v2");
441