1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2019 NXP
3
4 #include <linux/bitrev.h>
5 #include <linux/clk.h>
6 #include <linux/firmware.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of_platform.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/reset.h>
13 #include <sound/dmaengine_pcm.h>
14 #include <sound/pcm_iec958.h>
15 #include <sound/pcm_params.h>
16
17 #include "fsl_xcvr.h"
18 #include "fsl_utils.h"
19 #include "imx-pcm.h"
20
21 #define FSL_XCVR_CAPDS_SIZE 256
22 #define SPDIF_NUM_RATES 7
23
24 enum fsl_xcvr_pll_verison {
25 PLL_MX8MP,
26 PLL_MX95,
27 };
28
29 struct fsl_xcvr_soc_data {
30 const char *fw_name;
31 bool spdif_only;
32 bool use_edma;
33 bool use_phy;
34 enum fsl_xcvr_pll_verison pll_ver;
35 };
36
37 struct fsl_xcvr {
38 const struct fsl_xcvr_soc_data *soc_data;
39 struct platform_device *pdev;
40 struct regmap *regmap;
41 struct regmap *regmap_phy;
42 struct regmap *regmap_pll;
43 struct clk *ipg_clk;
44 struct clk *pll_ipg_clk;
45 struct clk *phy_clk;
46 struct clk *spba_clk;
47 struct clk *pll8k_clk;
48 struct clk *pll11k_clk;
49 struct reset_control *reset;
50 u8 streams;
51 u32 mode;
52 u32 arc_mode;
53 void __iomem *ram_addr;
54 struct snd_dmaengine_dai_dma_data dma_prms_rx;
55 struct snd_dmaengine_dai_dma_data dma_prms_tx;
56 struct snd_aes_iec958 rx_iec958;
57 struct snd_aes_iec958 tx_iec958;
58 u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
59 struct work_struct work_rst;
60 spinlock_t lock; /* Protect hw_reset and trigger */
61 struct snd_pcm_hw_constraint_list spdif_constr_rates;
62 u32 spdif_constr_rates_list[SPDIF_NUM_RATES];
63 };
64
65 static const char * const inc_mode[] = {
66 "On enabled and bitcount increment", "On enabled"
67 };
68
69 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,
70 FSL_XCVR_TX_DPTH_CNTR_CTRL,
71 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
72 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,
73 FSL_XCVR_RX_DPTH_CNTR_CTRL,
74 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode);
75
76 static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = {
77 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
78 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
79 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
80 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum,
81 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
82 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
83 FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
84 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
85 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL,
86 FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
87 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
88 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR,
89 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
90 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR,
91 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
92 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR,
93 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
94 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR,
95 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
96 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
97 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0,
98 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
99 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum,
100 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double),
101 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
102 FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0,
103 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
104 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL,
105 FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0,
106 fsl_asoc_get_volsw, fsl_asoc_put_volsw),
107 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR,
108 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
109 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR,
110 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
111 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR,
112 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
113 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR,
114 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx),
115 };
116
117 static const struct fsl_xcvr_pll_conf {
118 u8 mfi; /* min=0x18, max=0x38 */
119 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
120 u32 mfd; /* unsigned int */
121 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
122 } fsl_xcvr_pll_cfg[] = {
123 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */
124 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */
125 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */
126 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */
127 };
128
129 /*
130 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
131 * stream. Todo: to check how this case can be considered below
132 */
133 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
134 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
135 .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
136 .list = fsl_xcvr_earc_channels,
137 };
138
139 static const u32 fsl_xcvr_earc_rates[] = {
140 32000, 44100, 48000, 64000, 88200, 96000,
141 128000, 176400, 192000, 256000, 352800, 384000,
142 512000, 705600, 768000, 1024000, 1411200, 1536000,
143 };
144 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
145 .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
146 .list = fsl_xcvr_earc_rates,
147 };
148
149 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
150 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
151 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
152 .list = fsl_xcvr_spdif_channels,
153 };
154
155 static const u32 fsl_xcvr_spdif_rates[] = {
156 32000, 44100, 48000, 88200, 96000, 176400, 192000,
157 };
158 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
159 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
160 .list = fsl_xcvr_spdif_rates,
161 };
162
fsl_xcvr_arc_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)163 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
164 struct snd_ctl_elem_value *ucontrol)
165 {
166 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
167 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
168 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
169 unsigned int *item = ucontrol->value.enumerated.item;
170 int val = snd_soc_enum_item_to_val(e, item[0]);
171 int ret;
172
173 if (val < 0 || val > 1)
174 return -EINVAL;
175
176 ret = (xcvr->arc_mode != val);
177
178 xcvr->arc_mode = val;
179
180 return ret;
181 }
182
fsl_xcvr_arc_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)183 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *ucontrol)
185 {
186 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
187 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
188
189 ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
190
191 return 0;
192 }
193
194 static const u32 fsl_xcvr_phy_arc_cfg[] = {
195 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
196 };
197
198 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
199 static const struct soc_enum fsl_xcvr_arc_mode_enum =
200 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
201 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
202 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
203 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
204
205 /* Capabilities data structure, bytes */
fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)206 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
207 struct snd_ctl_elem_info *uinfo)
208 {
209 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
210 uinfo->count = FSL_XCVR_CAPDS_SIZE;
211
212 return 0;
213 }
214
fsl_xcvr_capds_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)215 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
216 struct snd_ctl_elem_value *ucontrol)
217 {
218 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
219 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
220
221 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
222
223 return 0;
224 }
225
fsl_xcvr_capds_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)226 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_value *ucontrol)
228 {
229 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
230 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
231 int changed;
232
233 changed = memcmp(xcvr->cap_ds, ucontrol->value.bytes.data,
234 sizeof(xcvr->cap_ds)) != 0;
235 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data,
236 sizeof(xcvr->cap_ds));
237
238 return changed;
239 }
240
241 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
242 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
243 .name = "Capabilities Data Structure",
244 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
245 .info = fsl_xcvr_type_capds_bytes_info,
246 .get = fsl_xcvr_capds_get,
247 .put = fsl_xcvr_capds_put,
248 };
249
fsl_xcvr_activate_ctl(struct snd_soc_dai * dai,const char * name,bool active)250 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
251 bool active)
252 {
253 struct snd_soc_card *card = dai->component->card;
254 struct snd_kcontrol *kctl;
255 bool enabled;
256
257 lockdep_assert_held(&card->snd_card->controls_rwsem);
258
259 kctl = snd_soc_card_get_kcontrol(card, name);
260 if (kctl == NULL)
261 return -ENOENT;
262
263 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
264 if (active == enabled)
265 return 0; /* nothing to do */
266
267 if (active)
268 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
269 else
270 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
271
272 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
273
274 return 1;
275 }
276
fsl_xcvr_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)277 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
278 struct snd_ctl_elem_value *ucontrol)
279 {
280 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
281 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
282 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
283 unsigned int *item = ucontrol->value.enumerated.item;
284 int val = snd_soc_enum_item_to_val(e, item[0]);
285 struct snd_soc_card *card = dai->component->card;
286 struct snd_soc_pcm_runtime *rtd;
287 int ret;
288
289 if (val < FSL_XCVR_MODE_SPDIF || val > FSL_XCVR_MODE_EARC)
290 return -EINVAL;
291
292 ret = (xcvr->mode != val);
293
294 xcvr->mode = val;
295
296 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
297 (xcvr->mode == FSL_XCVR_MODE_ARC));
298 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
299 (xcvr->mode == FSL_XCVR_MODE_EARC));
300 /* Allow playback for SPDIF only */
301 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
302 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
303 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
304 return ret;
305 }
306
fsl_xcvr_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)307 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
308 struct snd_ctl_elem_value *ucontrol)
309 {
310 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
311 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
312
313 ucontrol->value.enumerated.item[0] = xcvr->mode;
314
315 return 0;
316 }
317
318 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
319 static const struct soc_enum fsl_xcvr_mode_enum =
320 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
321 static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
322 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
323 fsl_xcvr_mode_get, fsl_xcvr_mode_put);
324
325 /** phy: true => phy, false => pll */
fsl_xcvr_ai_write(struct fsl_xcvr * xcvr,u8 reg,u32 data,bool phy)326 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
327 {
328 struct device *dev = &xcvr->pdev->dev;
329 u32 val, idx, tidx;
330 int ret;
331
332 idx = BIT(phy ? 26 : 24);
333 tidx = BIT(phy ? 27 : 25);
334
335 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
336 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
337 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
338 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
339
340 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
341 (val & idx) == ((val & tidx) >> 1),
342 10, 10000);
343 if (ret)
344 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
345 phy ? "PHY" : "PLL", reg, data);
346 return ret;
347 }
348
fsl_xcvr_ai_read(struct fsl_xcvr * xcvr,u8 reg,u32 * data,bool phy)349 static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy)
350 {
351 struct device *dev = &xcvr->pdev->dev;
352 u32 val, idx, tidx;
353 int ret;
354
355 idx = BIT(phy ? 26 : 24);
356 tidx = BIT(phy ? 27 : 25);
357
358 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
359 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
360 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
361
362 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
363 (val & idx) == ((val & tidx) >> 1),
364 10, 10000);
365 if (ret)
366 dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n",
367 phy ? "PHY" : "PLL", reg);
368
369 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data);
370
371 return ret;
372 }
373
fsl_xcvr_phy_reg_read(void * context,unsigned int reg,unsigned int * val)374 static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val)
375 {
376 struct fsl_xcvr *xcvr = context;
377
378 return fsl_xcvr_ai_read(xcvr, reg, val, 1);
379 }
380
fsl_xcvr_phy_reg_write(void * context,unsigned int reg,unsigned int val)381 static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val)
382 {
383 struct fsl_xcvr *xcvr = context;
384
385 return fsl_xcvr_ai_write(xcvr, reg, val, 1);
386 }
387
fsl_xcvr_pll_reg_read(void * context,unsigned int reg,unsigned int * val)388 static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val)
389 {
390 struct fsl_xcvr *xcvr = context;
391
392 return fsl_xcvr_ai_read(xcvr, reg, val, 0);
393 }
394
fsl_xcvr_pll_reg_write(void * context,unsigned int reg,unsigned int val)395 static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val)
396 {
397 struct fsl_xcvr *xcvr = context;
398
399 return fsl_xcvr_ai_write(xcvr, reg, val, 0);
400 }
401
fsl_xcvr_en_phy_pll(struct fsl_xcvr * xcvr,u32 freq,bool tx)402 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
403 {
404 struct device *dev = &xcvr->pdev->dev;
405 u32 i, div = 0, log2, val;
406 int ret;
407
408 if (!xcvr->soc_data->use_phy)
409 return 0;
410
411 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
412 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
413 div = fsl_xcvr_pll_cfg[i].fout / freq;
414 break;
415 }
416 }
417
418 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
419 return -EINVAL;
420
421 log2 = ilog2(div);
422
423 /* Release AI interface from reset */
424 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
425 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
426 if (ret < 0) {
427 dev_err(dev, "Error while setting IER0: %d\n", ret);
428 return ret;
429 }
430
431 switch (xcvr->soc_data->pll_ver) {
432 case PLL_MX8MP:
433 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
434 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP,
435 FSL_XCVR_PLL_BANDGAP_EN_VBG);
436
437 /* PLL: CTRL0: DIV_INTEGER */
438 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi);
439 /* PLL: NUMERATOR: MFN */
440 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn);
441 /* PLL: DENOMINATOR: MFD */
442 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd);
443 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
444 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
445 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP);
446 udelay(25);
447 /* PLL: CTRL0: Clear Hold Ring Off */
448 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
449 FSL_XCVR_PLL_CTRL0_HROFF);
450 udelay(100);
451 if (tx) { /* TX is enabled for SPDIF only */
452 /* PLL: POSTDIV: PDIV0 */
453 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
454 FSL_XCVR_PLL_PDIVx(log2, 0));
455 /* PLL: CTRL_SET: CLKMUX0_EN */
456 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
457 FSL_XCVR_PLL_CTRL0_CM0_EN);
458 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
459 /* PLL: POSTDIV: PDIV1 */
460 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
461 FSL_XCVR_PLL_PDIVx(log2, 1));
462 /* PLL: CTRL_SET: CLKMUX1_EN */
463 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
464 FSL_XCVR_PLL_CTRL0_CM1_EN);
465 } else { /* SPDIF / ARC RX */
466 /* PLL: POSTDIV: PDIV2 */
467 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
468 FSL_XCVR_PLL_PDIVx(log2, 2));
469 /* PLL: CTRL_SET: CLKMUX2_EN */
470 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
471 FSL_XCVR_PLL_CTRL0_CM2_EN);
472 }
473 break;
474 case PLL_MX95:
475 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div;
476 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val);
477 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT;
478 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val);
479 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR,
480 fsl_xcvr_pll_cfg[i].mfd);
481 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN;
482 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val);
483 break;
484 default:
485 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
486 return -EINVAL;
487 }
488
489 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
490 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
491 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
492 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
493 FSL_XCVR_PHY_CTRL_PHY_EN);
494 /* PHY: CTRL2_SET: EARC_TX_MODE */
495 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2,
496 FSL_XCVR_PHY_CTRL2_EARC_TXMS);
497 } else if (!tx) { /* SPDIF / ARC RX mode */
498 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
499 /* PHY: CTRL_SET: SPDIF_EN */
500 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
501 FSL_XCVR_PHY_CTRL_SPDIF_EN);
502 else /* PHY: CTRL_SET: ARC RX setup */
503 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
504 FSL_XCVR_PHY_CTRL_PHY_EN |
505 FSL_XCVR_PHY_CTRL_RX_CM_EN |
506 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]);
507 }
508
509 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
510 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
511 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
512 return 0;
513 }
514
fsl_xcvr_en_aud_pll(struct fsl_xcvr * xcvr,u32 freq)515 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
516 {
517 struct device *dev = &xcvr->pdev->dev;
518 int ret;
519
520 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
521 clk_disable_unprepare(xcvr->phy_clk);
522 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk,
523 xcvr->pll8k_clk, xcvr->pll11k_clk, freq);
524 ret = clk_set_rate(xcvr->phy_clk, freq);
525 if (ret < 0) {
526 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
527 return ret;
528 }
529 ret = clk_prepare_enable(xcvr->phy_clk);
530 if (ret) {
531 dev_err(dev, "failed to start PHY clock: %d\n", ret);
532 return ret;
533 }
534
535 if (!xcvr->soc_data->use_phy)
536 return 0;
537 /* Release AI interface from reset */
538 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
539 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
540 if (ret < 0) {
541 dev_err(dev, "Error while setting IER0: %d\n", ret);
542 return ret;
543 }
544
545 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
546 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
547 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
548 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
549 FSL_XCVR_PHY_CTRL_PHY_EN);
550 /* PHY: CTRL2_SET: EARC_TX_MODE */
551 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2,
552 FSL_XCVR_PHY_CTRL2_EARC_TXMS);
553 } else { /* SPDIF mode */
554 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
555 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
556 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
557 FSL_XCVR_PHY_CTRL_SPDIF_EN);
558 }
559
560 dev_dbg(dev, "PLL Fexp: %u\n", freq);
561
562 return 0;
563 }
564
565 #define FSL_XCVR_SPDIF_RX_FREQ 175000000
fsl_xcvr_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)566 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
567 struct snd_soc_dai *dai)
568 {
569 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
570 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
571 u32 m_ctl = 0, v_ctl = 0;
572 u32 r = substream->runtime->rate, ch = substream->runtime->channels;
573 u32 fout = 32 * r * ch * 10;
574 int ret = 0;
575
576 switch (xcvr->mode) {
577 case FSL_XCVR_MODE_SPDIF:
578 if (xcvr->soc_data->spdif_only && tx) {
579 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL,
580 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
581 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
582 if (ret < 0) {
583 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
584 return ret;
585 }
586 }
587 fallthrough;
588 case FSL_XCVR_MODE_ARC:
589 if (tx) {
590 ret = fsl_xcvr_en_aud_pll(xcvr, fout);
591 if (ret < 0) {
592 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
593 fout, ret);
594 return ret;
595 }
596
597 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL,
598 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
599 if (ret < 0) {
600 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
601 return ret;
602 }
603
604 /**
605 * set SPDIF MODE - this flag is used to gate
606 * SPDIF output, useless for SPDIF RX
607 */
608 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
609 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
610 } else {
611 /**
612 * Clear RX FIFO, flip RX FIFO bits,
613 * disable eARC related HW mode detects
614 */
615 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
616 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
617 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
618 FSL_XCVR_RX_DPTH_CTRL_COMP |
619 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
620 if (ret < 0) {
621 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
622 return ret;
623 }
624
625 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
626 if (ret < 0) {
627 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
628 FSL_XCVR_SPDIF_RX_FREQ, ret);
629 return ret;
630 }
631 }
632 break;
633 case FSL_XCVR_MODE_EARC:
634 if (!tx) {
635 /** Clear RX FIFO, flip RX FIFO bits */
636 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
637 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
638 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
639 if (ret < 0) {
640 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
641 return ret;
642 }
643
644 /** Enable eARC related HW mode detects */
645 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
646 FSL_XCVR_RX_DPTH_CTRL_COMP |
647 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
648 if (ret < 0) {
649 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
650 return ret;
651 }
652 }
653
654 /* clear CMDC RESET */
655 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
656 /* set TX_RX_MODE */
657 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
658 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
659 break;
660 }
661
662 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
663 if (ret < 0) {
664 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
665 return ret;
666 }
667
668 return 0;
669 }
670
fsl_xcvr_constr(const struct snd_pcm_substream * substream,const struct snd_pcm_hw_constraint_list * channels,const struct snd_pcm_hw_constraint_list * rates)671 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
672 const struct snd_pcm_hw_constraint_list *channels,
673 const struct snd_pcm_hw_constraint_list *rates)
674 {
675 struct snd_pcm_runtime *rt = substream->runtime;
676 int ret;
677
678 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
679 channels);
680 if (ret < 0)
681 return ret;
682
683 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
684 rates);
685 if (ret < 0)
686 return ret;
687
688 return 0;
689 }
690
fsl_xcvr_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)691 static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
692 struct snd_soc_dai *dai)
693 {
694 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
695 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
696 int ret = 0;
697
698 if (xcvr->streams & BIT(substream->stream)) {
699 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
700 return -EBUSY;
701 }
702
703 /*
704 * EDMA controller needs period size to be a multiple of
705 * tx/rx maxburst
706 */
707 if (xcvr->soc_data->use_edma)
708 snd_pcm_hw_constraint_step(substream->runtime, 0,
709 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
710 tx ? xcvr->dma_prms_tx.maxburst :
711 xcvr->dma_prms_rx.maxburst);
712
713 switch (xcvr->mode) {
714 case FSL_XCVR_MODE_SPDIF:
715 case FSL_XCVR_MODE_ARC:
716 if (xcvr->soc_data->spdif_only && tx)
717 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
718 &xcvr->spdif_constr_rates);
719 else
720 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
721 &fsl_xcvr_spdif_rates_constr);
722 break;
723 case FSL_XCVR_MODE_EARC:
724 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
725 &fsl_xcvr_earc_rates_constr);
726 break;
727 }
728 if (ret < 0)
729 return ret;
730
731 xcvr->streams |= BIT(substream->stream);
732
733 if (!xcvr->soc_data->spdif_only) {
734 struct snd_soc_card *card = dai->component->card;
735
736 /* Disable XCVR controls if there is stream started */
737 down_read(&card->snd_card->controls_rwsem);
738 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
739 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
740 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
741 up_read(&card->snd_card->controls_rwsem);
742 }
743
744 return 0;
745 }
746
fsl_xcvr_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)747 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
748 struct snd_soc_dai *dai)
749 {
750 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
751 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
752 u32 mask = 0, val = 0;
753 int ret;
754
755 xcvr->streams &= ~BIT(substream->stream);
756
757 /* Enable XCVR controls if there is no stream started */
758 if (!xcvr->streams) {
759 if (!xcvr->soc_data->spdif_only) {
760 struct snd_soc_card *card = dai->component->card;
761
762 down_read(&card->snd_card->controls_rwsem);
763 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
764 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
765 (xcvr->mode == FSL_XCVR_MODE_ARC));
766 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
767 (xcvr->mode == FSL_XCVR_MODE_EARC));
768 up_read(&card->snd_card->controls_rwsem);
769 }
770 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
771 FSL_XCVR_IRQ_EARC_ALL, 0);
772 if (ret < 0) {
773 dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
774 return;
775 }
776
777 /* clear SPDIF MODE */
778 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
779 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
780 }
781
782 if (xcvr->mode == FSL_XCVR_MODE_EARC) {
783 /* set CMDC RESET */
784 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
785 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
786 }
787
788 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
789 if (ret < 0) {
790 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
791 return;
792 }
793 }
794
fsl_xcvr_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)795 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
796 struct snd_soc_dai *dai)
797 {
798 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
799 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
800 unsigned long lock_flags;
801 int ret = 0;
802
803 spin_lock_irqsave(&xcvr->lock, lock_flags);
804
805 switch (cmd) {
806 case SNDRV_PCM_TRIGGER_START:
807 case SNDRV_PCM_TRIGGER_RESUME:
808 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
809 /* set DPATH RESET */
810 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
811 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
812 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx));
813 if (ret < 0) {
814 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret);
815 goto release_lock;
816 }
817
818 if (tx) {
819 switch (xcvr->mode) {
820 case FSL_XCVR_MODE_EARC:
821 /* set isr_cmdc_tx_en, w1c */
822 ret = regmap_write(xcvr->regmap,
823 FSL_XCVR_ISR_SET,
824 FSL_XCVR_ISR_CMDC_TX_EN);
825 if (ret < 0) {
826 dev_err(dai->dev, "err updating isr %d\n", ret);
827 goto release_lock;
828 }
829 fallthrough;
830 case FSL_XCVR_MODE_SPDIF:
831 ret = regmap_set_bits(xcvr->regmap,
832 FSL_XCVR_TX_DPTH_CTRL,
833 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
834 if (ret < 0) {
835 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
836 goto release_lock;
837 }
838 break;
839 }
840 }
841
842 /* enable DMA RD/WR */
843 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
844 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
845 if (ret < 0) {
846 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
847 goto release_lock;
848 }
849
850 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
851 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
852 if (ret < 0) {
853 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
854 goto release_lock;
855 }
856
857 /* clear DPATH RESET */
858 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
859 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
860 0);
861 if (ret < 0) {
862 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
863 goto release_lock;
864 }
865
866 break;
867 case SNDRV_PCM_TRIGGER_STOP:
868 case SNDRV_PCM_TRIGGER_SUSPEND:
869 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
870 /* disable DMA RD/WR */
871 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
872 FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
873 FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
874 if (ret < 0) {
875 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
876 goto release_lock;
877 }
878
879 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
880 FSL_XCVR_IRQ_EARC_ALL, 0);
881 if (ret < 0) {
882 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret);
883 goto release_lock;
884 }
885
886 if (tx) {
887 switch (xcvr->mode) {
888 case FSL_XCVR_MODE_SPDIF:
889 ret = regmap_clear_bits(xcvr->regmap,
890 FSL_XCVR_TX_DPTH_CTRL,
891 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
892 if (ret < 0) {
893 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
894 goto release_lock;
895 }
896 if (xcvr->soc_data->spdif_only)
897 break;
898 else
899 fallthrough;
900 case FSL_XCVR_MODE_EARC:
901 /* clear ISR_CMDC_TX_EN, W1C */
902 ret = regmap_write(xcvr->regmap,
903 FSL_XCVR_ISR_CLR,
904 FSL_XCVR_ISR_CMDC_TX_EN);
905 if (ret < 0) {
906 dev_err(dai->dev,
907 "Err updating ISR %d\n", ret);
908 goto release_lock;
909 }
910 break;
911 }
912 }
913 break;
914 default:
915 ret = -EINVAL;
916 break;
917 }
918
919 release_lock:
920 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
921 return ret;
922 }
923
fsl_xcvr_load_firmware(struct fsl_xcvr * xcvr)924 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
925 {
926 struct device *dev = &xcvr->pdev->dev;
927 const struct firmware *fw;
928 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
929 u32 mask, val;
930
931 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
932 if (ret) {
933 dev_err(dev, "failed to request firmware.\n");
934 return ret;
935 }
936
937 rem = fw->size;
938
939 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
940 if (rem > 16384) {
941 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
942 release_firmware(fw);
943 return -ENOMEM;
944 }
945
946 for (page = 0; page < 10; page++) {
947 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
948 FSL_XCVR_EXT_CTRL_PAGE_MASK,
949 FSL_XCVR_EXT_CTRL_PAGE(page));
950 if (ret < 0) {
951 dev_err(dev, "FW: failed to set page %d, err=%d\n",
952 page, ret);
953 goto err_firmware;
954 }
955
956 off = page * size;
957 out = min(rem, size);
958 /* IPG clock is assumed to be running, otherwise it will hang */
959 if (out > 0) {
960 /* write firmware into code memory */
961 memcpy_toio(xcvr->ram_addr, fw->data + off, out);
962 rem -= out;
963 if (rem == 0) {
964 /* last part of firmware written */
965 /* clean remaining part of code memory page */
966 memset_io(xcvr->ram_addr + out, 0, size - out);
967 }
968 } else {
969 /* clean current page, including data memory */
970 memset_io(xcvr->ram_addr, 0, size);
971 }
972 }
973
974 err_firmware:
975 release_firmware(fw);
976 if (ret < 0)
977 return ret;
978
979 /* configure watermarks */
980 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
981 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
982 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
983 /* disable DMA RD/WR */
984 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
985 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
986 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
987 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
988 val |= FSL_XCVR_EXT_CTRL_PAGE(8);
989
990 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
991 if (ret < 0) {
992 dev_err(dev, "Failed to set watermarks: %d\n", ret);
993 return ret;
994 }
995
996 /* Store Capabilities Data Structure into Data RAM */
997 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
998 FSL_XCVR_CAPDS_SIZE);
999 return 0;
1000 }
1001
fsl_xcvr_type_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1002 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
1003 struct snd_ctl_elem_info *uinfo)
1004 {
1005 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1006 uinfo->count = 1;
1007
1008 return 0;
1009 }
1010
fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1011 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_info *uinfo)
1013 {
1014 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1015 uinfo->count = sizeof_field(struct snd_aes_iec958, status);
1016
1017 return 0;
1018 }
1019
fsl_xcvr_rx_cs_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1020 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
1021 struct snd_ctl_elem_value *ucontrol)
1022 {
1023 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1024 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
1025
1026 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
1027
1028 return 0;
1029 }
1030
fsl_xcvr_tx_cs_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1031 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
1032 struct snd_ctl_elem_value *ucontrol)
1033 {
1034 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1035 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
1036
1037 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
1038
1039 return 0;
1040 }
1041
fsl_xcvr_tx_cs_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1042 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
1043 struct snd_ctl_elem_value *ucontrol)
1044 {
1045 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1046 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
1047 int changed;
1048
1049 changed = memcmp(xcvr->tx_iec958.status,
1050 ucontrol->value.iec958.status,
1051 sizeof(xcvr->tx_iec958.status)) != 0;
1052 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status,
1053 sizeof(xcvr->tx_iec958.status));
1054
1055 return changed;
1056 }
1057
1058 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
1059 /* Channel status controller */
1060 {
1061 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1062 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
1063 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1064 .info = fsl_xcvr_type_iec958_info,
1065 .get = fsl_xcvr_rx_cs_get,
1066 },
1067 /* Capture channel status, bytes */
1068 {
1069 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1070 .name = "Capture Channel Status",
1071 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1072 .info = fsl_xcvr_type_iec958_bytes_info,
1073 .get = fsl_xcvr_rx_cs_get,
1074 },
1075 };
1076
1077 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
1078 /* Channel status controller */
1079 {
1080 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1081 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1082 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
1083 .info = fsl_xcvr_type_iec958_info,
1084 .get = fsl_xcvr_tx_cs_get,
1085 .put = fsl_xcvr_tx_cs_put,
1086 },
1087 /* Playback channel status, bytes */
1088 {
1089 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1090 .name = "Playback Channel Status",
1091 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
1092 .info = fsl_xcvr_type_iec958_bytes_info,
1093 .get = fsl_xcvr_tx_cs_get,
1094 .put = fsl_xcvr_tx_cs_put,
1095 },
1096 };
1097
fsl_xcvr_dai_probe(struct snd_soc_dai * dai)1098 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
1099 {
1100 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
1101
1102 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
1103
1104 if (xcvr->soc_data->spdif_only)
1105 xcvr->mode = FSL_XCVR_MODE_SPDIF;
1106 else {
1107 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
1108 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
1109 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
1110 }
1111 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
1112 ARRAY_SIZE(fsl_xcvr_tx_ctls));
1113 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
1114 ARRAY_SIZE(fsl_xcvr_rx_ctls));
1115 return 0;
1116 }
1117
1118 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
1119 .probe = fsl_xcvr_dai_probe,
1120 .prepare = fsl_xcvr_prepare,
1121 .startup = fsl_xcvr_startup,
1122 .shutdown = fsl_xcvr_shutdown,
1123 .trigger = fsl_xcvr_trigger,
1124 };
1125
1126 static struct snd_soc_dai_driver fsl_xcvr_dai = {
1127 .ops = &fsl_xcvr_dai_ops,
1128 .playback = {
1129 .stream_name = "CPU-Playback",
1130 .channels_min = 1,
1131 .channels_max = 32,
1132 .rate_min = 32000,
1133 .rate_max = 1536000,
1134 .rates = SNDRV_PCM_RATE_KNOT,
1135 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1136 },
1137 .capture = {
1138 .stream_name = "CPU-Capture",
1139 .channels_min = 1,
1140 .channels_max = 32,
1141 .rate_min = 32000,
1142 .rate_max = 1536000,
1143 .rates = SNDRV_PCM_RATE_KNOT,
1144 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1145 },
1146 };
1147
fsl_xcvr_component_probe(struct snd_soc_component * component)1148 static int fsl_xcvr_component_probe(struct snd_soc_component *component)
1149 {
1150 struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component);
1151
1152 snd_soc_component_init_regmap(component, xcvr->regmap);
1153
1154 return 0;
1155 }
1156
1157 static const struct snd_soc_component_driver fsl_xcvr_comp = {
1158 .name = "fsl-xcvr-dai",
1159 .probe = fsl_xcvr_component_probe,
1160 .controls = fsl_xcvr_timestamp_ctrls,
1161 .num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls),
1162 .legacy_dai_naming = 1,
1163 };
1164
1165 static const struct reg_default fsl_xcvr_reg_defaults[] = {
1166 { FSL_XCVR_VERSION, 0x00000000 },
1167 { FSL_XCVR_EXT_CTRL, 0xF8204040 },
1168 { FSL_XCVR_EXT_STATUS, 0x00000000 },
1169 { FSL_XCVR_EXT_IER0, 0x00000000 },
1170 { FSL_XCVR_EXT_IER1, 0x00000000 },
1171 { FSL_XCVR_EXT_ISR, 0x00000000 },
1172 { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
1173 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
1174 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
1175 { FSL_XCVR_IER, 0x00000000 },
1176 { FSL_XCVR_ISR, 0x00000000 },
1177 { FSL_XCVR_ISR_SET, 0x00000000 },
1178 { FSL_XCVR_ISR_CLR, 0x00000000 },
1179 { FSL_XCVR_ISR_TOG, 0x00000000 },
1180 { FSL_XCVR_CLK_CTRL, 0x0000018F },
1181 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 },
1182 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 },
1183 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 },
1184 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 },
1185 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
1186 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
1187 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
1188 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
1189 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
1190 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 },
1191 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
1192 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
1193 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
1194 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
1195 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
1196 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
1197 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
1198 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
1199 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
1200 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
1201 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
1202 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
1203 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 },
1204 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
1205 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
1206 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
1207 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
1208 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 },
1209 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
1210 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
1211 { FSL_XCVR_DEBUG_REG_0, 0x00000000 },
1212 { FSL_XCVR_DEBUG_REG_1, 0x00000000 },
1213 };
1214
fsl_xcvr_readable_reg(struct device * dev,unsigned int reg)1215 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
1216 {
1217 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1218
1219 if (!xcvr->soc_data->use_phy)
1220 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
1221 reg > FSL_XCVR_TX_DPTH_BCRR)
1222 return false;
1223 switch (reg) {
1224 case FSL_XCVR_VERSION:
1225 case FSL_XCVR_EXT_CTRL:
1226 case FSL_XCVR_EXT_STATUS:
1227 case FSL_XCVR_EXT_IER0:
1228 case FSL_XCVR_EXT_IER1:
1229 case FSL_XCVR_EXT_ISR:
1230 case FSL_XCVR_EXT_ISR_SET:
1231 case FSL_XCVR_EXT_ISR_CLR:
1232 case FSL_XCVR_EXT_ISR_TOG:
1233 case FSL_XCVR_IER:
1234 case FSL_XCVR_ISR:
1235 case FSL_XCVR_ISR_SET:
1236 case FSL_XCVR_ISR_CLR:
1237 case FSL_XCVR_ISR_TOG:
1238 case FSL_XCVR_PHY_AI_CTRL:
1239 case FSL_XCVR_PHY_AI_CTRL_SET:
1240 case FSL_XCVR_PHY_AI_CTRL_CLR:
1241 case FSL_XCVR_PHY_AI_CTRL_TOG:
1242 case FSL_XCVR_PHY_AI_RDATA:
1243 case FSL_XCVR_CLK_CTRL:
1244 case FSL_XCVR_RX_DPTH_CTRL:
1245 case FSL_XCVR_RX_DPTH_CTRL_SET:
1246 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1247 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1248 case FSL_XCVR_RX_CS_DATA_0:
1249 case FSL_XCVR_RX_CS_DATA_1:
1250 case FSL_XCVR_RX_CS_DATA_2:
1251 case FSL_XCVR_RX_CS_DATA_3:
1252 case FSL_XCVR_RX_CS_DATA_4:
1253 case FSL_XCVR_RX_CS_DATA_5:
1254 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1255 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1256 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1257 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1258 case FSL_XCVR_RX_DPTH_TSCR:
1259 case FSL_XCVR_RX_DPTH_BCR:
1260 case FSL_XCVR_RX_DPTH_BCTR:
1261 case FSL_XCVR_RX_DPTH_BCRR:
1262 case FSL_XCVR_TX_DPTH_CTRL:
1263 case FSL_XCVR_TX_DPTH_CTRL_SET:
1264 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1265 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1266 case FSL_XCVR_TX_CS_DATA_0:
1267 case FSL_XCVR_TX_CS_DATA_1:
1268 case FSL_XCVR_TX_CS_DATA_2:
1269 case FSL_XCVR_TX_CS_DATA_3:
1270 case FSL_XCVR_TX_CS_DATA_4:
1271 case FSL_XCVR_TX_CS_DATA_5:
1272 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1273 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1274 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1275 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1276 case FSL_XCVR_TX_DPTH_TSCR:
1277 case FSL_XCVR_TX_DPTH_BCR:
1278 case FSL_XCVR_TX_DPTH_BCTR:
1279 case FSL_XCVR_TX_DPTH_BCRR:
1280 case FSL_XCVR_DEBUG_REG_0:
1281 case FSL_XCVR_DEBUG_REG_1:
1282 return true;
1283 default:
1284 return false;
1285 }
1286 }
1287
fsl_xcvr_writeable_reg(struct device * dev,unsigned int reg)1288 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
1289 {
1290 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1291
1292 if (!xcvr->soc_data->use_phy)
1293 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
1294 return false;
1295 switch (reg) {
1296 case FSL_XCVR_EXT_CTRL:
1297 case FSL_XCVR_EXT_IER0:
1298 case FSL_XCVR_EXT_IER1:
1299 case FSL_XCVR_EXT_ISR:
1300 case FSL_XCVR_EXT_ISR_SET:
1301 case FSL_XCVR_EXT_ISR_CLR:
1302 case FSL_XCVR_EXT_ISR_TOG:
1303 case FSL_XCVR_IER:
1304 case FSL_XCVR_ISR_SET:
1305 case FSL_XCVR_ISR_CLR:
1306 case FSL_XCVR_ISR_TOG:
1307 case FSL_XCVR_PHY_AI_CTRL:
1308 case FSL_XCVR_PHY_AI_CTRL_SET:
1309 case FSL_XCVR_PHY_AI_CTRL_CLR:
1310 case FSL_XCVR_PHY_AI_CTRL_TOG:
1311 case FSL_XCVR_PHY_AI_WDATA:
1312 case FSL_XCVR_CLK_CTRL:
1313 case FSL_XCVR_RX_DPTH_CTRL:
1314 case FSL_XCVR_RX_DPTH_CTRL_SET:
1315 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1316 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1317 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1318 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1319 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1320 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1321 case FSL_XCVR_TX_DPTH_CTRL:
1322 case FSL_XCVR_TX_DPTH_CTRL_SET:
1323 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1324 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1325 case FSL_XCVR_TX_CS_DATA_0:
1326 case FSL_XCVR_TX_CS_DATA_1:
1327 case FSL_XCVR_TX_CS_DATA_2:
1328 case FSL_XCVR_TX_CS_DATA_3:
1329 case FSL_XCVR_TX_CS_DATA_4:
1330 case FSL_XCVR_TX_CS_DATA_5:
1331 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1332 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1333 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1334 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1335 return true;
1336 default:
1337 return false;
1338 }
1339 }
1340
fsl_xcvr_volatile_reg(struct device * dev,unsigned int reg)1341 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1342 {
1343 switch (reg) {
1344 case FSL_XCVR_EXT_STATUS:
1345 case FSL_XCVR_EXT_ISR:
1346 case FSL_XCVR_EXT_ISR_SET:
1347 case FSL_XCVR_EXT_ISR_CLR:
1348 case FSL_XCVR_EXT_ISR_TOG:
1349 case FSL_XCVR_ISR:
1350 case FSL_XCVR_ISR_SET:
1351 case FSL_XCVR_ISR_CLR:
1352 case FSL_XCVR_ISR_TOG:
1353 case FSL_XCVR_PHY_AI_CTRL:
1354 case FSL_XCVR_PHY_AI_CTRL_SET:
1355 case FSL_XCVR_PHY_AI_CTRL_CLR:
1356 case FSL_XCVR_PHY_AI_CTRL_TOG:
1357 case FSL_XCVR_PHY_AI_RDATA:
1358 case FSL_XCVR_RX_CS_DATA_0:
1359 case FSL_XCVR_RX_CS_DATA_1:
1360 case FSL_XCVR_RX_CS_DATA_2:
1361 case FSL_XCVR_RX_CS_DATA_3:
1362 case FSL_XCVR_RX_CS_DATA_4:
1363 case FSL_XCVR_RX_CS_DATA_5:
1364 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1365 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1366 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1367 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1368 case FSL_XCVR_RX_DPTH_TSCR:
1369 case FSL_XCVR_RX_DPTH_BCR:
1370 case FSL_XCVR_RX_DPTH_BCTR:
1371 case FSL_XCVR_RX_DPTH_BCRR:
1372 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1373 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1374 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1375 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1376 case FSL_XCVR_TX_DPTH_TSCR:
1377 case FSL_XCVR_TX_DPTH_BCR:
1378 case FSL_XCVR_TX_DPTH_BCTR:
1379 case FSL_XCVR_TX_DPTH_BCRR:
1380 case FSL_XCVR_DEBUG_REG_0:
1381 case FSL_XCVR_DEBUG_REG_1:
1382 return true;
1383 default:
1384 return false;
1385 }
1386 }
1387
1388 static const struct regmap_config fsl_xcvr_regmap_cfg = {
1389 .reg_bits = 32,
1390 .reg_stride = 4,
1391 .val_bits = 32,
1392 .max_register = FSL_XCVR_MAX_REG,
1393 .reg_defaults = fsl_xcvr_reg_defaults,
1394 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
1395 .readable_reg = fsl_xcvr_readable_reg,
1396 .volatile_reg = fsl_xcvr_volatile_reg,
1397 .writeable_reg = fsl_xcvr_writeable_reg,
1398 .cache_type = REGCACHE_FLAT,
1399 };
1400
1401 static const struct reg_default fsl_xcvr_phy_reg_defaults[] = {
1402 { FSL_XCVR_PHY_CTRL, 0x58200804 },
1403 { FSL_XCVR_PHY_STATUS, 0x00000000 },
1404 { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 },
1405 { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 },
1406 { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 },
1407 { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 },
1408 { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 },
1409 { FSL_XCVR_PHY_CTRL2, 0x80000000 },
1410 };
1411
1412 static const struct regmap_config fsl_xcvr_regmap_phy_cfg = {
1413 .name = "phy",
1414 .reg_bits = 8,
1415 .reg_stride = 4,
1416 .val_bits = 32,
1417 .max_register = FSL_XCVR_PHY_CTRL2_TOG,
1418 .reg_defaults = fsl_xcvr_phy_reg_defaults,
1419 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults),
1420 .cache_type = REGCACHE_FLAT,
1421 .reg_read = fsl_xcvr_phy_reg_read,
1422 .reg_write = fsl_xcvr_phy_reg_write,
1423 };
1424
1425 static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = {
1426 .name = "pllv0",
1427 .reg_bits = 8,
1428 .reg_stride = 4,
1429 .val_bits = 32,
1430 .max_register = FSL_XCVR_PLL_STAT0_TOG,
1431 .cache_type = REGCACHE_FLAT,
1432 .reg_read = fsl_xcvr_pll_reg_read,
1433 .reg_write = fsl_xcvr_pll_reg_write,
1434 };
1435
1436 static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = {
1437 .name = "pllv1",
1438 .reg_bits = 8,
1439 .reg_stride = 4,
1440 .val_bits = 32,
1441 .max_register = FSL_XCVR_GP_PLL_STATUS_TOG,
1442 .cache_type = REGCACHE_FLAT,
1443 .reg_read = fsl_xcvr_pll_reg_read,
1444 .reg_write = fsl_xcvr_pll_reg_write,
1445 };
1446
reset_rx_work(struct work_struct * work)1447 static void reset_rx_work(struct work_struct *work)
1448 {
1449 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst);
1450 struct device *dev = &xcvr->pdev->dev;
1451 unsigned long lock_flags;
1452 u32 ext_ctrl;
1453
1454 dev_dbg(dev, "reset rx path\n");
1455 spin_lock_irqsave(&xcvr->lock, lock_flags);
1456 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl);
1457
1458 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) {
1459 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1460 FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
1461 FSL_XCVR_EXT_CTRL_DMA_RD_DIS);
1462 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1463 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
1464 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET);
1465 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1466 FSL_XCVR_EXT_CTRL_DMA_RD_DIS,
1467 0);
1468 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1469 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET,
1470 0);
1471 }
1472 spin_unlock_irqrestore(&xcvr->lock, lock_flags);
1473 }
1474
irq0_isr(int irq,void * devid)1475 static irqreturn_t irq0_isr(int irq, void *devid)
1476 {
1477 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1478 struct device *dev = &xcvr->pdev->dev;
1479 struct regmap *regmap = xcvr->regmap;
1480 void __iomem *reg_ctrl, *reg_buff;
1481 u32 isr, isr_clr = 0, val, i;
1482
1483 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
1484
1485 if (isr & FSL_XCVR_IRQ_NEW_CS) {
1486 dev_dbg(dev, "Received new CS block\n");
1487 isr_clr |= FSL_XCVR_IRQ_NEW_CS;
1488 if (xcvr->soc_data->fw_name) {
1489 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
1490 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1491 FSL_XCVR_EXT_CTRL_PAGE_MASK,
1492 FSL_XCVR_EXT_CTRL_PAGE(8));
1493
1494 /* Find updated CS buffer */
1495 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1496 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1497 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1498 if (!val) {
1499 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1500 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1501 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1502 }
1503
1504 if (val) {
1505 /* copy CS buffer */
1506 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1507 sizeof(xcvr->rx_iec958.status));
1508 for (i = 0; i < 6; i++) {
1509 val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1510 *(u32 *)(xcvr->rx_iec958.status + i*4) =
1511 bitrev32(val);
1512 }
1513 /* clear CS control register */
1514 writel_relaxed(0, reg_ctrl);
1515 }
1516 } else {
1517 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0,
1518 (u32 *)&xcvr->rx_iec958.status[0]);
1519 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1,
1520 (u32 *)&xcvr->rx_iec958.status[4]);
1521 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2,
1522 (u32 *)&xcvr->rx_iec958.status[8]);
1523 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3,
1524 (u32 *)&xcvr->rx_iec958.status[12]);
1525 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4,
1526 (u32 *)&xcvr->rx_iec958.status[16]);
1527 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5,
1528 (u32 *)&xcvr->rx_iec958.status[20]);
1529 for (i = 0; i < 6; i++) {
1530 val = *(u32 *)(xcvr->rx_iec958.status + i * 4);
1531 *(u32 *)(xcvr->rx_iec958.status + i * 4) =
1532 bitrev32(val);
1533 }
1534 regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
1535 FSL_XCVR_RX_DPTH_CTRL_CSA);
1536 }
1537 }
1538 if (isr & FSL_XCVR_IRQ_NEW_UD) {
1539 dev_dbg(dev, "Received new UD block\n");
1540 isr_clr |= FSL_XCVR_IRQ_NEW_UD;
1541 }
1542 if (isr & FSL_XCVR_IRQ_MUTE) {
1543 dev_dbg(dev, "HW mute bit detected\n");
1544 isr_clr |= FSL_XCVR_IRQ_MUTE;
1545 }
1546 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
1547 dev_dbg(dev, "RX/TX FIFO full/empty\n");
1548 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
1549 }
1550 if (isr & FSL_XCVR_IRQ_ARC_MODE) {
1551 dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
1552 isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
1553 }
1554 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
1555 dev_dbg(dev, "DMA read request\n");
1556 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
1557 }
1558 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
1559 dev_dbg(dev, "DMA write request\n");
1560 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
1561 }
1562 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) {
1563 dev_dbg(dev, "CMDC status update\n");
1564 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD;
1565 }
1566 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) {
1567 dev_dbg(dev, "Preamble mismatch\n");
1568 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH;
1569 }
1570 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) {
1571 dev_dbg(dev, "Unexpected preamble received\n");
1572 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC;
1573 }
1574 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) {
1575 dev_dbg(dev, "M/W preamble mismatch\n");
1576 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH;
1577 }
1578 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) {
1579 dev_dbg(dev, "B preamble mismatch\n");
1580 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH;
1581 }
1582
1583 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH |
1584 FSL_XCVR_IRQ_UNEXP_PRE_REC |
1585 FSL_XCVR_IRQ_M_W_PRE_MISMATCH |
1586 FSL_XCVR_IRQ_B_PRE_MISMATCH)) {
1587 schedule_work(&xcvr->work_rst);
1588 }
1589
1590 if (isr_clr) {
1591 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
1592 return IRQ_HANDLED;
1593 }
1594
1595 return IRQ_NONE;
1596 }
1597
1598 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
1599 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1600 .use_phy = true,
1601 .pll_ver = PLL_MX8MP,
1602 };
1603
1604 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
1605 .spdif_only = true,
1606 .use_edma = true,
1607 };
1608
1609 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = {
1610 .fw_name = "imx/xcvr/xcvr-imx95.bin",
1611 .spdif_only = true,
1612 .use_phy = true,
1613 .use_edma = true,
1614 .pll_ver = PLL_MX95,
1615 };
1616
1617 static const struct of_device_id fsl_xcvr_dt_ids[] = {
1618 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1619 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1620 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
1621 { /* sentinel */ }
1622 };
1623 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
1624
fsl_xcvr_probe(struct platform_device * pdev)1625 static int fsl_xcvr_probe(struct platform_device *pdev)
1626 {
1627 struct device *dev = &pdev->dev;
1628 struct fsl_xcvr *xcvr;
1629 struct resource *rx_res, *tx_res;
1630 void __iomem *regs;
1631 int ret, irq;
1632
1633 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1634 if (!xcvr)
1635 return -ENOMEM;
1636
1637 xcvr->pdev = pdev;
1638 xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1639
1640 xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1641 if (IS_ERR(xcvr->ipg_clk))
1642 return dev_err_probe(dev, PTR_ERR(xcvr->ipg_clk),
1643 "failed to get ipg clock\n");
1644
1645 xcvr->phy_clk = devm_clk_get(dev, "phy");
1646 if (IS_ERR(xcvr->phy_clk))
1647 return dev_err_probe(dev, PTR_ERR(xcvr->phy_clk),
1648 "failed to get phy clock\n");
1649
1650 xcvr->spba_clk = devm_clk_get(dev, "spba");
1651 if (IS_ERR(xcvr->spba_clk))
1652 return dev_err_probe(dev, PTR_ERR(xcvr->spba_clk),
1653 "failed to get spba clock\n");
1654
1655 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1656 if (IS_ERR(xcvr->pll_ipg_clk))
1657 return dev_err_probe(dev, PTR_ERR(xcvr->pll_ipg_clk),
1658 "failed to get pll_ipg clock\n");
1659
1660 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk,
1661 &xcvr->pll11k_clk);
1662
1663 if (xcvr->soc_data->spdif_only) {
1664 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk))
1665 xcvr->pll8k_clk = xcvr->phy_clk;
1666 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates,
1667 &fsl_xcvr_spdif_rates_constr,
1668 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL,
1669 xcvr->spdif_constr_rates_list);
1670 }
1671
1672 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1673 if (IS_ERR(xcvr->ram_addr))
1674 return PTR_ERR(xcvr->ram_addr);
1675
1676 regs = devm_platform_ioremap_resource_byname(pdev, "regs");
1677 if (IS_ERR(regs))
1678 return PTR_ERR(regs);
1679
1680 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1681 &fsl_xcvr_regmap_cfg);
1682 if (IS_ERR(xcvr->regmap))
1683 return dev_err_probe(dev, PTR_ERR(xcvr->regmap), "failed to init XCVR regmap\n");
1684
1685 if (xcvr->soc_data->use_phy) {
1686 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr,
1687 &fsl_xcvr_regmap_phy_cfg);
1688 if (IS_ERR(xcvr->regmap_phy))
1689 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_phy),
1690 "failed to init XCVR PHY regmap\n");
1691
1692 switch (xcvr->soc_data->pll_ver) {
1693 case PLL_MX8MP:
1694 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr,
1695 &fsl_xcvr_regmap_pllv0_cfg);
1696 if (IS_ERR(xcvr->regmap_pll))
1697 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll),
1698 "failed to init XCVR PLL regmap\n");
1699 break;
1700 case PLL_MX95:
1701 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr,
1702 &fsl_xcvr_regmap_pllv1_cfg);
1703 if (IS_ERR(xcvr->regmap_pll))
1704 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll),
1705 "failed to init XCVR PLL regmap\n");
1706 break;
1707 default:
1708 return dev_err_probe(dev, -EINVAL,
1709 "Error for PLL version %d\n",
1710 xcvr->soc_data->pll_ver);
1711 }
1712 }
1713
1714 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1715 if (IS_ERR(xcvr->reset))
1716 return dev_err_probe(dev, PTR_ERR(xcvr->reset),
1717 "failed to get XCVR reset control\n");
1718
1719 /* get IRQs */
1720 irq = platform_get_irq(pdev, 0);
1721 if (irq < 0)
1722 return irq;
1723
1724 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1725 if (ret)
1726 return dev_err_probe(dev, ret, "failed to claim IRQ0\n");
1727
1728 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
1729 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
1730 if (!rx_res || !tx_res)
1731 return dev_err_probe(dev, -EINVAL, "could not find rxfifo or txfifo resource\n");
1732 xcvr->dma_prms_rx.chan_name = "rx";
1733 xcvr->dma_prms_tx.chan_name = "tx";
1734 xcvr->dma_prms_rx.addr = rx_res->start;
1735 xcvr->dma_prms_tx.addr = tx_res->start;
1736 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1737 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1738
1739 platform_set_drvdata(pdev, xcvr);
1740 pm_runtime_enable(dev);
1741 regcache_cache_only(xcvr->regmap, true);
1742 if (xcvr->soc_data->use_phy) {
1743 regcache_cache_only(xcvr->regmap_phy, true);
1744 regcache_cache_only(xcvr->regmap_pll, true);
1745 }
1746
1747 /*
1748 * Register platform component before registering cpu dai for there
1749 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1750 */
1751 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1752 if (ret) {
1753 pm_runtime_disable(dev);
1754 return dev_err_probe(dev, ret, "failed to pcm register\n");
1755 }
1756
1757 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1758 &fsl_xcvr_dai, 1);
1759 if (ret) {
1760 pm_runtime_disable(dev);
1761 dev_err(dev, "failed to register component %s\n",
1762 fsl_xcvr_comp.name);
1763 }
1764
1765 INIT_WORK(&xcvr->work_rst, reset_rx_work);
1766 spin_lock_init(&xcvr->lock);
1767 return ret;
1768 }
1769
fsl_xcvr_remove(struct platform_device * pdev)1770 static void fsl_xcvr_remove(struct platform_device *pdev)
1771 {
1772 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev);
1773
1774 cancel_work_sync(&xcvr->work_rst);
1775 pm_runtime_disable(&pdev->dev);
1776 }
1777
fsl_xcvr_runtime_suspend(struct device * dev)1778 static int fsl_xcvr_runtime_suspend(struct device *dev)
1779 {
1780 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1781 int ret;
1782
1783 if (!xcvr->soc_data->spdif_only &&
1784 xcvr->mode == FSL_XCVR_MODE_EARC) {
1785 /* Assert M0+ reset */
1786 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1787 FSL_XCVR_EXT_CTRL_CORE_RESET,
1788 FSL_XCVR_EXT_CTRL_CORE_RESET);
1789 if (ret < 0)
1790 dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1791 }
1792
1793 regcache_cache_only(xcvr->regmap, true);
1794 if (xcvr->soc_data->use_phy) {
1795 regcache_cache_only(xcvr->regmap_phy, true);
1796 regcache_cache_only(xcvr->regmap_pll, true);
1797 }
1798
1799 clk_disable_unprepare(xcvr->spba_clk);
1800 clk_disable_unprepare(xcvr->phy_clk);
1801 clk_disable_unprepare(xcvr->pll_ipg_clk);
1802 clk_disable_unprepare(xcvr->ipg_clk);
1803
1804 return 0;
1805 }
1806
fsl_xcvr_runtime_resume(struct device * dev)1807 static int fsl_xcvr_runtime_resume(struct device *dev)
1808 {
1809 struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1810 int ret;
1811
1812 ret = reset_control_assert(xcvr->reset);
1813 if (ret < 0) {
1814 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1815 return ret;
1816 }
1817
1818 ret = clk_prepare_enable(xcvr->ipg_clk);
1819 if (ret) {
1820 dev_err(dev, "failed to start IPG clock.\n");
1821 return ret;
1822 }
1823
1824 ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1825 if (ret) {
1826 dev_err(dev, "failed to start PLL IPG clock.\n");
1827 goto stop_ipg_clk;
1828 }
1829
1830 ret = clk_prepare_enable(xcvr->phy_clk);
1831 if (ret) {
1832 dev_err(dev, "failed to start PHY clock: %d\n", ret);
1833 goto stop_pll_ipg_clk;
1834 }
1835
1836 ret = clk_prepare_enable(xcvr->spba_clk);
1837 if (ret) {
1838 dev_err(dev, "failed to start SPBA clock.\n");
1839 goto stop_phy_clk;
1840 }
1841
1842 ret = reset_control_deassert(xcvr->reset);
1843 if (ret) {
1844 dev_err(dev, "failed to deassert M0+ reset.\n");
1845 goto stop_spba_clk;
1846 }
1847
1848 regcache_cache_only(xcvr->regmap, false);
1849 regcache_mark_dirty(xcvr->regmap);
1850 ret = regcache_sync(xcvr->regmap);
1851
1852 if (ret) {
1853 dev_err(dev, "failed to sync regcache.\n");
1854 goto stop_spba_clk;
1855 }
1856
1857 if (xcvr->soc_data->use_phy) {
1858 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
1859 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
1860 if (ret < 0) {
1861 dev_err(dev, "Error while release PHY reset: %d\n", ret);
1862 goto stop_spba_clk;
1863 }
1864
1865 regcache_cache_only(xcvr->regmap_phy, false);
1866 regcache_mark_dirty(xcvr->regmap_phy);
1867 ret = regcache_sync(xcvr->regmap_phy);
1868 if (ret) {
1869 dev_err(dev, "failed to sync phy regcache.\n");
1870 goto stop_spba_clk;
1871 }
1872
1873 regcache_cache_only(xcvr->regmap_pll, false);
1874 regcache_mark_dirty(xcvr->regmap_pll);
1875 ret = regcache_sync(xcvr->regmap_pll);
1876 if (ret) {
1877 dev_err(dev, "failed to sync pll regcache.\n");
1878 goto stop_spba_clk;
1879 }
1880 }
1881
1882 if (xcvr->soc_data->fw_name) {
1883 ret = fsl_xcvr_load_firmware(xcvr);
1884 if (ret) {
1885 dev_err(dev, "failed to load firmware.\n");
1886 goto stop_spba_clk;
1887 }
1888
1889 /* Release M0+ reset */
1890 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1891 FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
1892 if (ret < 0) {
1893 dev_err(dev, "M0+ core release failed: %d\n", ret);
1894 goto stop_spba_clk;
1895 }
1896
1897 /* Let M0+ core complete firmware initialization */
1898 msleep(50);
1899 }
1900
1901 return 0;
1902
1903 stop_spba_clk:
1904 clk_disable_unprepare(xcvr->spba_clk);
1905 stop_phy_clk:
1906 clk_disable_unprepare(xcvr->phy_clk);
1907 stop_pll_ipg_clk:
1908 clk_disable_unprepare(xcvr->pll_ipg_clk);
1909 stop_ipg_clk:
1910 clk_disable_unprepare(xcvr->ipg_clk);
1911
1912 return ret;
1913 }
1914
1915 static const struct dev_pm_ops fsl_xcvr_pm_ops = {
1916 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL)
1917 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1918 };
1919
1920 static struct platform_driver fsl_xcvr_driver = {
1921 .probe = fsl_xcvr_probe,
1922 .driver = {
1923 .name = "fsl-xcvr",
1924 .pm = pm_ptr(&fsl_xcvr_pm_ops),
1925 .of_match_table = fsl_xcvr_dt_ids,
1926 },
1927 .remove = fsl_xcvr_remove,
1928 };
1929 module_platform_driver(fsl_xcvr_driver);
1930
1931 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
1932 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
1933 MODULE_LICENSE("GPL v2");
1934