1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
4 *
5 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
6 * Signal 11 Software
7 */
8
9 #include <linux/spi/spi.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13 #include <linux/ieee802154.h>
14 #include <linux/irq.h>
15 #include <net/cfg802154.h>
16 #include <net/mac802154.h>
17
18 /* MRF24J40 Short Address Registers */
19 #define REG_RXMCR 0x00 /* Receive MAC control */
20 #define BIT_PROMI BIT(0)
21 #define BIT_ERRPKT BIT(1)
22 #define BIT_NOACKRSP BIT(5)
23 #define BIT_PANCOORD BIT(3)
24
25 #define REG_PANIDL 0x01 /* PAN ID (low) */
26 #define REG_PANIDH 0x02 /* PAN ID (high) */
27 #define REG_SADRL 0x03 /* Short address (low) */
28 #define REG_SADRH 0x04 /* Short address (high) */
29 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
30 #define REG_EADR1 0x06
31 #define REG_EADR2 0x07
32 #define REG_EADR3 0x08
33 #define REG_EADR4 0x09
34 #define REG_EADR5 0x0A
35 #define REG_EADR6 0x0B
36 #define REG_EADR7 0x0C
37 #define REG_RXFLUSH 0x0D
38 #define REG_ORDER 0x10
39 #define REG_TXMCR 0x11 /* Transmit MAC control */
40 #define TXMCR_MIN_BE_SHIFT 3
41 #define TXMCR_MIN_BE_MASK 0x18
42 #define TXMCR_CSMA_RETRIES_SHIFT 0
43 #define TXMCR_CSMA_RETRIES_MASK 0x07
44
45 #define REG_ACKTMOUT 0x12
46 #define REG_ESLOTG1 0x13
47 #define REG_SYMTICKL 0x14
48 #define REG_SYMTICKH 0x15
49 #define REG_PACON0 0x16 /* Power Amplifier Control */
50 #define REG_PACON1 0x17 /* Power Amplifier Control */
51 #define REG_PACON2 0x18 /* Power Amplifier Control */
52 #define REG_TXBCON0 0x1A
53 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
54 #define BIT_TXNTRIG BIT(0)
55 #define BIT_TXNSECEN BIT(1)
56 #define BIT_TXNACKREQ BIT(2)
57
58 #define REG_TXG1CON 0x1C
59 #define REG_TXG2CON 0x1D
60 #define REG_ESLOTG23 0x1E
61 #define REG_ESLOTG45 0x1F
62 #define REG_ESLOTG67 0x20
63 #define REG_TXPEND 0x21
64 #define REG_WAKECON 0x22
65 #define REG_FROMOFFSET 0x23
66 #define REG_TXSTAT 0x24 /* TX MAC Status Register */
67 #define REG_TXBCON1 0x25
68 #define REG_GATECLK 0x26
69 #define REG_TXTIME 0x27
70 #define REG_HSYMTMRL 0x28
71 #define REG_HSYMTMRH 0x29
72 #define REG_SOFTRST 0x2A /* Soft Reset */
73 #define REG_SECCON0 0x2C
74 #define REG_SECCON1 0x2D
75 #define REG_TXSTBL 0x2E /* TX Stabilization */
76 #define REG_RXSR 0x30
77 #define REG_INTSTAT 0x31 /* Interrupt Status */
78 #define BIT_TXNIF BIT(0)
79 #define BIT_RXIF BIT(3)
80 #define BIT_SECIF BIT(4)
81 #define BIT_SECIGNORE BIT(7)
82
83 #define REG_INTCON 0x32 /* Interrupt Control */
84 #define BIT_TXNIE BIT(0)
85 #define BIT_RXIE BIT(3)
86 #define BIT_SECIE BIT(4)
87
88 #define REG_GPIO 0x33 /* GPIO */
89 #define REG_TRISGPIO 0x34 /* GPIO direction */
90 #define REG_SLPACK 0x35
91 #define REG_RFCTL 0x36 /* RF Control Mode Register */
92 #define BIT_RFRST BIT(2)
93
94 #define REG_SECCR2 0x37
95 #define REG_BBREG0 0x38
96 #define REG_BBREG1 0x39 /* Baseband Registers */
97 #define BIT_RXDECINV BIT(2)
98
99 #define REG_BBREG2 0x3A /* */
100 #define BBREG2_CCA_MODE_SHIFT 6
101 #define BBREG2_CCA_MODE_MASK 0xc0
102
103 #define REG_BBREG3 0x3B
104 #define REG_BBREG4 0x3C
105 #define REG_BBREG6 0x3E /* */
106 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
107
108 /* MRF24J40 Long Address Registers */
109 #define REG_RFCON0 0x200 /* RF Control Registers */
110 #define RFCON0_CH_SHIFT 4
111 #define RFCON0_CH_MASK 0xf0
112 #define RFOPT_RECOMMEND 3
113
114 #define REG_RFCON1 0x201
115 #define REG_RFCON2 0x202
116 #define REG_RFCON3 0x203
117
118 #define TXPWRL_MASK 0xc0
119 #define TXPWRL_SHIFT 6
120 #define TXPWRL_30 0x3
121 #define TXPWRL_20 0x2
122 #define TXPWRL_10 0x1
123 #define TXPWRL_0 0x0
124
125 #define TXPWRS_MASK 0x38
126 #define TXPWRS_SHIFT 3
127 #define TXPWRS_6_3 0x7
128 #define TXPWRS_4_9 0x6
129 #define TXPWRS_3_7 0x5
130 #define TXPWRS_2_8 0x4
131 #define TXPWRS_1_9 0x3
132 #define TXPWRS_1_2 0x2
133 #define TXPWRS_0_5 0x1
134 #define TXPWRS_0 0x0
135
136 #define REG_RFCON5 0x205
137 #define REG_RFCON6 0x206
138 #define REG_RFCON7 0x207
139 #define REG_RFCON8 0x208
140 #define REG_SLPCAL0 0x209
141 #define REG_SLPCAL1 0x20A
142 #define REG_SLPCAL2 0x20B
143 #define REG_RFSTATE 0x20F
144 #define REG_RSSI 0x210
145 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
146 #define BIT_INTEDGE BIT(1)
147
148 #define REG_SLPCON1 0x220
149 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
150 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
151 #define REG_REMCNTL 0x224
152 #define REG_REMCNTH 0x225
153 #define REG_MAINCNT0 0x226
154 #define REG_MAINCNT1 0x227
155 #define REG_MAINCNT2 0x228
156 #define REG_MAINCNT3 0x229
157 #define REG_TESTMODE 0x22F /* Test mode */
158 #define REG_ASSOEAR0 0x230
159 #define REG_ASSOEAR1 0x231
160 #define REG_ASSOEAR2 0x232
161 #define REG_ASSOEAR3 0x233
162 #define REG_ASSOEAR4 0x234
163 #define REG_ASSOEAR5 0x235
164 #define REG_ASSOEAR6 0x236
165 #define REG_ASSOEAR7 0x237
166 #define REG_ASSOSAR0 0x238
167 #define REG_ASSOSAR1 0x239
168 #define REG_UNONCE0 0x240
169 #define REG_UNONCE1 0x241
170 #define REG_UNONCE2 0x242
171 #define REG_UNONCE3 0x243
172 #define REG_UNONCE4 0x244
173 #define REG_UNONCE5 0x245
174 #define REG_UNONCE6 0x246
175 #define REG_UNONCE7 0x247
176 #define REG_UNONCE8 0x248
177 #define REG_UNONCE9 0x249
178 #define REG_UNONCE10 0x24A
179 #define REG_UNONCE11 0x24B
180 #define REG_UNONCE12 0x24C
181 #define REG_RX_FIFO 0x300 /* Receive FIFO */
182
183 /* Device configuration: Only channels 11-26 on page 0 are supported. */
184 #define MRF24J40_CHAN_MIN 11
185 #define MRF24J40_CHAN_MAX 26
186 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
187 - ((u32)1 << MRF24J40_CHAN_MIN))
188
189 #define TX_FIFO_SIZE 128 /* From datasheet */
190 #define RX_FIFO_SIZE 144 /* From datasheet */
191 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
192
193 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
194
195 /* Device Private Data */
196 struct mrf24j40 {
197 struct spi_device *spi;
198 struct ieee802154_hw *hw;
199
200 struct regmap *regmap_short;
201 struct regmap *regmap_long;
202
203 /* for writing txfifo */
204 struct spi_message tx_msg;
205 u8 tx_hdr_buf[2];
206 struct spi_transfer tx_hdr_trx;
207 u8 tx_len_buf[2];
208 struct spi_transfer tx_len_trx;
209 struct spi_transfer tx_buf_trx;
210 struct sk_buff *tx_skb;
211
212 /* post transmit message to send frame out */
213 struct spi_message tx_post_msg;
214 u8 tx_post_buf[2];
215 struct spi_transfer tx_post_trx;
216
217 /* for protect/unprotect/read length rxfifo */
218 struct spi_message rx_msg;
219 u8 rx_buf[3];
220 struct spi_transfer rx_trx;
221
222 /* receive handling */
223 struct spi_message rx_buf_msg;
224 u8 rx_addr_buf[2];
225 struct spi_transfer rx_addr_trx;
226 u8 rx_lqi_buf[2];
227 struct spi_transfer rx_lqi_trx;
228 u8 rx_fifo_buf[RX_FIFO_SIZE];
229 struct spi_transfer rx_fifo_buf_trx;
230
231 /* isr handling for reading intstat */
232 struct spi_message irq_msg;
233 u8 irq_buf[2];
234 struct spi_transfer irq_trx;
235 };
236
237 /* regmap information for short address register access */
238 #define MRF24J40_SHORT_WRITE 0x01
239 #define MRF24J40_SHORT_READ 0x00
240 #define MRF24J40_SHORT_NUMREGS 0x3F
241
242 /* regmap information for long address register access */
243 #define MRF24J40_LONG_ACCESS 0x80
244 #define MRF24J40_LONG_NUMREGS 0x38F
245
246 /* Read/Write SPI Commands for Short and Long Address registers. */
247 #define MRF24J40_READSHORT(reg) ((reg) << 1)
248 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
249 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
250 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
251
252 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
253 #define MAX_SPI_SPEED_HZ 10000000
254
255 #define printdev(X) (&X->spi->dev)
256
257 static bool
mrf24j40_short_reg_writeable(struct device * dev,unsigned int reg)258 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
259 {
260 switch (reg) {
261 case REG_RXMCR:
262 case REG_PANIDL:
263 case REG_PANIDH:
264 case REG_SADRL:
265 case REG_SADRH:
266 case REG_EADR0:
267 case REG_EADR1:
268 case REG_EADR2:
269 case REG_EADR3:
270 case REG_EADR4:
271 case REG_EADR5:
272 case REG_EADR6:
273 case REG_EADR7:
274 case REG_RXFLUSH:
275 case REG_ORDER:
276 case REG_TXMCR:
277 case REG_ACKTMOUT:
278 case REG_ESLOTG1:
279 case REG_SYMTICKL:
280 case REG_SYMTICKH:
281 case REG_PACON0:
282 case REG_PACON1:
283 case REG_PACON2:
284 case REG_TXBCON0:
285 case REG_TXNCON:
286 case REG_TXG1CON:
287 case REG_TXG2CON:
288 case REG_ESLOTG23:
289 case REG_ESLOTG45:
290 case REG_ESLOTG67:
291 case REG_TXPEND:
292 case REG_WAKECON:
293 case REG_FROMOFFSET:
294 case REG_TXBCON1:
295 case REG_GATECLK:
296 case REG_TXTIME:
297 case REG_HSYMTMRL:
298 case REG_HSYMTMRH:
299 case REG_SOFTRST:
300 case REG_SECCON0:
301 case REG_SECCON1:
302 case REG_TXSTBL:
303 case REG_RXSR:
304 case REG_INTCON:
305 case REG_TRISGPIO:
306 case REG_GPIO:
307 case REG_RFCTL:
308 case REG_SECCR2:
309 case REG_SLPACK:
310 case REG_BBREG0:
311 case REG_BBREG1:
312 case REG_BBREG2:
313 case REG_BBREG3:
314 case REG_BBREG4:
315 case REG_BBREG6:
316 case REG_CCAEDTH:
317 return true;
318 default:
319 return false;
320 }
321 }
322
323 static bool
mrf24j40_short_reg_readable(struct device * dev,unsigned int reg)324 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
325 {
326 bool rc;
327
328 /* all writeable are also readable */
329 rc = mrf24j40_short_reg_writeable(dev, reg);
330 if (rc)
331 return rc;
332
333 /* readonly regs */
334 switch (reg) {
335 case REG_TXSTAT:
336 case REG_INTSTAT:
337 return true;
338 default:
339 return false;
340 }
341 }
342
343 static bool
mrf24j40_short_reg_volatile(struct device * dev,unsigned int reg)344 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
345 {
346 /* can be changed during runtime */
347 switch (reg) {
348 case REG_TXSTAT:
349 case REG_INTSTAT:
350 case REG_RXFLUSH:
351 case REG_TXNCON:
352 case REG_SOFTRST:
353 case REG_RFCTL:
354 case REG_TXBCON0:
355 case REG_TXG1CON:
356 case REG_TXG2CON:
357 case REG_TXBCON1:
358 case REG_SECCON0:
359 case REG_RXSR:
360 case REG_SLPACK:
361 case REG_SECCR2:
362 case REG_BBREG6:
363 /* use them in spi_async and regmap so it's volatile */
364 case REG_BBREG1:
365 return true;
366 default:
367 return false;
368 }
369 }
370
371 static bool
mrf24j40_short_reg_precious(struct device * dev,unsigned int reg)372 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
373 {
374 /* don't clear irq line on read */
375 switch (reg) {
376 case REG_INTSTAT:
377 return true;
378 default:
379 return false;
380 }
381 }
382
383 static const struct regmap_config mrf24j40_short_regmap = {
384 .name = "mrf24j40_short",
385 .reg_bits = 7,
386 .val_bits = 8,
387 .pad_bits = 1,
388 .write_flag_mask = MRF24J40_SHORT_WRITE,
389 .read_flag_mask = MRF24J40_SHORT_READ,
390 .cache_type = REGCACHE_MAPLE,
391 .max_register = MRF24J40_SHORT_NUMREGS,
392 .writeable_reg = mrf24j40_short_reg_writeable,
393 .readable_reg = mrf24j40_short_reg_readable,
394 .volatile_reg = mrf24j40_short_reg_volatile,
395 .precious_reg = mrf24j40_short_reg_precious,
396 };
397
398 static bool
mrf24j40_long_reg_writeable(struct device * dev,unsigned int reg)399 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
400 {
401 switch (reg) {
402 case REG_RFCON0:
403 case REG_RFCON1:
404 case REG_RFCON2:
405 case REG_RFCON3:
406 case REG_RFCON5:
407 case REG_RFCON6:
408 case REG_RFCON7:
409 case REG_RFCON8:
410 case REG_SLPCAL2:
411 case REG_SLPCON0:
412 case REG_SLPCON1:
413 case REG_WAKETIMEL:
414 case REG_WAKETIMEH:
415 case REG_REMCNTL:
416 case REG_REMCNTH:
417 case REG_MAINCNT0:
418 case REG_MAINCNT1:
419 case REG_MAINCNT2:
420 case REG_MAINCNT3:
421 case REG_TESTMODE:
422 case REG_ASSOEAR0:
423 case REG_ASSOEAR1:
424 case REG_ASSOEAR2:
425 case REG_ASSOEAR3:
426 case REG_ASSOEAR4:
427 case REG_ASSOEAR5:
428 case REG_ASSOEAR6:
429 case REG_ASSOEAR7:
430 case REG_ASSOSAR0:
431 case REG_ASSOSAR1:
432 case REG_UNONCE0:
433 case REG_UNONCE1:
434 case REG_UNONCE2:
435 case REG_UNONCE3:
436 case REG_UNONCE4:
437 case REG_UNONCE5:
438 case REG_UNONCE6:
439 case REG_UNONCE7:
440 case REG_UNONCE8:
441 case REG_UNONCE9:
442 case REG_UNONCE10:
443 case REG_UNONCE11:
444 case REG_UNONCE12:
445 return true;
446 default:
447 return false;
448 }
449 }
450
451 static bool
mrf24j40_long_reg_readable(struct device * dev,unsigned int reg)452 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
453 {
454 bool rc;
455
456 /* all writeable are also readable */
457 rc = mrf24j40_long_reg_writeable(dev, reg);
458 if (rc)
459 return rc;
460
461 /* readonly regs */
462 switch (reg) {
463 case REG_SLPCAL0:
464 case REG_SLPCAL1:
465 case REG_RFSTATE:
466 case REG_RSSI:
467 return true;
468 default:
469 return false;
470 }
471 }
472
473 static bool
mrf24j40_long_reg_volatile(struct device * dev,unsigned int reg)474 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
475 {
476 /* can be changed during runtime */
477 switch (reg) {
478 case REG_SLPCAL0:
479 case REG_SLPCAL1:
480 case REG_SLPCAL2:
481 case REG_RFSTATE:
482 case REG_RSSI:
483 case REG_MAINCNT3:
484 return true;
485 default:
486 return false;
487 }
488 }
489
490 static const struct regmap_config mrf24j40_long_regmap = {
491 .name = "mrf24j40_long",
492 .reg_bits = 11,
493 .val_bits = 8,
494 .pad_bits = 5,
495 .write_flag_mask = MRF24J40_LONG_ACCESS,
496 .read_flag_mask = MRF24J40_LONG_ACCESS,
497 .cache_type = REGCACHE_MAPLE,
498 .max_register = MRF24J40_LONG_NUMREGS,
499 .writeable_reg = mrf24j40_long_reg_writeable,
500 .readable_reg = mrf24j40_long_reg_readable,
501 .volatile_reg = mrf24j40_long_reg_volatile,
502 };
503
mrf24j40_long_regmap_write(void * context,const void * data,size_t count)504 static int mrf24j40_long_regmap_write(void *context, const void *data,
505 size_t count)
506 {
507 struct spi_device *spi = context;
508 u8 buf[3];
509
510 if (count > 3)
511 return -EINVAL;
512
513 /* regmap supports read/write mask only in frist byte
514 * long write access need to set the 12th bit, so we
515 * make special handling for write.
516 */
517 memcpy(buf, data, count);
518 buf[1] |= (1 << 4);
519
520 return spi_write(spi, buf, count);
521 }
522
523 static int
mrf24j40_long_regmap_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)524 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
525 void *val, size_t val_size)
526 {
527 struct spi_device *spi = context;
528
529 return spi_write_then_read(spi, reg, reg_size, val, val_size);
530 }
531
532 static const struct regmap_bus mrf24j40_long_regmap_bus = {
533 .write = mrf24j40_long_regmap_write,
534 .read = mrf24j40_long_regmap_read,
535 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
536 .val_format_endian_default = REGMAP_ENDIAN_BIG,
537 };
538
write_tx_buf_complete(void * context)539 static void write_tx_buf_complete(void *context)
540 {
541 struct mrf24j40 *devrec = context;
542 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
543 u8 val = BIT_TXNTRIG;
544 int ret;
545
546 if (ieee802154_is_secen(fc))
547 val |= BIT_TXNSECEN;
548
549 if (ieee802154_is_ackreq(fc))
550 val |= BIT_TXNACKREQ;
551
552 devrec->tx_post_msg.complete = NULL;
553 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
554 devrec->tx_post_buf[1] = val;
555
556 ret = spi_async(devrec->spi, &devrec->tx_post_msg);
557 if (ret)
558 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
559 }
560
561 /* This function relies on an undocumented write method. Once a write command
562 and address is set, as many bytes of data as desired can be clocked into
563 the device. The datasheet only shows setting one byte at a time. */
write_tx_buf(struct mrf24j40 * devrec,u16 reg,const u8 * data,size_t length)564 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
565 const u8 *data, size_t length)
566 {
567 u16 cmd;
568 int ret;
569
570 /* Range check the length. 2 bytes are used for the length fields.*/
571 if (length > TX_FIFO_SIZE-2) {
572 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
573 length = TX_FIFO_SIZE-2;
574 }
575
576 cmd = MRF24J40_WRITELONG(reg);
577 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
578 devrec->tx_hdr_buf[1] = cmd & 0xff;
579 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
580 devrec->tx_len_buf[1] = length; /* Total length */
581 devrec->tx_buf_trx.tx_buf = data;
582 devrec->tx_buf_trx.len = length;
583
584 ret = spi_async(devrec->spi, &devrec->tx_msg);
585 if (ret)
586 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
587
588 return ret;
589 }
590
mrf24j40_tx(struct ieee802154_hw * hw,struct sk_buff * skb)591 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
592 {
593 struct mrf24j40 *devrec = hw->priv;
594
595 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
596 devrec->tx_skb = skb;
597
598 return write_tx_buf(devrec, 0x000, skb->data, skb->len);
599 }
600
mrf24j40_ed(struct ieee802154_hw * hw,u8 * level)601 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
602 {
603 /* TODO: */
604 pr_warn("mrf24j40: ed not implemented\n");
605 *level = 0;
606 return 0;
607 }
608
mrf24j40_start(struct ieee802154_hw * hw)609 static int mrf24j40_start(struct ieee802154_hw *hw)
610 {
611 struct mrf24j40 *devrec = hw->priv;
612
613 dev_dbg(printdev(devrec), "start\n");
614
615 /* Clear TXNIE and RXIE. Enable interrupts */
616 return regmap_update_bits(devrec->regmap_short, REG_INTCON,
617 BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);
618 }
619
mrf24j40_stop(struct ieee802154_hw * hw)620 static void mrf24j40_stop(struct ieee802154_hw *hw)
621 {
622 struct mrf24j40 *devrec = hw->priv;
623
624 dev_dbg(printdev(devrec), "stop\n");
625
626 /* Set TXNIE and RXIE. Disable Interrupts */
627 regmap_update_bits(devrec->regmap_short, REG_INTCON,
628 BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);
629 }
630
mrf24j40_set_channel(struct ieee802154_hw * hw,u8 page,u8 channel)631 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
632 {
633 struct mrf24j40 *devrec = hw->priv;
634 u8 val;
635 int ret;
636
637 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
638
639 WARN_ON(page != 0);
640 WARN_ON(channel < MRF24J40_CHAN_MIN);
641 WARN_ON(channel > MRF24J40_CHAN_MAX);
642
643 /* Set Channel TODO */
644 val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
645 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
646 RFCON0_CH_MASK, val);
647 if (ret)
648 return ret;
649
650 /* RF Reset */
651 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
652 BIT_RFRST);
653 if (ret)
654 return ret;
655
656 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
657 if (!ret)
658 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
659
660 return ret;
661 }
662
mrf24j40_filter(struct ieee802154_hw * hw,struct ieee802154_hw_addr_filt * filt,unsigned long changed)663 static int mrf24j40_filter(struct ieee802154_hw *hw,
664 struct ieee802154_hw_addr_filt *filt,
665 unsigned long changed)
666 {
667 struct mrf24j40 *devrec = hw->priv;
668
669 dev_dbg(printdev(devrec), "filter\n");
670
671 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
672 /* Short Addr */
673 u8 addrh, addrl;
674
675 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
676 addrl = le16_to_cpu(filt->short_addr) & 0xff;
677
678 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
679 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
680 dev_dbg(printdev(devrec),
681 "Set short addr to %04hx\n", filt->short_addr);
682 }
683
684 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
685 /* Device Address */
686 u8 i, addr[8];
687
688 memcpy(addr, &filt->ieee_addr, 8);
689 for (i = 0; i < 8; i++)
690 regmap_write(devrec->regmap_short, REG_EADR0 + i,
691 addr[i]);
692
693 #ifdef DEBUG
694 pr_debug("Set long addr to: ");
695 for (i = 0; i < 8; i++)
696 pr_debug("%02hhx ", addr[7 - i]);
697 pr_debug("\n");
698 #endif
699 }
700
701 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
702 /* PAN ID */
703 u8 panidl, panidh;
704
705 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
706 panidl = le16_to_cpu(filt->pan_id) & 0xff;
707 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
708 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
709
710 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
711 }
712
713 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
714 /* Pan Coordinator */
715 u8 val;
716 int ret;
717
718 if (filt->pan_coord)
719 val = BIT_PANCOORD;
720 else
721 val = 0;
722 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
723 BIT_PANCOORD, val);
724 if (ret)
725 return ret;
726
727 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
728 * REG_ORDER is maintained as default (no beacon/superframe).
729 */
730
731 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
732 filt->pan_coord ? "on" : "off");
733 }
734
735 return 0;
736 }
737
mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 * devrec)738 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
739 {
740 int ret;
741
742 /* Turn back on reception of packets off the air. */
743 devrec->rx_msg.complete = NULL;
744 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
745 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
746 ret = spi_async(devrec->spi, &devrec->rx_msg);
747 if (ret)
748 dev_err(printdev(devrec), "failed to unlock rx buffer\n");
749 }
750
mrf24j40_handle_rx_read_buf_complete(void * context)751 static void mrf24j40_handle_rx_read_buf_complete(void *context)
752 {
753 struct mrf24j40 *devrec = context;
754 u8 len = devrec->rx_buf[2];
755 u8 rx_local_buf[RX_FIFO_SIZE];
756 struct sk_buff *skb;
757
758 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
759 mrf24j40_handle_rx_read_buf_unlock(devrec);
760
761 skb = dev_alloc_skb(IEEE802154_MTU);
762 if (!skb) {
763 dev_err(printdev(devrec), "failed to allocate skb\n");
764 return;
765 }
766
767 skb_put_data(skb, rx_local_buf, len);
768 ieee802154_rx_irqsafe(devrec->hw, skb, 0);
769
770 #ifdef DEBUG
771 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
772 rx_local_buf, len, 0);
773 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
774 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
775 #endif
776 }
777
mrf24j40_handle_rx_read_buf(void * context)778 static void mrf24j40_handle_rx_read_buf(void *context)
779 {
780 struct mrf24j40 *devrec = context;
781 u16 cmd;
782 int ret;
783
784 /* if length is invalid read the full MTU */
785 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
786 devrec->rx_buf[2] = IEEE802154_MTU;
787
788 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
789 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
790 devrec->rx_addr_buf[1] = cmd & 0xff;
791 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
792 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
793 if (ret) {
794 dev_err(printdev(devrec), "failed to read rx buffer\n");
795 mrf24j40_handle_rx_read_buf_unlock(devrec);
796 }
797 }
798
mrf24j40_handle_rx_read_len(void * context)799 static void mrf24j40_handle_rx_read_len(void *context)
800 {
801 struct mrf24j40 *devrec = context;
802 u16 cmd;
803 int ret;
804
805 /* read the length of received frame */
806 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
807 devrec->rx_trx.len = 3;
808 cmd = MRF24J40_READLONG(REG_RX_FIFO);
809 devrec->rx_buf[0] = cmd >> 8 & 0xff;
810 devrec->rx_buf[1] = cmd & 0xff;
811
812 ret = spi_async(devrec->spi, &devrec->rx_msg);
813 if (ret) {
814 dev_err(printdev(devrec), "failed to read rx buffer length\n");
815 mrf24j40_handle_rx_read_buf_unlock(devrec);
816 }
817 }
818
mrf24j40_handle_rx(struct mrf24j40 * devrec)819 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
820 {
821 /* Turn off reception of packets off the air. This prevents the
822 * device from overwriting the buffer while we're reading it.
823 */
824 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
825 devrec->rx_trx.len = 2;
826 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
827 devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
828
829 return spi_async(devrec->spi, &devrec->rx_msg);
830 }
831
832 static int
mrf24j40_csma_params(struct ieee802154_hw * hw,u8 min_be,u8 max_be,u8 retries)833 mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
834 u8 retries)
835 {
836 struct mrf24j40 *devrec = hw->priv;
837 u8 val;
838
839 /* min_be */
840 val = min_be << TXMCR_MIN_BE_SHIFT;
841 /* csma backoffs */
842 val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
843
844 return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
845 TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
846 val);
847 }
848
mrf24j40_set_cca_mode(struct ieee802154_hw * hw,const struct wpan_phy_cca * cca)849 static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
850 const struct wpan_phy_cca *cca)
851 {
852 struct mrf24j40 *devrec = hw->priv;
853 u8 val;
854
855 /* mapping 802.15.4 to driver spec */
856 switch (cca->mode) {
857 case NL802154_CCA_ENERGY:
858 val = 2;
859 break;
860 case NL802154_CCA_CARRIER:
861 val = 1;
862 break;
863 case NL802154_CCA_ENERGY_CARRIER:
864 switch (cca->opt) {
865 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
866 val = 3;
867 break;
868 default:
869 return -EINVAL;
870 }
871 break;
872 default:
873 return -EINVAL;
874 }
875
876 return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
877 BBREG2_CCA_MODE_MASK,
878 val << BBREG2_CCA_MODE_SHIFT);
879 }
880
881 /* array for representing ed levels */
882 static const s32 mrf24j40_ed_levels[] = {
883 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
884 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
885 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
886 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
887 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
888 -4000, -3900, -3800, -3700, -3600, -3500
889 };
890
891 /* map ed levels to register value */
892 static const s32 mrf24j40_ed_levels_map[][2] = {
893 { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
894 { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
895 { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
896 { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
897 { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
898 { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
899 { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
900 { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },
901 { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },
902 { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
903 { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
904 { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
905 { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
906 { -3700, 253 }, { -3600, 254 }, { -3500, 255 },
907 };
908
mrf24j40_set_cca_ed_level(struct ieee802154_hw * hw,s32 mbm)909 static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
910 {
911 struct mrf24j40 *devrec = hw->priv;
912 int i;
913
914 for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
915 if (mrf24j40_ed_levels_map[i][0] == mbm)
916 return regmap_write(devrec->regmap_short, REG_CCAEDTH,
917 mrf24j40_ed_levels_map[i][1]);
918 }
919
920 return -EINVAL;
921 }
922
923 static const s32 mrf24j40ma_powers[] = {
924 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,
925 -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,
926 -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,
927 };
928
mrf24j40_set_txpower(struct ieee802154_hw * hw,s32 mbm)929 static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
930 {
931 struct mrf24j40 *devrec = hw->priv;
932 s32 small_scale;
933 u8 val;
934
935 if (0 >= mbm && mbm > -1000) {
936 val = TXPWRL_0 << TXPWRL_SHIFT;
937 small_scale = mbm;
938 } else if (-1000 >= mbm && mbm > -2000) {
939 val = TXPWRL_10 << TXPWRL_SHIFT;
940 small_scale = mbm + 1000;
941 } else if (-2000 >= mbm && mbm > -3000) {
942 val = TXPWRL_20 << TXPWRL_SHIFT;
943 small_scale = mbm + 2000;
944 } else if (-3000 >= mbm && mbm > -4000) {
945 val = TXPWRL_30 << TXPWRL_SHIFT;
946 small_scale = mbm + 3000;
947 } else {
948 return -EINVAL;
949 }
950
951 switch (small_scale) {
952 case 0:
953 val |= (TXPWRS_0 << TXPWRS_SHIFT);
954 break;
955 case -50:
956 val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
957 break;
958 case -120:
959 val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
960 break;
961 case -190:
962 val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
963 break;
964 case -280:
965 val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
966 break;
967 case -370:
968 val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
969 break;
970 case -490:
971 val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
972 break;
973 case -630:
974 val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
975 break;
976 default:
977 return -EINVAL;
978 }
979
980 return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
981 TXPWRL_MASK | TXPWRS_MASK, val);
982 }
983
mrf24j40_set_promiscuous_mode(struct ieee802154_hw * hw,bool on)984 static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
985 {
986 struct mrf24j40 *devrec = hw->priv;
987 int ret;
988
989 if (on) {
990 /* set PROMI, ERRPKT and NOACKRSP */
991 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
992 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
993 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
994 } else {
995 /* clear PROMI, ERRPKT and NOACKRSP */
996 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
997 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
998 0);
999 }
1000
1001 return ret;
1002 }
1003
1004 static const struct ieee802154_ops mrf24j40_ops = {
1005 .owner = THIS_MODULE,
1006 .xmit_async = mrf24j40_tx,
1007 .ed = mrf24j40_ed,
1008 .start = mrf24j40_start,
1009 .stop = mrf24j40_stop,
1010 .set_channel = mrf24j40_set_channel,
1011 .set_hw_addr_filt = mrf24j40_filter,
1012 .set_csma_params = mrf24j40_csma_params,
1013 .set_cca_mode = mrf24j40_set_cca_mode,
1014 .set_cca_ed_level = mrf24j40_set_cca_ed_level,
1015 .set_txpower = mrf24j40_set_txpower,
1016 .set_promiscuous_mode = mrf24j40_set_promiscuous_mode,
1017 };
1018
mrf24j40_intstat_complete(void * context)1019 static void mrf24j40_intstat_complete(void *context)
1020 {
1021 struct mrf24j40 *devrec = context;
1022 u8 intstat = devrec->irq_buf[1];
1023
1024 enable_irq(devrec->spi->irq);
1025
1026 /* Ignore Rx security decryption */
1027 if (intstat & BIT_SECIF)
1028 regmap_write_async(devrec->regmap_short, REG_SECCON0,
1029 BIT_SECIGNORE);
1030
1031 /* Check for TX complete */
1032 if (intstat & BIT_TXNIF)
1033 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
1034
1035 /* Check for Rx */
1036 if (intstat & BIT_RXIF)
1037 mrf24j40_handle_rx(devrec);
1038 }
1039
mrf24j40_isr(int irq,void * data)1040 static irqreturn_t mrf24j40_isr(int irq, void *data)
1041 {
1042 struct mrf24j40 *devrec = data;
1043 int ret;
1044
1045 disable_irq_nosync(irq);
1046
1047 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
1048 devrec->irq_buf[1] = 0;
1049
1050 /* Read the interrupt status */
1051 ret = spi_async(devrec->spi, &devrec->irq_msg);
1052 if (ret) {
1053 enable_irq(irq);
1054 return IRQ_NONE;
1055 }
1056
1057 return IRQ_HANDLED;
1058 }
1059
mrf24j40_hw_init(struct mrf24j40 * devrec)1060 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
1061 {
1062 u32 irq_type;
1063 int ret;
1064
1065 /* Initialize the device.
1066 From datasheet section 3.2: Initialization. */
1067 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
1068 if (ret)
1069 goto err_ret;
1070
1071 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
1072 if (ret)
1073 goto err_ret;
1074
1075 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
1076 if (ret)
1077 goto err_ret;
1078
1079 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
1080 if (ret)
1081 goto err_ret;
1082
1083 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
1084 if (ret)
1085 goto err_ret;
1086
1087 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
1088 if (ret)
1089 goto err_ret;
1090
1091 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
1092 if (ret)
1093 goto err_ret;
1094
1095 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
1096 if (ret)
1097 goto err_ret;
1098
1099 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
1100 if (ret)
1101 goto err_ret;
1102
1103 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
1104 if (ret)
1105 goto err_ret;
1106
1107 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
1108 if (ret)
1109 goto err_ret;
1110
1111 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
1112 if (ret)
1113 goto err_ret;
1114
1115 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
1116 if (ret)
1117 goto err_ret;
1118
1119 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
1120 if (ret)
1121 goto err_ret;
1122
1123 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
1124 if (ret)
1125 goto err_ret;
1126
1127 udelay(192);
1128
1129 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
1130 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
1131 if (ret)
1132 goto err_ret;
1133
1134 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
1135 /* Enable external amplifier.
1136 * From MRF24J40MC datasheet section 1.3: Operation.
1137 */
1138 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
1139 0x07);
1140
1141 /* Set GPIO3 as output. */
1142 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
1143 0x08);
1144
1145 /* Set GPIO3 HIGH to enable U5 voltage regulator */
1146 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
1147
1148 /* Reduce TX pwr to meet FCC requirements.
1149 * From MRF24J40MC datasheet section 3.1.1
1150 */
1151 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
1152 }
1153
1154 irq_type = irq_get_trigger_type(devrec->spi->irq);
1155 if (irq_type == IRQ_TYPE_EDGE_RISING ||
1156 irq_type == IRQ_TYPE_EDGE_FALLING)
1157 dev_warn(&devrec->spi->dev,
1158 "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");
1159 switch (irq_type) {
1160 case IRQ_TYPE_EDGE_RISING:
1161 case IRQ_TYPE_LEVEL_HIGH:
1162 /* set interrupt polarity to rising */
1163 ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
1164 BIT_INTEDGE, BIT_INTEDGE);
1165 if (ret)
1166 goto err_ret;
1167 break;
1168 default:
1169 /* default is falling edge */
1170 break;
1171 }
1172
1173 return 0;
1174
1175 err_ret:
1176 return ret;
1177 }
1178
1179 static void
mrf24j40_setup_tx_spi_messages(struct mrf24j40 * devrec)1180 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1181 {
1182 spi_message_init(&devrec->tx_msg);
1183 devrec->tx_msg.context = devrec;
1184 devrec->tx_msg.complete = write_tx_buf_complete;
1185 devrec->tx_hdr_trx.len = 2;
1186 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1187 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1188 devrec->tx_len_trx.len = 2;
1189 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1190 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1191 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1192
1193 spi_message_init(&devrec->tx_post_msg);
1194 devrec->tx_post_msg.context = devrec;
1195 devrec->tx_post_trx.len = 2;
1196 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1197 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1198 }
1199
1200 static void
mrf24j40_setup_rx_spi_messages(struct mrf24j40 * devrec)1201 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
1202 {
1203 spi_message_init(&devrec->rx_msg);
1204 devrec->rx_msg.context = devrec;
1205 devrec->rx_trx.len = 2;
1206 devrec->rx_trx.tx_buf = devrec->rx_buf;
1207 devrec->rx_trx.rx_buf = devrec->rx_buf;
1208 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1209
1210 spi_message_init(&devrec->rx_buf_msg);
1211 devrec->rx_buf_msg.context = devrec;
1212 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1213 devrec->rx_addr_trx.len = 2;
1214 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1215 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1216 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1217 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1218 devrec->rx_lqi_trx.len = 2;
1219 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1220 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1221 }
1222
1223 static void
mrf24j40_setup_irq_spi_messages(struct mrf24j40 * devrec)1224 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1225 {
1226 spi_message_init(&devrec->irq_msg);
1227 devrec->irq_msg.context = devrec;
1228 devrec->irq_msg.complete = mrf24j40_intstat_complete;
1229 devrec->irq_trx.len = 2;
1230 devrec->irq_trx.tx_buf = devrec->irq_buf;
1231 devrec->irq_trx.rx_buf = devrec->irq_buf;
1232 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1233 }
1234
mrf24j40_phy_setup(struct mrf24j40 * devrec)1235 static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
1236 {
1237 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1238 devrec->hw->phy->current_channel = 11;
1239
1240 /* mrf24j40 supports max_minbe 0 - 3 */
1241 devrec->hw->phy->supported.max_minbe = 3;
1242 /* datasheet doesn't say anything about max_be, but we have min_be
1243 * So we assume the max_be default.
1244 */
1245 devrec->hw->phy->supported.min_maxbe = 5;
1246 devrec->hw->phy->supported.max_maxbe = 5;
1247
1248 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
1249 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1250 BIT(NL802154_CCA_CARRIER) |
1251 BIT(NL802154_CCA_ENERGY_CARRIER);
1252 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
1253
1254 devrec->hw->phy->cca_ed_level = -6900;
1255 devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
1256 devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
1257
1258 switch (spi_get_device_id(devrec->spi)->driver_data) {
1259 case MRF24J40:
1260 case MRF24J40MA:
1261 devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
1262 devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
1263 devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
1264 break;
1265 default:
1266 break;
1267 }
1268 }
1269
mrf24j40_probe(struct spi_device * spi)1270 static int mrf24j40_probe(struct spi_device *spi)
1271 {
1272 int ret = -ENOMEM, irq_type;
1273 struct ieee802154_hw *hw;
1274 struct mrf24j40 *devrec;
1275
1276 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
1277
1278 /* Register with the 802154 subsystem */
1279
1280 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1281 if (!hw)
1282 goto err_ret;
1283
1284 devrec = hw->priv;
1285 devrec->spi = spi;
1286 spi_set_drvdata(spi, devrec);
1287 devrec->hw = hw;
1288 devrec->hw->parent = &spi->dev;
1289 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1290 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1291 IEEE802154_HW_CSMA_PARAMS |
1292 IEEE802154_HW_PROMISCUOUS;
1293
1294 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
1295 WPAN_PHY_FLAG_CCA_ED_LEVEL;
1296
1297 mrf24j40_setup_tx_spi_messages(devrec);
1298 mrf24j40_setup_rx_spi_messages(devrec);
1299 mrf24j40_setup_irq_spi_messages(devrec);
1300
1301 devrec->regmap_short = devm_regmap_init_spi(spi,
1302 &mrf24j40_short_regmap);
1303 if (IS_ERR(devrec->regmap_short)) {
1304 ret = PTR_ERR(devrec->regmap_short);
1305 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1306 ret);
1307 goto err_register_device;
1308 }
1309
1310 devrec->regmap_long = devm_regmap_init(&spi->dev,
1311 &mrf24j40_long_regmap_bus,
1312 spi, &mrf24j40_long_regmap);
1313 if (IS_ERR(devrec->regmap_long)) {
1314 ret = PTR_ERR(devrec->regmap_long);
1315 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1316 ret);
1317 goto err_register_device;
1318 }
1319
1320 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1321 dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1322 MAX_SPI_SPEED_HZ);
1323 ret = -EINVAL;
1324 goto err_register_device;
1325 }
1326
1327 ret = mrf24j40_hw_init(devrec);
1328 if (ret)
1329 goto err_register_device;
1330
1331 mrf24j40_phy_setup(devrec);
1332
1333 /* request IRQF_TRIGGER_LOW as fallback default */
1334 irq_type = irq_get_trigger_type(spi->irq);
1335 if (!irq_type)
1336 irq_type = IRQF_TRIGGER_LOW;
1337
1338 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1339 irq_type, dev_name(&spi->dev), devrec);
1340 if (ret) {
1341 dev_err(printdev(devrec), "Unable to get IRQ");
1342 goto err_register_device;
1343 }
1344
1345 dev_dbg(printdev(devrec), "registered mrf24j40\n");
1346 ret = ieee802154_register_hw(devrec->hw);
1347 if (ret)
1348 goto err_register_device;
1349
1350 return 0;
1351
1352 err_register_device:
1353 ieee802154_free_hw(devrec->hw);
1354 err_ret:
1355 return ret;
1356 }
1357
mrf24j40_remove(struct spi_device * spi)1358 static void mrf24j40_remove(struct spi_device *spi)
1359 {
1360 struct mrf24j40 *devrec = spi_get_drvdata(spi);
1361
1362 dev_dbg(printdev(devrec), "remove\n");
1363
1364 ieee802154_unregister_hw(devrec->hw);
1365 ieee802154_free_hw(devrec->hw);
1366 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1367 * complete? */
1368 }
1369
1370 static const struct of_device_id mrf24j40_of_match[] = {
1371 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1372 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1373 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1374 { },
1375 };
1376 MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1377
1378 static const struct spi_device_id mrf24j40_ids[] = {
1379 { "mrf24j40", MRF24J40 },
1380 { "mrf24j40ma", MRF24J40MA },
1381 { "mrf24j40mc", MRF24J40MC },
1382 { },
1383 };
1384 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1385
1386 static struct spi_driver mrf24j40_driver = {
1387 .driver = {
1388 .of_match_table = mrf24j40_of_match,
1389 .name = "mrf24j40",
1390 },
1391 .id_table = mrf24j40_ids,
1392 .probe = mrf24j40_probe,
1393 .remove = mrf24j40_remove,
1394 };
1395
1396 module_spi_driver(mrf24j40_driver);
1397
1398 MODULE_LICENSE("GPL");
1399 MODULE_AUTHOR("Alan Ott");
1400 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
1401