1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2019 Protonic Holland 4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix 5 */ 6 7/dts-v1/; 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10#include "imx6dl.dtsi" 11 12/ { 13 model = "Van der Laan LANMCU"; 14 compatible = "vdl,lanmcu", "fsl,imx6dl"; 15 16 chosen { 17 stdout-path = &uart4; 18 }; 19 20 clock_ksz8081: clock-ksz8081 { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <50000000>; 24 clock-output-names = "enet_ref_pad"; 25 }; 26 27 backlight: backlight { 28 compatible = "pwm-backlight"; 29 pwms = <&pwm1 0 5000000 0>; 30 brightness-levels = <0 1000>; 31 num-interpolated-steps = <20>; 32 default-brightness-level = <19>; 33 }; 34 35 display { 36 compatible = "fsl,imx-parallel-display"; 37 pinctrl-0 = <&pinctrl_ipu1_disp>; 38 pinctrl-names = "default"; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 port@0 { 43 reg = <0>; 44 45 display_in: endpoint { 46 remote-endpoint = <&ipu1_di0_disp0>; 47 }; 48 }; 49 50 port@1 { 51 reg = <1>; 52 53 display_out: endpoint { 54 remote-endpoint = <&panel_in>; 55 }; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_leds>; 63 64 led-0 { 65 label = "debug0"; 66 function = LED_FUNCTION_STATUS; 67 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 68 linux,default-trigger = "heartbeat"; 69 }; 70 }; 71 72 panel { 73 compatible = "edt,etm0700g0bdh6"; 74 backlight = <&backlight>; 75 power-supply = <®_panel>; 76 77 port { 78 panel_in: endpoint { 79 remote-endpoint = <&display_out>; 80 }; 81 }; 82 }; 83 84 reg_otg_vbus: regulator-otg-vbus { 85 compatible = "regulator-fixed"; 86 regulator-name = "otg-vbus"; 87 regulator-min-microvolt = <5000000>; 88 regulator-max-microvolt = <5000000>; 89 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 }; 92 93 reg_panel: regulator-panel { 94 compatible = "regulator-fixed"; 95 regulator-name = "panel"; 96 regulator-min-microvolt = <3300000>; 97 regulator-max-microvolt = <3300000>; 98 }; 99 100 usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { 101 compatible = "mmc-pwrseq-simple"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_wifi_npd>; 104 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; 105 }; 106 107}; 108 109&can1 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_can1>; 112 status = "okay"; 113}; 114 115&can2 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_can2>; 118 status = "okay"; 119}; 120 121&clks { 122 clocks = <&clock_ksz8081>; 123 clock-names = "enet_ref_pad"; 124 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; 125 assigned-clock-parents = <&clock_ksz8081>; 126}; 127 128&fec { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_enet>; 131 phy-mode = "rmii"; 132 phy-handle = <&rgmii_phy>; 133 status = "okay"; 134 135 mdio { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 /* Microchip KSZ8081RNA PHY */ 140 rgmii_phy: ethernet-phy@0 { 141 reg = <0>; 142 interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; 143 reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; 144 reset-assert-us = <10000>; 145 reset-deassert-us = <300>; 146 }; 147 }; 148}; 149 150&gpio1 { 151 gpio-line-names = 152 "", "SD1_CD", "", "", "", "", "", "", 153 "DEBUG_0", "BL_PWM", "", "", "", "", "", "", 154 "", "", "", "", "", "", "", "ENET_LED_GREEN", 155 "", "", "", "", "", "", "", ""; 156}; 157 158&gpio3 { 159 gpio-line-names = 160 "", "", "", "", "", "", "", "", 161 "", "", "", "", "", "", "", "", 162 "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", 163 "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; 164}; 165 166&gpio5 { 167 gpio-line-names = 168 "", "", "", "", "", "", "", "", 169 "", "", "", "", "", "", "", "", 170 "", "", "", "", "", "", "ENET_RST", "ENET_INT", 171 "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; 172}; 173 174&gpio6 { 175 gpio-line-names = 176 "", "", "", "", "", "", "", "", 177 "", "", "WLAN_REG_ON", "", "", "", "", "", 178 "", "", "", "", "", "", "", "", 179 "", "", "", "", "", "", "", ""; 180}; 181 182&gpio7 { 183 gpio-line-names = 184 "", "", "", "", "", "", "", "", 185 "EMMC_RST", "", "", "", "", "", "", "", 186 "", "", "", "", "", "", "", "", 187 "", "", "", "", "", "", "", ""; 188}; 189 190&i2c1 { 191 clock-frequency = <100000>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_i2c1>; 194 status = "okay"; 195 196 /* additional i2c devices are added automatically by the boot loader */ 197}; 198 199&i2c3 { 200 clock-frequency = <100000>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_i2c3>; 203 status = "okay"; 204 205 touchscreen@38 { 206 compatible = "edt,edt-ft5406"; 207 reg = <0x38>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_ts_edt>; 210 interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; 211 212 touchscreen-size-x = <1792>; 213 touchscreen-size-y = <1024>; 214 215 touchscreen-fuzz-x = <0>; 216 touchscreen-fuzz-y = <0>; 217 218 /* Touch screen calibration */ 219 threshold = <50>; 220 gain = <5>; 221 offset = <10>; 222 }; 223 224 rtc@51 { 225 compatible = "nxp,pcf8563"; 226 reg = <0x51>; 227 }; 228}; 229 230&ipu1_di0_disp0 { 231 remote-endpoint = <&display_in>; 232}; 233 234&pwm1 { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_pwm1>; 237 status = "okay"; 238}; 239 240&uart2 { 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_uart2>; 243 linux,rs485-enabled-at-boot-time; 244 uart-has-rtscts; 245 status = "okay"; 246}; 247 248&uart3 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_uart3>; 251 linux,rs485-enabled-at-boot-time; 252 uart-has-rtscts; 253 status = "okay"; 254}; 255 256&uart4 { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart4>; 259 status = "okay"; 260}; 261 262&usbotg { 263 vbus-supply = <®_otg_vbus>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_usbotg>; 266 phy_type = "utmi"; 267 dr_mode = "host"; 268 over-current-active-low; 269 status = "okay"; 270}; 271 272&usbphynop1 { 273 status = "disabled"; 274}; 275 276&usbphynop2 { 277 status = "disabled"; 278}; 279 280&usdhc1 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_usdhc1>; 283 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 284 no-1-8-v; 285 disable-wp; 286 cap-sd-highspeed; 287 no-mmc; 288 no-sdio; 289 status = "okay"; 290}; 291 292&usdhc2 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_usdhc2>; 295 no-1-8-v; 296 non-removable; 297 mmc-pwrseq = <&usdhc2_wifi_pwrseq>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "okay"; 301 302 wifi@1 { 303 reg = <1>; 304 compatible = "brcm,bcm4329-fmac"; 305 }; 306}; 307 308&usdhc3 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_usdhc3>; 311 bus-width = <8>; 312 no-1-8-v; 313 non-removable; 314 no-sd; 315 no-sdio; 316 status = "okay"; 317}; 318 319&iomuxc { 320 pinctrl_can1: can1grp { 321 fsl,pins = < 322 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 323 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 324 >; 325 }; 326 327 pinctrl_can2: can2grp { 328 fsl,pins = < 329 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 330 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 331 >; 332 }; 333 334 pinctrl_enet: enetgrp { 335 fsl,pins = < 336 /* MX6QDL_ENET_PINGRP4 */ 337 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 338 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 339 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 340 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 341 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 342 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 343 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 344 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 345 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 346 347 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 348 /* Phy reset */ 349 MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 350 /* nINTRP */ 351 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 352 >; 353 }; 354 355 pinctrl_i2c1: i2c1grp { 356 fsl,pins = < 357 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 358 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 359 >; 360 }; 361 362 pinctrl_i2c3: i2c3grp { 363 fsl,pins = < 364 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 365 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 366 >; 367 }; 368 369 pinctrl_ipu1_disp: ipudisp1grp { 370 fsl,pins = < 371 /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ 372 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 373 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 374 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 375 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 376 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 377 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 378 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 379 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 380 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 381 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 382 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 383 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 384 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 385 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 386 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 387 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 388 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 389 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 390 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 391 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 392 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 393 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 394 >; 395 }; 396 397 pinctrl_leds: ledsgrp { 398 fsl,pins = < 399 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 400 >; 401 }; 402 403 pinctrl_pwm1: pwm1grp { 404 fsl,pins = < 405 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 406 >; 407 }; 408 409 pinctrl_ts_edt: ts1grp { 410 fsl,pins = < 411 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 412 >; 413 }; 414 415 pinctrl_uart2: uart2grp { 416 fsl,pins = < 417 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 418 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 419 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 420 >; 421 }; 422 423 pinctrl_uart3: uart3grp { 424 fsl,pins = < 425 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 426 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 427 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 428 >; 429 }; 430 431 pinctrl_uart4: uart4grp { 432 fsl,pins = < 433 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 434 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 435 >; 436 }; 437 438 pinctrl_usbotg: usbotggrp { 439 fsl,pins = < 440 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 441 /* power enable, high active */ 442 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 443 >; 444 }; 445 446 pinctrl_usdhc1: usdhc1grp { 447 fsl,pins = < 448 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 449 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 450 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 451 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 452 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 453 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 454 MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 455 >; 456 }; 457 458 pinctrl_usdhc2: usdhc2grp { 459 fsl,pins = < 460 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 461 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 462 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 463 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 464 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 465 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 466 >; 467 }; 468 469 pinctrl_usdhc3: usdhc3grp { 470 fsl,pins = < 471 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 472 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 473 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 474 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 475 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 476 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 477 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 478 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 479 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 480 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 481 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 482 >; 483 }; 484 485 pinctrl_wifi_npd: wifigrp { 486 fsl,pins = < 487 /* WL_REG_ON */ 488 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 489 >; 490 }; 491}; 492