1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel MAX 10 BMC HWMON Driver
4 *
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
6 *
7 */
8 #include <linux/device.h>
9 #include <linux/hwmon.h>
10 #include <linux/mfd/intel-m10-bmc.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13
14 struct m10bmc_sdata {
15 unsigned int reg_input;
16 unsigned int reg_max;
17 unsigned int reg_crit;
18 unsigned int reg_hyst;
19 unsigned int reg_min;
20 unsigned int multiplier;
21 const char *label;
22 };
23
24 struct m10bmc_hwmon_board_data {
25 const struct m10bmc_sdata *tables[hwmon_max];
26 const struct hwmon_channel_info * const *hinfo;
27 };
28
29 struct m10bmc_hwmon {
30 struct device *dev;
31 struct hwmon_chip_info chip;
32 char *hw_name;
33 struct intel_m10bmc *m10bmc;
34 const struct m10bmc_hwmon_board_data *bdata;
35 };
36
37 static const struct m10bmc_sdata n3000bmc_temp_tbl[] = {
38 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Temperature" },
39 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" },
40 { 0x11c, 0x124, 0x120, 0x0, 0x0, 500, "QSFP0 Temperature" },
41 { 0x12c, 0x134, 0x130, 0x0, 0x0, 500, "QSFP1 Temperature" },
42 { 0x168, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A Temperature" },
43 { 0x16c, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A SerDes Temperature" },
44 { 0x170, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B Temperature" },
45 { 0x174, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B SerDes Temperature" },
46 };
47
48 static const struct m10bmc_sdata n3000bmc_in_tbl[] = {
49 { 0x128, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
50 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
51 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
52 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Voltage" },
53 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1, "1.2V Voltage" },
54 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Voltage" },
55 { 0x158, 0x0, 0x0, 0x0, 0x0, 1, "1.8V Voltage" },
56 { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "3.3V Voltage" },
57 };
58
59 static const struct m10bmc_sdata n3000bmc_curr_tbl[] = {
60 { 0x140, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
61 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Current" },
62 { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Current" },
63 };
64
65 static const struct m10bmc_sdata n3000bmc_power_tbl[] = {
66 { 0x160, 0x0, 0x0, 0x0, 0x0, 1000, "Board Power" },
67 };
68
69 static const struct hwmon_channel_info * const n3000bmc_hinfo[] = {
70 HWMON_CHANNEL_INFO(temp,
71 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
72 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
73 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
74 HWMON_T_LABEL,
75 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
76 HWMON_T_LABEL,
77 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
78 HWMON_T_LABEL,
79 HWMON_T_INPUT | HWMON_T_LABEL,
80 HWMON_T_INPUT | HWMON_T_LABEL,
81 HWMON_T_INPUT | HWMON_T_LABEL,
82 HWMON_T_INPUT | HWMON_T_LABEL),
83 HWMON_CHANNEL_INFO(in,
84 HWMON_I_INPUT | HWMON_I_LABEL,
85 HWMON_I_INPUT | HWMON_I_LABEL,
86 HWMON_I_INPUT | HWMON_I_LABEL,
87 HWMON_I_INPUT | HWMON_I_LABEL,
88 HWMON_I_INPUT | HWMON_I_LABEL,
89 HWMON_I_INPUT | HWMON_I_LABEL,
90 HWMON_I_INPUT | HWMON_I_LABEL,
91 HWMON_I_INPUT | HWMON_I_LABEL),
92 HWMON_CHANNEL_INFO(curr,
93 HWMON_C_INPUT | HWMON_C_LABEL,
94 HWMON_C_INPUT | HWMON_C_LABEL,
95 HWMON_C_INPUT | HWMON_C_LABEL),
96 HWMON_CHANNEL_INFO(power,
97 HWMON_P_INPUT | HWMON_P_LABEL),
98 NULL
99 };
100
101 static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {
102 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Inlet Air Temperature" },
103 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },
104 { 0x11c, 0x120, 0x124, 0x128, 0x0, 500, "Board Exhaust Air Temperature" },
105 { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },
106 { 0x138, 0x13c, 0x140, 0x144, 0x0, 500, "RDIMM0 Temperature" },
107 { 0x148, 0x14c, 0x150, 0x154, 0x0, 500, "RDIMM1 Temperature" },
108 { 0x158, 0x15c, 0x160, 0x164, 0x0, 500, "RDIMM2 Temperature" },
109 { 0x168, 0x16c, 0x170, 0x174, 0x0, 500, "RDIMM3 Temperature" },
110 { 0x178, 0x17c, 0x180, 0x0, 0x0, 500, "QSFP0 Temperature" },
111 { 0x188, 0x18c, 0x190, 0x0, 0x0, 500, "QSFP1 Temperature" },
112 { 0x1a0, 0x1a4, 0x1a8, 0x0, 0x0, 500, "3.3v Temperature" },
113 { 0x1bc, 0x1c0, 0x1c4, 0x0, 0x0, 500, "VCCERAM Temperature" },
114 { 0x1d8, 0x1dc, 0x1e0, 0x0, 0x0, 500, "VCCR Temperature" },
115 { 0x1f4, 0x1f8, 0x1fc, 0x0, 0x0, 500, "VCCT Temperature" },
116 { 0x210, 0x214, 0x218, 0x0, 0x0, 500, "1.8v Temperature" },
117 { 0x22c, 0x230, 0x234, 0x0, 0x0, 500, "12v Backplane Temperature" },
118 { 0x248, 0x24c, 0x250, 0x0, 0x0, 500, "12v AUX Temperature" },
119 };
120
121 static const struct m10bmc_sdata d5005bmc_in_tbl[] = {
122 { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },
123 { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },
124 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },
125 { 0x1ac, 0x1b0, 0x1b4, 0x0, 0x0, 1, "3.3v Voltage" },
126 { 0x1c8, 0x1cc, 0x1d0, 0x0, 0x0, 1, "VCCERAM Voltage" },
127 { 0x1e4, 0x1e8, 0x1ec, 0x0, 0x0, 1, "VCCR Voltage" },
128 { 0x200, 0x204, 0x208, 0x0, 0x0, 1, "VCCT Voltage" },
129 { 0x21c, 0x220, 0x224, 0x0, 0x0, 1, "1.8v Voltage" },
130 { 0x238, 0x0, 0x0, 0x0, 0x23c, 1, "12v Backplane Voltage" },
131 { 0x254, 0x0, 0x0, 0x0, 0x258, 1, "12v AUX Voltage" },
132 };
133
134 static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {
135 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },
136 { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1, "3.3v Current" },
137 { 0x1d4, 0x0, 0x0, 0x0, 0x0, 1, "VCCERAM Current" },
138 { 0x1f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCR Current" },
139 { 0x20c, 0x0, 0x0, 0x0, 0x0, 1, "VCCT Current" },
140 { 0x228, 0x0, 0x0, 0x0, 0x0, 1, "1.8v Current" },
141 { 0x240, 0x244, 0x0, 0x0, 0x0, 1, "12v Backplane Current" },
142 { 0x25c, 0x260, 0x0, 0x0, 0x0, 1, "12v AUX Current" },
143 };
144
145 static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {
146 .tables = {
147 [hwmon_temp] = n3000bmc_temp_tbl,
148 [hwmon_in] = n3000bmc_in_tbl,
149 [hwmon_curr] = n3000bmc_curr_tbl,
150 [hwmon_power] = n3000bmc_power_tbl,
151 },
152
153 .hinfo = n3000bmc_hinfo,
154 };
155
156 static const struct hwmon_channel_info * const d5005bmc_hinfo[] = {
157 HWMON_CHANNEL_INFO(temp,
158 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
159 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
160 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
161 HWMON_T_LABEL,
162 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
163 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
164 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
165 HWMON_T_LABEL,
166 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
167 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
168 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
169 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
170 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
171 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
172 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
173 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
174 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
175 HWMON_T_LABEL,
176 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
177 HWMON_T_LABEL,
178 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
179 HWMON_T_LABEL,
180 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
181 HWMON_T_LABEL,
182 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
183 HWMON_T_LABEL,
184 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
185 HWMON_T_LABEL,
186 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
187 HWMON_T_LABEL,
188 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
189 HWMON_T_LABEL,
190 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
191 HWMON_T_LABEL),
192 HWMON_CHANNEL_INFO(in,
193 HWMON_I_INPUT | HWMON_I_LABEL,
194 HWMON_I_INPUT | HWMON_I_LABEL,
195 HWMON_I_INPUT | HWMON_I_LABEL,
196 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
197 HWMON_I_LABEL,
198 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
199 HWMON_I_LABEL,
200 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
201 HWMON_I_LABEL,
202 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
203 HWMON_I_LABEL,
204 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |
205 HWMON_I_LABEL,
206 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL,
207 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL),
208 HWMON_CHANNEL_INFO(curr,
209 HWMON_C_INPUT | HWMON_C_LABEL,
210 HWMON_C_INPUT | HWMON_C_LABEL,
211 HWMON_C_INPUT | HWMON_C_LABEL,
212 HWMON_C_INPUT | HWMON_C_LABEL,
213 HWMON_C_INPUT | HWMON_C_LABEL,
214 HWMON_C_INPUT | HWMON_C_LABEL,
215 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL,
216 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL),
217 NULL
218 };
219
220 static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
221 .tables = {
222 [hwmon_temp] = d5005bmc_temp_tbl,
223 [hwmon_in] = d5005bmc_in_tbl,
224 [hwmon_curr] = d5005bmc_curr_tbl,
225 },
226
227 .hinfo = d5005bmc_hinfo,
228 };
229
230 static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
231 { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
232 { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
233 { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
234 { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
235 { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
236 { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
237 { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
238 { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
239 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
240 { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
241 { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
242 { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
243 { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
244 { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
245 { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
246 { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
247 { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
248 };
249
250 static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
251 { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
252 { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
253 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
254 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
255 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
256 { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
257 { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
258 { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
259 { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
260 { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
261 { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
262 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
263 { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
264 };
265
266 static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
267 { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
268 { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
269 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
270 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
271 { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
272 { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
273 { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
274 { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
275 { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
276 { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
277 { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
278 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
279 { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
280 };
281
282 static const struct hwmon_channel_info * const n5010bmc_hinfo[] = {
283 HWMON_CHANNEL_INFO(temp,
284 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
285 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
286 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
287 HWMON_T_INPUT | HWMON_T_LABEL,
288 HWMON_T_INPUT | HWMON_T_LABEL,
289 HWMON_T_INPUT | HWMON_T_LABEL,
290 HWMON_T_INPUT | HWMON_T_LABEL,
291 HWMON_T_INPUT | HWMON_T_LABEL,
292 HWMON_T_INPUT | HWMON_T_LABEL,
293 HWMON_T_INPUT | HWMON_T_LABEL,
294 HWMON_T_INPUT | HWMON_T_LABEL,
295 HWMON_T_INPUT | HWMON_T_LABEL,
296 HWMON_T_INPUT | HWMON_T_LABEL,
297 HWMON_T_INPUT | HWMON_T_LABEL,
298 HWMON_T_INPUT | HWMON_T_LABEL,
299 HWMON_T_INPUT | HWMON_T_LABEL,
300 HWMON_T_INPUT | HWMON_T_LABEL),
301 HWMON_CHANNEL_INFO(in,
302 HWMON_I_INPUT | HWMON_I_LABEL,
303 HWMON_I_INPUT | HWMON_I_LABEL,
304 HWMON_I_INPUT | HWMON_I_LABEL,
305 HWMON_I_INPUT | HWMON_I_LABEL,
306 HWMON_I_INPUT | HWMON_I_LABEL,
307 HWMON_I_INPUT | HWMON_I_LABEL,
308 HWMON_I_INPUT | HWMON_I_LABEL,
309 HWMON_I_INPUT | HWMON_I_LABEL,
310 HWMON_I_INPUT | HWMON_I_LABEL,
311 HWMON_I_INPUT | HWMON_I_LABEL,
312 HWMON_I_INPUT | HWMON_I_LABEL,
313 HWMON_I_INPUT | HWMON_I_LABEL,
314 HWMON_I_INPUT | HWMON_I_LABEL),
315 HWMON_CHANNEL_INFO(curr,
316 HWMON_C_INPUT | HWMON_C_LABEL,
317 HWMON_C_INPUT | HWMON_C_LABEL,
318 HWMON_C_INPUT | HWMON_C_LABEL,
319 HWMON_C_INPUT | HWMON_C_LABEL,
320 HWMON_C_INPUT | HWMON_C_LABEL,
321 HWMON_C_INPUT | HWMON_C_LABEL,
322 HWMON_C_INPUT | HWMON_C_LABEL,
323 HWMON_C_INPUT | HWMON_C_LABEL,
324 HWMON_C_INPUT | HWMON_C_LABEL,
325 HWMON_C_INPUT | HWMON_C_LABEL,
326 HWMON_C_INPUT | HWMON_C_LABEL,
327 HWMON_C_INPUT | HWMON_C_LABEL,
328 HWMON_C_INPUT | HWMON_C_LABEL),
329 NULL
330 };
331
332 static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
333 .tables = {
334 [hwmon_temp] = n5010bmc_temp_tbl,
335 [hwmon_in] = n5010bmc_in_tbl,
336 [hwmon_curr] = n5010bmc_curr_tbl,
337 },
338
339 .hinfo = n5010bmc_hinfo,
340 };
341
342 static const struct m10bmc_sdata n6000bmc_temp_tbl[] = {
343 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, "FPGA E-TILE Temperature #1" },
344 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, "FPGA E-TILE Temperature #2" },
345 { 0x45c, 0x460, 0x464, 0x0, 0x0, 500, "FPGA E-TILE Temperature #3" },
346 { 0x468, 0x46c, 0x470, 0x0, 0x0, 500, "FPGA E-TILE Temperature #4" },
347 { 0x474, 0x478, 0x47c, 0x0, 0x0, 500, "FPGA P-TILE Temperature" },
348 { 0x484, 0x488, 0x48c, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #1" },
349 { 0x490, 0x494, 0x498, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #2" },
350 { 0x49c, 0x4a0, 0x4a4, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #3" },
351 { 0x4a8, 0x4ac, 0x4b0, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #4" },
352 { 0x4b4, 0x4b8, 0x4bc, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #5" },
353 { 0x4c0, 0x4c4, 0x4c8, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #1" },
354 { 0x4cc, 0x4d0, 0x4d4, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #2" },
355 { 0x4d8, 0x4dc, 0x4e0, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #3" },
356 { 0x4e4, 0x4e8, 0x4ec, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #4" },
357 { 0x4f0, 0x4f4, 0x4f8, 0x52c, 0x0, 500, "Board Top Near FPGA Temperature" },
358 { 0x4fc, 0x500, 0x504, 0x52c, 0x0, 500, "Board Bottom Near CVL Temperature" },
359 { 0x508, 0x50c, 0x510, 0x52c, 0x0, 500, "Board Top East Near VRs Temperature" },
360 { 0x514, 0x518, 0x51c, 0x52c, 0x0, 500, "CVL Die Temperature" },
361 { 0x520, 0x524, 0x528, 0x52c, 0x0, 500, "Board Rear Side Temperature" },
362 { 0x530, 0x534, 0x538, 0x52c, 0x0, 500, "Board Front Side Temperature" },
363 { 0x53c, 0x540, 0x544, 0x0, 0x0, 500, "QSFP1 Case Temperature" },
364 { 0x548, 0x54c, 0x550, 0x0, 0x0, 500, "QSFP2 Case Temperature" },
365 { 0x554, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 0 VR Temperature" },
366 { 0x560, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 1 VR Temperature" },
367 { 0x56c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 2 VR Temperature" },
368 { 0x578, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage VR Controller Temperature" },
369 { 0x584, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH VR Temperature" },
370 { 0x590, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCC_1V2 VR Temperature" },
371 { 0x59c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH, VCC_1V2 VR Controller Temperature" },
372 { 0x5a8, 0x0, 0x0, 0x0, 0x0, 500, "3V3 VR Temperature" },
373 { 0x5b4, 0x0, 0x0, 0x0, 0x0, 500, "CVL Core Voltage VR Temperature" },
374 { 0x5c4, 0x5c8, 0x5cc, 0x5c0, 0x0, 500, "FPGA P-Tile Temperature [Remote]" },
375 { 0x5d0, 0x5d4, 0x5d8, 0x5c0, 0x0, 500, "FPGA E-Tile Temperature [Remote]" },
376 { 0x5dc, 0x5e0, 0x5e4, 0x5c0, 0x0, 500, "FPGA SDM Temperature [Remote]" },
377 { 0x5e8, 0x5ec, 0x5f0, 0x5c0, 0x0, 500, "FPGA Corner Temperature [Remote]" },
378 };
379
380 static const struct m10bmc_sdata n6000bmc_in_tbl[] = {
381 { 0x5f4, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 12V PCIe Rail Voltage" },
382 { 0x60c, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 12V Aux Rail Voltage" },
383 { 0x624, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 3V3 PCIe Rail Voltage" },
384 { 0x63c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Voltage" },
385 { 0x644, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Voltage" },
386 { 0x64c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Voltage" },
387 { 0x654, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" },
388 { 0x664, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Voltage" },
389 { 0x674, 0x0, 0x0, 0x0, 0x0, 1, "CVL Non Core Rails Inlet Voltage" },
390 { 0x684, 0x0, 0x0, 0x0, 0x0, 1, "MAX10 & Board CLK PWR 3V3 Inlet Voltage" },
391 { 0x694, 0x0, 0x0, 0x0, 0x0, 1, "CVL Core Voltage Rail Voltage" },
392 { 0x6ac, 0x0, 0x0, 0x0, 0x0, 1, "Board 3V3 VR Voltage" },
393 { 0x6b4, 0x0, 0x0, 0x0, 0x0, 1, "QSFP 3V3 Rail Voltage" },
394 { 0x6c4, 0x0, 0x0, 0x0, 0x0, 1, "QSFP (Primary) Supply Rail Voltage" },
395 { 0x6c8, 0x0, 0x0, 0x0, 0x0, 1, "QSFP (Secondary) Supply Rail Voltage" },
396 { 0x6cc, 0x0, 0x0, 0x0, 0x0, 1, "VCCCLK_GXER_2V5 Voltage" },
397 { 0x6d0, 0x0, 0x0, 0x0, 0x0, 1, "AVDDH_1V1_CVL Voltage" },
398 { 0x6d4, 0x0, 0x0, 0x0, 0x0, 1, "VDDH_1V8_CVL Voltage" },
399 { 0x6d8, 0x0, 0x0, 0x0, 0x0, 1, "VCCA_PLL Voltage" },
400 { 0x6e0, 0x0, 0x0, 0x0, 0x0, 1, "VCCRT_GXER_0V9 Voltage" },
401 { 0x6e8, 0x0, 0x0, 0x0, 0x0, 1, "VCCRT_GXPL_0V9 Voltage" },
402 { 0x6f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCH_GXPL_1V8 Voltage" },
403 { 0x6f4, 0x0, 0x0, 0x0, 0x0, 1, "VCCPT_1V8 Voltage" },
404 { 0x6fc, 0x0, 0x0, 0x0, 0x0, 1, "VCC_3V3_M10 Voltage" },
405 { 0x700, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V8_M10 Voltage" },
406 { 0x704, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V2_EMIF1_2_3 Voltage" },
407 { 0x70c, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V2_EMIF4_5 Voltage" },
408 { 0x714, 0x0, 0x0, 0x0, 0x0, 1, "VCCA_1V8 Voltage" },
409 { 0x718, 0x0, 0x0, 0x0, 0x0, 1, "VCCH_GXER_1V1 Voltage" },
410 { 0x71c, 0x0, 0x0, 0x0, 0x0, 1, "AVDD_ETH_0V9_CVL Voltage" },
411 { 0x720, 0x0, 0x0, 0x0, 0x0, 1, "AVDD_PCIE_0V9_CVL Voltage" },
412 };
413
414 static const struct m10bmc_sdata n6000bmc_curr_tbl[] = {
415 { 0x600, 0x604, 0x608, 0x0, 0x0, 1, "Inlet 12V PCIe Rail Current" },
416 { 0x618, 0x61c, 0x620, 0x0, 0x0, 1, "Inlet 12V Aux Rail Current" },
417 { 0x630, 0x634, 0x638, 0x0, 0x0, 1, "Inlet 3V3 PCIe Rail Current" },
418 { 0x640, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Current" },
419 { 0x648, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Current" },
420 { 0x650, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Current" },
421 { 0x658, 0x65c, 0x660, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Current" },
422 { 0x668, 0x66c, 0x670, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Current" },
423 { 0x678, 0x67c, 0x680, 0x0, 0x0, 1, "CVL Non Core Rails Inlet Current" },
424 { 0x688, 0x68c, 0x690, 0x0, 0x0, 1, "MAX10 & Board CLK PWR 3V3 Inlet Current" },
425 { 0x698, 0x0, 0x0, 0x0, 0x0, 1, "CVL Core Voltage Rail Current" },
426 { 0x6b0, 0x0, 0x0, 0x0, 0x0, 1, "Board 3V3 VR Current" },
427 { 0x6b8, 0x6bc, 0x6c0, 0x0, 0x0, 1, "QSFP 3V3 Rail Current" },
428 };
429
430 static const struct m10bmc_sdata n6000bmc_power_tbl[] = {
431 { 0x724, 0x0, 0x0, 0x0, 0x0, 1000, "Board Power" },
432 };
433
434 static const struct hwmon_channel_info * const n6000bmc_hinfo[] = {
435 HWMON_CHANNEL_INFO(temp,
436 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
437 HWMON_T_LABEL,
438 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
439 HWMON_T_LABEL,
440 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
441 HWMON_T_LABEL,
442 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
443 HWMON_T_LABEL,
444 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
445 HWMON_T_LABEL,
446 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
447 HWMON_T_LABEL,
448 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
449 HWMON_T_LABEL,
450 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
451 HWMON_T_LABEL,
452 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
453 HWMON_T_LABEL,
454 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
455 HWMON_T_LABEL,
456 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
457 HWMON_T_LABEL,
458 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
459 HWMON_T_LABEL,
460 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
461 HWMON_T_LABEL,
462 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
463 HWMON_T_LABEL,
464 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
465 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
466 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
467 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
468 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
469 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
470 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
471 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
472 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
473 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
474 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
475 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
476 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
477 HWMON_T_LABEL,
478 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
479 HWMON_T_LABEL,
480 HWMON_T_INPUT | HWMON_T_LABEL,
481 HWMON_T_INPUT | HWMON_T_LABEL,
482 HWMON_T_INPUT | HWMON_T_LABEL,
483 HWMON_T_INPUT | HWMON_T_LABEL,
484 HWMON_T_INPUT | HWMON_T_LABEL,
485 HWMON_T_INPUT | HWMON_T_LABEL,
486 HWMON_T_INPUT | HWMON_T_LABEL,
487 HWMON_T_INPUT | HWMON_T_LABEL,
488 HWMON_T_INPUT | HWMON_T_LABEL,
489 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
490 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
491 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
492 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
493 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
494 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,
495 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
496 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL),
497 HWMON_CHANNEL_INFO(in,
498 HWMON_I_INPUT | HWMON_I_LABEL,
499 HWMON_I_INPUT | HWMON_I_LABEL,
500 HWMON_I_INPUT | HWMON_I_LABEL,
501 HWMON_I_INPUT | HWMON_I_LABEL,
502 HWMON_I_INPUT | HWMON_I_LABEL,
503 HWMON_I_INPUT | HWMON_I_LABEL,
504 HWMON_I_INPUT | HWMON_I_LABEL,
505 HWMON_I_INPUT | HWMON_I_LABEL,
506 HWMON_I_INPUT | HWMON_I_LABEL,
507 HWMON_I_INPUT | HWMON_I_LABEL,
508 HWMON_I_INPUT | HWMON_I_LABEL,
509 HWMON_I_INPUT | HWMON_I_LABEL,
510 HWMON_I_INPUT | HWMON_I_LABEL,
511 HWMON_I_INPUT | HWMON_I_LABEL,
512 HWMON_I_INPUT | HWMON_I_LABEL,
513 HWMON_I_INPUT | HWMON_I_LABEL,
514 HWMON_I_INPUT | HWMON_I_LABEL,
515 HWMON_I_INPUT | HWMON_I_LABEL,
516 HWMON_I_INPUT | HWMON_I_LABEL,
517 HWMON_I_INPUT | HWMON_I_LABEL,
518 HWMON_I_INPUT | HWMON_I_LABEL,
519 HWMON_I_INPUT | HWMON_I_LABEL,
520 HWMON_I_INPUT | HWMON_I_LABEL,
521 HWMON_I_INPUT | HWMON_I_LABEL,
522 HWMON_I_INPUT | HWMON_I_LABEL,
523 HWMON_I_INPUT | HWMON_I_LABEL,
524 HWMON_I_INPUT | HWMON_I_LABEL,
525 HWMON_I_INPUT | HWMON_I_LABEL,
526 HWMON_I_INPUT | HWMON_I_LABEL,
527 HWMON_I_INPUT | HWMON_I_LABEL,
528 HWMON_I_INPUT | HWMON_I_LABEL),
529 HWMON_CHANNEL_INFO(curr,
530 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
531 HWMON_C_LABEL,
532 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
533 HWMON_C_LABEL,
534 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
535 HWMON_C_LABEL,
536 HWMON_C_INPUT | HWMON_C_LABEL,
537 HWMON_C_INPUT | HWMON_C_LABEL,
538 HWMON_C_INPUT | HWMON_C_LABEL,
539 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
540 HWMON_C_LABEL,
541 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
542 HWMON_C_LABEL,
543 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
544 HWMON_C_LABEL,
545 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
546 HWMON_C_LABEL,
547 HWMON_C_INPUT | HWMON_C_LABEL,
548 HWMON_C_INPUT | HWMON_C_LABEL,
549 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |
550 HWMON_C_LABEL),
551 HWMON_CHANNEL_INFO(power,
552 HWMON_P_INPUT | HWMON_P_LABEL),
553 NULL
554 };
555
556 static const struct m10bmc_hwmon_board_data n6000bmc_hwmon_bdata = {
557 .tables = {
558 [hwmon_temp] = n6000bmc_temp_tbl,
559 [hwmon_in] = n6000bmc_in_tbl,
560 [hwmon_curr] = n6000bmc_curr_tbl,
561 [hwmon_power] = n6000bmc_power_tbl,
562 },
563
564 .hinfo = n6000bmc_hinfo,
565 };
566
567 static const struct m10bmc_sdata *
find_sensor_data(struct m10bmc_hwmon * hw,enum hwmon_sensor_types type,int channel)568 find_sensor_data(struct m10bmc_hwmon *hw, enum hwmon_sensor_types type,
569 int channel)
570 {
571 const struct m10bmc_sdata *tbl;
572
573 tbl = hw->bdata->tables[type];
574 if (!tbl)
575 return ERR_PTR(-EOPNOTSUPP);
576
577 return &tbl[channel];
578 }
579
do_sensor_read(struct m10bmc_hwmon * hw,const struct m10bmc_sdata * data,unsigned int regoff,long * val)580 static int do_sensor_read(struct m10bmc_hwmon *hw,
581 const struct m10bmc_sdata *data,
582 unsigned int regoff, long *val)
583 {
584 unsigned int regval;
585 int ret;
586
587 ret = m10bmc_sys_read(hw->m10bmc, regoff, ®val);
588 if (ret)
589 return ret;
590
591 /*
592 * BMC Firmware will return 0xdeadbeef if the sensor value is invalid
593 * at that time. This usually happens on sensor channels which connect
594 * to external pluggable modules, e.g. QSFP temperature and voltage.
595 * When the QSFP is unplugged from cage, driver will get 0xdeadbeef
596 * from their registers.
597 */
598 if (regval == 0xdeadbeef)
599 return -ENODATA;
600
601 *val = regval * data->multiplier;
602
603 return 0;
604 }
605
m10bmc_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)606 static int m10bmc_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
607 u32 attr, int channel, long *val)
608 {
609 struct m10bmc_hwmon *hw = dev_get_drvdata(dev);
610 unsigned int reg = 0, reg_hyst = 0;
611 const struct m10bmc_sdata *data;
612 long hyst, value;
613 int ret;
614
615 data = find_sensor_data(hw, type, channel);
616 if (IS_ERR(data))
617 return PTR_ERR(data);
618
619 switch (type) {
620 case hwmon_temp:
621 switch (attr) {
622 case hwmon_temp_input:
623 reg = data->reg_input;
624 break;
625 case hwmon_temp_max_hyst:
626 reg_hyst = data->reg_hyst;
627 fallthrough;
628 case hwmon_temp_max:
629 reg = data->reg_max;
630 break;
631 case hwmon_temp_crit_hyst:
632 reg_hyst = data->reg_hyst;
633 fallthrough;
634 case hwmon_temp_crit:
635 reg = data->reg_crit;
636 break;
637 default:
638 return -EOPNOTSUPP;
639 }
640 break;
641 case hwmon_in:
642 switch (attr) {
643 case hwmon_in_input:
644 reg = data->reg_input;
645 break;
646 case hwmon_in_max:
647 reg = data->reg_max;
648 break;
649 case hwmon_in_crit:
650 reg = data->reg_crit;
651 break;
652 case hwmon_in_min:
653 reg = data->reg_min;
654 break;
655 default:
656 return -EOPNOTSUPP;
657 }
658 break;
659 case hwmon_curr:
660 switch (attr) {
661 case hwmon_curr_input:
662 reg = data->reg_input;
663 break;
664 case hwmon_curr_max:
665 reg = data->reg_max;
666 break;
667 case hwmon_curr_crit:
668 reg = data->reg_crit;
669 break;
670 default:
671 return -EOPNOTSUPP;
672 }
673 break;
674 case hwmon_power:
675 switch (attr) {
676 case hwmon_power_input:
677 reg = data->reg_input;
678 break;
679 default:
680 return -EOPNOTSUPP;
681 }
682 break;
683 default:
684 return -EOPNOTSUPP;
685 }
686
687 if (!reg)
688 return -EOPNOTSUPP;
689
690 ret = do_sensor_read(hw, data, reg, &value);
691 if (ret)
692 return ret;
693
694 if (reg_hyst) {
695 ret = do_sensor_read(hw, data, reg_hyst, &hyst);
696 if (ret)
697 return ret;
698
699 value -= hyst;
700 }
701
702 *val = value;
703
704 return 0;
705 }
706
m10bmc_hwmon_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)707 static int m10bmc_hwmon_read_string(struct device *dev,
708 enum hwmon_sensor_types type,
709 u32 attr, int channel, const char **str)
710 {
711 struct m10bmc_hwmon *hw = dev_get_drvdata(dev);
712 const struct m10bmc_sdata *data;
713
714 data = find_sensor_data(hw, type, channel);
715 if (IS_ERR(data))
716 return PTR_ERR(data);
717
718 *str = data->label;
719
720 return 0;
721 }
722
723 static const struct hwmon_ops m10bmc_hwmon_ops = {
724 .visible = 0444,
725 .read = m10bmc_hwmon_read,
726 .read_string = m10bmc_hwmon_read_string,
727 };
728
m10bmc_hwmon_probe(struct platform_device * pdev)729 static int m10bmc_hwmon_probe(struct platform_device *pdev)
730 {
731 const struct platform_device_id *id = platform_get_device_id(pdev);
732 struct intel_m10bmc *m10bmc = dev_get_drvdata(pdev->dev.parent);
733 struct device *hwmon_dev, *dev = &pdev->dev;
734 struct m10bmc_hwmon *hw;
735
736 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
737 if (!hw)
738 return -ENOMEM;
739
740 hw->dev = dev;
741 hw->m10bmc = m10bmc;
742 hw->bdata = (const struct m10bmc_hwmon_board_data *)id->driver_data;
743
744 hw->chip.info = hw->bdata->hinfo;
745 hw->chip.ops = &m10bmc_hwmon_ops;
746
747 hw->hw_name = devm_hwmon_sanitize_name(dev, id->name);
748 if (IS_ERR(hw->hw_name))
749 return PTR_ERR(hw->hw_name);
750
751 hwmon_dev = devm_hwmon_device_register_with_info(dev, hw->hw_name,
752 hw, &hw->chip, NULL);
753 return PTR_ERR_OR_ZERO(hwmon_dev);
754 }
755
756 static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
757 {
758 .name = "n3000bmc-hwmon",
759 .driver_data = (unsigned long)&n3000bmc_hwmon_bdata,
760 },
761 {
762 .name = "d5005bmc-hwmon",
763 .driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
764 },
765 {
766 .name = "n5010bmc-hwmon",
767 .driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
768 },
769 {
770 .name = "n6000bmc-hwmon",
771 .driver_data = (unsigned long)&n6000bmc_hwmon_bdata,
772 },
773 { }
774 };
775 MODULE_DEVICE_TABLE(platform, intel_m10bmc_hwmon_ids);
776
777 static struct platform_driver intel_m10bmc_hwmon_driver = {
778 .probe = m10bmc_hwmon_probe,
779 .driver = {
780 .name = "intel-m10-bmc-hwmon",
781 },
782 .id_table = intel_m10bmc_hwmon_ids,
783 };
784 module_platform_driver(intel_m10bmc_hwmon_driver);
785
786 MODULE_AUTHOR("Intel Corporation");
787 MODULE_DESCRIPTION("Intel MAX 10 BMC hardware monitor");
788 MODULE_LICENSE("GPL");
789 MODULE_IMPORT_NS("INTEL_M10_BMC_CORE");
790