1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/bitrev.h> 5 #include <linux/clk.h> 6 #include <linux/firmware.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <linux/reset.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_iec958.h> 15 #include <sound/pcm_params.h> 16 17 #include "fsl_xcvr.h" 18 #include "fsl_utils.h" 19 #include "imx-pcm.h" 20 21 #define FSL_XCVR_CAPDS_SIZE 256 22 #define SPDIF_NUM_RATES 7 23 24 enum fsl_xcvr_pll_verison { 25 PLL_MX8MP, 26 PLL_MX95, 27 }; 28 29 struct fsl_xcvr_soc_data { 30 const char *fw_name; 31 bool spdif_only; 32 bool use_edma; 33 bool use_phy; 34 enum fsl_xcvr_pll_verison pll_ver; 35 }; 36 37 struct fsl_xcvr { 38 const struct fsl_xcvr_soc_data *soc_data; 39 struct platform_device *pdev; 40 struct regmap *regmap; 41 struct regmap *regmap_phy; 42 struct regmap *regmap_pll; 43 struct clk *ipg_clk; 44 struct clk *pll_ipg_clk; 45 struct clk *phy_clk; 46 struct clk *spba_clk; 47 struct clk *pll8k_clk; 48 struct clk *pll11k_clk; 49 struct reset_control *reset; 50 u8 streams; 51 u32 mode; 52 u32 arc_mode; 53 void __iomem *ram_addr; 54 struct snd_dmaengine_dai_dma_data dma_prms_rx; 55 struct snd_dmaengine_dai_dma_data dma_prms_tx; 56 struct snd_aes_iec958 rx_iec958; 57 struct snd_aes_iec958 tx_iec958; 58 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 59 struct work_struct work_rst; 60 spinlock_t lock; /* Protect hw_reset and trigger */ 61 struct snd_pcm_hw_constraint_list spdif_constr_rates; 62 u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; 63 }; 64 65 static const char * const inc_mode[] = { 66 "On enabled and bitcount increment", "On enabled" 67 }; 68 69 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum, 70 FSL_XCVR_TX_DPTH_CNTR_CTRL, 71 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode); 72 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum, 73 FSL_XCVR_RX_DPTH_CNTR_CTRL, 74 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode); 75 76 static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = { 77 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 78 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0, 79 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 80 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum, 81 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 82 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 83 FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0, 84 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 85 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 86 FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0, 87 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 88 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR, 89 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 90 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR, 91 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 92 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR, 93 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 94 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR, 95 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 96 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 97 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0, 98 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 99 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum, 100 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 101 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 102 FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0, 103 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 104 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 105 FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0, 106 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 107 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR, 108 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 109 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR, 110 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 111 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR, 112 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 113 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR, 114 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 115 }; 116 117 static const struct fsl_xcvr_pll_conf { 118 u8 mfi; /* min=0x18, max=0x38 */ 119 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 120 u32 mfd; /* unsigned int */ 121 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 122 } fsl_xcvr_pll_cfg[] = { 123 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 124 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 125 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 126 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 127 }; 128 129 /* 130 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 131 * stream. Todo: to check how this case can be considered below 132 */ 133 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 134 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 135 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 136 .list = fsl_xcvr_earc_channels, 137 }; 138 139 static const u32 fsl_xcvr_earc_rates[] = { 140 32000, 44100, 48000, 64000, 88200, 96000, 141 128000, 176400, 192000, 256000, 352800, 384000, 142 512000, 705600, 768000, 1024000, 1411200, 1536000, 143 }; 144 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 145 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 146 .list = fsl_xcvr_earc_rates, 147 }; 148 149 static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 150 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 151 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 152 .list = fsl_xcvr_spdif_channels, 153 }; 154 155 static const u32 fsl_xcvr_spdif_rates[] = { 156 32000, 44100, 48000, 88200, 96000, 176400, 192000, 157 }; 158 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 159 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 160 .list = fsl_xcvr_spdif_rates, 161 }; 162 163 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 164 struct snd_ctl_elem_value *ucontrol) 165 { 166 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 167 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 168 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 169 unsigned int *item = ucontrol->value.enumerated.item; 170 int val = snd_soc_enum_item_to_val(e, item[0]); 171 int ret; 172 173 if (val < 0 || val > 1) 174 return -EINVAL; 175 176 ret = (xcvr->arc_mode != val); 177 178 xcvr->arc_mode = val; 179 180 return ret; 181 } 182 183 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 184 struct snd_ctl_elem_value *ucontrol) 185 { 186 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 187 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 188 189 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 190 191 return 0; 192 } 193 194 static const u32 fsl_xcvr_phy_arc_cfg[] = { 195 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 196 }; 197 198 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 199 static const struct soc_enum fsl_xcvr_arc_mode_enum = 200 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 201 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 202 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 203 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 204 205 /* Capabilities data structure, bytes */ 206 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 207 struct snd_ctl_elem_info *uinfo) 208 { 209 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 210 uinfo->count = FSL_XCVR_CAPDS_SIZE; 211 212 return 0; 213 } 214 215 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 216 struct snd_ctl_elem_value *ucontrol) 217 { 218 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 219 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 220 221 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 222 223 return 0; 224 } 225 226 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 227 struct snd_ctl_elem_value *ucontrol) 228 { 229 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 230 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 231 int changed; 232 233 changed = memcmp(xcvr->cap_ds, ucontrol->value.bytes.data, 234 sizeof(xcvr->cap_ds)) != 0; 235 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, 236 sizeof(xcvr->cap_ds)); 237 238 return changed; 239 } 240 241 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 242 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 243 .name = "Capabilities Data Structure", 244 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 245 .info = fsl_xcvr_type_capds_bytes_info, 246 .get = fsl_xcvr_capds_get, 247 .put = fsl_xcvr_capds_put, 248 }; 249 250 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 251 bool active) 252 { 253 struct snd_soc_card *card = dai->component->card; 254 struct snd_kcontrol *kctl; 255 bool enabled; 256 257 lockdep_assert_held(&card->snd_card->controls_rwsem); 258 259 kctl = snd_soc_card_get_kcontrol(card, name); 260 if (kctl == NULL) 261 return -ENOENT; 262 263 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 264 if (active == enabled) 265 return 0; /* nothing to do */ 266 267 if (active) 268 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 269 else 270 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 271 272 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 273 274 return 1; 275 } 276 277 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 278 struct snd_ctl_elem_value *ucontrol) 279 { 280 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 281 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 282 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 283 unsigned int *item = ucontrol->value.enumerated.item; 284 int val = snd_soc_enum_item_to_val(e, item[0]); 285 struct snd_soc_card *card = dai->component->card; 286 struct snd_soc_pcm_runtime *rtd; 287 int ret; 288 289 if (val < FSL_XCVR_MODE_SPDIF || val > FSL_XCVR_MODE_EARC) 290 return -EINVAL; 291 292 ret = (xcvr->mode != val); 293 294 xcvr->mode = val; 295 296 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 297 (xcvr->mode == FSL_XCVR_MODE_ARC)); 298 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 299 (xcvr->mode == FSL_XCVR_MODE_EARC)); 300 /* Allow playback for SPDIF only */ 301 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 302 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 303 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 304 return ret; 305 } 306 307 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 308 struct snd_ctl_elem_value *ucontrol) 309 { 310 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 311 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 312 313 ucontrol->value.enumerated.item[0] = xcvr->mode; 314 315 return 0; 316 } 317 318 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 319 static const struct soc_enum fsl_xcvr_mode_enum = 320 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 321 static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 322 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 323 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 324 325 /** phy: true => phy, false => pll */ 326 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 327 { 328 struct device *dev = &xcvr->pdev->dev; 329 u32 val, idx, tidx; 330 int ret; 331 332 idx = BIT(phy ? 26 : 24); 333 tidx = BIT(phy ? 27 : 25); 334 335 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 336 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 337 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 338 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 339 340 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 341 (val & idx) == ((val & tidx) >> 1), 342 10, 10000); 343 if (ret) 344 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 345 phy ? "PHY" : "PLL", reg, data); 346 return ret; 347 } 348 349 static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) 350 { 351 struct device *dev = &xcvr->pdev->dev; 352 u32 val, idx, tidx; 353 int ret; 354 355 idx = BIT(phy ? 26 : 24); 356 tidx = BIT(phy ? 27 : 25); 357 358 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 359 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 360 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 361 362 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 363 (val & idx) == ((val & tidx) >> 1), 364 10, 10000); 365 if (ret) 366 dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", 367 phy ? "PHY" : "PLL", reg); 368 369 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); 370 371 return ret; 372 } 373 374 static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) 375 { 376 struct fsl_xcvr *xcvr = context; 377 378 return fsl_xcvr_ai_read(xcvr, reg, val, 1); 379 } 380 381 static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) 382 { 383 struct fsl_xcvr *xcvr = context; 384 385 return fsl_xcvr_ai_write(xcvr, reg, val, 1); 386 } 387 388 static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) 389 { 390 struct fsl_xcvr *xcvr = context; 391 392 return fsl_xcvr_ai_read(xcvr, reg, val, 0); 393 } 394 395 static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) 396 { 397 struct fsl_xcvr *xcvr = context; 398 399 return fsl_xcvr_ai_write(xcvr, reg, val, 0); 400 } 401 402 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 403 { 404 struct device *dev = &xcvr->pdev->dev; 405 u32 i, div = 0, log2, val; 406 int ret; 407 408 if (!xcvr->soc_data->use_phy) 409 return 0; 410 411 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 412 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 413 div = fsl_xcvr_pll_cfg[i].fout / freq; 414 break; 415 } 416 } 417 418 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 419 return -EINVAL; 420 421 log2 = ilog2(div); 422 423 /* Release AI interface from reset */ 424 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 425 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 426 if (ret < 0) { 427 dev_err(dev, "Error while setting IER0: %d\n", ret); 428 return ret; 429 } 430 431 switch (xcvr->soc_data->pll_ver) { 432 case PLL_MX8MP: 433 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 434 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, 435 FSL_XCVR_PLL_BANDGAP_EN_VBG); 436 437 /* PLL: CTRL0: DIV_INTEGER */ 438 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); 439 /* PLL: NUMERATOR: MFN */ 440 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); 441 /* PLL: DENOMINATOR: MFD */ 442 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); 443 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 444 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 445 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); 446 udelay(25); 447 /* PLL: CTRL0: Clear Hold Ring Off */ 448 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 449 FSL_XCVR_PLL_CTRL0_HROFF); 450 udelay(100); 451 if (tx) { /* TX is enabled for SPDIF only */ 452 /* PLL: POSTDIV: PDIV0 */ 453 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 454 FSL_XCVR_PLL_PDIVx(log2, 0)); 455 /* PLL: CTRL_SET: CLKMUX0_EN */ 456 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 457 FSL_XCVR_PLL_CTRL0_CM0_EN); 458 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 459 /* PLL: POSTDIV: PDIV1 */ 460 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 461 FSL_XCVR_PLL_PDIVx(log2, 1)); 462 /* PLL: CTRL_SET: CLKMUX1_EN */ 463 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 464 FSL_XCVR_PLL_CTRL0_CM1_EN); 465 } else { /* SPDIF / ARC RX */ 466 /* PLL: POSTDIV: PDIV2 */ 467 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 468 FSL_XCVR_PLL_PDIVx(log2, 2)); 469 /* PLL: CTRL_SET: CLKMUX2_EN */ 470 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 471 FSL_XCVR_PLL_CTRL0_CM2_EN); 472 } 473 break; 474 case PLL_MX95: 475 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; 476 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); 477 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; 478 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); 479 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, 480 fsl_xcvr_pll_cfg[i].mfd); 481 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; 482 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); 483 break; 484 default: 485 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); 486 return -EINVAL; 487 } 488 489 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 490 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 491 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 492 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 493 FSL_XCVR_PHY_CTRL_PHY_EN); 494 /* PHY: CTRL2_SET: EARC_TX_MODE */ 495 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 496 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 497 } else if (!tx) { /* SPDIF / ARC RX mode */ 498 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 499 /* PHY: CTRL_SET: SPDIF_EN */ 500 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 501 FSL_XCVR_PHY_CTRL_SPDIF_EN); 502 else /* PHY: CTRL_SET: ARC RX setup */ 503 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 504 FSL_XCVR_PHY_CTRL_PHY_EN | 505 FSL_XCVR_PHY_CTRL_RX_CM_EN | 506 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); 507 } 508 509 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 510 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 511 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 512 return 0; 513 } 514 515 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 516 { 517 struct device *dev = &xcvr->pdev->dev; 518 int ret; 519 520 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; 521 clk_disable_unprepare(xcvr->phy_clk); 522 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, 523 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); 524 ret = clk_set_rate(xcvr->phy_clk, freq); 525 if (ret < 0) { 526 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 527 return ret; 528 } 529 ret = clk_prepare_enable(xcvr->phy_clk); 530 if (ret) { 531 dev_err(dev, "failed to start PHY clock: %d\n", ret); 532 return ret; 533 } 534 535 if (!xcvr->soc_data->use_phy) 536 return 0; 537 /* Release AI interface from reset */ 538 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 539 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 540 if (ret < 0) { 541 dev_err(dev, "Error while setting IER0: %d\n", ret); 542 return ret; 543 } 544 545 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 546 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 547 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 548 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 549 FSL_XCVR_PHY_CTRL_PHY_EN); 550 /* PHY: CTRL2_SET: EARC_TX_MODE */ 551 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 552 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 553 } else { /* SPDIF mode */ 554 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 555 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 556 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 557 FSL_XCVR_PHY_CTRL_SPDIF_EN); 558 } 559 560 dev_dbg(dev, "PLL Fexp: %u\n", freq); 561 562 return 0; 563 } 564 565 #define FSL_XCVR_SPDIF_RX_FREQ 175000000 566 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 567 struct snd_soc_dai *dai) 568 { 569 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 570 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 571 u32 m_ctl = 0, v_ctl = 0; 572 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 573 u32 fout = 32 * r * ch * 10; 574 int ret = 0; 575 576 switch (xcvr->mode) { 577 case FSL_XCVR_MODE_SPDIF: 578 if (xcvr->soc_data->spdif_only && tx) { 579 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 580 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, 581 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); 582 if (ret < 0) { 583 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); 584 return ret; 585 } 586 } 587 fallthrough; 588 case FSL_XCVR_MODE_ARC: 589 if (tx) { 590 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 591 if (ret < 0) { 592 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 593 fout, ret); 594 return ret; 595 } 596 597 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 598 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 599 if (ret < 0) { 600 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 601 return ret; 602 } 603 604 /** 605 * set SPDIF MODE - this flag is used to gate 606 * SPDIF output, useless for SPDIF RX 607 */ 608 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 609 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 610 } else { 611 /** 612 * Clear RX FIFO, flip RX FIFO bits, 613 * disable eARC related HW mode detects 614 */ 615 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 616 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 617 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 618 FSL_XCVR_RX_DPTH_CTRL_COMP | 619 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 620 if (ret < 0) { 621 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 622 return ret; 623 } 624 625 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 626 if (ret < 0) { 627 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 628 FSL_XCVR_SPDIF_RX_FREQ, ret); 629 return ret; 630 } 631 } 632 break; 633 case FSL_XCVR_MODE_EARC: 634 if (!tx) { 635 /** Clear RX FIFO, flip RX FIFO bits */ 636 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 637 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 638 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 639 if (ret < 0) { 640 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 641 return ret; 642 } 643 644 /** Enable eARC related HW mode detects */ 645 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 646 FSL_XCVR_RX_DPTH_CTRL_COMP | 647 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 648 if (ret < 0) { 649 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 650 return ret; 651 } 652 } 653 654 /* clear CMDC RESET */ 655 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 656 /* set TX_RX_MODE */ 657 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 658 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 659 break; 660 } 661 662 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 663 if (ret < 0) { 664 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 672 const struct snd_pcm_hw_constraint_list *channels, 673 const struct snd_pcm_hw_constraint_list *rates) 674 { 675 struct snd_pcm_runtime *rt = substream->runtime; 676 int ret; 677 678 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 679 channels); 680 if (ret < 0) 681 return ret; 682 683 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 684 rates); 685 if (ret < 0) 686 return ret; 687 688 return 0; 689 } 690 691 static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 692 struct snd_soc_dai *dai) 693 { 694 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 695 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 696 int ret = 0; 697 698 if (xcvr->streams & BIT(substream->stream)) { 699 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 700 return -EBUSY; 701 } 702 703 /* 704 * EDMA controller needs period size to be a multiple of 705 * tx/rx maxburst 706 */ 707 if (xcvr->soc_data->use_edma) 708 snd_pcm_hw_constraint_step(substream->runtime, 0, 709 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 710 tx ? xcvr->dma_prms_tx.maxburst : 711 xcvr->dma_prms_rx.maxburst); 712 713 switch (xcvr->mode) { 714 case FSL_XCVR_MODE_SPDIF: 715 case FSL_XCVR_MODE_ARC: 716 if (xcvr->soc_data->spdif_only && tx) 717 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 718 &xcvr->spdif_constr_rates); 719 else 720 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 721 &fsl_xcvr_spdif_rates_constr); 722 break; 723 case FSL_XCVR_MODE_EARC: 724 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 725 &fsl_xcvr_earc_rates_constr); 726 break; 727 } 728 if (ret < 0) 729 return ret; 730 731 xcvr->streams |= BIT(substream->stream); 732 733 if (!xcvr->soc_data->spdif_only) { 734 struct snd_soc_card *card = dai->component->card; 735 736 /* Disable XCVR controls if there is stream started */ 737 down_read(&card->snd_card->controls_rwsem); 738 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 739 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 740 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 741 up_read(&card->snd_card->controls_rwsem); 742 } 743 744 return 0; 745 } 746 747 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 748 struct snd_soc_dai *dai) 749 { 750 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 751 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 752 u32 mask = 0, val = 0; 753 int ret; 754 755 xcvr->streams &= ~BIT(substream->stream); 756 757 /* Enable XCVR controls if there is no stream started */ 758 if (!xcvr->streams) { 759 if (!xcvr->soc_data->spdif_only) { 760 struct snd_soc_card *card = dai->component->card; 761 762 down_read(&card->snd_card->controls_rwsem); 763 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 764 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 765 (xcvr->mode == FSL_XCVR_MODE_ARC)); 766 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 767 (xcvr->mode == FSL_XCVR_MODE_EARC)); 768 up_read(&card->snd_card->controls_rwsem); 769 } 770 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 771 FSL_XCVR_IRQ_EARC_ALL, 0); 772 if (ret < 0) { 773 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 774 return; 775 } 776 777 /* clear SPDIF MODE */ 778 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 779 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 780 } 781 782 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 783 /* set CMDC RESET */ 784 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 785 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 786 } 787 788 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 789 if (ret < 0) { 790 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 791 return; 792 } 793 } 794 795 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 796 struct snd_soc_dai *dai) 797 { 798 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 799 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 800 int ret = 0; 801 802 guard(spinlock_irqsave)(&xcvr->lock); 803 804 switch (cmd) { 805 case SNDRV_PCM_TRIGGER_START: 806 case SNDRV_PCM_TRIGGER_RESUME: 807 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 808 /* set DPATH RESET */ 809 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 810 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 811 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx)); 812 if (ret < 0) { 813 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); 814 return ret; 815 } 816 817 if (tx) { 818 switch (xcvr->mode) { 819 case FSL_XCVR_MODE_EARC: 820 /* set isr_cmdc_tx_en, w1c */ 821 ret = regmap_write(xcvr->regmap, 822 FSL_XCVR_ISR_SET, 823 FSL_XCVR_ISR_CMDC_TX_EN); 824 if (ret < 0) { 825 dev_err(dai->dev, "err updating isr %d\n", ret); 826 return ret; 827 } 828 fallthrough; 829 case FSL_XCVR_MODE_SPDIF: 830 ret = regmap_set_bits(xcvr->regmap, 831 FSL_XCVR_TX_DPTH_CTRL, 832 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 833 if (ret < 0) { 834 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 835 return ret; 836 } 837 break; 838 } 839 } 840 841 /* enable DMA RD/WR */ 842 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 843 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 844 if (ret < 0) { 845 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 846 return ret; 847 } 848 849 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 850 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 851 if (ret < 0) { 852 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 853 return ret; 854 } 855 856 /* clear DPATH RESET */ 857 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 858 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 859 0); 860 if (ret < 0) { 861 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 862 return ret; 863 } 864 865 break; 866 case SNDRV_PCM_TRIGGER_STOP: 867 case SNDRV_PCM_TRIGGER_SUSPEND: 868 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 869 /* disable DMA RD/WR */ 870 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 871 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 872 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 873 if (ret < 0) { 874 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 875 return ret; 876 } 877 878 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 879 FSL_XCVR_IRQ_EARC_ALL, 0); 880 if (ret < 0) { 881 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); 882 return ret; 883 } 884 885 if (tx) { 886 switch (xcvr->mode) { 887 case FSL_XCVR_MODE_SPDIF: 888 ret = regmap_clear_bits(xcvr->regmap, 889 FSL_XCVR_TX_DPTH_CTRL, 890 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 891 if (ret < 0) { 892 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 893 return ret; 894 } 895 if (xcvr->soc_data->spdif_only) 896 break; 897 else 898 fallthrough; 899 case FSL_XCVR_MODE_EARC: 900 /* clear ISR_CMDC_TX_EN, W1C */ 901 ret = regmap_write(xcvr->regmap, 902 FSL_XCVR_ISR_CLR, 903 FSL_XCVR_ISR_CMDC_TX_EN); 904 if (ret < 0) { 905 dev_err(dai->dev, 906 "Err updating ISR %d\n", ret); 907 return ret; 908 } 909 break; 910 } 911 } 912 break; 913 default: 914 ret = -EINVAL; 915 break; 916 } 917 918 return ret; 919 } 920 921 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 922 { 923 struct device *dev = &xcvr->pdev->dev; 924 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 925 u32 mask, val; 926 927 const struct firmware *fw __free(firmware) = NULL; 928 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 929 if (ret) { 930 dev_err(dev, "failed to request firmware.\n"); 931 return ret; 932 } 933 934 rem = fw->size; 935 936 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 937 if (rem > 16384) { 938 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 939 return -ENOMEM; 940 } 941 942 for (page = 0; page < 10; page++) { 943 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 944 FSL_XCVR_EXT_CTRL_PAGE_MASK, 945 FSL_XCVR_EXT_CTRL_PAGE(page)); 946 if (ret < 0) { 947 dev_err(dev, "FW: failed to set page %d, err=%d\n", 948 page, ret); 949 return ret; 950 } 951 952 off = page * size; 953 out = min(rem, size); 954 /* IPG clock is assumed to be running, otherwise it will hang */ 955 if (out > 0) { 956 /* write firmware into code memory */ 957 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 958 rem -= out; 959 if (rem == 0) { 960 /* last part of firmware written */ 961 /* clean remaining part of code memory page */ 962 memset_io(xcvr->ram_addr + out, 0, size - out); 963 } 964 } else { 965 /* clean current page, including data memory */ 966 memset_io(xcvr->ram_addr, 0, size); 967 } 968 } 969 970 /* configure watermarks */ 971 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 972 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 973 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 974 /* disable DMA RD/WR */ 975 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 976 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 977 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 978 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 979 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 980 981 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 982 if (ret < 0) { 983 dev_err(dev, "Failed to set watermarks: %d\n", ret); 984 return ret; 985 } 986 987 /* Store Capabilities Data Structure into Data RAM */ 988 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 989 FSL_XCVR_CAPDS_SIZE); 990 return 0; 991 } 992 993 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 994 struct snd_ctl_elem_info *uinfo) 995 { 996 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 997 uinfo->count = 1; 998 999 return 0; 1000 } 1001 1002 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 1003 struct snd_ctl_elem_info *uinfo) 1004 { 1005 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1006 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 1007 1008 return 0; 1009 } 1010 1011 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 1012 struct snd_ctl_elem_value *ucontrol) 1013 { 1014 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1015 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1016 1017 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 1018 1019 return 0; 1020 } 1021 1022 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 1023 struct snd_ctl_elem_value *ucontrol) 1024 { 1025 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1026 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1027 1028 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 1029 1030 return 0; 1031 } 1032 1033 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 1034 struct snd_ctl_elem_value *ucontrol) 1035 { 1036 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1037 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1038 int changed; 1039 1040 changed = memcmp(xcvr->tx_iec958.status, 1041 ucontrol->value.iec958.status, 1042 sizeof(xcvr->tx_iec958.status)) != 0; 1043 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 1044 sizeof(xcvr->tx_iec958.status)); 1045 1046 return changed; 1047 } 1048 1049 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 1050 /* Channel status controller */ 1051 { 1052 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1053 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1054 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1055 .info = fsl_xcvr_type_iec958_info, 1056 .get = fsl_xcvr_rx_cs_get, 1057 }, 1058 /* Capture channel status, bytes */ 1059 { 1060 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1061 .name = "Capture Channel Status", 1062 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1063 .info = fsl_xcvr_type_iec958_bytes_info, 1064 .get = fsl_xcvr_rx_cs_get, 1065 }, 1066 }; 1067 1068 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 1069 /* Channel status controller */ 1070 { 1071 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1072 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1073 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1074 .info = fsl_xcvr_type_iec958_info, 1075 .get = fsl_xcvr_tx_cs_get, 1076 .put = fsl_xcvr_tx_cs_put, 1077 }, 1078 /* Playback channel status, bytes */ 1079 { 1080 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1081 .name = "Playback Channel Status", 1082 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1083 .info = fsl_xcvr_type_iec958_bytes_info, 1084 .get = fsl_xcvr_tx_cs_get, 1085 .put = fsl_xcvr_tx_cs_put, 1086 }, 1087 }; 1088 1089 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 1090 { 1091 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1092 1093 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 1094 1095 if (xcvr->soc_data->spdif_only) 1096 xcvr->mode = FSL_XCVR_MODE_SPDIF; 1097 else { 1098 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 1099 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 1100 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 1101 } 1102 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 1103 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 1104 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 1105 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 1106 return 0; 1107 } 1108 1109 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 1110 .probe = fsl_xcvr_dai_probe, 1111 .prepare = fsl_xcvr_prepare, 1112 .startup = fsl_xcvr_startup, 1113 .shutdown = fsl_xcvr_shutdown, 1114 .trigger = fsl_xcvr_trigger, 1115 }; 1116 1117 static struct snd_soc_dai_driver fsl_xcvr_dai = { 1118 .ops = &fsl_xcvr_dai_ops, 1119 .playback = { 1120 .stream_name = "CPU-Playback", 1121 .channels_min = 1, 1122 .channels_max = 32, 1123 .rate_min = 32000, 1124 .rate_max = 1536000, 1125 .rates = SNDRV_PCM_RATE_KNOT, 1126 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1127 }, 1128 .capture = { 1129 .stream_name = "CPU-Capture", 1130 .channels_min = 1, 1131 .channels_max = 32, 1132 .rate_min = 32000, 1133 .rate_max = 1536000, 1134 .rates = SNDRV_PCM_RATE_KNOT, 1135 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1136 }, 1137 }; 1138 1139 static int fsl_xcvr_component_probe(struct snd_soc_component *component) 1140 { 1141 struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component); 1142 1143 snd_soc_component_init_regmap(component, xcvr->regmap); 1144 1145 return 0; 1146 } 1147 1148 static const struct snd_soc_component_driver fsl_xcvr_comp = { 1149 .name = "fsl-xcvr-dai", 1150 .probe = fsl_xcvr_component_probe, 1151 .controls = fsl_xcvr_timestamp_ctrls, 1152 .num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls), 1153 .legacy_dai_naming = 1, 1154 }; 1155 1156 static const struct reg_default fsl_xcvr_reg_defaults[] = { 1157 { FSL_XCVR_VERSION, 0x00000000 }, 1158 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 1159 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 1160 { FSL_XCVR_EXT_IER0, 0x00000000 }, 1161 { FSL_XCVR_EXT_IER1, 0x00000000 }, 1162 { FSL_XCVR_EXT_ISR, 0x00000000 }, 1163 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 1164 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 1165 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 1166 { FSL_XCVR_IER, 0x00000000 }, 1167 { FSL_XCVR_ISR, 0x00000000 }, 1168 { FSL_XCVR_ISR_SET, 0x00000000 }, 1169 { FSL_XCVR_ISR_CLR, 0x00000000 }, 1170 { FSL_XCVR_ISR_TOG, 0x00000000 }, 1171 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 1172 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 1173 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 1174 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 1175 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 1176 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 1177 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1178 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1179 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1180 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 1181 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 1182 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 1183 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 1184 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 1185 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 1186 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 1187 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 1188 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 1189 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 1190 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 1191 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 1192 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 1193 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 1194 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 1195 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1196 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1197 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1198 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 1199 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 1200 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 1201 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 1202 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 1203 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 1204 }; 1205 1206 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 1207 { 1208 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1209 1210 if (!xcvr->soc_data->use_phy) 1211 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1212 reg > FSL_XCVR_TX_DPTH_BCRR) 1213 return false; 1214 switch (reg) { 1215 case FSL_XCVR_VERSION: 1216 case FSL_XCVR_EXT_CTRL: 1217 case FSL_XCVR_EXT_STATUS: 1218 case FSL_XCVR_EXT_IER0: 1219 case FSL_XCVR_EXT_IER1: 1220 case FSL_XCVR_EXT_ISR: 1221 case FSL_XCVR_EXT_ISR_SET: 1222 case FSL_XCVR_EXT_ISR_CLR: 1223 case FSL_XCVR_EXT_ISR_TOG: 1224 case FSL_XCVR_IER: 1225 case FSL_XCVR_ISR: 1226 case FSL_XCVR_ISR_SET: 1227 case FSL_XCVR_ISR_CLR: 1228 case FSL_XCVR_ISR_TOG: 1229 case FSL_XCVR_PHY_AI_CTRL: 1230 case FSL_XCVR_PHY_AI_CTRL_SET: 1231 case FSL_XCVR_PHY_AI_CTRL_CLR: 1232 case FSL_XCVR_PHY_AI_CTRL_TOG: 1233 case FSL_XCVR_PHY_AI_RDATA: 1234 case FSL_XCVR_CLK_CTRL: 1235 case FSL_XCVR_RX_DPTH_CTRL: 1236 case FSL_XCVR_RX_DPTH_CTRL_SET: 1237 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1238 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1239 case FSL_XCVR_RX_CS_DATA_0: 1240 case FSL_XCVR_RX_CS_DATA_1: 1241 case FSL_XCVR_RX_CS_DATA_2: 1242 case FSL_XCVR_RX_CS_DATA_3: 1243 case FSL_XCVR_RX_CS_DATA_4: 1244 case FSL_XCVR_RX_CS_DATA_5: 1245 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1246 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1247 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1248 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1249 case FSL_XCVR_RX_DPTH_TSCR: 1250 case FSL_XCVR_RX_DPTH_BCR: 1251 case FSL_XCVR_RX_DPTH_BCTR: 1252 case FSL_XCVR_RX_DPTH_BCRR: 1253 case FSL_XCVR_TX_DPTH_CTRL: 1254 case FSL_XCVR_TX_DPTH_CTRL_SET: 1255 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1256 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1257 case FSL_XCVR_TX_CS_DATA_0: 1258 case FSL_XCVR_TX_CS_DATA_1: 1259 case FSL_XCVR_TX_CS_DATA_2: 1260 case FSL_XCVR_TX_CS_DATA_3: 1261 case FSL_XCVR_TX_CS_DATA_4: 1262 case FSL_XCVR_TX_CS_DATA_5: 1263 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1264 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1265 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1266 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1267 case FSL_XCVR_TX_DPTH_TSCR: 1268 case FSL_XCVR_TX_DPTH_BCR: 1269 case FSL_XCVR_TX_DPTH_BCTR: 1270 case FSL_XCVR_TX_DPTH_BCRR: 1271 case FSL_XCVR_DEBUG_REG_0: 1272 case FSL_XCVR_DEBUG_REG_1: 1273 return true; 1274 default: 1275 return false; 1276 } 1277 } 1278 1279 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1280 { 1281 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1282 1283 if (!xcvr->soc_data->use_phy) 1284 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1285 return false; 1286 switch (reg) { 1287 case FSL_XCVR_EXT_CTRL: 1288 case FSL_XCVR_EXT_IER0: 1289 case FSL_XCVR_EXT_IER1: 1290 case FSL_XCVR_EXT_ISR: 1291 case FSL_XCVR_EXT_ISR_SET: 1292 case FSL_XCVR_EXT_ISR_CLR: 1293 case FSL_XCVR_EXT_ISR_TOG: 1294 case FSL_XCVR_IER: 1295 case FSL_XCVR_ISR_SET: 1296 case FSL_XCVR_ISR_CLR: 1297 case FSL_XCVR_ISR_TOG: 1298 case FSL_XCVR_PHY_AI_CTRL: 1299 case FSL_XCVR_PHY_AI_CTRL_SET: 1300 case FSL_XCVR_PHY_AI_CTRL_CLR: 1301 case FSL_XCVR_PHY_AI_CTRL_TOG: 1302 case FSL_XCVR_PHY_AI_WDATA: 1303 case FSL_XCVR_CLK_CTRL: 1304 case FSL_XCVR_RX_DPTH_CTRL: 1305 case FSL_XCVR_RX_DPTH_CTRL_SET: 1306 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1307 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1308 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1309 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1310 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1311 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1312 case FSL_XCVR_TX_DPTH_CTRL: 1313 case FSL_XCVR_TX_DPTH_CTRL_SET: 1314 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1315 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1316 case FSL_XCVR_TX_CS_DATA_0: 1317 case FSL_XCVR_TX_CS_DATA_1: 1318 case FSL_XCVR_TX_CS_DATA_2: 1319 case FSL_XCVR_TX_CS_DATA_3: 1320 case FSL_XCVR_TX_CS_DATA_4: 1321 case FSL_XCVR_TX_CS_DATA_5: 1322 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1323 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1324 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1325 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1326 return true; 1327 default: 1328 return false; 1329 } 1330 } 1331 1332 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1333 { 1334 switch (reg) { 1335 case FSL_XCVR_EXT_STATUS: 1336 case FSL_XCVR_EXT_ISR: 1337 case FSL_XCVR_EXT_ISR_SET: 1338 case FSL_XCVR_EXT_ISR_CLR: 1339 case FSL_XCVR_EXT_ISR_TOG: 1340 case FSL_XCVR_ISR: 1341 case FSL_XCVR_ISR_SET: 1342 case FSL_XCVR_ISR_CLR: 1343 case FSL_XCVR_ISR_TOG: 1344 case FSL_XCVR_PHY_AI_CTRL: 1345 case FSL_XCVR_PHY_AI_CTRL_SET: 1346 case FSL_XCVR_PHY_AI_CTRL_CLR: 1347 case FSL_XCVR_PHY_AI_CTRL_TOG: 1348 case FSL_XCVR_PHY_AI_RDATA: 1349 case FSL_XCVR_RX_CS_DATA_0: 1350 case FSL_XCVR_RX_CS_DATA_1: 1351 case FSL_XCVR_RX_CS_DATA_2: 1352 case FSL_XCVR_RX_CS_DATA_3: 1353 case FSL_XCVR_RX_CS_DATA_4: 1354 case FSL_XCVR_RX_CS_DATA_5: 1355 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1356 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1357 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1358 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1359 case FSL_XCVR_RX_DPTH_TSCR: 1360 case FSL_XCVR_RX_DPTH_BCR: 1361 case FSL_XCVR_RX_DPTH_BCTR: 1362 case FSL_XCVR_RX_DPTH_BCRR: 1363 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1364 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1365 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1366 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1367 case FSL_XCVR_TX_DPTH_TSCR: 1368 case FSL_XCVR_TX_DPTH_BCR: 1369 case FSL_XCVR_TX_DPTH_BCTR: 1370 case FSL_XCVR_TX_DPTH_BCRR: 1371 case FSL_XCVR_DEBUG_REG_0: 1372 case FSL_XCVR_DEBUG_REG_1: 1373 return true; 1374 default: 1375 return false; 1376 } 1377 } 1378 1379 static const struct regmap_config fsl_xcvr_regmap_cfg = { 1380 .reg_bits = 32, 1381 .reg_stride = 4, 1382 .val_bits = 32, 1383 .max_register = FSL_XCVR_MAX_REG, 1384 .reg_defaults = fsl_xcvr_reg_defaults, 1385 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1386 .readable_reg = fsl_xcvr_readable_reg, 1387 .volatile_reg = fsl_xcvr_volatile_reg, 1388 .writeable_reg = fsl_xcvr_writeable_reg, 1389 .cache_type = REGCACHE_FLAT, 1390 }; 1391 1392 static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { 1393 { FSL_XCVR_PHY_CTRL, 0x58200804 }, 1394 { FSL_XCVR_PHY_STATUS, 0x00000000 }, 1395 { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, 1396 { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, 1397 { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, 1398 { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, 1399 { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, 1400 { FSL_XCVR_PHY_CTRL2, 0x80000000 }, 1401 }; 1402 1403 static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { 1404 .name = "phy", 1405 .reg_bits = 8, 1406 .reg_stride = 4, 1407 .val_bits = 32, 1408 .max_register = FSL_XCVR_PHY_CTRL2_TOG, 1409 .reg_defaults = fsl_xcvr_phy_reg_defaults, 1410 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), 1411 .cache_type = REGCACHE_FLAT, 1412 .reg_read = fsl_xcvr_phy_reg_read, 1413 .reg_write = fsl_xcvr_phy_reg_write, 1414 }; 1415 1416 static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { 1417 .name = "pllv0", 1418 .reg_bits = 8, 1419 .reg_stride = 4, 1420 .val_bits = 32, 1421 .max_register = FSL_XCVR_PLL_STAT0_TOG, 1422 .cache_type = REGCACHE_FLAT, 1423 .reg_read = fsl_xcvr_pll_reg_read, 1424 .reg_write = fsl_xcvr_pll_reg_write, 1425 }; 1426 1427 static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { 1428 .name = "pllv1", 1429 .reg_bits = 8, 1430 .reg_stride = 4, 1431 .val_bits = 32, 1432 .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, 1433 .cache_type = REGCACHE_FLAT, 1434 .reg_read = fsl_xcvr_pll_reg_read, 1435 .reg_write = fsl_xcvr_pll_reg_write, 1436 }; 1437 1438 static void reset_rx_work(struct work_struct *work) 1439 { 1440 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); 1441 struct device *dev = &xcvr->pdev->dev; 1442 u32 ext_ctrl; 1443 1444 dev_dbg(dev, "reset rx path\n"); 1445 guard(spinlock_irqsave)(&xcvr->lock); 1446 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl); 1447 1448 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) { 1449 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1450 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1451 FSL_XCVR_EXT_CTRL_DMA_RD_DIS); 1452 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1453 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1454 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET); 1455 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1456 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1457 0); 1458 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1459 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1460 0); 1461 } 1462 } 1463 1464 static irqreturn_t irq0_isr(int irq, void *devid) 1465 { 1466 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1467 struct device *dev = &xcvr->pdev->dev; 1468 struct regmap *regmap = xcvr->regmap; 1469 void __iomem *reg_ctrl, *reg_buff; 1470 u32 isr, isr_clr = 0, val, i; 1471 1472 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1473 1474 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1475 dev_dbg(dev, "Received new CS block\n"); 1476 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1477 if (xcvr->soc_data->fw_name) { 1478 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1479 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1480 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1481 FSL_XCVR_EXT_CTRL_PAGE(8)); 1482 1483 /* Find updated CS buffer */ 1484 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1485 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1486 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1487 if (!val) { 1488 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1489 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1490 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1491 } 1492 1493 if (val) { 1494 /* copy CS buffer */ 1495 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1496 sizeof(xcvr->rx_iec958.status)); 1497 for (i = 0; i < 6; i++) { 1498 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1499 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1500 bitrev32(val); 1501 } 1502 /* clear CS control register */ 1503 writel_relaxed(0, reg_ctrl); 1504 } 1505 } else { 1506 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0, 1507 (u32 *)&xcvr->rx_iec958.status[0]); 1508 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1, 1509 (u32 *)&xcvr->rx_iec958.status[4]); 1510 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2, 1511 (u32 *)&xcvr->rx_iec958.status[8]); 1512 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3, 1513 (u32 *)&xcvr->rx_iec958.status[12]); 1514 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4, 1515 (u32 *)&xcvr->rx_iec958.status[16]); 1516 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5, 1517 (u32 *)&xcvr->rx_iec958.status[20]); 1518 for (i = 0; i < 6; i++) { 1519 val = *(u32 *)(xcvr->rx_iec958.status + i * 4); 1520 *(u32 *)(xcvr->rx_iec958.status + i * 4) = 1521 bitrev32(val); 1522 } 1523 regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 1524 FSL_XCVR_RX_DPTH_CTRL_CSA); 1525 } 1526 } 1527 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1528 dev_dbg(dev, "Received new UD block\n"); 1529 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1530 } 1531 if (isr & FSL_XCVR_IRQ_MUTE) { 1532 dev_dbg(dev, "HW mute bit detected\n"); 1533 isr_clr |= FSL_XCVR_IRQ_MUTE; 1534 } 1535 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1536 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1537 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1538 } 1539 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1540 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1541 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1542 } 1543 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1544 dev_dbg(dev, "DMA read request\n"); 1545 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1546 } 1547 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1548 dev_dbg(dev, "DMA write request\n"); 1549 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1550 } 1551 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) { 1552 dev_dbg(dev, "CMDC status update\n"); 1553 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD; 1554 } 1555 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) { 1556 dev_dbg(dev, "Preamble mismatch\n"); 1557 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH; 1558 } 1559 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) { 1560 dev_dbg(dev, "Unexpected preamble received\n"); 1561 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC; 1562 } 1563 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) { 1564 dev_dbg(dev, "M/W preamble mismatch\n"); 1565 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH; 1566 } 1567 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) { 1568 dev_dbg(dev, "B preamble mismatch\n"); 1569 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH; 1570 } 1571 1572 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH | 1573 FSL_XCVR_IRQ_UNEXP_PRE_REC | 1574 FSL_XCVR_IRQ_M_W_PRE_MISMATCH | 1575 FSL_XCVR_IRQ_B_PRE_MISMATCH)) { 1576 schedule_work(&xcvr->work_rst); 1577 } 1578 1579 if (isr_clr) { 1580 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1581 return IRQ_HANDLED; 1582 } 1583 1584 return IRQ_NONE; 1585 } 1586 1587 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1588 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1589 .use_phy = true, 1590 .pll_ver = PLL_MX8MP, 1591 }; 1592 1593 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1594 .spdif_only = true, 1595 .use_edma = true, 1596 }; 1597 1598 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = { 1599 .fw_name = "imx/xcvr/xcvr-imx95.bin", 1600 .spdif_only = true, 1601 .use_phy = true, 1602 .use_edma = true, 1603 .pll_ver = PLL_MX95, 1604 }; 1605 1606 static const struct of_device_id fsl_xcvr_dt_ids[] = { 1607 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1608 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1609 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data}, 1610 { /* sentinel */ } 1611 }; 1612 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1613 1614 static int fsl_xcvr_probe(struct platform_device *pdev) 1615 { 1616 struct device *dev = &pdev->dev; 1617 struct fsl_xcvr *xcvr; 1618 struct resource *rx_res, *tx_res; 1619 void __iomem *regs; 1620 int ret, irq; 1621 1622 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1623 if (!xcvr) 1624 return -ENOMEM; 1625 1626 xcvr->pdev = pdev; 1627 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1628 1629 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1630 if (IS_ERR(xcvr->ipg_clk)) 1631 return dev_err_probe(dev, PTR_ERR(xcvr->ipg_clk), 1632 "failed to get ipg clock\n"); 1633 1634 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1635 if (IS_ERR(xcvr->phy_clk)) 1636 return dev_err_probe(dev, PTR_ERR(xcvr->phy_clk), 1637 "failed to get phy clock\n"); 1638 1639 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1640 if (IS_ERR(xcvr->spba_clk)) 1641 return dev_err_probe(dev, PTR_ERR(xcvr->spba_clk), 1642 "failed to get spba clock\n"); 1643 1644 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1645 if (IS_ERR(xcvr->pll_ipg_clk)) 1646 return dev_err_probe(dev, PTR_ERR(xcvr->pll_ipg_clk), 1647 "failed to get pll_ipg clock\n"); 1648 1649 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, 1650 &xcvr->pll11k_clk); 1651 1652 if (xcvr->soc_data->spdif_only) { 1653 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) 1654 xcvr->pll8k_clk = xcvr->phy_clk; 1655 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, 1656 &fsl_xcvr_spdif_rates_constr, 1657 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, 1658 xcvr->spdif_constr_rates_list); 1659 } 1660 1661 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1662 if (IS_ERR(xcvr->ram_addr)) 1663 return PTR_ERR(xcvr->ram_addr); 1664 1665 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1666 if (IS_ERR(regs)) 1667 return PTR_ERR(regs); 1668 1669 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1670 &fsl_xcvr_regmap_cfg); 1671 if (IS_ERR(xcvr->regmap)) 1672 return dev_err_probe(dev, PTR_ERR(xcvr->regmap), "failed to init XCVR regmap\n"); 1673 1674 if (xcvr->soc_data->use_phy) { 1675 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, 1676 &fsl_xcvr_regmap_phy_cfg); 1677 if (IS_ERR(xcvr->regmap_phy)) 1678 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_phy), 1679 "failed to init XCVR PHY regmap\n"); 1680 1681 switch (xcvr->soc_data->pll_ver) { 1682 case PLL_MX8MP: 1683 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1684 &fsl_xcvr_regmap_pllv0_cfg); 1685 if (IS_ERR(xcvr->regmap_pll)) 1686 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1687 "failed to init XCVR PLL regmap\n"); 1688 break; 1689 case PLL_MX95: 1690 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1691 &fsl_xcvr_regmap_pllv1_cfg); 1692 if (IS_ERR(xcvr->regmap_pll)) 1693 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1694 "failed to init XCVR PLL regmap\n"); 1695 break; 1696 default: 1697 return dev_err_probe(dev, -EINVAL, 1698 "Error for PLL version %d\n", 1699 xcvr->soc_data->pll_ver); 1700 } 1701 } 1702 1703 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1704 if (IS_ERR(xcvr->reset)) 1705 return dev_err_probe(dev, PTR_ERR(xcvr->reset), 1706 "failed to get XCVR reset control\n"); 1707 1708 /* get IRQs */ 1709 irq = platform_get_irq(pdev, 0); 1710 if (irq < 0) 1711 return irq; 1712 1713 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1714 if (ret) 1715 return dev_err_probe(dev, ret, "failed to claim IRQ0\n"); 1716 1717 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1718 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1719 if (!rx_res || !tx_res) 1720 return dev_err_probe(dev, -EINVAL, "could not find rxfifo or txfifo resource\n"); 1721 xcvr->dma_prms_rx.chan_name = "rx"; 1722 xcvr->dma_prms_tx.chan_name = "tx"; 1723 xcvr->dma_prms_rx.addr = rx_res->start; 1724 xcvr->dma_prms_tx.addr = tx_res->start; 1725 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1726 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1727 1728 platform_set_drvdata(pdev, xcvr); 1729 pm_runtime_enable(dev); 1730 regcache_cache_only(xcvr->regmap, true); 1731 if (xcvr->soc_data->use_phy) { 1732 regcache_cache_only(xcvr->regmap_phy, true); 1733 regcache_cache_only(xcvr->regmap_pll, true); 1734 } 1735 1736 /* 1737 * Register platform component before registering cpu dai for there 1738 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1739 */ 1740 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1741 if (ret) { 1742 pm_runtime_disable(dev); 1743 return dev_err_probe(dev, ret, "failed to pcm register\n"); 1744 } 1745 1746 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1747 &fsl_xcvr_dai, 1); 1748 if (ret) { 1749 pm_runtime_disable(dev); 1750 dev_err(dev, "failed to register component %s\n", 1751 fsl_xcvr_comp.name); 1752 } 1753 1754 INIT_WORK(&xcvr->work_rst, reset_rx_work); 1755 spin_lock_init(&xcvr->lock); 1756 return ret; 1757 } 1758 1759 static void fsl_xcvr_remove(struct platform_device *pdev) 1760 { 1761 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev); 1762 1763 cancel_work_sync(&xcvr->work_rst); 1764 pm_runtime_disable(&pdev->dev); 1765 } 1766 1767 static int fsl_xcvr_runtime_suspend(struct device *dev) 1768 { 1769 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1770 int ret; 1771 1772 if (!xcvr->soc_data->spdif_only && 1773 xcvr->mode == FSL_XCVR_MODE_EARC) { 1774 /* Assert M0+ reset */ 1775 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1776 FSL_XCVR_EXT_CTRL_CORE_RESET, 1777 FSL_XCVR_EXT_CTRL_CORE_RESET); 1778 if (ret < 0) 1779 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1780 } 1781 1782 regcache_cache_only(xcvr->regmap, true); 1783 if (xcvr->soc_data->use_phy) { 1784 regcache_cache_only(xcvr->regmap_phy, true); 1785 regcache_cache_only(xcvr->regmap_pll, true); 1786 } 1787 1788 clk_disable_unprepare(xcvr->spba_clk); 1789 clk_disable_unprepare(xcvr->phy_clk); 1790 clk_disable_unprepare(xcvr->pll_ipg_clk); 1791 clk_disable_unprepare(xcvr->ipg_clk); 1792 1793 return 0; 1794 } 1795 1796 static int fsl_xcvr_runtime_resume(struct device *dev) 1797 { 1798 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1799 int ret; 1800 1801 ret = reset_control_assert(xcvr->reset); 1802 if (ret < 0) { 1803 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1804 return ret; 1805 } 1806 1807 ret = clk_prepare_enable(xcvr->ipg_clk); 1808 if (ret) { 1809 dev_err(dev, "failed to start IPG clock.\n"); 1810 return ret; 1811 } 1812 1813 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1814 if (ret) { 1815 dev_err(dev, "failed to start PLL IPG clock.\n"); 1816 goto stop_ipg_clk; 1817 } 1818 1819 ret = clk_prepare_enable(xcvr->phy_clk); 1820 if (ret) { 1821 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1822 goto stop_pll_ipg_clk; 1823 } 1824 1825 ret = clk_prepare_enable(xcvr->spba_clk); 1826 if (ret) { 1827 dev_err(dev, "failed to start SPBA clock.\n"); 1828 goto stop_phy_clk; 1829 } 1830 1831 ret = reset_control_deassert(xcvr->reset); 1832 if (ret) { 1833 dev_err(dev, "failed to deassert M0+ reset.\n"); 1834 goto stop_spba_clk; 1835 } 1836 1837 regcache_cache_only(xcvr->regmap, false); 1838 regcache_mark_dirty(xcvr->regmap); 1839 ret = regcache_sync(xcvr->regmap); 1840 1841 if (ret) { 1842 dev_err(dev, "failed to sync regcache.\n"); 1843 goto stop_spba_clk; 1844 } 1845 1846 if (xcvr->soc_data->use_phy) { 1847 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 1848 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 1849 if (ret < 0) { 1850 dev_err(dev, "Error while release PHY reset: %d\n", ret); 1851 goto stop_spba_clk; 1852 } 1853 1854 regcache_cache_only(xcvr->regmap_phy, false); 1855 regcache_mark_dirty(xcvr->regmap_phy); 1856 ret = regcache_sync(xcvr->regmap_phy); 1857 if (ret) { 1858 dev_err(dev, "failed to sync phy regcache.\n"); 1859 goto stop_spba_clk; 1860 } 1861 1862 regcache_cache_only(xcvr->regmap_pll, false); 1863 regcache_mark_dirty(xcvr->regmap_pll); 1864 ret = regcache_sync(xcvr->regmap_pll); 1865 if (ret) { 1866 dev_err(dev, "failed to sync pll regcache.\n"); 1867 goto stop_spba_clk; 1868 } 1869 } 1870 1871 if (xcvr->soc_data->fw_name) { 1872 ret = fsl_xcvr_load_firmware(xcvr); 1873 if (ret) { 1874 dev_err(dev, "failed to load firmware.\n"); 1875 goto stop_spba_clk; 1876 } 1877 1878 /* Release M0+ reset */ 1879 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1880 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1881 if (ret < 0) { 1882 dev_err(dev, "M0+ core release failed: %d\n", ret); 1883 goto stop_spba_clk; 1884 } 1885 1886 /* Let M0+ core complete firmware initialization */ 1887 msleep(50); 1888 } 1889 1890 return 0; 1891 1892 stop_spba_clk: 1893 clk_disable_unprepare(xcvr->spba_clk); 1894 stop_phy_clk: 1895 clk_disable_unprepare(xcvr->phy_clk); 1896 stop_pll_ipg_clk: 1897 clk_disable_unprepare(xcvr->pll_ipg_clk); 1898 stop_ipg_clk: 1899 clk_disable_unprepare(xcvr->ipg_clk); 1900 1901 return ret; 1902 } 1903 1904 static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1905 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL) 1906 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1907 }; 1908 1909 static struct platform_driver fsl_xcvr_driver = { 1910 .probe = fsl_xcvr_probe, 1911 .driver = { 1912 .name = "fsl-xcvr", 1913 .pm = pm_ptr(&fsl_xcvr_pm_ops), 1914 .of_match_table = fsl_xcvr_dt_ids, 1915 }, 1916 .remove = fsl_xcvr_remove, 1917 }; 1918 module_platform_driver(fsl_xcvr_driver); 1919 1920 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1921 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1922 MODULE_LICENSE("GPL v2"); 1923