1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/net/ti-dp83867.h> 13 14#include "imx8mp.dtsi" 15 16/ { 17 model = "Gateworks Venice GW74xx i.MX8MP board"; 18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 19 20 aliases { 21 ethernet0 = &eqos; 22 ethernet1 = &fec; 23 ethernet2 = &lan1; 24 ethernet3 = &lan2; 25 ethernet4 = &lan3; 26 ethernet5 = &lan4; 27 ethernet6 = &lan5; 28 rtc0 = &gsc_rtc; 29 rtc1 = &snvs_rtc; 30 }; 31 32 chosen { 33 stdout-path = &uart2; 34 }; 35 36 memory@40000000 { 37 device_type = "memory"; 38 reg = <0x0 0x40000000 0 0x80000000>; 39 }; 40 41 connector { 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_usbcon1>; 44 compatible = "gpio-usb-b-connector", "usb-b-connector"; 45 type = "micro"; 46 label = "Type-C"; 47 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 48 49 port { 50 usb_dr_connector: endpoint { 51 remote-endpoint = <&usb3_dwc>; 52 }; 53 }; 54 }; 55 56 gpio-keys { 57 compatible = "gpio-keys"; 58 59 key-0 { 60 label = "user_pb"; 61 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 62 linux,code = <BTN_0>; 63 }; 64 65 key-1 { 66 label = "user_pb1x"; 67 linux,code = <BTN_1>; 68 interrupt-parent = <&gsc>; 69 interrupts = <0>; 70 }; 71 72 key-2 { 73 label = "key_erased"; 74 linux,code = <BTN_2>; 75 interrupt-parent = <&gsc>; 76 interrupts = <1>; 77 }; 78 79 key-3 { 80 label = "eeprom_wp"; 81 linux,code = <BTN_3>; 82 interrupt-parent = <&gsc>; 83 interrupts = <2>; 84 }; 85 86 key-4 { 87 label = "tamper"; 88 linux,code = <BTN_4>; 89 interrupt-parent = <&gsc>; 90 interrupts = <5>; 91 }; 92 93 key-5 { 94 label = "switch_hold"; 95 linux,code = <BTN_5>; 96 interrupt-parent = <&gsc>; 97 interrupts = <7>; 98 }; 99 }; 100 101 led-controller { 102 compatible = "gpio-leds"; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_gpio_leds>; 105 106 led-0 { 107 function = LED_FUNCTION_HEARTBEAT; 108 color = <LED_COLOR_ID_GREEN>; 109 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 110 default-state = "on"; 111 linux,default-trigger = "heartbeat"; 112 }; 113 114 led-1 { 115 function = LED_FUNCTION_STATUS; 116 color = <LED_COLOR_ID_RED>; 117 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 118 default-state = "off"; 119 }; 120 }; 121 122 pcie0_refclk: pcie0-refclk { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <100000000>; 126 }; 127 128 pps { 129 compatible = "pps-gpio"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pps>; 132 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 133 }; 134 135 reg_usb2_vbus: regulator-usb2 { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_reg_usb2>; 138 compatible = "regulator-fixed"; 139 regulator-name = "usb_usb2_vbus"; 140 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 141 enable-active-high; 142 regulator-min-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>; 144 }; 145 146 reg_can1_stby: regulator-can1-stby { 147 compatible = "regulator-fixed"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_reg_can1>; 150 regulator-name = "can1_stby"; 151 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 }; 155 156 reg_can2_stby: regulator-can2-stby { 157 compatible = "regulator-fixed"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_reg_can2>; 160 regulator-name = "can2_stby"; 161 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 }; 165 166 reg_wifi_en: regulator-wifi-en { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_reg_wifi>; 169 compatible = "regulator-fixed"; 170 regulator-name = "wl"; 171 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 172 startup-delay-us = <70000>; 173 enable-active-high; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177}; 178 179&A53_0 { 180 cpu-supply = <®_arm>; 181}; 182 183&A53_1 { 184 cpu-supply = <®_arm>; 185}; 186 187&A53_2 { 188 cpu-supply = <®_arm>; 189}; 190 191&A53_3 { 192 cpu-supply = <®_arm>; 193}; 194 195&ecspi1 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_spi1>; 198 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 199 status = "okay"; 200 201 tpm@0 { 202 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 203 reg = <0x0>; 204 spi-max-frequency = <25000000>; 205 }; 206}; 207 208/* off-board header */ 209&ecspi2 { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_spi2>; 212 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 213 status = "okay"; 214}; 215 216&eqos { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_eqos>; 219 phy-mode = "rgmii-id"; 220 phy-handle = <ðphy0>; 221 status = "okay"; 222 223 mdio { 224 compatible = "snps,dwmac-mdio"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 ethphy0: ethernet-phy@0 { 229 compatible = "ethernet-phy-ieee802.3-c22"; 230 reg = <0x0>; 231 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 232 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 233 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 234 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 235 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 236 237 leds { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 led@1 { 242 reg = <1>; 243 color = <LED_COLOR_ID_AMBER>; 244 function = LED_FUNCTION_LAN; 245 default-state = "keep"; 246 }; 247 248 led@2 { 249 reg = <2>; 250 color = <LED_COLOR_ID_GREEN>; 251 function = LED_FUNCTION_LAN; 252 default-state = "keep"; 253 }; 254 }; 255 }; 256 }; 257}; 258 259&fec { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_fec>; 262 phy-mode = "rgmii-id"; 263 local-mac-address = [00 00 00 00 00 00]; 264 status = "okay"; 265 266 fixed-link { 267 speed = <1000>; 268 full-duplex; 269 }; 270}; 271 272&flexcan1 { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_flexcan1>; 275 xceiver-supply = <®_can1_stby>; 276 status = "okay"; 277}; 278 279&flexcan2 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_flexcan2>; 282 xceiver-supply = <®_can2_stby>; 283 status = "okay"; 284}; 285 286&gpio1 { 287 gpio-line-names = 288 "", "", "", "", "", "", "", "", 289 "", "dio0", "", "dio1", "", "", "", "", 290 "", "", "", "", "", "", "", "", 291 "", "", "", "", "", "", "", ""; 292}; 293 294&gpio2 { 295 gpio-line-names = 296 "", "", "", "", "", "", "m2_pin20", "", 297 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", 298 "", "", "pcie2_wdis#", "", "", "", "", "", 299 "", "", "", "", "", "", "", ""; 300}; 301 302&gpio3 { 303 gpio-line-names = 304 "", "", "", "", "", "", "m2_rst", "", 305 "", "", "", "", "", "", "m2_wdis2#", "", 306 "", "", "", "", "", "", "", "", 307 "", "", "", "", "", "", "", ""; 308}; 309 310&gpio4 { 311 gpio-line-names = 312 "", "", "m2_off#", "", "", "", "", "", 313 "", "", "", "", "", "", "", "", 314 "", "", "m2_wdis1#", "", "", "", "", "", 315 "", "", "", "", "", "", "", "rs485_en"; 316}; 317 318&gpio5 { 319 gpio-line-names = 320 "rs485_hd", "rs485_term", "", "", "", "", "", "", 321 "", "", "", "", "", "", "", "", 322 "", "", "", "", "", "", "", "", 323 "", "", "", "", "", "", "", ""; 324}; 325 326&i2c1 { 327 clock-frequency = <100000>; 328 pinctrl-names = "default", "gpio"; 329 pinctrl-0 = <&pinctrl_i2c1>; 330 pinctrl-1 = <&pinctrl_i2c1_gpio>; 331 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 332 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 333 status = "okay"; 334 335 gsc: gsc@20 { 336 compatible = "gw,gsc"; 337 reg = <0x20>; 338 pinctrl-0 = <&pinctrl_gsc>; 339 interrupt-parent = <&gpio4>; 340 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 341 interrupt-controller; 342 #interrupt-cells = <1>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 adc { 347 compatible = "gw,gsc-adc"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 channel@6 { 352 gw,mode = <0>; 353 reg = <0x06>; 354 label = "temp"; 355 }; 356 357 channel@8 { 358 gw,mode = <3>; 359 reg = <0x08>; 360 label = "vdd_bat"; 361 }; 362 363 channel@16 { 364 gw,mode = <4>; 365 reg = <0x16>; 366 label = "fan_tach"; 367 }; 368 369 channel@82 { 370 gw,mode = <2>; 371 reg = <0x82>; 372 label = "vdd_adc1"; 373 gw,voltage-divider-ohms = <10000 10000>; 374 }; 375 376 channel@84 { 377 gw,mode = <2>; 378 reg = <0x84>; 379 label = "vdd_adc2"; 380 gw,voltage-divider-ohms = <10000 10000>; 381 }; 382 383 channel@86 { 384 gw,mode = <2>; 385 reg = <0x86>; 386 label = "vdd_vin"; 387 gw,voltage-divider-ohms = <22100 1000>; 388 }; 389 390 channel@88 { 391 gw,mode = <2>; 392 reg = <0x88>; 393 label = "vdd_3p3"; 394 gw,voltage-divider-ohms = <10000 10000>; 395 }; 396 397 channel@8c { 398 gw,mode = <2>; 399 reg = <0x8c>; 400 label = "vdd_2p5"; 401 gw,voltage-divider-ohms = <10000 10000>; 402 }; 403 404 channel@90 { 405 gw,mode = <2>; 406 reg = <0x90>; 407 label = "vdd_soc"; 408 }; 409 410 channel@92 { 411 gw,mode = <2>; 412 reg = <0x92>; 413 label = "vdd_arm"; 414 }; 415 416 channel@98 { 417 gw,mode = <2>; 418 reg = <0x98>; 419 label = "vdd_1p8"; 420 }; 421 422 channel@9a { 423 gw,mode = <2>; 424 reg = <0x9a>; 425 label = "vdd_1p2"; 426 }; 427 428 channel@9c { 429 gw,mode = <2>; 430 reg = <0x9c>; 431 label = "vdd_dram"; 432 }; 433 434 channel@9e { 435 gw,mode = <2>; 436 reg = <0x9e>; 437 label = "vdd_1p0"; 438 }; 439 440 channel@a2 { 441 gw,mode = <2>; 442 reg = <0xa2>; 443 label = "vdd_gsc"; 444 gw,voltage-divider-ohms = <10000 10000>; 445 }; 446 }; 447 448 fan-controller@a { 449 compatible = "gw,gsc-fan"; 450 reg = <0x0a>; 451 }; 452 }; 453 454 gpio: gpio@23 { 455 compatible = "nxp,pca9555"; 456 reg = <0x23>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-parent = <&gsc>; 460 interrupts = <4>; 461 }; 462 463 eeprom@50 { 464 compatible = "atmel,24c02"; 465 reg = <0x50>; 466 pagesize = <16>; 467 }; 468 469 eeprom@51 { 470 compatible = "atmel,24c02"; 471 reg = <0x51>; 472 pagesize = <16>; 473 }; 474 475 eeprom@52 { 476 compatible = "atmel,24c02"; 477 reg = <0x52>; 478 pagesize = <16>; 479 }; 480 481 eeprom@53 { 482 compatible = "atmel,24c02"; 483 reg = <0x53>; 484 pagesize = <16>; 485 }; 486 487 gsc_rtc: rtc@68 { 488 compatible = "dallas,ds1672"; 489 reg = <0x68>; 490 }; 491}; 492 493&i2c2 { 494 clock-frequency = <400000>; 495 pinctrl-names = "default", "gpio"; 496 pinctrl-0 = <&pinctrl_i2c2>; 497 pinctrl-1 = <&pinctrl_i2c2_gpio>; 498 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 499 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 500 status = "okay"; 501 502 accelerometer@19 { 503 compatible = "st,lis2de12"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_accel>; 506 reg = <0x19>; 507 st,drdy-int-pin = <1>; 508 interrupt-parent = <&gpio1>; 509 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 510 }; 511 512 switch: switch@5f { 513 compatible = "microchip,ksz9897"; 514 reg = <0x5f>; 515 pinctrl-0 = <&pinctrl_ksz>; 516 interrupt-parent = <&gpio4>; 517 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 518 519 ports { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 lan1: port@0 { 524 reg = <0>; 525 label = "lan1"; 526 phy-mode = "internal"; 527 local-mac-address = [00 00 00 00 00 00]; 528 }; 529 530 lan2: port@1 { 531 reg = <1>; 532 label = "lan2"; 533 phy-mode = "internal"; 534 local-mac-address = [00 00 00 00 00 00]; 535 }; 536 537 lan3: port@2 { 538 reg = <2>; 539 label = "lan3"; 540 phy-mode = "internal"; 541 local-mac-address = [00 00 00 00 00 00]; 542 }; 543 544 lan4: port@3 { 545 reg = <3>; 546 label = "lan4"; 547 phy-mode = "internal"; 548 local-mac-address = [00 00 00 00 00 00]; 549 }; 550 551 lan5: port@4 { 552 reg = <4>; 553 label = "lan5"; 554 phy-mode = "internal"; 555 local-mac-address = [00 00 00 00 00 00]; 556 }; 557 558 port@5 { 559 reg = <5>; 560 ethernet = <&fec>; 561 phy-mode = "rgmii-id"; 562 563 fixed-link { 564 speed = <1000>; 565 full-duplex; 566 }; 567 }; 568 }; 569 }; 570}; 571 572&i2c3 { 573 clock-frequency = <400000>; 574 pinctrl-names = "default", "gpio"; 575 pinctrl-0 = <&pinctrl_i2c3>; 576 pinctrl-1 = <&pinctrl_i2c3_gpio>; 577 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 578 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 579 status = "okay"; 580 581 pmic@25 { 582 compatible = "nxp,pca9450c"; 583 reg = <0x25>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_pmic>; 586 interrupt-parent = <&gpio3>; 587 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 588 589 regulators { 590 BUCK1 { 591 regulator-name = "BUCK1"; 592 regulator-min-microvolt = <720000>; 593 regulator-max-microvolt = <1000000>; 594 regulator-boot-on; 595 regulator-always-on; 596 regulator-ramp-delay = <3125>; 597 }; 598 599 reg_arm: BUCK2 { 600 regulator-name = "BUCK2"; 601 regulator-min-microvolt = <720000>; 602 regulator-max-microvolt = <1025000>; 603 regulator-boot-on; 604 regulator-always-on; 605 regulator-ramp-delay = <3125>; 606 nxp,dvs-run-voltage = <950000>; 607 nxp,dvs-standby-voltage = <850000>; 608 }; 609 610 BUCK4 { 611 regulator-name = "BUCK4"; 612 regulator-min-microvolt = <3000000>; 613 regulator-max-microvolt = <3600000>; 614 regulator-boot-on; 615 regulator-always-on; 616 }; 617 618 BUCK5 { 619 regulator-name = "BUCK5"; 620 regulator-min-microvolt = <1650000>; 621 regulator-max-microvolt = <1950000>; 622 regulator-boot-on; 623 regulator-always-on; 624 }; 625 626 BUCK6 { 627 regulator-name = "BUCK6"; 628 regulator-min-microvolt = <1045000>; 629 regulator-max-microvolt = <1155000>; 630 regulator-boot-on; 631 regulator-always-on; 632 }; 633 634 LDO1 { 635 regulator-name = "LDO1"; 636 regulator-min-microvolt = <1650000>; 637 regulator-max-microvolt = <1950000>; 638 regulator-boot-on; 639 regulator-always-on; 640 }; 641 642 LDO3 { 643 regulator-name = "LDO3"; 644 regulator-min-microvolt = <1710000>; 645 regulator-max-microvolt = <1890000>; 646 regulator-boot-on; 647 regulator-always-on; 648 }; 649 650 LDO5 { 651 regulator-name = "LDO5"; 652 regulator-min-microvolt = <1800000>; 653 regulator-max-microvolt = <3300000>; 654 regulator-boot-on; 655 regulator-always-on; 656 }; 657 }; 658 }; 659}; 660 661/* off-board header */ 662&i2c4 { 663 clock-frequency = <400000>; 664 pinctrl-names = "default", "gpio"; 665 pinctrl-0 = <&pinctrl_i2c4>; 666 pinctrl-1 = <&pinctrl_i2c4_gpio>; 667 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 668 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 669 status = "okay"; 670}; 671 672&pcie_phy { 673 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 674 fsl,clkreq-unsupported; 675 clocks = <&pcie0_refclk>; 676 clock-names = "ref"; 677 status = "okay"; 678}; 679 680&pcie { 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pinctrl_pcie0>; 683 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; 684 status = "okay"; 685}; 686 687/* GPS / off-board header */ 688&uart1 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_uart1>; 691 status = "okay"; 692}; 693 694/* RS232 console */ 695&uart2 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_uart2>; 698 status = "okay"; 699}; 700 701/* bluetooth HCI */ 702&uart3 { 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 705 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 706 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 707 status = "okay"; 708 709 bluetooth { 710 compatible = "brcm,bcm4330-bt"; 711 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; 712 }; 713}; 714 715&uart4 { 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_uart4>; 718 status = "okay"; 719}; 720 721/* USB1 - Type C front panel */ 722&usb3_0 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_usb1>; 725 fsl,over-current-active-low; 726 status = "okay"; 727}; 728 729&usb3_phy0 { 730 status = "okay"; 731}; 732 733&usb_dwc3_0 { 734 /* dual role is implemented but not a full featured OTG */ 735 adp-disable; 736 hnp-disable; 737 srp-disable; 738 dr_mode = "otg"; 739 usb-role-switch; 740 role-switch-default-mode = "peripheral"; 741 status = "okay"; 742 743 port { 744 usb3_dwc: endpoint { 745 remote-endpoint = <&usb_dr_connector>; 746 }; 747 }; 748}; 749 750/* USB2 - USB3.0 Hub */ 751&usb3_phy1 { 752 vbus-supply = <®_usb2_vbus>; 753 status = "okay"; 754}; 755 756&usb3_1 { 757 fsl,permanently-attached; 758 fsl,disable-port-power-control; 759 status = "okay"; 760}; 761 762&usb_dwc3_1 { 763 dr_mode = "host"; 764 status = "okay"; 765}; 766 767/* SDIO WiFi */ 768&usdhc1 { 769 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 770 pinctrl-0 = <&pinctrl_usdhc1>; 771 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 772 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 773 bus-width = <4>; 774 non-removable; 775 vmmc-supply = <®_wifi_en>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "okay"; 779 780 wifi@0 { 781 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 782 reg = <0>; 783 }; 784}; 785 786/* eMMC */ 787&usdhc3 { 788 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 789 assigned-clock-rates = <400000000>; 790 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 791 pinctrl-0 = <&pinctrl_usdhc3>; 792 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 793 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 794 bus-width = <8>; 795 non-removable; 796 status = "okay"; 797}; 798 799&wdog1 { 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_wdog>; 802 fsl,ext-reset-output; 803 status = "okay"; 804}; 805 806&iomuxc { 807 pinctrl-names = "default"; 808 pinctrl-0 = <&pinctrl_hog>; 809 810 pinctrl_hog: hoggrp { 811 fsl,pins = < 812 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 813 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 814 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ 815 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS1# */ 816 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ 817 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ 818 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ 819 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 820 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 821 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 822 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000150 /* M2KST_WDIS2# */ 823 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 824 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 825 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ 826 >; 827 }; 828 829 pinctrl_accel: accelgrp { 830 fsl,pins = < 831 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 832 >; 833 }; 834 835 pinctrl_eqos: eqosgrp { 836 fsl,pins = < 837 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 838 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 839 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 840 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 841 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 842 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 843 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 844 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 845 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 846 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 847 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 848 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 849 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 850 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 851 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ 852 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ 853 >; 854 }; 855 856 pinctrl_fec: fecgrp { 857 fsl,pins = < 858 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 859 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 860 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 861 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 862 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 863 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 864 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 865 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 866 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 867 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 868 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 869 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 870 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 871 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 872 >; 873 }; 874 875 pinctrl_flexcan1: flexcan1grp { 876 fsl,pins = < 877 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 878 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 879 >; 880 }; 881 882 pinctrl_flexcan2: flexcan2grp { 883 fsl,pins = < 884 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 885 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 886 >; 887 }; 888 889 pinctrl_gsc: gscgrp { 890 fsl,pins = < 891 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 892 >; 893 }; 894 895 pinctrl_i2c1: i2c1grp { 896 fsl,pins = < 897 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 898 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 899 >; 900 }; 901 902 pinctrl_i2c1_gpio: i2c1gpiogrp { 903 fsl,pins = < 904 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 905 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 906 >; 907 }; 908 909 pinctrl_i2c2: i2c2grp { 910 fsl,pins = < 911 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 912 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 913 >; 914 }; 915 916 pinctrl_i2c2_gpio: i2c2gpiogrp { 917 fsl,pins = < 918 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 919 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 920 >; 921 }; 922 923 pinctrl_i2c3: i2c3grp { 924 fsl,pins = < 925 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 926 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 927 >; 928 }; 929 930 pinctrl_i2c3_gpio: i2c3gpiogrp { 931 fsl,pins = < 932 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 933 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 934 >; 935 }; 936 937 pinctrl_i2c4: i2c4grp { 938 fsl,pins = < 939 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 940 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 941 >; 942 }; 943 944 pinctrl_i2c4_gpio: i2c4gpiogrp { 945 fsl,pins = < 946 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 947 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 948 >; 949 }; 950 951 pinctrl_ksz: kszgrp { 952 fsl,pins = < 953 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ 954 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ 955 >; 956 }; 957 958 pinctrl_gpio_leds: ledgrp { 959 fsl,pins = < 960 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 961 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 962 >; 963 }; 964 965 pinctrl_pcie0: pciegrp { 966 fsl,pins = < 967 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 968 >; 969 }; 970 971 pinctrl_pmic: pmicgrp { 972 fsl,pins = < 973 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 974 >; 975 }; 976 977 pinctrl_pps: ppsgrp { 978 fsl,pins = < 979 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 980 >; 981 }; 982 983 pinctrl_reg_can1: regcan1grp { 984 fsl,pins = < 985 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 986 >; 987 }; 988 989 pinctrl_reg_can2: regcan2grp { 990 fsl,pins = < 991 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 992 >; 993 }; 994 995 pinctrl_reg_usb2: regusb2grp { 996 fsl,pins = < 997 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 998 >; 999 }; 1000 1001 pinctrl_reg_wifi: regwifigrp { 1002 fsl,pins = < 1003 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 1004 >; 1005 }; 1006 1007 pinctrl_spi1: spi1grp { 1008 fsl,pins = < 1009 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 1010 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 1011 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 1012 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 1013 >; 1014 }; 1015 1016 pinctrl_spi2: spi2grp { 1017 fsl,pins = < 1018 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 1019 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 1020 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 1021 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 1022 >; 1023 }; 1024 1025 pinctrl_uart1: uart1grp { 1026 fsl,pins = < 1027 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 1028 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 1029 >; 1030 }; 1031 1032 pinctrl_uart2: uart2grp { 1033 fsl,pins = < 1034 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 1035 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 1036 >; 1037 }; 1038 1039 pinctrl_uart3: uart3grp { 1040 fsl,pins = < 1041 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 1042 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 1043 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 1044 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 1045 >; 1046 }; 1047 1048 pinctrl_uart3_gpio: uart3gpiogrp { 1049 fsl,pins = < 1050 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 1051 >; 1052 }; 1053 1054 pinctrl_uart4: uart4grp { 1055 fsl,pins = < 1056 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 1057 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 1058 >; 1059 }; 1060 1061 pinctrl_usb1: usb1grp { 1062 fsl,pins = < 1063 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 1064 >; 1065 }; 1066 1067 pinctrl_usbcon1: usb1congrp { 1068 fsl,pins = < 1069 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 1070 >; 1071 }; 1072 1073 pinctrl_usdhc1: usdhc1grp { 1074 fsl,pins = < 1075 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 1076 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 1077 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 1078 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 1079 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 1080 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 1081 >; 1082 }; 1083 1084 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1085 fsl,pins = < 1086 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 1087 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 1088 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 1089 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 1090 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 1091 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 1092 >; 1093 }; 1094 1095 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1096 fsl,pins = < 1097 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 1098 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 1099 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 1100 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 1101 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 1102 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 1103 >; 1104 }; 1105 1106 pinctrl_usdhc3: usdhc3grp { 1107 fsl,pins = < 1108 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1109 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1110 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1111 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1112 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1113 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1114 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1115 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1116 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1117 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1118 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1119 >; 1120 }; 1121 1122 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1123 fsl,pins = < 1124 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1125 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1126 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1127 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1128 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1129 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1130 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1131 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1132 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1133 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1134 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1135 >; 1136 }; 1137 1138 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1139 fsl,pins = < 1140 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1141 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1142 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1143 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1144 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1145 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1146 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1147 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1148 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1149 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1150 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1151 >; 1152 }; 1153 1154 pinctrl_wdog: wdoggrp { 1155 fsl,pins = < 1156 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1157 >; 1158 }; 1159}; 1160