1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2024 Realtek Corporation
3 */
4
5 #include <linux/usb.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "phy.h"
9 #include "rtw88xxa.h"
10 #include "mac.h"
11 #include "reg.h"
12 #include "sec.h"
13 #include "debug.h"
14 #include "bf.h"
15 #include "efuse.h"
16 #include "usb.h"
17
rtw88xxa_efuse_grant(struct rtw_dev * rtwdev,bool on)18 void rtw88xxa_efuse_grant(struct rtw_dev *rtwdev, bool on)
19 {
20 if (on) {
21 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
22
23 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
24 rtw_write16_set(rtwdev, REG_SYS_CLKR,
25 BIT_LOADER_CLK_EN | BIT_ANA8M);
26 } else {
27 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
28 }
29 }
30 EXPORT_SYMBOL(rtw88xxa_efuse_grant);
31
rtw8812a_read_amplifier_type(struct rtw_dev * rtwdev)32 static void rtw8812a_read_amplifier_type(struct rtw_dev *rtwdev)
33 {
34 struct rtw_efuse *efuse = &rtwdev->efuse;
35
36 efuse->ext_pa_2g = (efuse->pa_type_2g & BIT(5)) &&
37 (efuse->pa_type_2g & BIT(4));
38 efuse->ext_lna_2g = (efuse->lna_type_2g & BIT(7)) &&
39 (efuse->lna_type_2g & BIT(3));
40
41 efuse->ext_pa_5g = (efuse->pa_type_5g & BIT(1)) &&
42 (efuse->pa_type_5g & BIT(0));
43 efuse->ext_lna_5g = (efuse->lna_type_5g & BIT(7)) &&
44 (efuse->lna_type_5g & BIT(3));
45
46 /* For rtw_phy_cond2: */
47 if (efuse->ext_pa_2g) {
48 u8 ext_type_pa_2g_a = u8_get_bits(efuse->lna_type_2g, BIT(2));
49 u8 ext_type_pa_2g_b = u8_get_bits(efuse->lna_type_2g, BIT(6));
50
51 efuse->gpa_type = (ext_type_pa_2g_b << 2) | ext_type_pa_2g_a;
52 }
53
54 if (efuse->ext_pa_5g) {
55 u8 ext_type_pa_5g_a = u8_get_bits(efuse->lna_type_5g, BIT(2));
56 u8 ext_type_pa_5g_b = u8_get_bits(efuse->lna_type_5g, BIT(6));
57
58 efuse->apa_type = (ext_type_pa_5g_b << 2) | ext_type_pa_5g_a;
59 }
60
61 if (efuse->ext_lna_2g) {
62 u8 ext_type_lna_2g_a = u8_get_bits(efuse->lna_type_2g,
63 BIT(1) | BIT(0));
64 u8 ext_type_lna_2g_b = u8_get_bits(efuse->lna_type_2g,
65 BIT(5) | BIT(4));
66
67 efuse->glna_type = (ext_type_lna_2g_b << 2) | ext_type_lna_2g_a;
68 }
69
70 if (efuse->ext_lna_5g) {
71 u8 ext_type_lna_5g_a = u8_get_bits(efuse->lna_type_5g,
72 BIT(1) | BIT(0));
73 u8 ext_type_lna_5g_b = u8_get_bits(efuse->lna_type_5g,
74 BIT(5) | BIT(4));
75
76 efuse->alna_type = (ext_type_lna_5g_b << 2) | ext_type_lna_5g_a;
77 }
78 }
79
rtw8812a_read_rfe_type(struct rtw_dev * rtwdev,struct rtw88xxa_efuse * map)80 static void rtw8812a_read_rfe_type(struct rtw_dev *rtwdev,
81 struct rtw88xxa_efuse *map)
82 {
83 struct rtw_efuse *efuse = &rtwdev->efuse;
84
85 if (map->rfe_option == 0xff) {
86 if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
87 efuse->rfe_option = 0;
88 else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
89 efuse->rfe_option = 2;
90 else
91 efuse->rfe_option = 4;
92 } else if (map->rfe_option & BIT(7)) {
93 if (efuse->ext_lna_5g) {
94 if (efuse->ext_pa_5g) {
95 if (efuse->ext_lna_2g && efuse->ext_pa_2g)
96 efuse->rfe_option = 3;
97 else
98 efuse->rfe_option = 0;
99 } else {
100 efuse->rfe_option = 2;
101 }
102 } else {
103 efuse->rfe_option = 4;
104 }
105 } else {
106 efuse->rfe_option = map->rfe_option & 0x3f;
107
108 /* Due to other customer already use incorrect EFUSE map for
109 * their product. We need to add workaround to prevent to
110 * modify spec and notify all customer to revise the IC 0xca
111 * content.
112 */
113 if (efuse->rfe_option == 4 &&
114 (efuse->ext_pa_5g || efuse->ext_pa_2g ||
115 efuse->ext_lna_5g || efuse->ext_lna_2g)) {
116 if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
117 efuse->rfe_option = 0;
118 else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
119 efuse->rfe_option = 2;
120 }
121 }
122 }
123
rtw88xxa_read_usb_type(struct rtw_dev * rtwdev)124 static void rtw88xxa_read_usb_type(struct rtw_dev *rtwdev)
125 {
126 struct rtw_efuse *efuse = &rtwdev->efuse;
127 struct rtw_hal *hal = &rtwdev->hal;
128 u8 antenna = 0;
129 u8 wmode = 0;
130 u8 val8, i;
131
132 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
133 BIT(RTW_CHANNEL_WIDTH_40) |
134 BIT(RTW_CHANNEL_WIDTH_80);
135 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
136
137 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
138 efuse->hw_cap.nss = 1;
139 else
140 efuse->hw_cap.nss = 2;
141
142 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
143 goto print_hw_cap;
144
145 for (i = 0; i < 2; i++) {
146 rtw_read8_physical_efuse(rtwdev, 1019 - i, &val8);
147
148 antenna = u8_get_bits(val8, GENMASK(7, 5));
149 if (antenna)
150 break;
151 antenna = u8_get_bits(val8, GENMASK(3, 1));
152 if (antenna)
153 break;
154 }
155
156 for (i = 0; i < 2; i++) {
157 rtw_read8_physical_efuse(rtwdev, 1021 - i, &val8);
158
159 wmode = u8_get_bits(val8, GENMASK(3, 2));
160 if (wmode)
161 break;
162 }
163
164 if (antenna == 1) {
165 rtw_info(rtwdev, "This RTL8812AU says it is 1T1R.\n");
166
167 efuse->hw_cap.nss = 1;
168 hal->rf_type = RF_1T1R;
169 hal->rf_path_num = 1;
170 hal->rf_phy_num = 1;
171 hal->antenna_tx = BB_PATH_A;
172 hal->antenna_rx = BB_PATH_A;
173 } else {
174 /* Override rtw_chip_parameter_setup(). It detects 8812au as 1T1R. */
175 efuse->hw_cap.nss = 2;
176 hal->rf_type = RF_2T2R;
177 hal->rf_path_num = 2;
178 hal->rf_phy_num = 2;
179 hal->antenna_tx = BB_PATH_AB;
180 hal->antenna_rx = BB_PATH_AB;
181
182 if (antenna == 2 && wmode == 2) {
183 rtw_info(rtwdev, "This RTL8812AU says it can't do VHT.\n");
184
185 /* Can't be EFUSE_HW_CAP_IGNORE and can't be
186 * EFUSE_HW_CAP_PTCL_VHT, so make it 1.
187 */
188 efuse->hw_cap.ptcl = 1;
189 efuse->hw_cap.bw &= ~BIT(RTW_CHANNEL_WIDTH_80);
190 }
191 }
192
193 print_hw_cap:
194 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
195 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
196 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
197 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
198 }
199
rtw88xxa_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)200 int rtw88xxa_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
201 {
202 const struct rtw_chip_info *chip = rtwdev->chip;
203 struct rtw_efuse *efuse = &rtwdev->efuse;
204 struct rtw88xxa_efuse *map;
205 int i;
206
207 if (chip->id == RTW_CHIP_TYPE_8812A)
208 rtwdev->hal.cut_version += 1;
209
210 if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
211 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
212 log_map, chip->log_efuse_size, true);
213
214 map = (struct rtw88xxa_efuse *)log_map;
215
216 efuse->rf_board_option = map->rf_board_option;
217 efuse->crystal_cap = map->xtal_k;
218 if (efuse->crystal_cap == 0xff)
219 efuse->crystal_cap = 0x20;
220 efuse->pa_type_2g = map->pa_type;
221 efuse->pa_type_5g = map->pa_type;
222 efuse->lna_type_2g = map->lna_type_2g;
223 efuse->lna_type_5g = map->lna_type_5g;
224 if (chip->id == RTW_CHIP_TYPE_8812A) {
225 rtw8812a_read_amplifier_type(rtwdev);
226 rtw8812a_read_rfe_type(rtwdev, map);
227
228 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(1));
229 }
230 efuse->channel_plan = map->channel_plan;
231 efuse->country_code[0] = map->country_code[0];
232 efuse->country_code[1] = map->country_code[1];
233 efuse->bt_setting = map->rf_bt_setting;
234 efuse->regd = map->rf_board_option & 0x7;
235 efuse->thermal_meter[0] = map->thermal_meter;
236 efuse->thermal_meter[1] = map->thermal_meter;
237 efuse->thermal_meter_k = map->thermal_meter;
238 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
239 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
240
241 rtw88xxa_read_usb_type(rtwdev);
242
243 if (chip->id == RTW_CHIP_TYPE_8821A)
244 efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
245 BIT_BT_FUNC_EN);
246 else
247 efuse->btcoex = (map->rf_board_option & 0xe0) == 0x20;
248 efuse->share_ant = !!(efuse->bt_setting & BIT(0));
249
250 /* No antenna diversity because it's disabled in the vendor driver */
251 efuse->ant_div_cfg = 0;
252
253 efuse->ant_div_type = map->rf_antenna_option;
254 if (efuse->ant_div_type == 0xff)
255 efuse->ant_div_type = 0x3;
256
257 for (i = 0; i < 4; i++)
258 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
259
260 switch (rtw_hci_type(rtwdev)) {
261 case RTW_HCI_TYPE_USB:
262 if (chip->id == RTW_CHIP_TYPE_8821A)
263 ether_addr_copy(efuse->addr, map->rtw8821au.mac_addr);
264 else
265 ether_addr_copy(efuse->addr, map->rtw8812au.mac_addr);
266 break;
267 case RTW_HCI_TYPE_PCIE:
268 case RTW_HCI_TYPE_SDIO:
269 default:
270 /* unsupported now */
271 return -EOPNOTSUPP;
272 }
273
274 return 0;
275 }
276 EXPORT_SYMBOL(rtw88xxa_read_efuse);
277
rtw88xxa_reset_8051(struct rtw_dev * rtwdev)278 static void rtw88xxa_reset_8051(struct rtw_dev *rtwdev)
279 {
280 const struct rtw_chip_info *chip = rtwdev->chip;
281 u8 val8;
282
283 /* Reset MCU IO Wrapper */
284 rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
285 if (chip->id == RTW_CHIP_TYPE_8812A)
286 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(3));
287 else
288 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(0));
289
290 val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN + 1);
291 rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 & ~BIT(2));
292
293 /* Enable MCU IO Wrapper */
294 rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
295 if (chip->id == RTW_CHIP_TYPE_8812A)
296 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(3));
297 else
298 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(0));
299
300 rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 | BIT(2));
301 }
302
303 /* A lightweight deinit function */
rtw88xxau_hw_reset(struct rtw_dev * rtwdev)304 static void rtw88xxau_hw_reset(struct rtw_dev *rtwdev)
305 {
306 u8 val8;
307
308 if (!(rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL))
309 return;
310
311 rtw88xxa_reset_8051(rtwdev);
312 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
313
314 /* before BB reset should do clock gated */
315 rtw_write32_set(rtwdev, REG_FPGA0_XCD_RF_PARA, BIT(6));
316
317 /* reset BB */
318 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN, BIT(0) | BIT(1));
319
320 /* reset RF */
321 rtw_write8(rtwdev, REG_RF_CTRL, 0);
322
323 /* reset TRX path */
324 rtw_write16(rtwdev, REG_CR, 0);
325
326 /* reset MAC, reg0x5[1], auto FSM off */
327 rtw_write8_set(rtwdev, REG_APS_FSMCO + 1, APS_FSMCO_MAC_OFF >> 8);
328
329 /* check if reg0x5[1] auto cleared */
330 if (read_poll_timeout_atomic(rtw_read8, val8,
331 !(val8 & (APS_FSMCO_MAC_OFF >> 8)),
332 1, 5000, false,
333 rtwdev, REG_APS_FSMCO + 1))
334 rtw_err(rtwdev, "%s: timed out waiting for 0x5[1]\n", __func__);
335
336 /* reg0x5[0], auto FSM on */
337 val8 |= APS_FSMCO_MAC_ENABLE >> 8;
338 rtw_write8(rtwdev, REG_APS_FSMCO + 1, val8);
339
340 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
341 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
342 }
343
rtw88xxau_init_power_on(struct rtw_dev * rtwdev)344 static int rtw88xxau_init_power_on(struct rtw_dev *rtwdev)
345 {
346 const struct rtw_chip_info *chip = rtwdev->chip;
347 u16 val16;
348 int ret;
349
350 ret = rtw_pwr_seq_parser(rtwdev, chip->pwr_on_seq);
351 if (ret) {
352 rtw_err(rtwdev, "power on flow failed\n");
353 return ret;
354 }
355
356 rtw_write16(rtwdev, REG_CR, 0);
357 val16 = BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN |
358 BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN |
359 BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN;
360 rtw_write16_set(rtwdev, REG_CR, val16);
361
362 if (chip->id == RTW_CHIP_TYPE_8821A) {
363 if (rtw_read8(rtwdev, REG_SYS_CFG1 + 3) & BIT(0))
364 rtw_write8_set(rtwdev, REG_LDO_SWR_CTRL, BIT(6));
365 }
366
367 return ret;
368 }
369
rtw88xxa_llt_write(struct rtw_dev * rtwdev,u32 address,u32 data)370 static int rtw88xxa_llt_write(struct rtw_dev *rtwdev, u32 address, u32 data)
371 {
372 u32 value = BIT_LLT_WRITE_ACCESS | (address << 8) | data;
373 int count = 0;
374
375 rtw_write32(rtwdev, REG_LLT_INIT, value);
376
377 do {
378 if (!rtw_read32_mask(rtwdev, REG_LLT_INIT, BIT(31) | BIT(30)))
379 break;
380
381 if (count > 20) {
382 rtw_err(rtwdev, "Failed to poll write LLT done at %d!\n",
383 address);
384 return -EBUSY;
385 }
386 } while (++count);
387
388 return 0;
389 }
390
rtw88xxa_llt_init(struct rtw_dev * rtwdev,u32 boundary)391 static int rtw88xxa_llt_init(struct rtw_dev *rtwdev, u32 boundary)
392 {
393 u32 last_entry = 255;
394 int status = 0;
395 u32 i;
396
397 for (i = 0; i < boundary - 1; i++) {
398 status = rtw88xxa_llt_write(rtwdev, i, i + 1);
399 if (status)
400 return status;
401 }
402
403 status = rtw88xxa_llt_write(rtwdev, boundary - 1, 0xFF);
404 if (status)
405 return status;
406
407 for (i = boundary; i < last_entry; i++) {
408 status = rtw88xxa_llt_write(rtwdev, i, i + 1);
409 if (status)
410 return status;
411 }
412
413 status = rtw88xxa_llt_write(rtwdev, last_entry, boundary);
414
415 return status;
416 }
417
rtw88xxau_init_queue_reserved_page(struct rtw_dev * rtwdev)418 static void rtw88xxau_init_queue_reserved_page(struct rtw_dev *rtwdev)
419 {
420 const struct rtw_chip_info *chip = rtwdev->chip;
421 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
422 const struct rtw_page_table *pg_tbl = NULL;
423 u16 pubq_num;
424 u32 val32;
425
426 switch (rtw_hci_type(rtwdev)) {
427 case RTW_HCI_TYPE_PCIE:
428 pg_tbl = &chip->page_table[1];
429 break;
430 case RTW_HCI_TYPE_USB:
431 if (rtwdev->hci.bulkout_num == 2)
432 pg_tbl = &chip->page_table[2];
433 else if (rtwdev->hci.bulkout_num == 3)
434 pg_tbl = &chip->page_table[3];
435 else if (rtwdev->hci.bulkout_num == 4)
436 pg_tbl = &chip->page_table[4];
437 break;
438 case RTW_HCI_TYPE_SDIO:
439 pg_tbl = &chip->page_table[0];
440 break;
441 default:
442 break;
443 }
444
445 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
446 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
447
448 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
449 rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
450
451 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
452 rtw_write32(rtwdev, REG_RQPN, val32);
453 }
454
rtw88xxau_init_tx_buffer_boundary(struct rtw_dev * rtwdev)455 static void rtw88xxau_init_tx_buffer_boundary(struct rtw_dev *rtwdev)
456 {
457 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
458
459 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
460 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
461 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
462 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
463 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
464 }
465
rtw88xxau_init_queue_priority(struct rtw_dev * rtwdev)466 static int rtw88xxau_init_queue_priority(struct rtw_dev *rtwdev)
467 {
468 const struct rtw_chip_info *chip = rtwdev->chip;
469 u8 bulkout_num = rtwdev->hci.bulkout_num;
470 const struct rtw_rqpn *rqpn = NULL;
471 u16 txdma_pq_map;
472
473 switch (rtw_hci_type(rtwdev)) {
474 case RTW_HCI_TYPE_PCIE:
475 rqpn = &chip->rqpn_table[1];
476 break;
477 case RTW_HCI_TYPE_USB:
478 if (bulkout_num == 2)
479 rqpn = &chip->rqpn_table[2];
480 else if (bulkout_num == 3)
481 rqpn = &chip->rqpn_table[3];
482 else if (bulkout_num == 4)
483 rqpn = &chip->rqpn_table[4];
484 else
485 return -EINVAL;
486 break;
487 case RTW_HCI_TYPE_SDIO:
488 rqpn = &chip->rqpn_table[0];
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 rtwdev->fifo.rqpn = rqpn;
495
496 txdma_pq_map = rtw_read16(rtwdev, REG_TXDMA_PQ_MAP) & 0x7;
497 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
498 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
499 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
500 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
501 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
502 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
503 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
504
505 /* Packet in Hi Queue Tx immediately (No constraint for ATIM Period). */
506 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && bulkout_num == 4)
507 rtw_write8(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
508
509 return 0;
510 }
511
rtw88xxa_init_wmac_setting(struct rtw_dev * rtwdev)512 static void rtw88xxa_init_wmac_setting(struct rtw_dev *rtwdev)
513 {
514 rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
515 rtwdev->hal.rxfltmap1 = 0x0400;
516 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
517 rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
518
519 rtw_write32(rtwdev, REG_MAR, 0xffffffff);
520 rtw_write32(rtwdev, REG_MAR + 4, 0xffffffff);
521 }
522
rtw88xxa_init_adaptive_ctrl(struct rtw_dev * rtwdev)523 static void rtw88xxa_init_adaptive_ctrl(struct rtw_dev *rtwdev)
524 {
525 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xffff1);
526 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
527 }
528
rtw88xxa_init_edca(struct rtw_dev * rtwdev)529 static void rtw88xxa_init_edca(struct rtw_dev *rtwdev)
530 {
531 rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
532 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
533
534 rtw_write16(rtwdev, REG_SIFS, 0x100a);
535 rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
536
537 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
538 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
539 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
540 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
541
542 rtw_write8(rtwdev, REG_USTIME_TSF, 0x50);
543 rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50);
544 }
545
rtw88xxau_tx_aggregation(struct rtw_dev * rtwdev)546 static void rtw88xxau_tx_aggregation(struct rtw_dev *rtwdev)
547 {
548 const struct rtw_chip_info *chip = rtwdev->chip;
549
550 rtw_write32_mask(rtwdev, REG_DWBCN0_CTRL, 0xf0,
551 chip->usb_tx_agg_desc_num);
552
553 if (chip->id == RTW_CHIP_TYPE_8821A)
554 rtw_write8(rtwdev, REG_DWBCN1_CTRL,
555 chip->usb_tx_agg_desc_num << 1);
556 }
557
rtw88xxa_init_beacon_parameters(struct rtw_dev * rtwdev)558 static void rtw88xxa_init_beacon_parameters(struct rtw_dev *rtwdev)
559 {
560 u16 val16;
561
562 val16 = (BIT_DIS_TSF_UDT << 8) | BIT_DIS_TSF_UDT;
563 if (rtwdev->efuse.btcoex)
564 val16 |= BIT_EN_BCN_FUNCTION;
565 rtw_write16(rtwdev, REG_BCN_CTRL, val16);
566
567 rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
568 rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
569 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
570 rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
571 }
572
rtw88xxa_phy_bb_config(struct rtw_dev * rtwdev)573 static void rtw88xxa_phy_bb_config(struct rtw_dev *rtwdev)
574 {
575 u8 val8, crystal_cap;
576
577 /* power on BB/RF domain */
578 val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
579 val8 |= BIT_FEN_USBA;
580 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
581
582 /* toggle BB reset */
583 val8 |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
584 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
585
586 rtw_write8(rtwdev, REG_RF_CTRL,
587 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
588 rtw_write8(rtwdev, REG_RF_B_CTRL,
589 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
590
591 rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
592 rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
593
594 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
595 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
596 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x7FF80000,
597 crystal_cap | (crystal_cap << 6));
598 else
599 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x00FFF000,
600 crystal_cap | (crystal_cap << 6));
601 }
602
rtw88xxa_phy_rf_config(struct rtw_dev * rtwdev)603 static void rtw88xxa_phy_rf_config(struct rtw_dev *rtwdev)
604 {
605 u8 rf_path;
606
607 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
608 rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
609 }
610
rtw8812a_config_1t(struct rtw_dev * rtwdev)611 static void rtw8812a_config_1t(struct rtw_dev *rtwdev)
612 {
613 /* BB OFDM RX Path_A */
614 rtw_write32_mask(rtwdev, REG_RXPSEL, 0xff, 0x11);
615
616 /* BB OFDM TX Path_A */
617 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKLWORD, 0x1111);
618
619 /* BB CCK R/Rx Path_A */
620 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0c000000, 0x0);
621
622 /* MCS support */
623 rtw_write32_mask(rtwdev, REG_RX_MCS_LIMIT, 0xc0000060, 0x4);
624
625 /* RF Path_B HSSI OFF */
626 rtw_write32_mask(rtwdev, REG_3WIRE_SWB, 0xf, 0x4);
627
628 /* RF Path_B Power Down */
629 rtw_write32_mask(rtwdev, REG_LSSI_WRITE_B, MASKDWORD, 0);
630
631 /* ADDA Path_B OFF */
632 rtw_write32_mask(rtwdev, REG_AFE_PWR1_B, MASKDWORD, 0);
633 rtw_write32_mask(rtwdev, REG_AFE_PWR2_B, MASKDWORD, 0);
634 }
635
636 static const u32 rtw88xxa_txscale_tbl[] = {
637 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
638 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
639 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
640 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
641 };
642
rtw88xxa_get_bb_swing(struct rtw_dev * rtwdev,u8 band,u8 path)643 static u32 rtw88xxa_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 path)
644 {
645 static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
646 struct rtw_efuse *efuse = &rtwdev->efuse;
647 u8 tx_bb_swing;
648
649 if (band == RTW_BAND_2G)
650 tx_bb_swing = efuse->tx_bb_swing_setting_2g;
651 else
652 tx_bb_swing = efuse->tx_bb_swing_setting_5g;
653
654 if (path == RF_PATH_B)
655 tx_bb_swing >>= 2;
656 tx_bb_swing &= 0x3;
657
658 return swing2setting[tx_bb_swing];
659 }
660
rtw88xxa_get_swing_index(struct rtw_dev * rtwdev)661 static u8 rtw88xxa_get_swing_index(struct rtw_dev *rtwdev)
662 {
663 u32 swing, table_value;
664 u8 i;
665
666 swing = rtw88xxa_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
667 RF_PATH_A);
668
669 for (i = 0; i < ARRAY_SIZE(rtw88xxa_txscale_tbl); i++) {
670 table_value = rtw88xxa_txscale_tbl[i];
671 if (swing == table_value)
672 return i;
673 }
674
675 return 24;
676 }
677
rtw88xxa_pwrtrack_init(struct rtw_dev * rtwdev)678 static void rtw88xxa_pwrtrack_init(struct rtw_dev *rtwdev)
679 {
680 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
681 u8 path;
682
683 dm_info->default_ofdm_index = rtw88xxa_get_swing_index(rtwdev);
684
685 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
686 dm_info->default_cck_index = 0;
687 else
688 dm_info->default_cck_index = 24;
689
690 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
691 ewma_thermal_init(&dm_info->avg_thermal[path]);
692 dm_info->delta_power_index[path] = 0;
693 dm_info->delta_power_index_last[path] = 0;
694 }
695
696 dm_info->pwr_trk_triggered = false;
697 dm_info->pwr_trk_init_trigger = true;
698 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
699 }
700
rtw88xxa_power_off(struct rtw_dev * rtwdev,const struct rtw_pwr_seq_cmd * const * enter_lps_flow)701 void rtw88xxa_power_off(struct rtw_dev *rtwdev,
702 const struct rtw_pwr_seq_cmd *const *enter_lps_flow)
703 {
704 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
705 enum usb_device_speed speed = rtwusb->udev->speed;
706 u16 ori_fsmc0;
707 u8 reg_cr;
708
709 reg_cr = rtw_read8(rtwdev, REG_CR);
710
711 /* Already powered off */
712 if (reg_cr == 0 || reg_cr == 0xEA)
713 return;
714
715 rtw_hci_stop(rtwdev);
716
717 if (!rtwdev->efuse.btcoex)
718 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
719
720 /* set Reg 0xf008[3:4] to 2'11 to enable U1/U2 Mode in USB3.0. */
721 if (speed == USB_SPEED_SUPER)
722 rtw_write8_set(rtwdev, REG_USB_MOD, 0x18);
723
724 rtw_write32(rtwdev, REG_HISR0, 0xffffffff);
725 rtw_write32(rtwdev, REG_HISR1, 0xffffffff);
726 rtw_write32(rtwdev, REG_HIMR0, 0);
727 rtw_write32(rtwdev, REG_HIMR1, 0);
728
729 if (rtwdev->efuse.btcoex)
730 rtw_coex_power_off_setting(rtwdev);
731
732 ori_fsmc0 = rtw_read16(rtwdev, REG_APS_FSMCO);
733 rtw_write16(rtwdev, REG_APS_FSMCO, ori_fsmc0 & ~APS_FSMCO_HW_POWERDOWN);
734
735 /* Stop Tx Report Timer. */
736 rtw_write8_clr(rtwdev, REG_TX_RPT_CTRL, BIT(1));
737
738 /* Stop Rx */
739 rtw_write8(rtwdev, REG_CR, 0);
740
741 rtw_pwr_seq_parser(rtwdev, enter_lps_flow);
742
743 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL)
744 rtw88xxa_reset_8051(rtwdev);
745
746 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(2));
747 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0);
748
749 rtw_pwr_seq_parser(rtwdev, rtwdev->chip->pwr_off_seq);
750
751 if (ori_fsmc0 & APS_FSMCO_HW_POWERDOWN)
752 rtw_write16_set(rtwdev, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN);
753
754 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
755 }
756 EXPORT_SYMBOL(rtw88xxa_power_off);
757
rtw88xxa_set_channel_bb_swing(struct rtw_dev * rtwdev,u8 band)758 static void rtw88xxa_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
759 {
760 rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
761 rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_A));
762 rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
763 rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_B));
764 rtw88xxa_pwrtrack_init(rtwdev);
765 }
766
rtw8821a_set_ext_band_switch(struct rtw_dev * rtwdev,u8 band)767 static void rtw8821a_set_ext_band_switch(struct rtw_dev *rtwdev, u8 band)
768 {
769 rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN, 0);
770 rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL, 1);
771 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf, 7);
772 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf0, 7);
773
774 if (band == RTW_BAND_2G)
775 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 1);
776 else
777 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 2);
778 }
779
rtw8821a_phy_set_rfe_reg_24g(struct rtw_dev * rtwdev)780 static void rtw8821a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
781 {
782 struct rtw_efuse *efuse = &rtwdev->efuse;
783
784 /* Turn off RF PA and LNA */
785
786 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
787 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x7);
788 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
789 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x7);
790
791 if (efuse->ext_lna_2g) {
792 /* Turn on 2.4G External LNA */
793 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 1);
794 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
795 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x2);
796 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x2);
797 } else {
798 /* Bypass 2.4G External LNA */
799 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
800 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
801 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
802 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
803 }
804 }
805
rtw8821a_phy_set_rfe_reg_5g(struct rtw_dev * rtwdev)806 static void rtw8821a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
807 {
808 /* Turn ON RF PA and LNA */
809
810 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
811 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x5);
812 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
813 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x4);
814
815 /* Bypass 2.4G External LNA */
816 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
817 rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
818 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
819 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
820 }
821
rtw8812a_phy_set_rfe_reg_24g(struct rtw_dev * rtwdev)822 static void rtw8812a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
823 {
824 switch (rtwdev->efuse.rfe_option) {
825 case 0:
826 case 2:
827 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
828 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
829 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
830 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
831 break;
832 case 1:
833 if (rtwdev->efuse.btcoex) {
834 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x777777);
835 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
836 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
837 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
838 } else {
839 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
840 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
841 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
842 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
843 }
844 break;
845 case 3:
846 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337770);
847 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337770);
848 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
849 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
850 rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
851 break;
852 case 4:
853 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
854 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
855 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x001);
856 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x001);
857 break;
858 case 5:
859 rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x77);
860 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
861 rtw_write8_clr(rtwdev, REG_RFE_INV_A + 3, BIT(0));
862 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
863 break;
864 case 6:
865 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07772770);
866 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07772770);
867 rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
868 rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
869 break;
870 default:
871 break;
872 }
873 }
874
rtw8812a_phy_set_rfe_reg_5g(struct rtw_dev * rtwdev)875 static void rtw8812a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
876 {
877 switch (rtwdev->efuse.rfe_option) {
878 case 0:
879 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
880 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
881 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
882 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
883 break;
884 case 1:
885 if (rtwdev->efuse.btcoex) {
886 rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x337717);
887 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
888 rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
889 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
890 } else {
891 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
892 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
893 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
894 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
895 }
896 break;
897 case 2:
898 case 4:
899 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337777);
900 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
901 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
902 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
903 break;
904 case 3:
905 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337717);
906 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337717);
907 rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
908 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
909 rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
910 break;
911 case 5:
912 rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x33);
913 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
914 rtw_write8_set(rtwdev, REG_RFE_INV_A + 3, BIT(0));
915 rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
916 break;
917 case 6:
918 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07737717);
919 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07737717);
920 rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
921 rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
922 break;
923 default:
924 break;
925 }
926 }
927
rtw88xxa_switch_band(struct rtw_dev * rtwdev,u8 new_band,u8 bw)928 static void rtw88xxa_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
929 {
930 const struct rtw_chip_info *chip = rtwdev->chip;
931 u16 basic_rates, reg_41a;
932
933 /* 8811au one antenna module doesn't support antenna div, so driver must
934 * control antenna band, otherwise one of the band will have issue
935 */
936 if (chip->id == RTW_CHIP_TYPE_8821A && !rtwdev->efuse.btcoex &&
937 rtwdev->efuse.ant_div_cfg == 0)
938 rtw8821a_set_ext_band_switch(rtwdev, new_band);
939
940 if (new_band == RTW_BAND_2G) {
941 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
942
943 if (chip->id == RTW_CHIP_TYPE_8821A) {
944 rtw8821a_phy_set_rfe_reg_24g(rtwdev);
945
946 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0);
947 } else {
948 rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x1);
949 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x17);
950
951 if (bw == RTW_CHANNEL_WIDTH_20 &&
952 rtwdev->hal.rf_type == RF_1T1R &&
953 !rtwdev->efuse.ext_lna_2g)
954 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x02);
955 else
956 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
957
958 rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 0);
959
960 rtw8812a_phy_set_rfe_reg_24g(rtwdev);
961 }
962
963 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x1);
964 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x1);
965
966 basic_rates = BIT(DESC_RATE1M) | BIT(DESC_RATE2M) |
967 BIT(DESC_RATE5_5M) | BIT(DESC_RATE11M) |
968 BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
969 BIT(DESC_RATE24M);
970 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);
971
972 rtw_write8_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
973 } else { /* RTW_BAND_5G */
974 if (chip->id == RTW_CHIP_TYPE_8821A)
975 rtw8821a_phy_set_rfe_reg_5g(rtwdev);
976
977 rtw_write8_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
978
979 read_poll_timeout_atomic(rtw_read16, reg_41a, (reg_41a & 0x30) == 0x30,
980 50, 2500, false, rtwdev, REG_TXPKT_EMPTY);
981
982 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
983
984 if (chip->id == RTW_CHIP_TYPE_8821A) {
985 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 1);
986 } else {
987 rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x2);
988 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x15);
989 rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
990
991 rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 1);
992
993 rtw8812a_phy_set_rfe_reg_5g(rtwdev);
994 }
995
996 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0);
997 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
998
999 basic_rates = BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
1000 BIT(DESC_RATE24M);
1001 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);
1002 }
1003
1004 rtw88xxa_set_channel_bb_swing(rtwdev, new_band);
1005 }
1006
rtw88xxa_power_on(struct rtw_dev * rtwdev)1007 int rtw88xxa_power_on(struct rtw_dev *rtwdev)
1008 {
1009 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
1010 const struct rtw_chip_info *chip = rtwdev->chip;
1011 struct rtw_efuse *efuse = &rtwdev->efuse;
1012 struct rtw_hal *hal = &rtwdev->hal;
1013 int ret;
1014
1015 if (test_bit(RTW_FLAG_POWERON, rtwdev->flags))
1016 return 0;
1017
1018 /* Override rtw_chip_efuse_info_setup() */
1019 if (chip->id == RTW_CHIP_TYPE_8821A)
1020 efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
1021 BIT_BT_FUNC_EN);
1022
1023 /* Override rtw_chip_efuse_info_setup() */
1024 if (chip->id == RTW_CHIP_TYPE_8812A)
1025 rtw8812a_read_amplifier_type(rtwdev);
1026
1027 ret = rtw_hci_setup(rtwdev);
1028 if (ret) {
1029 rtw_err(rtwdev, "failed to setup hci\n");
1030 goto err;
1031 }
1032
1033 /* Revise for U2/U3 switch we can not update RF-A/B reset.
1034 * Reset after MAC power on to prevent RF R/W error.
1035 * Is it a right method?
1036 */
1037 if (chip->id == RTW_CHIP_TYPE_8812A) {
1038 rtw_write8(rtwdev, REG_RF_CTRL, 5);
1039 rtw_write8(rtwdev, REG_RF_CTRL, 7);
1040 rtw_write8(rtwdev, REG_RF_B_CTRL, 5);
1041 rtw_write8(rtwdev, REG_RF_B_CTRL, 7);
1042 }
1043
1044 /* If HW didn't go through a complete de-initial procedure,
1045 * it probably occurs some problem for double initial
1046 * procedure.
1047 */
1048 rtw88xxau_hw_reset(rtwdev);
1049
1050 ret = rtw88xxau_init_power_on(rtwdev);
1051 if (ret) {
1052 rtw_err(rtwdev, "failed to power on\n");
1053 goto err;
1054 }
1055
1056 ret = rtw_set_trx_fifo_info(rtwdev);
1057 if (ret) {
1058 rtw_err(rtwdev, "failed to set trx fifo info\n");
1059 goto err;
1060 }
1061
1062 ret = rtw88xxa_llt_init(rtwdev, rtwdev->fifo.rsvd_boundary);
1063 if (ret) {
1064 rtw_err(rtwdev, "failed to init llt\n");
1065 goto err;
1066 }
1067
1068 rtw_write32_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
1069
1070 ret = rtw_wait_firmware_completion(rtwdev);
1071 if (ret) {
1072 rtw_err(rtwdev, "failed to wait firmware completion\n");
1073 goto err_off;
1074 }
1075
1076 ret = rtw_download_firmware(rtwdev, &rtwdev->fw);
1077 if (ret) {
1078 rtw_err(rtwdev, "failed to download firmware\n");
1079 goto err_off;
1080 }
1081
1082 rtw_write8(rtwdev, REG_HMETFR, 0xf);
1083
1084 rtw_load_table(rtwdev, chip->mac_tbl);
1085
1086 rtw88xxau_init_queue_reserved_page(rtwdev);
1087 rtw88xxau_init_tx_buffer_boundary(rtwdev);
1088 rtw88xxau_init_queue_priority(rtwdev);
1089
1090 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2,
1091 chip->rxff_size - REPORT_BUF - 1);
1092
1093 if (chip->id == RTW_CHIP_TYPE_8812A)
1094 rtw_write8(rtwdev, REG_PBP,
1095 u8_encode_bits(PBP_512, PBP_TX_MASK) |
1096 u8_encode_bits(PBP_64, PBP_RX_MASK));
1097
1098 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1099
1100 rtw_write32(rtwdev, REG_HIMR0, 0);
1101 rtw_write32(rtwdev, REG_HIMR1, 0);
1102
1103 rtw_write32_mask(rtwdev, REG_CR, 0x30000, 0x2);
1104
1105 rtw88xxa_init_wmac_setting(rtwdev);
1106 rtw88xxa_init_adaptive_ctrl(rtwdev);
1107 rtw88xxa_init_edca(rtwdev);
1108
1109 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
1110 rtw_write8(rtwdev, REG_ACKTO, 0x80);
1111
1112 rtw88xxau_tx_aggregation(rtwdev);
1113
1114 rtw88xxa_init_beacon_parameters(rtwdev);
1115 rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xff);
1116
1117 rtw_hci_interface_cfg(rtwdev);
1118
1119 /* usb3 rx interval */
1120 rtw_write8(rtwdev, REG_USB3_RXITV, 0x01);
1121
1122 /* burst length=4, set 0x3400 for burst length=2 */
1123 rtw_write16(rtwdev, REG_RXDMA_STATUS, 0x7400);
1124 rtw_write8(rtwdev, REG_RXDMA_STATUS + 1, 0xf5);
1125
1126 /* 0x456 = 0x70, sugguested by Zhilin */
1127 if (chip->id == RTW_CHIP_TYPE_8821A)
1128 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x5e);
1129 else
1130 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, 0x70);
1131
1132 rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, 0xffffffff);
1133 rtw_write8(rtwdev, REG_USTIME_TSF, 0x50);
1134 rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50);
1135
1136 if (rtwusb->udev->speed == USB_SPEED_SUPER)
1137 /* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */
1138 rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3));
1139
1140 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
1141
1142 /* for VHT packet length 11K */
1143 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, 0x18);
1144
1145 rtw_write8(rtwdev, REG_PIFS, 0x00);
1146
1147 if (chip->id == RTW_CHIP_TYPE_8821A) {
1148 /* 0x0a0a too small, it can't pass AC logo. change to 0x1f1f */
1149 rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f);
1150 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, 0x80);
1151 rtw_write32(rtwdev, REG_FAST_EDCA_CTRL, 0x03087777);
1152 } else {
1153 rtw_write16(rtwdev, REG_MAX_AGGR_NUM, 0x1f1f);
1154 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
1155 }
1156
1157 /* to prevent mac is reseted by bus. */
1158 rtw_write8_set(rtwdev, REG_RSV_CTRL, BIT(5) | BIT(6));
1159
1160 /* ARFB table 9 for 11ac 5G 2SS */
1161 rtw_write32(rtwdev, REG_ARFR0, 0x00000010);
1162 rtw_write32(rtwdev, REG_ARFRH0, 0xfffff000);
1163
1164 /* ARFB table 10 for 11ac 5G 1SS */
1165 rtw_write32(rtwdev, REG_ARFR1_V1, 0x00000010);
1166 rtw_write32(rtwdev, REG_ARFRH1_V1, 0x003ff000);
1167
1168 /* ARFB table 11 for 11ac 24G 1SS */
1169 rtw_write32(rtwdev, REG_ARFR2_V1, 0x00000015);
1170 rtw_write32(rtwdev, REG_ARFRH2_V1, 0x003ff000);
1171
1172 /* ARFB table 12 for 11ac 24G 2SS */
1173 rtw_write32(rtwdev, REG_ARFR3_V1, 0x00000015);
1174 rtw_write32(rtwdev, REG_ARFRH3_V1, 0xffcff000);
1175
1176 rtw_write8_set(rtwdev, REG_CR, BIT_MACTXEN | BIT_MACRXEN);
1177
1178 rtw88xxa_phy_bb_config(rtwdev);
1179 rtw88xxa_phy_rf_config(rtwdev);
1180
1181 if (chip->id == RTW_CHIP_TYPE_8812A && hal->rf_path_num == 1)
1182 rtw8812a_config_1t(rtwdev);
1183
1184 rtw88xxa_switch_band(rtwdev, RTW_BAND_2G, RTW_CHANNEL_WIDTH_20);
1185
1186 rtw_write32(rtwdev, RTW_SEC_CMD_REG, BIT(31) | BIT(30));
1187
1188 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xff);
1189 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff);
1190 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0);
1191
1192 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5));
1193
1194 rtw_phy_init(rtwdev);
1195
1196 rtw88xxa_pwrtrack_init(rtwdev);
1197
1198 /* 0x4c6[3] 1: RTS BW = Data BW
1199 * 0: RTS BW depends on CCA / secondary CCA result.
1200 */
1201 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3));
1202
1203 /* enable Tx report. */
1204 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x0f);
1205
1206 /* Pretx_en, for WEP/TKIP SEC */
1207 rtw_write8(rtwdev, REG_EARLY_MODE_CONTROL + 3, 0x01);
1208
1209 rtw_write16(rtwdev, REG_TX_RPT_TIME, 0x3df0);
1210
1211 /* Reset USB mode switch setting */
1212 rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0);
1213 rtw_write8(rtwdev, REG_ACLK_MON, 0x0);
1214
1215 rtw_write8(rtwdev, REG_USB_HRPWM, 0);
1216
1217 /* ack for xmit mgmt frames. */
1218 rtw_write32_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(12));
1219
1220 hal->cck_high_power = rtw_read32_mask(rtwdev, REG_CCK_RPT_FORMAT,
1221 BIT_CCK_RPT_FORMAT);
1222
1223 ret = rtw_hci_start(rtwdev);
1224 if (ret) {
1225 rtw_err(rtwdev, "failed to start hci\n");
1226 goto err_off;
1227 }
1228
1229 if (efuse->btcoex) {
1230 rtw_coex_power_on_setting(rtwdev);
1231 rtw_coex_init_hw_config(rtwdev, false);
1232 }
1233
1234 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
1235
1236 return 0;
1237
1238 err_off:
1239 chip->ops->power_off(rtwdev);
1240
1241 err:
1242 return ret;
1243 }
1244 EXPORT_SYMBOL(rtw88xxa_power_on);
1245
rtw88xxa_phy_read_rf(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask)1246 u32 rtw88xxa_phy_read_rf(struct rtw_dev *rtwdev,
1247 enum rtw_rf_path rf_path, u32 addr, u32 mask)
1248 {
1249 static const u32 pi_addr[2] = { REG_3WIRE_SWA, REG_3WIRE_SWB };
1250 static const u32 read_addr[2][2] = {
1251 { REG_SI_READ_A, REG_SI_READ_B },
1252 { REG_PI_READ_A, REG_PI_READ_B }
1253 };
1254 const struct rtw_chip_info *chip = rtwdev->chip;
1255 const struct rtw_hal *hal = &rtwdev->hal;
1256 bool set_cca, pi_mode;
1257 u32 val;
1258
1259 if (rf_path >= hal->rf_phy_num) {
1260 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1261 return INV_RF_DATA;
1262 }
1263
1264 /* CCA off to avoid reading the wrong value.
1265 * Toggling CCA would affect RF 0x0, skip it.
1266 */
1267 set_cca = addr != 0x0 && chip->id == RTW_CHIP_TYPE_8812A &&
1268 hal->cut_version != RTW_CHIP_VER_CUT_C;
1269
1270 if (set_cca)
1271 rtw_write32_set(rtwdev, REG_CCA2ND, BIT(3));
1272
1273 addr &= 0xff;
1274
1275 pi_mode = rtw_read32_mask(rtwdev, pi_addr[rf_path], 0x4);
1276
1277 rtw_write32_mask(rtwdev, REG_HSSI_READ, MASKBYTE0, addr);
1278
1279 if (chip->id == RTW_CHIP_TYPE_8821A ||
1280 hal->cut_version == RTW_CHIP_VER_CUT_C)
1281 udelay(20);
1282
1283 val = rtw_read32_mask(rtwdev, read_addr[pi_mode][rf_path], mask);
1284
1285 /* CCA on */
1286 if (set_cca)
1287 rtw_write32_clr(rtwdev, REG_CCA2ND, BIT(3));
1288
1289 return val;
1290 }
1291 EXPORT_SYMBOL(rtw88xxa_phy_read_rf);
1292
rtw8812a_phy_fix_spur(struct rtw_dev * rtwdev,u8 channel,u8 bw)1293 static void rtw8812a_phy_fix_spur(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1294 {
1295 /* C cut Item12 ADC FIFO CLOCK */
1296 if (rtwdev->hal.cut_version == RTW_CHIP_VER_CUT_C) {
1297 if (bw == RTW_CHANNEL_WIDTH_40 && channel == 11)
1298 rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x3);
1299 else
1300 rtw_write32_mask(rtwdev, REG_ADCCLK, 0xC00, 0x2);
1301
1302 /* A workaround to resolve 2480Mhz spur by setting ADC clock
1303 * as 160M.
1304 */
1305 if (bw == RTW_CHANNEL_WIDTH_20 && (channel == 13 || channel == 14)) {
1306 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3);
1307 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1308 } else if (bw == RTW_CHANNEL_WIDTH_40 && channel == 11) {
1309 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1310 } else if (bw != RTW_CHANNEL_WIDTH_80) {
1311 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2);
1312 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1313 }
1314 } else {
1315 /* A workaround to resolve 2480Mhz spur by setting ADC clock
1316 * as 160M.
1317 */
1318 if (bw == RTW_CHANNEL_WIDTH_20 && (channel == 13 || channel == 14))
1319 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x3);
1320 else if (channel <= 14) /* 2.4G only */
1321 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x300, 0x2);
1322 }
1323 }
1324
rtw88xxa_switch_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw)1325 static void rtw88xxa_switch_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1326 {
1327 struct rtw_hal *hal = &rtwdev->hal;
1328 u32 fc_area, rf_mod_ag;
1329 u8 path;
1330
1331 switch (channel) {
1332 case 36 ... 48:
1333 fc_area = 0x494;
1334 break;
1335 case 50 ... 64:
1336 fc_area = 0x453;
1337 break;
1338 case 100 ... 116:
1339 fc_area = 0x452;
1340 break;
1341 default:
1342 if (channel >= 118)
1343 fc_area = 0x412;
1344 else
1345 fc_area = 0x96a;
1346 break;
1347 }
1348
1349 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area);
1350
1351 for (path = 0; path < hal->rf_path_num; path++) {
1352 switch (channel) {
1353 case 36 ... 64:
1354 rf_mod_ag = 0x101;
1355 break;
1356 case 100 ... 140:
1357 rf_mod_ag = 0x301;
1358 break;
1359 default:
1360 if (channel > 140)
1361 rf_mod_ag = 0x501;
1362 else
1363 rf_mod_ag = 0x000;
1364 break;
1365 }
1366
1367 rtw_write_rf(rtwdev, path, RF_CFGCH,
1368 RF18_RFSI_MASK | RF18_BAND_MASK, rf_mod_ag);
1369
1370 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
1371 rtw8812a_phy_fix_spur(rtwdev, channel, bw);
1372
1373 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_CHANNEL_MASK, channel);
1374 }
1375 }
1376
rtw88xxa_set_reg_bw(struct rtw_dev * rtwdev,u8 bw)1377 static void rtw88xxa_set_reg_bw(struct rtw_dev *rtwdev, u8 bw)
1378 {
1379 u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL);
1380
1381 val16 &= ~BIT_RFMOD;
1382 if (bw == RTW_CHANNEL_WIDTH_80)
1383 val16 |= BIT_RFMOD_80M;
1384 else if (bw == RTW_CHANNEL_WIDTH_40)
1385 val16 |= BIT_RFMOD_40M;
1386
1387 rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16);
1388 }
1389
rtw88xxa_post_set_bw_mode(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)1390 static void rtw88xxa_post_set_bw_mode(struct rtw_dev *rtwdev, u8 channel,
1391 u8 bw, u8 primary_chan_idx)
1392 {
1393 struct rtw_hal *hal = &rtwdev->hal;
1394 u8 txsc40 = 0, txsc20, txsc;
1395 u8 reg_837, l1pkval;
1396
1397 rtw88xxa_set_reg_bw(rtwdev, bw);
1398
1399 txsc20 = primary_chan_idx;
1400 if (bw == RTW_CHANNEL_WIDTH_80) {
1401 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
1402 txsc40 = RTW_SC_40_UPPER;
1403 else
1404 txsc40 = RTW_SC_40_LOWER;
1405 }
1406
1407 txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40);
1408 rtw_write8(rtwdev, REG_DATA_SC, txsc);
1409
1410 reg_837 = rtw_read8(rtwdev, REG_BWINDICATION + 3);
1411
1412 switch (bw) {
1413 default:
1414 case RTW_CHANNEL_WIDTH_20:
1415 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300200);
1416 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1417
1418 if (hal->rf_type == RF_2T2R)
1419 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 7);
1420 else
1421 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, 8);
1422
1423 break;
1424 case RTW_CHANNEL_WIDTH_40:
1425 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300201);
1426 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0);
1427 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc);
1428 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc);
1429
1430 if (reg_837 & BIT(2)) {
1431 l1pkval = 6;
1432 } else {
1433 if (hal->rf_type == RF_2T2R)
1434 l1pkval = 7;
1435 else
1436 l1pkval = 8;
1437 }
1438
1439 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval);
1440
1441 if (txsc == RTW_SC_20_UPPER)
1442 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
1443 else
1444 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
1445
1446 break;
1447 case RTW_CHANNEL_WIDTH_80:
1448 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x003003C3, 0x00300202);
1449 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 1);
1450 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3C, txsc);
1451 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0000000, txsc);
1452
1453 if (reg_837 & BIT(2)) {
1454 l1pkval = 5;
1455 } else {
1456 if (hal->rf_type == RF_2T2R)
1457 l1pkval = 6;
1458 else
1459 l1pkval = 7;
1460 }
1461
1462 rtw_write32_mask(rtwdev, REG_L1PKTH, 0x03C00000, l1pkval);
1463
1464 break;
1465 }
1466 }
1467
rtw88xxa_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)1468 static void rtw88xxa_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1469 {
1470 u8 path;
1471
1472 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
1473 switch (bw) {
1474 case RTW_CHANNEL_WIDTH_5:
1475 case RTW_CHANNEL_WIDTH_10:
1476 case RTW_CHANNEL_WIDTH_20:
1477 default:
1478 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3);
1479 break;
1480 case RTW_CHANNEL_WIDTH_40:
1481 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1);
1482 break;
1483 case RTW_CHANNEL_WIDTH_80:
1484 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0);
1485 break;
1486 }
1487 }
1488 }
1489
rtw88xxa_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)1490 void rtw88xxa_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1491 u8 primary_chan_idx)
1492 {
1493 u8 old_band, new_band;
1494
1495 if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
1496 old_band = RTW_BAND_5G;
1497 else
1498 old_band = RTW_BAND_2G;
1499
1500 if (channel > 14)
1501 new_band = RTW_BAND_5G;
1502 else
1503 new_band = RTW_BAND_2G;
1504
1505 if (new_band != old_band)
1506 rtw88xxa_switch_band(rtwdev, new_band, bw);
1507
1508 rtw88xxa_switch_channel(rtwdev, channel, bw);
1509
1510 rtw88xxa_post_set_bw_mode(rtwdev, channel, bw, primary_chan_idx);
1511
1512 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
1513 rtw8812a_phy_fix_spur(rtwdev, channel, bw);
1514
1515 rtw88xxa_set_channel_rf(rtwdev, channel, bw);
1516 }
1517 EXPORT_SYMBOL(rtw88xxa_set_channel);
1518
rtw88xxa_query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat,s8 (* cck_rx_pwr)(u8 lna_idx,u8 vga_idx))1519 void rtw88xxa_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1520 struct rtw_rx_pkt_stat *pkt_stat,
1521 s8 (*cck_rx_pwr)(u8 lna_idx, u8 vga_idx))
1522 {
1523 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1524 struct rtw_jaguar_phy_status_rpt *rpt;
1525 u8 gain[RTW_RF_PATH_MAX], rssi, i;
1526 s8 rx_pwr_db, power_a, power_b;
1527 const s8 min_rx_power = -120;
1528 u8 lna_idx, vga_idx;
1529
1530 rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status;
1531
1532 if (pkt_stat->rate <= DESC_RATE11M) {
1533 lna_idx = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX);
1534 vga_idx = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX);
1535
1536 rx_pwr_db = cck_rx_pwr(lna_idx, vga_idx);
1537
1538 pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db;
1539 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1540 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
1541 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1542 pkt_stat->signal_power = rx_pwr_db;
1543 } else { /* OFDM rate */
1544 gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A);
1545 gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B);
1546
1547 for (i = RF_PATH_A; i < rtwdev->hal.rf_path_num; i++) {
1548 pkt_stat->rx_power[i] = gain[i] - 110;
1549 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1);
1550 dm_info->rssi[i] = rssi;
1551 }
1552
1553 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power,
1554 rtwdev->hal.rf_path_num);
1555
1556 power_a = pkt_stat->rx_power[RF_PATH_A];
1557 power_b = pkt_stat->rx_power[RF_PATH_B];
1558 if (rtwdev->hal.rf_path_num == 1)
1559 power_b = power_a;
1560
1561 pkt_stat->signal_power = max3(power_a, power_b, min_rx_power);
1562 }
1563 }
1564 EXPORT_SYMBOL(rtw88xxa_query_phy_status);
1565
1566 static void
rtw88xxa_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs,u32 * phy_pwr_idx)1567 rtw88xxa_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
1568 u8 rs, u32 *phy_pwr_idx)
1569 {
1570 static const u32 offset_txagc[2] = {
1571 REG_TX_AGC_A_CCK_11_CCK_1, REG_TX_AGC_B_CCK_11_CCK_1
1572 };
1573 u8 rate, rate_idx, pwr_index, shift;
1574 struct rtw_hal *hal = &rtwdev->hal;
1575 bool write_1ss_mcs9;
1576 u32 mask;
1577 int j;
1578
1579 for (j = 0; j < rtw_rate_size[rs]; j++) {
1580 rate = rtw_rate_section[rs][j];
1581
1582 pwr_index = hal->tx_pwr_tbl[path][rate];
1583
1584 shift = rate & 0x3;
1585 *phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
1586
1587 write_1ss_mcs9 = rate == DESC_RATEVHT1SS_MCS9 &&
1588 hal->rf_path_num == 1;
1589
1590 if (write_1ss_mcs9)
1591 mask = MASKLWORD;
1592 else
1593 mask = MASKDWORD;
1594
1595 if (shift == 0x3 || write_1ss_mcs9) {
1596 rate_idx = rate & 0xfc;
1597 if (rate >= DESC_RATEVHT1SS_MCS0)
1598 rate_idx -= 0x10;
1599
1600 rtw_write32_mask(rtwdev, offset_txagc[path] + rate_idx,
1601 mask, *phy_pwr_idx);
1602
1603 *phy_pwr_idx = 0;
1604 }
1605 }
1606 }
1607
rtw88xxa_tx_power_training(struct rtw_dev * rtwdev,u8 bw,u8 channel,u8 path)1608 static void rtw88xxa_tx_power_training(struct rtw_dev *rtwdev, u8 bw,
1609 u8 channel, u8 path)
1610 {
1611 static const u32 write_offset[] = {
1612 REG_TX_PWR_TRAINING_A, REG_TX_PWR_TRAINING_B,
1613 };
1614 u32 power_level, write_data;
1615 u8 i;
1616
1617 power_level = rtwdev->hal.tx_pwr_tbl[path][DESC_RATEMCS7];
1618 write_data = 0;
1619
1620 for (i = 0; i < 3; i++) {
1621 if (i == 0)
1622 power_level -= 10;
1623 else if (i == 1)
1624 power_level -= 8;
1625 else
1626 power_level -= 6;
1627
1628 write_data |= max_t(u32, power_level, 2) << (i * 8);
1629 }
1630
1631 rtw_write32_mask(rtwdev, write_offset[path], 0xffffff, write_data);
1632 }
1633
rtw88xxa_set_tx_power_index(struct rtw_dev * rtwdev)1634 void rtw88xxa_set_tx_power_index(struct rtw_dev *rtwdev)
1635 {
1636 struct rtw_hal *hal = &rtwdev->hal;
1637 u32 phy_pwr_idx = 0;
1638 int rs, path;
1639
1640 for (path = 0; path < hal->rf_path_num; path++) {
1641 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++) {
1642 if (hal->rf_path_num == 1 &&
1643 (rs == RTW_RATE_SECTION_HT_2S ||
1644 rs == RTW_RATE_SECTION_VHT_2S))
1645 continue;
1646
1647 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags) &&
1648 rs > RTW_RATE_SECTION_OFDM)
1649 continue;
1650
1651 if (hal->current_band_type == RTW_BAND_5G &&
1652 rs == RTW_RATE_SECTION_CCK)
1653 continue;
1654
1655 rtw88xxa_set_tx_power_index_by_rate(rtwdev, path, rs,
1656 &phy_pwr_idx);
1657 }
1658
1659 rtw88xxa_tx_power_training(rtwdev, hal->current_band_width,
1660 hal->current_channel, path);
1661 }
1662 }
1663 EXPORT_SYMBOL(rtw88xxa_set_tx_power_index);
1664
rtw88xxa_false_alarm_statistics(struct rtw_dev * rtwdev)1665 void rtw88xxa_false_alarm_statistics(struct rtw_dev *rtwdev)
1666 {
1667 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1668 u32 cck_fa_cnt, ofdm_fa_cnt;
1669 u32 crc32_cnt, cca32_cnt;
1670 u32 cck_enable;
1671
1672 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
1673 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
1674 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
1675
1676 dm_info->cck_fa_cnt = cck_fa_cnt;
1677 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1678 dm_info->total_fa_cnt = ofdm_fa_cnt;
1679 if (cck_enable)
1680 dm_info->total_fa_cnt += cck_fa_cnt;
1681
1682 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
1683 dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1684 dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1685
1686 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
1687 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1688 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1689
1690 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
1691 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1692 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1693
1694 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
1695 dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1696 dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1697
1698 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
1699 dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD);
1700 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1701 if (cck_enable) {
1702 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
1703 dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
1704 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1705 }
1706
1707 rtw_write32_set(rtwdev, REG_FAS, BIT(17));
1708 rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
1709 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1710 rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1711 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
1712 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
1713 }
1714 EXPORT_SYMBOL(rtw88xxa_false_alarm_statistics);
1715
rtw88xxa_iqk_backup_mac_bb(struct rtw_dev * rtwdev,u32 * macbb_backup,const u32 * backup_macbb_reg,u32 macbb_num)1716 void rtw88xxa_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
1717 u32 *macbb_backup,
1718 const u32 *backup_macbb_reg,
1719 u32 macbb_num)
1720 {
1721 u32 i;
1722
1723 /* [31] = 0 --> Page C */
1724 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1725
1726 /* save MACBB default value */
1727 for (i = 0; i < macbb_num; i++)
1728 macbb_backup[i] = rtw_read32(rtwdev, backup_macbb_reg[i]);
1729 }
1730 EXPORT_SYMBOL(rtw88xxa_iqk_backup_mac_bb);
1731
rtw88xxa_iqk_backup_afe(struct rtw_dev * rtwdev,u32 * afe_backup,const u32 * backup_afe_reg,u32 afe_num)1732 void rtw88xxa_iqk_backup_afe(struct rtw_dev *rtwdev, u32 *afe_backup,
1733 const u32 *backup_afe_reg, u32 afe_num)
1734 {
1735 u32 i;
1736
1737 /* [31] = 0 --> Page C */
1738 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1739
1740 /* Save AFE Parameters */
1741 for (i = 0; i < afe_num; i++)
1742 afe_backup[i] = rtw_read32(rtwdev, backup_afe_reg[i]);
1743 }
1744 EXPORT_SYMBOL(rtw88xxa_iqk_backup_afe);
1745
rtw88xxa_iqk_restore_mac_bb(struct rtw_dev * rtwdev,u32 * macbb_backup,const u32 * backup_macbb_reg,u32 macbb_num)1746 void rtw88xxa_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
1747 u32 *macbb_backup,
1748 const u32 *backup_macbb_reg,
1749 u32 macbb_num)
1750 {
1751 u32 i;
1752
1753 /* [31] = 0 --> Page C */
1754 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1755
1756 /* Reload MacBB Parameters */
1757 for (i = 0; i < macbb_num; i++)
1758 rtw_write32(rtwdev, backup_macbb_reg[i], macbb_backup[i]);
1759 }
1760 EXPORT_SYMBOL(rtw88xxa_iqk_restore_mac_bb);
1761
rtw88xxa_iqk_configure_mac(struct rtw_dev * rtwdev)1762 void rtw88xxa_iqk_configure_mac(struct rtw_dev *rtwdev)
1763 {
1764 /* [31] = 0 --> Page C */
1765 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0);
1766
1767 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
1768 rtw_write32_mask(rtwdev, REG_BCN_CTRL,
1769 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION, 0x0);
1770
1771 /* RX ante off */
1772 rtw_write8(rtwdev, REG_RXPSEL, 0x00);
1773
1774 /* CCA off */
1775 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xc);
1776
1777 /* CCK RX path off */
1778 rtw_write8(rtwdev, REG_CCK_RX + 3, 0xf);
1779 }
1780 EXPORT_SYMBOL(rtw88xxa_iqk_configure_mac);
1781
rtw88xxa_iqk_finish(int average,int threshold,int * x_temp,int * y_temp,int * x,int * y,bool break_inner,bool break_outer)1782 bool rtw88xxa_iqk_finish(int average, int threshold,
1783 int *x_temp, int *y_temp, int *x, int *y,
1784 bool break_inner, bool break_outer)
1785 {
1786 bool finish = false;
1787 int i, ii, dx, dy;
1788
1789 for (i = 0; i < average; i++) {
1790 for (ii = i + 1; ii < average; ii++) {
1791 dx = abs_diff(x_temp[i] >> 21, x_temp[ii] >> 21);
1792 dy = abs_diff(y_temp[i] >> 21, y_temp[ii] >> 21);
1793
1794 if (dx < threshold && dy < threshold) {
1795 *x = ((x_temp[i] >> 21) + (x_temp[ii] >> 21));
1796 *y = ((y_temp[i] >> 21) + (y_temp[ii] >> 21));
1797
1798 *x /= 2;
1799 *y /= 2;
1800
1801 finish = true;
1802
1803 if (break_inner)
1804 break;
1805 }
1806 }
1807
1808 if (finish && break_outer)
1809 break;
1810 }
1811
1812 return finish;
1813 }
1814 EXPORT_SYMBOL(rtw88xxa_iqk_finish);
1815
rtw88xxa_pwrtrack_set(struct rtw_dev * rtwdev,u8 tx_rate,u8 path)1816 static void rtw88xxa_pwrtrack_set(struct rtw_dev *rtwdev, u8 tx_rate, u8 path)
1817 {
1818 static const u32 reg_txscale[2] = { REG_TXSCALE_A, REG_TXSCALE_B };
1819 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1820 u8 cck_swing_idx, ofdm_swing_idx;
1821 u8 pwr_tracking_limit;
1822
1823 switch (tx_rate) {
1824 case DESC_RATE1M ... DESC_RATE11M:
1825 pwr_tracking_limit = 32;
1826 break;
1827 case DESC_RATE6M ... DESC_RATE48M:
1828 case DESC_RATEMCS3 ... DESC_RATEMCS4:
1829 case DESC_RATEMCS11 ... DESC_RATEMCS12:
1830 case DESC_RATEVHT1SS_MCS3 ... DESC_RATEVHT1SS_MCS4:
1831 case DESC_RATEVHT2SS_MCS3 ... DESC_RATEVHT2SS_MCS4:
1832 pwr_tracking_limit = 30;
1833 break;
1834 case DESC_RATE54M:
1835 case DESC_RATEMCS5 ... DESC_RATEMCS7:
1836 case DESC_RATEMCS13 ... DESC_RATEMCS15:
1837 case DESC_RATEVHT1SS_MCS5 ... DESC_RATEVHT1SS_MCS6:
1838 case DESC_RATEVHT2SS_MCS5 ... DESC_RATEVHT2SS_MCS6:
1839 pwr_tracking_limit = 28;
1840 break;
1841 case DESC_RATEMCS0 ... DESC_RATEMCS2:
1842 case DESC_RATEMCS8 ... DESC_RATEMCS10:
1843 case DESC_RATEVHT1SS_MCS0 ... DESC_RATEVHT1SS_MCS2:
1844 case DESC_RATEVHT2SS_MCS0 ... DESC_RATEVHT2SS_MCS2:
1845 pwr_tracking_limit = 34;
1846 break;
1847 case DESC_RATEVHT1SS_MCS7:
1848 case DESC_RATEVHT2SS_MCS7:
1849 pwr_tracking_limit = 26;
1850 break;
1851 default:
1852 case DESC_RATEVHT1SS_MCS8:
1853 case DESC_RATEVHT2SS_MCS8:
1854 pwr_tracking_limit = 24;
1855 break;
1856 case DESC_RATEVHT1SS_MCS9:
1857 case DESC_RATEVHT2SS_MCS9:
1858 pwr_tracking_limit = 22;
1859 break;
1860 }
1861
1862 cck_swing_idx = dm_info->delta_power_index[path] + dm_info->default_cck_index;
1863 ofdm_swing_idx = dm_info->delta_power_index[path] + dm_info->default_ofdm_index;
1864
1865 if (ofdm_swing_idx > pwr_tracking_limit) {
1866 if (path == RF_PATH_A)
1867 dm_info->txagc_remnant_cck = cck_swing_idx - pwr_tracking_limit;
1868 dm_info->txagc_remnant_ofdm[path] = ofdm_swing_idx - pwr_tracking_limit;
1869
1870 ofdm_swing_idx = pwr_tracking_limit;
1871 } else if (ofdm_swing_idx == 0) {
1872 if (path == RF_PATH_A)
1873 dm_info->txagc_remnant_cck = cck_swing_idx;
1874 dm_info->txagc_remnant_ofdm[path] = ofdm_swing_idx;
1875 } else {
1876 if (path == RF_PATH_A)
1877 dm_info->txagc_remnant_cck = 0;
1878 dm_info->txagc_remnant_ofdm[path] = 0;
1879 }
1880
1881 rtw_write32_mask(rtwdev, reg_txscale[path], GENMASK(31, 21),
1882 rtw88xxa_txscale_tbl[ofdm_swing_idx]);
1883 }
1884
rtw88xxa_phy_pwrtrack(struct rtw_dev * rtwdev,void (* do_lck)(struct rtw_dev * rtwdev),void (* do_iqk)(struct rtw_dev * rtwdev))1885 void rtw88xxa_phy_pwrtrack(struct rtw_dev *rtwdev,
1886 void (*do_lck)(struct rtw_dev *rtwdev),
1887 void (*do_iqk)(struct rtw_dev *rtwdev))
1888 {
1889 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1890 struct rtw_hal *hal = &rtwdev->hal;
1891 struct rtw_swing_table swing_table;
1892 s8 remnant_pre[RTW_RF_PATH_MAX];
1893 u8 thermal_value, delta, path;
1894 bool need_iqk;
1895
1896 rtw_phy_config_swing_table(rtwdev, &swing_table);
1897
1898 if (rtwdev->efuse.thermal_meter[0] == 0xff) {
1899 pr_err_once("efuse thermal meter is 0xff\n");
1900 return;
1901 }
1902
1903 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1904
1905 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1906
1907 need_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1908
1909 if (need_iqk && do_lck)
1910 do_lck(rtwdev);
1911
1912 if (dm_info->pwr_trk_init_trigger)
1913 dm_info->pwr_trk_init_trigger = false;
1914 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1915 RF_PATH_A))
1916 goto iqk;
1917
1918 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1919
1920 for (path = RF_PATH_A; path < hal->rf_path_num; path++) {
1921 remnant_pre[path] = dm_info->txagc_remnant_ofdm[path];
1922
1923 dm_info->delta_power_index[path] =
1924 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, path,
1925 RF_PATH_A, delta);
1926
1927 if (dm_info->delta_power_index[path] !=
1928 dm_info->delta_power_index_last[path]) {
1929 dm_info->delta_power_index_last[path] =
1930 dm_info->delta_power_index[path];
1931
1932 rtw88xxa_pwrtrack_set(rtwdev, dm_info->tx_rate, path);
1933 }
1934 }
1935
1936 for (path = RF_PATH_A; path < hal->rf_path_num; path++) {
1937 if (remnant_pre[path] != dm_info->txagc_remnant_ofdm[path]) {
1938 rtw_phy_set_tx_power_level(rtwdev,
1939 hal->current_channel);
1940 break;
1941 }
1942 }
1943
1944 iqk:
1945 if (need_iqk)
1946 do_iqk(rtwdev);
1947 }
1948 EXPORT_SYMBOL(rtw88xxa_phy_pwrtrack);
1949
rtw88xxa_phy_cck_pd_set(struct rtw_dev * rtwdev,u8 new_lvl)1950 void rtw88xxa_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1951 {
1952 static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed};
1953 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1954
1955 /* Override rtw_phy_cck_pd_lv_link(). It implements something
1956 * like type 2/3/4. We need type 1 here.
1957 */
1958 if (rtw_is_assoc(rtwdev)) {
1959 if (dm_info->min_rssi > 60) {
1960 new_lvl = CCK_PD_LV3;
1961 } else if (dm_info->min_rssi > 35) {
1962 new_lvl = CCK_PD_LV2;
1963 } else if (dm_info->min_rssi > 20) {
1964 if (dm_info->cck_fa_avg > 500)
1965 new_lvl = CCK_PD_LV2;
1966 else if (dm_info->cck_fa_avg < 250)
1967 new_lvl = CCK_PD_LV1;
1968 else
1969 return;
1970 } else {
1971 new_lvl = CCK_PD_LV1;
1972 }
1973 }
1974
1975 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1976 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1977
1978 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1979 return;
1980
1981 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1982 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1983
1984 rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]);
1985 }
1986 EXPORT_SYMBOL(rtw88xxa_phy_cck_pd_set);
1987
1988 MODULE_AUTHOR("Realtek Corporation");
1989 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821a/8811a/8812a common code");
1990 MODULE_LICENSE("Dual BSD/GPL");
1991