1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_clear_pf_cfg - Clear PF configuration 208 * @hw: pointer to the hardware structure 209 * 210 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 211 * configuration, flow director filters, etc.). 212 */ 213 int ice_clear_pf_cfg(struct ice_hw *hw) 214 { 215 struct libie_aq_desc desc; 216 217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 218 219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 220 } 221 222 /** 223 * ice_aq_manage_mac_read - manage MAC address read command 224 * @hw: pointer to the HW struct 225 * @buf: a virtual buffer to hold the manage MAC read response 226 * @buf_size: Size of the virtual buffer 227 * @cd: pointer to command details structure or NULL 228 * 229 * This function is used to return per PF station MAC address (0x0107). 230 * NOTE: Upon successful completion of this command, MAC address information 231 * is returned in user specified buffer. Please interpret user specified 232 * buffer as "manage_mac_read" response. 233 * Response such as various MAC addresses are stored in HW struct (port.mac) 234 * ice_discover_dev_caps is expected to be called before this function is 235 * called. 236 */ 237 static int 238 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 239 struct ice_sq_cd *cd) 240 { 241 struct ice_aqc_manage_mac_read_resp *resp; 242 struct ice_aqc_manage_mac_read *cmd; 243 struct libie_aq_desc desc; 244 int status; 245 u16 flags; 246 u8 i; 247 248 cmd = libie_aq_raw(&desc); 249 250 if (buf_size < sizeof(*resp)) 251 return -EINVAL; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 254 255 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 256 if (status) 257 return status; 258 259 resp = buf; 260 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 261 262 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 263 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 264 return -EIO; 265 } 266 267 /* A single port can report up to two (LAN and WoL) addresses */ 268 for (i = 0; i < cmd->num_addr; i++) 269 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 270 ether_addr_copy(hw->port_info->mac.lan_addr, 271 resp[i].mac_addr); 272 ether_addr_copy(hw->port_info->mac.perm_addr, 273 resp[i].mac_addr); 274 break; 275 } 276 277 return 0; 278 } 279 280 /** 281 * ice_aq_get_phy_caps - returns PHY capabilities 282 * @pi: port information structure 283 * @qual_mods: report qualified modules 284 * @report_mode: report mode capabilities 285 * @pcaps: structure for PHY capabilities to be filled 286 * @cd: pointer to command details structure or NULL 287 * 288 * Returns the various PHY capabilities supported on the Port (0x0600) 289 */ 290 int 291 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 292 struct ice_aqc_get_phy_caps_data *pcaps, 293 struct ice_sq_cd *cd) 294 { 295 struct ice_aqc_get_phy_caps *cmd; 296 u16 pcaps_size = sizeof(*pcaps); 297 struct libie_aq_desc desc; 298 const char *prefix; 299 struct ice_hw *hw; 300 int status; 301 302 cmd = libie_aq_raw(&desc); 303 304 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 305 return -EINVAL; 306 hw = pi->hw; 307 308 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 309 !ice_fw_supports_report_dflt_cfg(hw)) 310 return -EINVAL; 311 312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 313 314 if (qual_mods) 315 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 316 317 cmd->param0 |= cpu_to_le16(report_mode); 318 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 319 320 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 321 322 switch (report_mode) { 323 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 324 prefix = "phy_caps_media"; 325 break; 326 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 327 prefix = "phy_caps_no_media"; 328 break; 329 case ICE_AQC_REPORT_ACTIVE_CFG: 330 prefix = "phy_caps_active"; 331 break; 332 case ICE_AQC_REPORT_DFLT_CFG: 333 prefix = "phy_caps_default"; 334 break; 335 default: 336 prefix = "phy_caps_invalid"; 337 } 338 339 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 340 le64_to_cpu(pcaps->phy_type_high), prefix); 341 342 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 343 prefix, report_mode); 344 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 345 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 346 pcaps->low_power_ctrl_an); 347 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 348 pcaps->eee_cap); 349 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 350 pcaps->eeer_value); 351 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 352 pcaps->link_fec_options); 353 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 354 prefix, pcaps->module_compliance_enforcement); 355 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 356 prefix, pcaps->extended_compliance_code); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 358 pcaps->module_type[0]); 359 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 360 pcaps->module_type[1]); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 362 pcaps->module_type[2]); 363 364 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 365 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 366 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 367 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 368 sizeof(pi->phy.link_info.module_type)); 369 } 370 371 return status; 372 } 373 374 /** 375 * ice_aq_get_link_topo_handle - get link topology node return status 376 * @pi: port information structure 377 * @node_type: requested node type 378 * @cd: pointer to command details structure or NULL 379 * 380 * Get link topology node return status for specified node type (0x06E0) 381 * 382 * Node type cage can be used to determine if cage is present. If AQC 383 * returns error (ENOENT), then no cage present. If no cage present, then 384 * connection type is backplane or BASE-T. 385 */ 386 static int 387 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 388 struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_topo *cmd; 391 struct libie_aq_desc desc; 392 393 cmd = libie_aq_raw(&desc); 394 395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 396 397 cmd->addr.topo_params.node_type_ctx = 398 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 399 ICE_AQC_LINK_TOPO_NODE_CTX_S); 400 401 /* set node type */ 402 cmd->addr.topo_params.node_type_ctx |= 403 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 404 405 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 406 } 407 408 /** 409 * ice_aq_get_netlist_node 410 * @hw: pointer to the hw struct 411 * @cmd: get_link_topo AQ structure 412 * @node_part_number: output node part number if node found 413 * @node_handle: output node handle parameter if node found 414 * 415 * Get netlist node handle. 416 */ 417 int 418 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 419 u8 *node_part_number, u16 *node_handle) 420 { 421 struct ice_aqc_get_link_topo *resp; 422 struct libie_aq_desc desc; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 resp = libie_aq_raw(&desc); 426 *resp = *cmd; 427 428 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 429 return -EINTR; 430 431 if (node_handle) 432 *node_handle = le16_to_cpu(resp->addr.handle); 433 if (node_part_number) 434 *node_part_number = resp->node_part_num; 435 436 return 0; 437 } 438 439 /** 440 * ice_find_netlist_node 441 * @hw: pointer to the hw struct 442 * @node_type: type of netlist node to look for 443 * @ctx: context of the search 444 * @node_part_number: node part number to look for 445 * @node_handle: output parameter if node found - optional 446 * 447 * Scan the netlist for a node handle of the given node type and part number. 448 * 449 * If node_handle is non-NULL it will be modified on function exit. It is only 450 * valid if the function returns zero, and should be ignored on any non-zero 451 * return value. 452 * 453 * Return: 454 * * 0 if the node is found, 455 * * -ENOENT if no handle was found, 456 * * negative error code on failure to access the AQ. 457 */ 458 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 459 u8 node_part_number, u16 *node_handle) 460 { 461 u8 idx; 462 463 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 464 struct ice_aqc_get_link_topo cmd = {}; 465 u8 rec_node_part_number; 466 int status; 467 468 cmd.addr.topo_params.node_type_ctx = 469 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 470 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 471 cmd.addr.topo_params.index = idx; 472 473 status = ice_aq_get_netlist_node(hw, &cmd, 474 &rec_node_part_number, 475 node_handle); 476 if (status) 477 return status; 478 479 if (rec_node_part_number == node_part_number) 480 return 0; 481 } 482 483 return -ENOENT; 484 } 485 486 /** 487 * ice_is_media_cage_present 488 * @pi: port information structure 489 * 490 * Returns true if media cage is present, else false. If no cage, then 491 * media type is backplane or BASE-T. 492 */ 493 static bool ice_is_media_cage_present(struct ice_port_info *pi) 494 { 495 /* Node type cage can be used to determine if cage is present. If AQC 496 * returns error (ENOENT), then no cage present. If no cage present then 497 * connection type is backplane or BASE-T. 498 */ 499 return !ice_aq_get_link_topo_handle(pi, 500 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 501 NULL); 502 } 503 504 /** 505 * ice_get_media_type - Gets media type 506 * @pi: port information structure 507 */ 508 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 509 { 510 struct ice_link_status *hw_link_info; 511 512 if (!pi) 513 return ICE_MEDIA_UNKNOWN; 514 515 hw_link_info = &pi->phy.link_info; 516 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 517 /* If more than one media type is selected, report unknown */ 518 return ICE_MEDIA_UNKNOWN; 519 520 if (hw_link_info->phy_type_low) { 521 /* 1G SGMII is a special case where some DA cable PHYs 522 * may show this as an option when it really shouldn't 523 * be since SGMII is meant to be between a MAC and a PHY 524 * in a backplane. Try to detect this case and handle it 525 */ 526 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 527 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 528 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 529 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 530 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 531 return ICE_MEDIA_DA; 532 533 switch (hw_link_info->phy_type_low) { 534 case ICE_PHY_TYPE_LOW_1000BASE_SX: 535 case ICE_PHY_TYPE_LOW_1000BASE_LX: 536 case ICE_PHY_TYPE_LOW_10GBASE_SR: 537 case ICE_PHY_TYPE_LOW_10GBASE_LR: 538 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 539 case ICE_PHY_TYPE_LOW_25GBASE_SR: 540 case ICE_PHY_TYPE_LOW_25GBASE_LR: 541 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 542 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 543 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 544 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 545 case ICE_PHY_TYPE_LOW_50GBASE_SR: 546 case ICE_PHY_TYPE_LOW_50GBASE_FR: 547 case ICE_PHY_TYPE_LOW_50GBASE_LR: 548 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 549 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 550 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_DR: 552 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 553 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 554 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 555 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 556 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 557 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 558 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 559 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 560 return ICE_MEDIA_FIBER; 561 case ICE_PHY_TYPE_LOW_100BASE_TX: 562 case ICE_PHY_TYPE_LOW_1000BASE_T: 563 case ICE_PHY_TYPE_LOW_2500BASE_T: 564 case ICE_PHY_TYPE_LOW_5GBASE_T: 565 case ICE_PHY_TYPE_LOW_10GBASE_T: 566 case ICE_PHY_TYPE_LOW_25GBASE_T: 567 return ICE_MEDIA_BASET; 568 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 569 case ICE_PHY_TYPE_LOW_25GBASE_CR: 570 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 571 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 572 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 573 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 574 case ICE_PHY_TYPE_LOW_50GBASE_CP: 575 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 577 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 578 return ICE_MEDIA_DA; 579 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2: 582 case ICE_PHY_TYPE_LOW_50G_AUI2: 583 case ICE_PHY_TYPE_LOW_50G_AUI1: 584 case ICE_PHY_TYPE_LOW_100G_AUI4: 585 case ICE_PHY_TYPE_LOW_100G_CAUI4: 586 if (ice_is_media_cage_present(pi)) 587 return ICE_MEDIA_DA; 588 fallthrough; 589 case ICE_PHY_TYPE_LOW_1000BASE_KX: 590 case ICE_PHY_TYPE_LOW_2500BASE_KX: 591 case ICE_PHY_TYPE_LOW_2500BASE_X: 592 case ICE_PHY_TYPE_LOW_5GBASE_KR: 593 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 594 case ICE_PHY_TYPE_LOW_25GBASE_KR: 595 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 596 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 597 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 599 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 600 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 601 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 602 return ICE_MEDIA_BACKPLANE; 603 } 604 } else { 605 switch (hw_link_info->phy_type_high) { 606 case ICE_PHY_TYPE_HIGH_100G_AUI2: 607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 608 if (ice_is_media_cage_present(pi)) 609 return ICE_MEDIA_DA; 610 fallthrough; 611 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 612 return ICE_MEDIA_BACKPLANE; 613 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 614 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 615 return ICE_MEDIA_FIBER; 616 } 617 } 618 return ICE_MEDIA_UNKNOWN; 619 } 620 621 /** 622 * ice_get_link_status_datalen 623 * @hw: pointer to the HW struct 624 * 625 * Returns datalength for the Get Link Status AQ command, which is bigger for 626 * newer adapter families handled by ice driver. 627 */ 628 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 629 { 630 switch (hw->mac_type) { 631 case ICE_MAC_E830: 632 return ICE_AQC_LS_DATA_SIZE_V2; 633 case ICE_MAC_E810: 634 default: 635 return ICE_AQC_LS_DATA_SIZE_V1; 636 } 637 } 638 639 /** 640 * ice_aq_get_link_info 641 * @pi: port information structure 642 * @ena_lse: enable/disable LinkStatusEvent reporting 643 * @link: pointer to link status structure - optional 644 * @cd: pointer to command details structure or NULL 645 * 646 * Get Link Status (0x607). Returns the link status of the adapter. 647 */ 648 int 649 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 650 struct ice_link_status *link, struct ice_sq_cd *cd) 651 { 652 struct ice_aqc_get_link_status_data link_data = { 0 }; 653 struct ice_aqc_get_link_status *resp; 654 struct ice_link_status *li_old, *li; 655 enum ice_media_type *hw_media_type; 656 struct ice_fc_info *hw_fc_info; 657 struct libie_aq_desc desc; 658 bool tx_pause, rx_pause; 659 struct ice_hw *hw; 660 u16 cmd_flags; 661 int status; 662 663 if (!pi) 664 return -EINVAL; 665 hw = pi->hw; 666 li_old = &pi->phy.link_info_old; 667 hw_media_type = &pi->phy.media_type; 668 li = &pi->phy.link_info; 669 hw_fc_info = &pi->fc; 670 671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 672 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 673 resp = libie_aq_raw(&desc); 674 resp->cmd_flags = cpu_to_le16(cmd_flags); 675 resp->lport_num = pi->lport; 676 677 status = ice_aq_send_cmd(hw, &desc, &link_data, 678 ice_get_link_status_datalen(hw), cd); 679 if (status) 680 return status; 681 682 /* save off old link status information */ 683 *li_old = *li; 684 685 /* update current link status information */ 686 li->link_speed = le16_to_cpu(link_data.link_speed); 687 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 688 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 689 *hw_media_type = ice_get_media_type(pi); 690 li->link_info = link_data.link_info; 691 li->link_cfg_err = link_data.link_cfg_err; 692 li->an_info = link_data.an_info; 693 li->ext_info = link_data.ext_info; 694 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 695 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 696 li->topo_media_conflict = link_data.topo_media_conflict; 697 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 698 ICE_AQ_CFG_PACING_TYPE_M); 699 700 /* update fc info */ 701 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 702 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 703 if (tx_pause && rx_pause) 704 hw_fc_info->current_mode = ICE_FC_FULL; 705 else if (tx_pause) 706 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 707 else if (rx_pause) 708 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 709 else 710 hw_fc_info->current_mode = ICE_FC_NONE; 711 712 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 713 714 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 715 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 716 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 717 (unsigned long long)li->phy_type_low); 718 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 719 (unsigned long long)li->phy_type_high); 720 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 721 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 722 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 723 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 724 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 725 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 726 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 727 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 728 li->max_frame_size); 729 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 730 731 /* save link status information */ 732 if (link) 733 *link = *li; 734 735 /* flag cleared so calling functions don't call AQ again */ 736 pi->phy.get_link_info = false; 737 738 return 0; 739 } 740 741 /** 742 * ice_fill_tx_timer_and_fc_thresh 743 * @hw: pointer to the HW struct 744 * @cmd: pointer to MAC cfg structure 745 * 746 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 747 * descriptor 748 */ 749 static void 750 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 751 struct ice_aqc_set_mac_cfg *cmd) 752 { 753 u32 val, fc_thres_m; 754 755 /* We read back the transmit timer and FC threshold value of 756 * LFC. Thus, we will use index = 757 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 758 * 759 * Also, because we are operating on transmit timer and FC 760 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 761 */ 762 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 763 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 764 765 if (hw->mac_type == ICE_MAC_E830) { 766 /* Retrieve the transmit timer */ 767 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 768 cmd->tx_tmr_value = 769 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 770 771 /* Retrieve the fc threshold */ 772 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 773 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 774 } else { 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, 777 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 778 cmd->tx_tmr_value = 779 le16_encode_bits(val, 780 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 781 782 /* Retrieve the fc threshold */ 783 val = rd32(hw, 784 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 785 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 786 } 787 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 788 } 789 790 /** 791 * ice_aq_set_mac_cfg 792 * @hw: pointer to the HW struct 793 * @max_frame_size: Maximum Frame Size to be supported 794 * @cd: pointer to command details structure or NULL 795 * 796 * Set MAC configuration (0x0603) 797 */ 798 int 799 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 800 { 801 struct ice_aqc_set_mac_cfg *cmd; 802 struct libie_aq_desc desc; 803 804 cmd = libie_aq_raw(&desc); 805 806 if (max_frame_size == 0) 807 return -EINVAL; 808 809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 810 811 cmd->max_frame_size = cpu_to_le16(max_frame_size); 812 813 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 814 815 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 816 } 817 818 /** 819 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 820 * @hw: pointer to the HW struct 821 */ 822 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 823 { 824 struct ice_switch_info *sw; 825 int status; 826 827 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 828 sizeof(*hw->switch_info), GFP_KERNEL); 829 sw = hw->switch_info; 830 831 if (!sw) 832 return -ENOMEM; 833 834 INIT_LIST_HEAD(&sw->vsi_list_map_head); 835 sw->prof_res_bm_init = 0; 836 837 /* Initialize recipe count with default recipes read from NVM */ 838 sw->recp_cnt = ICE_SW_LKUP_LAST; 839 840 status = ice_init_def_sw_recp(hw); 841 if (status) { 842 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 843 return status; 844 } 845 return 0; 846 } 847 848 /** 849 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 850 * @hw: pointer to the HW struct 851 */ 852 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 853 { 854 struct ice_switch_info *sw = hw->switch_info; 855 struct ice_vsi_list_map_info *v_pos_map; 856 struct ice_vsi_list_map_info *v_tmp_map; 857 struct ice_sw_recipe *recps; 858 u8 i; 859 860 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 861 list_entry) { 862 list_del(&v_pos_map->list_entry); 863 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 864 } 865 recps = sw->recp_list; 866 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 867 recps[i].root_rid = i; 868 869 if (recps[i].adv_rule) { 870 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 871 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 872 873 mutex_destroy(&recps[i].filt_rule_lock); 874 list_for_each_entry_safe(lst_itr, tmp_entry, 875 &recps[i].filt_rules, 876 list_entry) { 877 list_del(&lst_itr->list_entry); 878 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 879 devm_kfree(ice_hw_to_dev(hw), lst_itr); 880 } 881 } else { 882 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 883 884 mutex_destroy(&recps[i].filt_rule_lock); 885 list_for_each_entry_safe(lst_itr, tmp_entry, 886 &recps[i].filt_rules, 887 list_entry) { 888 list_del(&lst_itr->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), lst_itr); 890 } 891 } 892 } 893 ice_rm_all_sw_replay_rule_info(hw); 894 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 895 devm_kfree(ice_hw_to_dev(hw), sw); 896 } 897 898 /** 899 * ice_get_itr_intrl_gran 900 * @hw: pointer to the HW struct 901 * 902 * Determines the ITR/INTRL granularities based on the maximum aggregate 903 * bandwidth according to the device's configuration during power-on. 904 */ 905 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 906 { 907 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 908 rd32(hw, GL_PWR_MODE_CTL)); 909 910 switch (max_agg_bw) { 911 case ICE_MAX_AGG_BW_200G: 912 case ICE_MAX_AGG_BW_100G: 913 case ICE_MAX_AGG_BW_50G: 914 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 915 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 916 break; 917 case ICE_MAX_AGG_BW_25G: 918 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 919 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 920 break; 921 } 922 } 923 924 /** 925 * ice_wait_fw_load - wait for PHY firmware loading to complete 926 * @hw: pointer to the hardware structure 927 * @timeout: milliseconds that can elapse before timing out, 0 to bypass waiting 928 * 929 * Return: 930 * * 0 on success 931 * * negative on timeout 932 */ 933 static int ice_wait_fw_load(struct ice_hw *hw, u32 timeout) 934 { 935 int fw_loading_reg; 936 937 if (!timeout) 938 return 0; 939 940 fw_loading_reg = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 941 /* notify the user only once if PHY FW is still loading */ 942 if (fw_loading_reg) 943 dev_info(ice_hw_to_dev(hw), "Link initialization is blocked by PHY FW initialization. Link initialization will continue after PHY FW initialization completes.\n"); 944 else 945 return 0; 946 947 return rd32_poll_timeout(hw, GL_MNG_FWSM, fw_loading_reg, 948 !(fw_loading_reg & GL_MNG_FWSM_FW_LOADING_M), 949 10000, timeout * 1000); 950 } 951 952 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 953 u16 size) 954 { 955 struct ice_hw *hw = priv; 956 957 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 958 } 959 960 static int __fwlog_init(struct ice_hw *hw) 961 { 962 struct ice_pf *pf = hw->back; 963 struct libie_fwlog_api api = { 964 .pdev = pf->pdev, 965 .send_cmd = __fwlog_send_cmd, 966 .priv = hw, 967 }; 968 int err; 969 970 /* only support fw log commands on PF 0 */ 971 if (hw->bus.func) 972 return -EINVAL; 973 974 err = ice_debugfs_pf_init(pf); 975 if (err) 976 return err; 977 978 api.debugfs_root = pf->ice_debugfs_pf; 979 980 return libie_fwlog_init(&hw->fwlog, &api); 981 } 982 983 /** 984 * ice_init_hw - main hardware initialization routine 985 * @hw: pointer to the hardware structure 986 */ 987 int ice_init_hw(struct ice_hw *hw) 988 { 989 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 990 void *mac_buf __free(kfree) = NULL; 991 u16 mac_buf_len; 992 int status; 993 994 /* Set MAC type based on DeviceID */ 995 status = ice_set_mac_type(hw); 996 if (status) 997 return status; 998 999 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1000 1001 status = ice_reset(hw, ICE_RESET_PFR); 1002 if (status) 1003 return status; 1004 1005 ice_get_itr_intrl_gran(hw); 1006 1007 status = ice_create_all_ctrlq(hw); 1008 if (status) 1009 goto err_unroll_cqinit; 1010 1011 status = __fwlog_init(hw); 1012 if (status) 1013 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1014 status); 1015 1016 status = ice_clear_pf_cfg(hw); 1017 if (status) 1018 goto err_unroll_cqinit; 1019 1020 /* Set bit to enable Flow Director filters */ 1021 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1022 INIT_LIST_HEAD(&hw->fdir_list_head); 1023 1024 ice_clear_pxe_mode(hw); 1025 1026 status = ice_init_nvm(hw); 1027 if (status) 1028 goto err_unroll_cqinit; 1029 1030 status = ice_get_caps(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 if (!hw->port_info) 1035 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1036 sizeof(*hw->port_info), 1037 GFP_KERNEL); 1038 if (!hw->port_info) { 1039 status = -ENOMEM; 1040 goto err_unroll_cqinit; 1041 } 1042 1043 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1044 /* set the back pointer to HW */ 1045 hw->port_info->hw = hw; 1046 1047 /* Initialize port_info struct with switch configuration data */ 1048 status = ice_get_initial_sw_cfg(hw); 1049 if (status) 1050 goto err_unroll_alloc; 1051 1052 hw->evb_veb = true; 1053 1054 /* init xarray for identifying scheduling nodes uniquely */ 1055 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1056 1057 /* Query the allocated resources for Tx scheduler */ 1058 status = ice_sched_query_res_alloc(hw); 1059 if (status) { 1060 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1061 goto err_unroll_alloc; 1062 } 1063 ice_sched_get_psm_clk_freq(hw); 1064 1065 /* Initialize port_info struct with scheduler data */ 1066 status = ice_sched_init_port(hw->port_info); 1067 if (status) 1068 goto err_unroll_sched; 1069 1070 pcaps = kzalloc_obj(*pcaps); 1071 if (!pcaps) { 1072 status = -ENOMEM; 1073 goto err_unroll_sched; 1074 } 1075 1076 /* Initialize port_info struct with PHY capabilities */ 1077 status = ice_aq_get_phy_caps(hw->port_info, false, 1078 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1079 NULL); 1080 if (status) 1081 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1082 status); 1083 1084 /* Initialize port_info struct with link information */ 1085 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1086 if (status) 1087 goto err_unroll_sched; 1088 1089 /* need a valid SW entry point to build a Tx tree */ 1090 if (!hw->sw_entry_point_layer) { 1091 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1092 status = -EIO; 1093 goto err_unroll_sched; 1094 } 1095 INIT_LIST_HEAD(&hw->agg_list); 1096 /* Initialize max burst size */ 1097 if (!hw->max_burst_size) 1098 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1099 1100 status = ice_init_fltr_mgmt_struct(hw); 1101 if (status) 1102 goto err_unroll_sched; 1103 1104 /* Get MAC information */ 1105 /* A single port can report up to two (LAN and WoL) addresses */ 1106 mac_buf = kzalloc_objs(struct ice_aqc_manage_mac_read_resp, 2); 1107 if (!mac_buf) { 1108 status = -ENOMEM; 1109 goto err_unroll_fltr_mgmt_struct; 1110 } 1111 1112 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1113 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1114 1115 if (status) 1116 goto err_unroll_fltr_mgmt_struct; 1117 /* enable jumbo frame support at MAC level */ 1118 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1119 if (status) 1120 goto err_unroll_fltr_mgmt_struct; 1121 /* Obtain counter base index which would be used by flow director */ 1122 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1123 if (status) 1124 goto err_unroll_fltr_mgmt_struct; 1125 status = ice_init_hw_tbls(hw); 1126 if (status) 1127 goto err_unroll_fltr_mgmt_struct; 1128 1129 mutex_init(&hw->tnl_lock); 1130 ice_init_chk_recipe_reuse_support(hw); 1131 1132 /* Some cards require longer initialization times 1133 * due to necessity of loading FW from an external source. 1134 * This can take even half a minute. 1135 */ 1136 status = ice_wait_fw_load(hw, 30000); 1137 if (status) { 1138 dev_err(ice_hw_to_dev(hw), "ice_wait_fw_load timed out"); 1139 goto err_unroll_fltr_mgmt_struct; 1140 } 1141 1142 hw->lane_num = ice_get_phy_lane_number(hw); 1143 1144 return 0; 1145 err_unroll_fltr_mgmt_struct: 1146 ice_cleanup_fltr_mgmt_struct(hw); 1147 err_unroll_sched: 1148 ice_sched_cleanup_all(hw); 1149 err_unroll_alloc: 1150 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1151 err_unroll_cqinit: 1152 ice_destroy_all_ctrlq(hw); 1153 return status; 1154 } 1155 1156 static void __fwlog_deinit(struct ice_hw *hw) 1157 { 1158 /* only support fw log commands on PF 0 */ 1159 if (hw->bus.func) 1160 return; 1161 1162 ice_debugfs_pf_deinit(hw->back); 1163 libie_fwlog_deinit(&hw->fwlog); 1164 } 1165 1166 /** 1167 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1168 * @hw: pointer to the hardware structure 1169 * 1170 * This should be called only during nominal operation, not as a result of 1171 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1172 * applicable initializations if it fails for any reason. 1173 */ 1174 void ice_deinit_hw(struct ice_hw *hw) 1175 { 1176 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1177 ice_cleanup_fltr_mgmt_struct(hw); 1178 1179 ice_sched_cleanup_all(hw); 1180 ice_sched_clear_agg(hw); 1181 ice_free_seg(hw); 1182 ice_free_hw_tbls(hw); 1183 mutex_destroy(&hw->tnl_lock); 1184 __fwlog_deinit(hw); 1185 ice_destroy_all_ctrlq(hw); 1186 1187 /* Clear VSI contexts if not already cleared */ 1188 ice_clear_all_vsi_ctx(hw); 1189 } 1190 1191 /** 1192 * ice_check_reset - Check to see if a global reset is complete 1193 * @hw: pointer to the hardware structure 1194 */ 1195 int ice_check_reset(struct ice_hw *hw) 1196 { 1197 u32 cnt, reg = 0, grst_timeout, uld_mask; 1198 1199 /* Poll for Device Active state in case a recent CORER, GLOBR, 1200 * or EMPR has occurred. The grst delay value is in 100ms units. 1201 * Add 1sec for outstanding AQ commands that can take a long time. 1202 */ 1203 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1204 rd32(hw, GLGEN_RSTCTL)) + 10; 1205 1206 for (cnt = 0; cnt < grst_timeout; cnt++) { 1207 mdelay(100); 1208 reg = rd32(hw, GLGEN_RSTAT); 1209 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1210 break; 1211 } 1212 1213 if (cnt == grst_timeout) { 1214 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1215 return -EIO; 1216 } 1217 1218 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1219 GLNVM_ULD_PCIER_DONE_1_M |\ 1220 GLNVM_ULD_CORER_DONE_M |\ 1221 GLNVM_ULD_GLOBR_DONE_M |\ 1222 GLNVM_ULD_POR_DONE_M |\ 1223 GLNVM_ULD_POR_DONE_1_M |\ 1224 GLNVM_ULD_PCIER_DONE_2_M) 1225 1226 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1227 GLNVM_ULD_PE_DONE_M : 0); 1228 1229 /* Device is Active; check Global Reset processes are done */ 1230 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1231 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1232 if (reg == uld_mask) { 1233 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1234 break; 1235 } 1236 mdelay(10); 1237 } 1238 1239 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1240 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1241 reg); 1242 return -EIO; 1243 } 1244 1245 return 0; 1246 } 1247 1248 /** 1249 * ice_pf_reset - Reset the PF 1250 * @hw: pointer to the hardware structure 1251 * 1252 * If a global reset has been triggered, this function checks 1253 * for its completion and then issues the PF reset 1254 */ 1255 static int ice_pf_reset(struct ice_hw *hw) 1256 { 1257 u32 cnt, reg; 1258 1259 /* If at function entry a global reset was already in progress, i.e. 1260 * state is not 'device active' or any of the reset done bits are not 1261 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1262 * global reset is done. 1263 */ 1264 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1265 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1266 /* poll on global reset currently in progress until done */ 1267 if (ice_check_reset(hw)) 1268 return -EIO; 1269 1270 return 0; 1271 } 1272 1273 /* Reset the PF */ 1274 reg = rd32(hw, PFGEN_CTRL); 1275 1276 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1277 1278 /* Wait for the PFR to complete. The wait time is the global config lock 1279 * timeout plus the PFR timeout which will account for a possible reset 1280 * that is occurring during a download package operation. 1281 */ 1282 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1283 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1284 reg = rd32(hw, PFGEN_CTRL); 1285 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1286 break; 1287 1288 mdelay(1); 1289 } 1290 1291 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1292 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1293 return -EIO; 1294 } 1295 1296 return 0; 1297 } 1298 1299 /** 1300 * ice_reset - Perform different types of reset 1301 * @hw: pointer to the hardware structure 1302 * @req: reset request 1303 * 1304 * This function triggers a reset as specified by the req parameter. 1305 * 1306 * Note: 1307 * If anything other than a PF reset is triggered, PXE mode is restored. 1308 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1309 * interface has been restored in the rebuild flow. 1310 */ 1311 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1312 { 1313 u32 val = 0; 1314 1315 switch (req) { 1316 case ICE_RESET_PFR: 1317 return ice_pf_reset(hw); 1318 case ICE_RESET_CORER: 1319 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1320 val = GLGEN_RTRIG_CORER_M; 1321 break; 1322 case ICE_RESET_GLOBR: 1323 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1324 val = GLGEN_RTRIG_GLOBR_M; 1325 break; 1326 default: 1327 return -EINVAL; 1328 } 1329 1330 val |= rd32(hw, GLGEN_RTRIG); 1331 wr32(hw, GLGEN_RTRIG, val); 1332 ice_flush(hw); 1333 1334 /* wait for the FW to be ready */ 1335 return ice_check_reset(hw); 1336 } 1337 1338 /** 1339 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1340 * @hw: pointer to the hardware structure 1341 * @rxq_ctx: pointer to the packed Rx queue context 1342 * @rxq_index: the index of the Rx queue 1343 */ 1344 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1345 const ice_rxq_ctx_buf_t *rxq_ctx, 1346 u32 rxq_index) 1347 { 1348 /* Copy each dword separately to HW */ 1349 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1350 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1351 1352 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1353 1354 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1355 } 1356 } 1357 1358 /** 1359 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1360 * @hw: pointer to the hardware structure 1361 * @rxq_ctx: pointer to the packed Rx queue context 1362 * @rxq_index: the index of the Rx queue 1363 */ 1364 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1365 ice_rxq_ctx_buf_t *rxq_ctx, 1366 u32 rxq_index) 1367 { 1368 u32 *ctx = (u32 *)rxq_ctx; 1369 1370 /* Copy each dword separately from HW */ 1371 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1372 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1373 1374 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1375 } 1376 } 1377 1378 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1379 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1380 1381 /* LAN Rx Queue Context */ 1382 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1383 /* Field Width LSB */ 1384 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1385 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1386 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1387 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1388 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1389 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1390 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1391 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1392 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1393 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1394 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1395 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1396 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1397 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1398 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1399 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1400 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1401 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1402 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1403 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1404 }; 1405 1406 /** 1407 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1408 * @ctx: the Rx queue context to pack 1409 * @buf: the HW buffer to pack into 1410 * 1411 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1412 * bit-packed HW layout. 1413 */ 1414 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1415 ice_rxq_ctx_buf_t *buf) 1416 { 1417 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1418 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1419 } 1420 1421 /** 1422 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1423 * @buf: the HW buffer to unpack from 1424 * @ctx: the Rx queue context to unpack 1425 * 1426 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1427 * structure. 1428 */ 1429 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1430 struct ice_rlan_ctx *ctx) 1431 { 1432 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1433 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1434 } 1435 1436 /** 1437 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1438 * @hw: pointer to the hardware structure 1439 * @rlan_ctx: pointer to the unpacked Rx queue context 1440 * @rxq_index: the index of the Rx queue 1441 * 1442 * Pack the sparse Rx Queue context into dense hardware format and write it 1443 * into the HW register space. 1444 * 1445 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1446 */ 1447 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1448 u32 rxq_index) 1449 { 1450 ice_rxq_ctx_buf_t buf = {}; 1451 1452 if (rxq_index > QRX_CTRL_MAX_INDEX) 1453 return -EINVAL; 1454 1455 ice_pack_rxq_ctx(rlan_ctx, &buf); 1456 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1457 1458 return 0; 1459 } 1460 1461 /** 1462 * ice_read_rxq_ctx - Read Rx queue context from HW 1463 * @hw: pointer to the hardware structure 1464 * @rlan_ctx: pointer to the Rx queue context 1465 * @rxq_index: the index of the Rx queue 1466 * 1467 * Read the Rx queue context from the hardware registers, and unpack it into 1468 * the sparse Rx queue context structure. 1469 * 1470 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1471 */ 1472 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1473 u32 rxq_index) 1474 { 1475 ice_rxq_ctx_buf_t buf = {}; 1476 1477 if (rxq_index > QRX_CTRL_MAX_INDEX) 1478 return -EINVAL; 1479 1480 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1481 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1482 1483 return 0; 1484 } 1485 1486 /* LAN Tx Queue Context */ 1487 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1488 /* Field Width LSB */ 1489 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1490 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1491 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1492 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1493 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1494 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1495 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1496 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1497 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1498 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1499 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1500 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1501 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1502 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1503 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1504 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1505 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1506 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1507 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1508 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1509 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1510 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1511 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1512 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1513 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1514 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1515 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1516 }; 1517 1518 /** 1519 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1520 * @ctx: the Tx queue context to pack 1521 * @buf: the Admin Queue HW buffer to pack into 1522 * 1523 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1524 * bit-packed Admin Queue layout. 1525 */ 1526 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1527 { 1528 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1529 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1530 } 1531 1532 /** 1533 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1534 * @ctx: the Tx queue context to pack 1535 * @buf: the HW buffer to pack into 1536 * 1537 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1538 * bit-packed HW layout, including the internal data portion. 1539 */ 1540 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1541 ice_txq_ctx_buf_full_t *buf) 1542 { 1543 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1544 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1545 } 1546 1547 /** 1548 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1549 * @buf: the HW buffer to unpack from 1550 * @ctx: the Tx queue context to unpack 1551 * 1552 * Unpack the Tx queue context from the HW buffer (including the full internal 1553 * state) into the CPU-friendly structure. 1554 */ 1555 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1556 struct ice_tlan_ctx *ctx) 1557 { 1558 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1559 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1560 } 1561 1562 /** 1563 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1564 * @hw: pointer to the hardware structure 1565 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1566 * @txq_index: the index of the Tx queue 1567 * 1568 * Copy Tx Queue context from HW register space to dense structure 1569 */ 1570 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1571 ice_txq_ctx_buf_full_t *txq_ctx, 1572 u32 txq_index) 1573 { 1574 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1575 u32 *ctx = (u32 *)txq_ctx; 1576 u32 txq_base, reg; 1577 1578 /* Get Tx queue base within card space */ 1579 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1580 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1581 1582 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1583 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1584 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1585 txq_base + txq_index) | 1586 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1587 1588 /* Prevent other PFs on the same adapter from accessing the Tx queue 1589 * context interface concurrently. 1590 */ 1591 spin_lock(&pf->adapter->txq_ctx_lock); 1592 1593 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1594 ice_flush(hw); 1595 1596 /* Copy each dword separately from HW */ 1597 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1598 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1599 1600 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1601 } 1602 1603 spin_unlock(&pf->adapter->txq_ctx_lock); 1604 } 1605 1606 /** 1607 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1608 * @hw: pointer to the hardware structure 1609 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1610 * @txq_index: the index of the Tx queue 1611 */ 1612 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1613 const ice_txq_ctx_buf_full_t *txq_ctx, 1614 u32 txq_index) 1615 { 1616 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1617 u32 txq_base, reg; 1618 1619 /* Get Tx queue base within card space */ 1620 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1621 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1622 1623 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1624 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1625 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1626 txq_base + txq_index) | 1627 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1628 1629 /* Prevent other PFs on the same adapter from accessing the Tx queue 1630 * context interface concurrently. 1631 */ 1632 spin_lock(&pf->adapter->txq_ctx_lock); 1633 1634 /* Copy each dword separately to HW */ 1635 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1636 u32 ctx = ((const u32 *)txq_ctx)[i]; 1637 1638 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1639 1640 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1641 } 1642 1643 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1644 ice_flush(hw); 1645 1646 spin_unlock(&pf->adapter->txq_ctx_lock); 1647 } 1648 1649 /** 1650 * ice_read_txq_ctx - Read Tx queue context from HW 1651 * @hw: pointer to the hardware structure 1652 * @tlan_ctx: pointer to the Tx queue context 1653 * @txq_index: the index of the Tx queue 1654 * 1655 * Read the Tx queue context from the HW registers, then unpack it into the 1656 * ice_tlan_ctx structure for use. 1657 * 1658 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1659 */ 1660 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1661 u32 txq_index) 1662 { 1663 ice_txq_ctx_buf_full_t buf = {}; 1664 1665 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1666 return -EINVAL; 1667 1668 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1669 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1670 1671 return 0; 1672 } 1673 1674 /** 1675 * ice_write_txq_ctx - Write Tx queue context to HW 1676 * @hw: pointer to the hardware structure 1677 * @tlan_ctx: pointer to the Tx queue context 1678 * @txq_index: the index of the Tx queue 1679 * 1680 * Pack the Tx queue context into the dense HW layout, then write it into the 1681 * HW registers. 1682 * 1683 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1684 */ 1685 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1686 u32 txq_index) 1687 { 1688 ice_txq_ctx_buf_full_t buf = {}; 1689 1690 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1691 return -EINVAL; 1692 1693 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1694 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1695 1696 return 0; 1697 } 1698 1699 /* Tx time Queue Context */ 1700 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1701 /* Field Width LSB */ 1702 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1703 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1704 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1705 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1706 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1707 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1708 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1709 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1710 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1711 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1712 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1713 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1714 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1715 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1716 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1717 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1718 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1719 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1720 }; 1721 1722 /** 1723 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1724 * @ctx: the Tx time queue context to pack 1725 * @buf: the HW buffer to pack into 1726 * 1727 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1728 * its bit-packed HW layout. 1729 */ 1730 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1731 ice_txtime_ctx_buf_t *buf) 1732 { 1733 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1734 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1735 } 1736 1737 /* Sideband Queue command wrappers */ 1738 1739 /** 1740 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1741 * @hw: pointer to the HW struct 1742 * @desc: descriptor describing the command 1743 * @buf: buffer to use for indirect commands (NULL for direct commands) 1744 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1745 * @cd: pointer to command details structure 1746 */ 1747 static int 1748 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1749 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1750 { 1751 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1752 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1753 } 1754 1755 /** 1756 * ice_sbq_rw_reg - Fill Sideband Queue command 1757 * @hw: pointer to the HW struct 1758 * @in: message info to be filled in descriptor 1759 * @flags: control queue descriptor flags 1760 */ 1761 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1762 { 1763 struct ice_sbq_cmd_desc desc = {0}; 1764 struct ice_sbq_msg_req msg = {0}; 1765 u16 msg_len; 1766 int status; 1767 1768 msg_len = sizeof(msg); 1769 1770 msg.dest_dev = in->dest_dev; 1771 msg.opcode = in->opcode; 1772 msg.flags = ICE_SBQ_MSG_FLAGS; 1773 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1774 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1775 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1776 1777 if (in->opcode) 1778 msg.data = cpu_to_le32(in->data); 1779 else 1780 /* data read comes back in completion, so shorten the struct by 1781 * sizeof(msg.data) 1782 */ 1783 msg_len -= sizeof(msg.data); 1784 1785 desc.flags = cpu_to_le16(flags); 1786 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1787 desc.param0.cmd_len = cpu_to_le16(msg_len); 1788 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1789 if (!status && !in->opcode) 1790 in->data = le32_to_cpu 1791 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1792 return status; 1793 } 1794 1795 /* FW Admin Queue command wrappers */ 1796 1797 /* Software lock/mutex that is meant to be held while the Global Config Lock 1798 * in firmware is acquired by the software to prevent most (but not all) types 1799 * of AQ commands from being sent to FW 1800 */ 1801 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1802 1803 /** 1804 * ice_should_retry_sq_send_cmd 1805 * @opcode: AQ opcode 1806 * 1807 * Decide if we should retry the send command routine for the ATQ, depending 1808 * on the opcode. 1809 */ 1810 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1811 { 1812 switch (opcode) { 1813 case ice_aqc_opc_get_link_topo: 1814 case ice_aqc_opc_lldp_stop: 1815 case ice_aqc_opc_lldp_start: 1816 case ice_aqc_opc_lldp_filter_ctrl: 1817 case ice_aqc_opc_sff_eeprom: 1818 return true; 1819 } 1820 1821 return false; 1822 } 1823 1824 /** 1825 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1826 * @hw: pointer to the HW struct 1827 * @cq: pointer to the specific Control queue 1828 * @desc: prefilled descriptor describing the command 1829 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1830 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1831 * @cd: pointer to command details structure 1832 * 1833 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1834 * Queue if the EBUSY AQ error is returned. 1835 */ 1836 static int 1837 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1838 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1839 struct ice_sq_cd *cd) 1840 { 1841 struct libie_aq_desc desc_cpy; 1842 bool is_cmd_for_retry; 1843 u8 *buf_cpy = NULL; 1844 u8 idx = 0; 1845 u16 opcode; 1846 int status; 1847 1848 opcode = le16_to_cpu(desc->opcode); 1849 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1850 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1851 1852 if (is_cmd_for_retry) { 1853 if (buf) { 1854 buf_cpy = kmemdup(buf, buf_size, GFP_KERNEL); 1855 if (!buf_cpy) 1856 return -ENOMEM; 1857 } 1858 1859 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1860 } 1861 1862 do { 1863 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1864 1865 if (!is_cmd_for_retry || !status || 1866 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1867 break; 1868 1869 if (buf_cpy) 1870 memcpy(buf, buf_cpy, buf_size); 1871 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1872 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1873 1874 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1875 1876 kfree(buf_cpy); 1877 return status; 1878 } 1879 1880 /** 1881 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1882 * @hw: pointer to the HW struct 1883 * @desc: descriptor describing the command 1884 * @buf: buffer to use for indirect commands (NULL for direct commands) 1885 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1886 * @cd: pointer to command details structure 1887 * 1888 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1889 */ 1890 int 1891 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1892 u16 buf_size, struct ice_sq_cd *cd) 1893 { 1894 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1895 bool lock_acquired = false; 1896 int status; 1897 1898 /* When a package download is in process (i.e. when the firmware's 1899 * Global Configuration Lock resource is held), only the Download 1900 * Package, Get Version, Get Package Info List, Upload Section, 1901 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1902 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1903 * Recipes to Profile Association, and Release Resource (with resource 1904 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1905 * must block until the package download completes and the Global Config 1906 * Lock is released. See also ice_acquire_global_cfg_lock(). 1907 */ 1908 switch (le16_to_cpu(desc->opcode)) { 1909 case ice_aqc_opc_download_pkg: 1910 case ice_aqc_opc_get_pkg_info_list: 1911 case ice_aqc_opc_get_ver: 1912 case ice_aqc_opc_upload_section: 1913 case ice_aqc_opc_update_pkg: 1914 case ice_aqc_opc_set_port_params: 1915 case ice_aqc_opc_get_vlan_mode_parameters: 1916 case ice_aqc_opc_set_vlan_mode_parameters: 1917 case ice_aqc_opc_set_tx_topo: 1918 case ice_aqc_opc_get_tx_topo: 1919 case ice_aqc_opc_add_recipe: 1920 case ice_aqc_opc_recipe_to_profile: 1921 case ice_aqc_opc_get_recipe: 1922 case ice_aqc_opc_get_recipe_to_profile: 1923 break; 1924 case ice_aqc_opc_release_res: 1925 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1926 break; 1927 fallthrough; 1928 default: 1929 mutex_lock(&ice_global_cfg_lock_sw); 1930 lock_acquired = true; 1931 break; 1932 } 1933 1934 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1935 if (lock_acquired) 1936 mutex_unlock(&ice_global_cfg_lock_sw); 1937 1938 return status; 1939 } 1940 1941 /** 1942 * ice_aq_get_fw_ver 1943 * @hw: pointer to the HW struct 1944 * @cd: pointer to command details structure or NULL 1945 * 1946 * Get the firmware version (0x0001) from the admin queue commands 1947 */ 1948 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1949 { 1950 struct libie_aqc_get_ver *resp; 1951 struct libie_aq_desc desc; 1952 int status; 1953 1954 resp = &desc.params.get_ver; 1955 1956 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1957 1958 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1959 1960 if (!status) { 1961 hw->fw_branch = resp->fw_branch; 1962 hw->fw_maj_ver = resp->fw_major; 1963 hw->fw_min_ver = resp->fw_minor; 1964 hw->fw_patch = resp->fw_patch; 1965 hw->fw_build = le32_to_cpu(resp->fw_build); 1966 hw->api_branch = resp->api_branch; 1967 hw->api_maj_ver = resp->api_major; 1968 hw->api_min_ver = resp->api_minor; 1969 hw->api_patch = resp->api_patch; 1970 } 1971 1972 return status; 1973 } 1974 1975 /** 1976 * ice_aq_send_driver_ver 1977 * @hw: pointer to the HW struct 1978 * @dv: driver's major, minor version 1979 * @cd: pointer to command details structure or NULL 1980 * 1981 * Send the driver version (0x0002) to the firmware 1982 */ 1983 int 1984 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1985 struct ice_sq_cd *cd) 1986 { 1987 struct libie_aqc_driver_ver *cmd; 1988 struct libie_aq_desc desc; 1989 u16 len; 1990 1991 cmd = &desc.params.driver_ver; 1992 1993 if (!dv) 1994 return -EINVAL; 1995 1996 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1997 1998 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1999 cmd->major_ver = dv->major_ver; 2000 cmd->minor_ver = dv->minor_ver; 2001 cmd->build_ver = dv->build_ver; 2002 cmd->subbuild_ver = dv->subbuild_ver; 2003 2004 len = 0; 2005 while (len < sizeof(dv->driver_string) && 2006 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2007 len++; 2008 2009 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2010 } 2011 2012 /** 2013 * ice_aq_q_shutdown 2014 * @hw: pointer to the HW struct 2015 * @unloading: is the driver unloading itself 2016 * 2017 * Tell the Firmware that we're shutting down the AdminQ and whether 2018 * or not the driver is unloading as well (0x0003). 2019 */ 2020 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2021 { 2022 struct ice_aqc_q_shutdown *cmd; 2023 struct libie_aq_desc desc; 2024 2025 cmd = libie_aq_raw(&desc); 2026 2027 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2028 2029 if (unloading) 2030 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2031 2032 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2033 } 2034 2035 /** 2036 * ice_aq_req_res 2037 * @hw: pointer to the HW struct 2038 * @res: resource ID 2039 * @access: access type 2040 * @sdp_number: resource number 2041 * @timeout: the maximum time in ms that the driver may hold the resource 2042 * @cd: pointer to command details structure or NULL 2043 * 2044 * Requests common resource using the admin queue commands (0x0008). 2045 * When attempting to acquire the Global Config Lock, the driver can 2046 * learn of three states: 2047 * 1) 0 - acquired lock, and can perform download package 2048 * 2) -EIO - did not get lock, driver should fail to load 2049 * 3) -EALREADY - did not get lock, but another driver has 2050 * successfully downloaded the package; the driver does 2051 * not have to download the package and can continue 2052 * loading 2053 * 2054 * Note that if the caller is in an acquire lock, perform action, release lock 2055 * phase of operation, it is possible that the FW may detect a timeout and issue 2056 * a CORER. In this case, the driver will receive a CORER interrupt and will 2057 * have to determine its cause. The calling thread that is handling this flow 2058 * will likely get an error propagated back to it indicating the Download 2059 * Package, Update Package or the Release Resource AQ commands timed out. 2060 */ 2061 static int 2062 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2063 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2064 struct ice_sq_cd *cd) 2065 { 2066 struct libie_aqc_req_res *cmd_resp; 2067 struct libie_aq_desc desc; 2068 int status; 2069 2070 cmd_resp = &desc.params.res_owner; 2071 2072 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2073 2074 cmd_resp->res_id = cpu_to_le16(res); 2075 cmd_resp->access_type = cpu_to_le16(access); 2076 cmd_resp->res_number = cpu_to_le32(sdp_number); 2077 cmd_resp->timeout = cpu_to_le32(*timeout); 2078 *timeout = 0; 2079 2080 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2081 2082 /* The completion specifies the maximum time in ms that the driver 2083 * may hold the resource in the Timeout field. 2084 */ 2085 2086 /* Global config lock response utilizes an additional status field. 2087 * 2088 * If the Global config lock resource is held by some other driver, the 2089 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2090 * and the timeout field indicates the maximum time the current owner 2091 * of the resource has to free it. 2092 */ 2093 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2094 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2095 *timeout = le32_to_cpu(cmd_resp->timeout); 2096 return 0; 2097 } else if (le16_to_cpu(cmd_resp->status) == 2098 LIBIE_AQ_RES_GLBL_IN_PROG) { 2099 *timeout = le32_to_cpu(cmd_resp->timeout); 2100 return -EIO; 2101 } else if (le16_to_cpu(cmd_resp->status) == 2102 LIBIE_AQ_RES_GLBL_DONE) { 2103 return -EALREADY; 2104 } 2105 2106 /* invalid FW response, force a timeout immediately */ 2107 *timeout = 0; 2108 return -EIO; 2109 } 2110 2111 /* If the resource is held by some other driver, the command completes 2112 * with a busy return value and the timeout field indicates the maximum 2113 * time the current owner of the resource has to free it. 2114 */ 2115 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2116 *timeout = le32_to_cpu(cmd_resp->timeout); 2117 2118 return status; 2119 } 2120 2121 /** 2122 * ice_aq_release_res 2123 * @hw: pointer to the HW struct 2124 * @res: resource ID 2125 * @sdp_number: resource number 2126 * @cd: pointer to command details structure or NULL 2127 * 2128 * release common resource using the admin queue commands (0x0009) 2129 */ 2130 static int 2131 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2132 struct ice_sq_cd *cd) 2133 { 2134 struct libie_aqc_req_res *cmd; 2135 struct libie_aq_desc desc; 2136 2137 cmd = &desc.params.res_owner; 2138 2139 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2140 2141 cmd->res_id = cpu_to_le16(res); 2142 cmd->res_number = cpu_to_le32(sdp_number); 2143 2144 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2145 } 2146 2147 /** 2148 * ice_acquire_res 2149 * @hw: pointer to the HW structure 2150 * @res: resource ID 2151 * @access: access type (read or write) 2152 * @timeout: timeout in milliseconds 2153 * 2154 * This function will attempt to acquire the ownership of a resource. 2155 */ 2156 int 2157 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2158 enum ice_aq_res_access_type access, u32 timeout) 2159 { 2160 #define ICE_RES_POLLING_DELAY_MS 10 2161 u32 delay = ICE_RES_POLLING_DELAY_MS; 2162 u32 time_left = timeout; 2163 int status; 2164 2165 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2166 2167 /* A return code of -EALREADY means that another driver has 2168 * previously acquired the resource and performed any necessary updates; 2169 * in this case the caller does not obtain the resource and has no 2170 * further work to do. 2171 */ 2172 if (status == -EALREADY) 2173 goto ice_acquire_res_exit; 2174 2175 if (status) 2176 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2177 2178 /* If necessary, poll until the current lock owner timeouts */ 2179 timeout = time_left; 2180 while (status && timeout && time_left) { 2181 mdelay(delay); 2182 timeout = (timeout > delay) ? timeout - delay : 0; 2183 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2184 2185 if (status == -EALREADY) 2186 /* lock free, but no work to do */ 2187 break; 2188 2189 if (!status) 2190 /* lock acquired */ 2191 break; 2192 } 2193 if (status && status != -EALREADY) 2194 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2195 2196 ice_acquire_res_exit: 2197 if (status == -EALREADY) { 2198 if (access == ICE_RES_WRITE) 2199 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2200 else 2201 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2202 } 2203 return status; 2204 } 2205 2206 /** 2207 * ice_release_res 2208 * @hw: pointer to the HW structure 2209 * @res: resource ID 2210 * 2211 * This function will release a resource using the proper Admin Command. 2212 */ 2213 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2214 { 2215 unsigned long timeout; 2216 int status; 2217 2218 /* there are some rare cases when trying to release the resource 2219 * results in an admin queue timeout, so handle them correctly 2220 */ 2221 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2222 do { 2223 status = ice_aq_release_res(hw, res, 0, NULL); 2224 if (status != -EIO) 2225 break; 2226 usleep_range(1000, 2000); 2227 } while (time_before(jiffies, timeout)); 2228 } 2229 2230 /** 2231 * ice_aq_alloc_free_res - command to allocate/free resources 2232 * @hw: pointer to the HW struct 2233 * @buf: Indirect buffer to hold data parameters and response 2234 * @buf_size: size of buffer for indirect commands 2235 * @opc: pass in the command opcode 2236 * 2237 * Helper function to allocate/free resources using the admin queue commands 2238 */ 2239 int ice_aq_alloc_free_res(struct ice_hw *hw, 2240 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2241 enum ice_adminq_opc opc) 2242 { 2243 struct ice_aqc_alloc_free_res_cmd *cmd; 2244 struct libie_aq_desc desc; 2245 2246 cmd = libie_aq_raw(&desc); 2247 2248 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2249 return -EINVAL; 2250 2251 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2252 2253 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2254 2255 cmd->num_entries = cpu_to_le16(1); 2256 2257 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2258 } 2259 2260 /** 2261 * ice_alloc_hw_res - allocate resource 2262 * @hw: pointer to the HW struct 2263 * @type: type of resource 2264 * @num: number of resources to allocate 2265 * @btm: allocate from bottom 2266 * @res: pointer to array that will receive the resources 2267 */ 2268 int 2269 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2270 { 2271 struct ice_aqc_alloc_free_res_elem *buf; 2272 u16 buf_len; 2273 int status; 2274 2275 buf_len = struct_size(buf, elem, num); 2276 buf = kzalloc(buf_len, GFP_KERNEL); 2277 if (!buf) 2278 return -ENOMEM; 2279 2280 /* Prepare buffer to allocate resource. */ 2281 buf->num_elems = cpu_to_le16(num); 2282 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2283 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2284 if (btm) 2285 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2286 2287 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2288 if (status) 2289 goto ice_alloc_res_exit; 2290 2291 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2292 2293 ice_alloc_res_exit: 2294 kfree(buf); 2295 return status; 2296 } 2297 2298 /** 2299 * ice_free_hw_res - free allocated HW resource 2300 * @hw: pointer to the HW struct 2301 * @type: type of resource to free 2302 * @num: number of resources 2303 * @res: pointer to array that contains the resources to free 2304 */ 2305 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2306 { 2307 struct ice_aqc_alloc_free_res_elem *buf; 2308 u16 buf_len; 2309 int status; 2310 2311 buf_len = struct_size(buf, elem, num); 2312 buf = kzalloc(buf_len, GFP_KERNEL); 2313 if (!buf) 2314 return -ENOMEM; 2315 2316 /* Prepare buffer to free resource. */ 2317 buf->num_elems = cpu_to_le16(num); 2318 buf->res_type = cpu_to_le16(type); 2319 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2320 2321 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2322 if (status) 2323 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2324 2325 kfree(buf); 2326 return status; 2327 } 2328 2329 /** 2330 * ice_get_num_per_func - determine number of resources per PF 2331 * @hw: pointer to the HW structure 2332 * @max: value to be evenly split between each PF 2333 * 2334 * Determine the number of valid functions by going through the bitmap returned 2335 * from parsing capabilities and use this to calculate the number of resources 2336 * per PF based on the max value passed in. 2337 */ 2338 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2339 { 2340 u8 funcs; 2341 2342 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2343 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2344 ICE_CAPS_VALID_FUNCS_M); 2345 2346 if (!funcs) 2347 return 0; 2348 2349 return max / funcs; 2350 } 2351 2352 /** 2353 * ice_parse_common_caps - parse common device/function capabilities 2354 * @hw: pointer to the HW struct 2355 * @caps: pointer to common capabilities structure 2356 * @elem: the capability element to parse 2357 * @prefix: message prefix for tracing capabilities 2358 * 2359 * Given a capability element, extract relevant details into the common 2360 * capability structure. 2361 * 2362 * Returns: true if the capability matches one of the common capability ids, 2363 * false otherwise. 2364 */ 2365 static bool 2366 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2367 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2368 { 2369 u32 logical_id = le32_to_cpu(elem->logical_id); 2370 u32 phys_id = le32_to_cpu(elem->phys_id); 2371 u32 number = le32_to_cpu(elem->number); 2372 u16 cap = le16_to_cpu(elem->cap); 2373 bool found = true; 2374 2375 switch (cap) { 2376 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2377 caps->valid_functions = number; 2378 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2379 caps->valid_functions); 2380 break; 2381 case LIBIE_AQC_CAPS_SRIOV: 2382 caps->sr_iov_1_1 = (number == 1); 2383 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2384 caps->sr_iov_1_1); 2385 break; 2386 case LIBIE_AQC_CAPS_DCB: 2387 caps->dcb = (number == 1); 2388 caps->active_tc_bitmap = logical_id; 2389 caps->maxtc = phys_id; 2390 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2391 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2392 caps->active_tc_bitmap); 2393 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2394 break; 2395 case LIBIE_AQC_CAPS_RSS: 2396 caps->rss_table_size = number; 2397 caps->rss_table_entry_width = logical_id; 2398 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2399 caps->rss_table_size); 2400 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2401 caps->rss_table_entry_width); 2402 break; 2403 case LIBIE_AQC_CAPS_RXQS: 2404 caps->num_rxq = number; 2405 caps->rxq_first_id = phys_id; 2406 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2407 caps->num_rxq); 2408 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2409 caps->rxq_first_id); 2410 break; 2411 case LIBIE_AQC_CAPS_TXQS: 2412 caps->num_txq = number; 2413 caps->txq_first_id = phys_id; 2414 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2415 caps->num_txq); 2416 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2417 caps->txq_first_id); 2418 break; 2419 case LIBIE_AQC_CAPS_MSIX: 2420 caps->num_msix_vectors = number; 2421 caps->msix_vector_first_id = phys_id; 2422 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2423 caps->num_msix_vectors); 2424 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2425 caps->msix_vector_first_id); 2426 break; 2427 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2428 caps->nvm_update_pending_nvm = true; 2429 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2430 break; 2431 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2432 caps->nvm_update_pending_orom = true; 2433 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2434 break; 2435 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2436 caps->nvm_update_pending_netlist = true; 2437 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2438 break; 2439 case LIBIE_AQC_CAPS_NVM_MGMT: 2440 caps->nvm_unified_update = 2441 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2442 true : false; 2443 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2444 caps->nvm_unified_update); 2445 break; 2446 case LIBIE_AQC_CAPS_RDMA: 2447 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2448 caps->rdma = (number == 1); 2449 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2450 break; 2451 case LIBIE_AQC_CAPS_MAX_MTU: 2452 caps->max_mtu = number; 2453 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2454 prefix, caps->max_mtu); 2455 break; 2456 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2457 caps->pcie_reset_avoidance = (number > 0); 2458 ice_debug(hw, ICE_DBG_INIT, 2459 "%s: pcie_reset_avoidance = %d\n", prefix, 2460 caps->pcie_reset_avoidance); 2461 break; 2462 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2463 caps->reset_restrict_support = (number == 1); 2464 ice_debug(hw, ICE_DBG_INIT, 2465 "%s: reset_restrict_support = %d\n", prefix, 2466 caps->reset_restrict_support); 2467 break; 2468 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2469 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2470 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2471 prefix, caps->roce_lag); 2472 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2473 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2474 prefix, caps->sriov_lag); 2475 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2476 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2477 prefix, caps->sriov_aa_lag); 2478 break; 2479 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2480 caps->tx_sched_topo_comp_mode_en = (number == 1); 2481 break; 2482 default: 2483 /* Not one of the recognized common capabilities */ 2484 found = false; 2485 } 2486 2487 return found; 2488 } 2489 2490 /** 2491 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2492 * @hw: pointer to the HW structure 2493 * @caps: pointer to capabilities structure to fix 2494 * 2495 * Re-calculate the capabilities that are dependent on the number of physical 2496 * ports; i.e. some features are not supported or function differently on 2497 * devices with more than 4 ports. 2498 */ 2499 static void 2500 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2501 { 2502 /* This assumes device capabilities are always scanned before function 2503 * capabilities during the initialization flow. 2504 */ 2505 if (hw->dev_caps.num_funcs > 4) { 2506 /* Max 4 TCs per port */ 2507 caps->maxtc = 4; 2508 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2509 caps->maxtc); 2510 if (caps->rdma) { 2511 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2512 caps->rdma = 0; 2513 } 2514 2515 /* print message only when processing device capabilities 2516 * during initialization. 2517 */ 2518 if (caps == &hw->dev_caps.common_cap) 2519 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2520 } 2521 } 2522 2523 /** 2524 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2525 * @hw: pointer to the HW struct 2526 * @func_p: pointer to function capabilities structure 2527 * @cap: pointer to the capability element to parse 2528 * 2529 * Extract function capabilities for ICE_AQC_CAPS_VF. 2530 */ 2531 static void 2532 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2533 struct libie_aqc_list_caps_elem *cap) 2534 { 2535 u32 logical_id = le32_to_cpu(cap->logical_id); 2536 u32 number = le32_to_cpu(cap->number); 2537 2538 func_p->num_allocd_vfs = number; 2539 func_p->vf_base_id = logical_id; 2540 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2541 func_p->num_allocd_vfs); 2542 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2543 func_p->vf_base_id); 2544 } 2545 2546 /** 2547 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2548 * @hw: pointer to the HW struct 2549 * @func_p: pointer to function capabilities structure 2550 * @cap: pointer to the capability element to parse 2551 * 2552 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2553 */ 2554 static void 2555 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2556 struct libie_aqc_list_caps_elem *cap) 2557 { 2558 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2559 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2560 le32_to_cpu(cap->number)); 2561 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2562 func_p->guar_num_vsi); 2563 } 2564 2565 /** 2566 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2567 * @hw: pointer to the HW struct 2568 * @func_p: pointer to function capabilities structure 2569 * @cap: pointer to the capability element to parse 2570 * 2571 * Extract function capabilities for ICE_AQC_CAPS_1588. 2572 */ 2573 static void 2574 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2575 struct libie_aqc_list_caps_elem *cap) 2576 { 2577 struct ice_ts_func_info *info = &func_p->ts_func_info; 2578 u32 number = le32_to_cpu(cap->number); 2579 2580 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2581 func_p->common_cap.ieee_1588 = info->ena; 2582 2583 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2584 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2585 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2586 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2587 2588 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2589 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2590 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2591 } else { 2592 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2593 info->clk_src = ICE_CLK_SRC_TIME_REF; 2594 } 2595 2596 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2597 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2598 } else { 2599 /* Unknown clock frequency, so assume a (probably incorrect) 2600 * default to avoid out-of-bounds look ups of frequency 2601 * related information. 2602 */ 2603 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2604 info->clk_freq); 2605 info->time_ref = ICE_TSPLL_FREQ_25_000; 2606 } 2607 2608 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2609 func_p->common_cap.ieee_1588); 2610 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2611 info->src_tmr_owned); 2612 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2613 info->tmr_ena); 2614 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2615 info->tmr_index_owned); 2616 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2617 info->tmr_index_assoc); 2618 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2619 info->clk_freq); 2620 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2621 info->clk_src); 2622 } 2623 2624 /** 2625 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2626 * @hw: pointer to the HW struct 2627 * @func_p: pointer to function capabilities structure 2628 * 2629 * Extract function capabilities for ICE_AQC_CAPS_FD. 2630 */ 2631 static void 2632 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2633 { 2634 u32 reg_val, gsize, bsize; 2635 2636 reg_val = rd32(hw, GLQF_FD_SIZE); 2637 switch (hw->mac_type) { 2638 case ICE_MAC_E830: 2639 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2640 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2641 break; 2642 case ICE_MAC_E810: 2643 default: 2644 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2645 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2646 } 2647 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2648 func_p->fd_fltr_best_effort = bsize; 2649 2650 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2651 func_p->fd_fltr_guar); 2652 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2653 func_p->fd_fltr_best_effort); 2654 } 2655 2656 /** 2657 * ice_parse_func_caps - Parse function capabilities 2658 * @hw: pointer to the HW struct 2659 * @func_p: pointer to function capabilities structure 2660 * @buf: buffer containing the function capability records 2661 * @cap_count: the number of capabilities 2662 * 2663 * Helper function to parse function (0x000A) capabilities list. For 2664 * capabilities shared between device and function, this relies on 2665 * ice_parse_common_caps. 2666 * 2667 * Loop through the list of provided capabilities and extract the relevant 2668 * data into the function capabilities structured. 2669 */ 2670 static void 2671 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2672 void *buf, u32 cap_count) 2673 { 2674 struct libie_aqc_list_caps_elem *cap_resp; 2675 u32 i; 2676 2677 cap_resp = buf; 2678 2679 memset(func_p, 0, sizeof(*func_p)); 2680 2681 for (i = 0; i < cap_count; i++) { 2682 u16 cap = le16_to_cpu(cap_resp[i].cap); 2683 bool found; 2684 2685 found = ice_parse_common_caps(hw, &func_p->common_cap, 2686 &cap_resp[i], "func caps"); 2687 2688 switch (cap) { 2689 case LIBIE_AQC_CAPS_VF: 2690 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2691 break; 2692 case LIBIE_AQC_CAPS_VSI: 2693 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2694 break; 2695 case LIBIE_AQC_CAPS_1588: 2696 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2697 break; 2698 case LIBIE_AQC_CAPS_FD: 2699 ice_parse_fdir_func_caps(hw, func_p); 2700 break; 2701 default: 2702 /* Don't list common capabilities as unknown */ 2703 if (!found) 2704 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2705 i, cap); 2706 break; 2707 } 2708 } 2709 2710 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2711 } 2712 2713 /** 2714 * ice_func_id_to_logical_id - map from function id to logical pf id 2715 * @active_function_bitmap: active function bitmap 2716 * @pf_id: function number of device 2717 * 2718 * Return: logical PF ID. 2719 */ 2720 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2721 { 2722 u8 logical_id = 0; 2723 u8 i; 2724 2725 for (i = 0; i < pf_id; i++) 2726 if (active_function_bitmap & BIT(i)) 2727 logical_id++; 2728 2729 return logical_id; 2730 } 2731 2732 /** 2733 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2734 * @hw: pointer to the HW struct 2735 * @dev_p: pointer to device capabilities structure 2736 * @cap: capability element to parse 2737 * 2738 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2739 */ 2740 static void 2741 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2742 struct libie_aqc_list_caps_elem *cap) 2743 { 2744 u32 number = le32_to_cpu(cap->number); 2745 2746 dev_p->num_funcs = hweight32(number); 2747 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2748 dev_p->num_funcs); 2749 2750 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2751 } 2752 2753 /** 2754 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2755 * @hw: pointer to the HW struct 2756 * @dev_p: pointer to device capabilities structure 2757 * @cap: capability element to parse 2758 * 2759 * Parse ICE_AQC_CAPS_VF for device capabilities. 2760 */ 2761 static void 2762 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2763 struct libie_aqc_list_caps_elem *cap) 2764 { 2765 u32 number = le32_to_cpu(cap->number); 2766 2767 dev_p->num_vfs_exposed = number; 2768 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2769 dev_p->num_vfs_exposed); 2770 } 2771 2772 /** 2773 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2774 * @hw: pointer to the HW struct 2775 * @dev_p: pointer to device capabilities structure 2776 * @cap: capability element to parse 2777 * 2778 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2779 */ 2780 static void 2781 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2782 struct libie_aqc_list_caps_elem *cap) 2783 { 2784 u32 number = le32_to_cpu(cap->number); 2785 2786 dev_p->num_vsi_allocd_to_host = number; 2787 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2788 dev_p->num_vsi_allocd_to_host); 2789 } 2790 2791 /** 2792 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2793 * @hw: pointer to the HW struct 2794 * @dev_p: pointer to device capabilities structure 2795 * @cap: capability element to parse 2796 * 2797 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2798 */ 2799 static void 2800 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2801 struct libie_aqc_list_caps_elem *cap) 2802 { 2803 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2804 u32 logical_id = le32_to_cpu(cap->logical_id); 2805 u32 phys_id = le32_to_cpu(cap->phys_id); 2806 u32 number = le32_to_cpu(cap->number); 2807 2808 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2809 dev_p->common_cap.ieee_1588 = info->ena; 2810 2811 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2812 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2813 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2814 2815 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2816 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2817 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2818 2819 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2820 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2821 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2822 2823 info->ena_ports = logical_id; 2824 info->tmr_own_map = phys_id; 2825 2826 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2827 dev_p->common_cap.ieee_1588); 2828 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2829 info->tmr0_owner); 2830 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2831 info->tmr0_owned); 2832 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2833 info->tmr0_ena); 2834 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2835 info->tmr1_owner); 2836 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2837 info->tmr1_owned); 2838 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2839 info->tmr1_ena); 2840 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2841 info->ts_ll_read); 2842 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2843 info->ts_ll_int_read); 2844 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2845 info->ll_phy_tmr_update); 2846 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2847 info->ena_ports); 2848 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2849 info->tmr_own_map); 2850 } 2851 2852 /** 2853 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2854 * @hw: pointer to the HW struct 2855 * @dev_p: pointer to device capabilities structure 2856 * @cap: capability element to parse 2857 * 2858 * Parse ICE_AQC_CAPS_FD for device capabilities. 2859 */ 2860 static void 2861 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2862 struct libie_aqc_list_caps_elem *cap) 2863 { 2864 u32 number = le32_to_cpu(cap->number); 2865 2866 dev_p->num_flow_director_fltr = number; 2867 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2868 dev_p->num_flow_director_fltr); 2869 } 2870 2871 /** 2872 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2873 * @hw: pointer to the HW struct 2874 * @dev_p: pointer to device capabilities structure 2875 * @cap: capability element to parse 2876 * 2877 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2878 * enabled sensors. 2879 */ 2880 static void 2881 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2882 struct libie_aqc_list_caps_elem *cap) 2883 { 2884 dev_p->supported_sensors = le32_to_cpu(cap->number); 2885 2886 ice_debug(hw, ICE_DBG_INIT, 2887 "dev caps: supported sensors (bitmap) = 0x%x\n", 2888 dev_p->supported_sensors); 2889 } 2890 2891 /** 2892 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2893 * @hw: pointer to the HW struct 2894 * @dev_p: pointer to device capabilities structure 2895 * @cap: capability element to parse 2896 * 2897 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2898 */ 2899 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2900 struct ice_hw_dev_caps *dev_p, 2901 struct libie_aqc_list_caps_elem *cap) 2902 { 2903 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2904 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2905 2906 dev_info(ice_hw_to_dev(hw), 2907 "PF is configured in %s mode with IP instance ID %d\n", 2908 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2909 "primary" : "secondary", dev_p->nac_topo.id); 2910 2911 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2912 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2913 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2914 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2915 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2916 dev_p->nac_topo.id); 2917 } 2918 2919 /** 2920 * ice_parse_dev_caps - Parse device capabilities 2921 * @hw: pointer to the HW struct 2922 * @dev_p: pointer to device capabilities structure 2923 * @buf: buffer containing the device capability records 2924 * @cap_count: the number of capabilities 2925 * 2926 * Helper device to parse device (0x000B) capabilities list. For 2927 * capabilities shared between device and function, this relies on 2928 * ice_parse_common_caps. 2929 * 2930 * Loop through the list of provided capabilities and extract the relevant 2931 * data into the device capabilities structured. 2932 */ 2933 static void 2934 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2935 void *buf, u32 cap_count) 2936 { 2937 struct libie_aqc_list_caps_elem *cap_resp; 2938 u32 i; 2939 2940 cap_resp = buf; 2941 2942 memset(dev_p, 0, sizeof(*dev_p)); 2943 2944 for (i = 0; i < cap_count; i++) { 2945 u16 cap = le16_to_cpu(cap_resp[i].cap); 2946 bool found; 2947 2948 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2949 &cap_resp[i], "dev caps"); 2950 2951 switch (cap) { 2952 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2953 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2954 break; 2955 case LIBIE_AQC_CAPS_VF: 2956 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2957 break; 2958 case LIBIE_AQC_CAPS_VSI: 2959 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2960 break; 2961 case LIBIE_AQC_CAPS_1588: 2962 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2963 break; 2964 case LIBIE_AQC_CAPS_FD: 2965 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2966 break; 2967 case LIBIE_AQC_CAPS_SENSOR_READING: 2968 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2969 break; 2970 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2971 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2972 break; 2973 default: 2974 /* Don't list common capabilities as unknown */ 2975 if (!found) 2976 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2977 i, cap); 2978 break; 2979 } 2980 } 2981 2982 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2983 } 2984 2985 /** 2986 * ice_is_phy_rclk_in_netlist 2987 * @hw: pointer to the hw struct 2988 * 2989 * Check if the PHY Recovered Clock device is present in the netlist 2990 */ 2991 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2992 { 2993 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2994 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2995 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2996 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2997 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2998 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 2999 return false; 3000 3001 return true; 3002 } 3003 3004 /** 3005 * ice_is_clock_mux_in_netlist 3006 * @hw: pointer to the hw struct 3007 * 3008 * Check if the Clock Multiplexer device is present in the netlist 3009 */ 3010 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3011 { 3012 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3013 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3014 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3015 NULL)) 3016 return false; 3017 3018 return true; 3019 } 3020 3021 /** 3022 * ice_is_cgu_in_netlist - check for CGU presence 3023 * @hw: pointer to the hw struct 3024 * 3025 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3026 * Save the CGU part number in the hw structure for later use. 3027 * Return: 3028 * * true - cgu is present 3029 * * false - cgu is not present 3030 */ 3031 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3032 { 3033 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3034 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3035 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3036 NULL)) { 3037 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3038 return true; 3039 } else if (!ice_find_netlist_node(hw, 3040 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3041 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3042 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3043 NULL)) { 3044 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3045 return true; 3046 } 3047 3048 return false; 3049 } 3050 3051 /** 3052 * ice_is_gps_in_netlist 3053 * @hw: pointer to the hw struct 3054 * 3055 * Check if the GPS generic device is present in the netlist 3056 */ 3057 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3058 { 3059 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3060 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3061 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3062 return false; 3063 3064 return true; 3065 } 3066 3067 /** 3068 * ice_aq_list_caps - query function/device capabilities 3069 * @hw: pointer to the HW struct 3070 * @buf: a buffer to hold the capabilities 3071 * @buf_size: size of the buffer 3072 * @cap_count: if not NULL, set to the number of capabilities reported 3073 * @opc: capabilities type to discover, device or function 3074 * @cd: pointer to command details structure or NULL 3075 * 3076 * Get the function (0x000A) or device (0x000B) capabilities description from 3077 * firmware and store it in the buffer. 3078 * 3079 * If the cap_count pointer is not NULL, then it is set to the number of 3080 * capabilities firmware will report. Note that if the buffer size is too 3081 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3082 * cap_count will still be updated in this case. It is recommended that the 3083 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3084 * firmware could return) to avoid this. 3085 */ 3086 int 3087 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3088 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3089 { 3090 struct libie_aqc_list_caps *cmd; 3091 struct libie_aq_desc desc; 3092 int status; 3093 3094 cmd = &desc.params.get_cap; 3095 3096 if (opc != ice_aqc_opc_list_func_caps && 3097 opc != ice_aqc_opc_list_dev_caps) 3098 return -EINVAL; 3099 3100 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3101 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3102 3103 if (cap_count) 3104 *cap_count = le32_to_cpu(cmd->count); 3105 3106 return status; 3107 } 3108 3109 /** 3110 * ice_discover_dev_caps - Read and extract device capabilities 3111 * @hw: pointer to the hardware structure 3112 * @dev_caps: pointer to device capabilities structure 3113 * 3114 * Read the device capabilities and extract them into the dev_caps structure 3115 * for later use. 3116 */ 3117 int 3118 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3119 { 3120 u32 cap_count = 0; 3121 void *cbuf; 3122 int status; 3123 3124 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3125 if (!cbuf) 3126 return -ENOMEM; 3127 3128 /* Although the driver doesn't know the number of capabilities the 3129 * device will return, we can simply send a 4KB buffer, the maximum 3130 * possible size that firmware can return. 3131 */ 3132 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3133 3134 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3135 ice_aqc_opc_list_dev_caps, NULL); 3136 if (!status) 3137 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3138 kfree(cbuf); 3139 3140 return status; 3141 } 3142 3143 /** 3144 * ice_discover_func_caps - Read and extract function capabilities 3145 * @hw: pointer to the hardware structure 3146 * @func_caps: pointer to function capabilities structure 3147 * 3148 * Read the function capabilities and extract them into the func_caps structure 3149 * for later use. 3150 */ 3151 static int 3152 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3153 { 3154 u32 cap_count = 0; 3155 void *cbuf; 3156 int status; 3157 3158 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3159 if (!cbuf) 3160 return -ENOMEM; 3161 3162 /* Although the driver doesn't know the number of capabilities the 3163 * device will return, we can simply send a 4KB buffer, the maximum 3164 * possible size that firmware can return. 3165 */ 3166 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3167 3168 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3169 ice_aqc_opc_list_func_caps, NULL); 3170 if (!status) 3171 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3172 kfree(cbuf); 3173 3174 return status; 3175 } 3176 3177 /** 3178 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3179 * @hw: pointer to the hardware structure 3180 */ 3181 void ice_set_safe_mode_caps(struct ice_hw *hw) 3182 { 3183 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3184 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3185 struct ice_hw_common_caps cached_caps; 3186 u32 num_funcs; 3187 3188 /* cache some func_caps values that should be restored after memset */ 3189 cached_caps = func_caps->common_cap; 3190 3191 /* unset func capabilities */ 3192 memset(func_caps, 0, sizeof(*func_caps)); 3193 3194 #define ICE_RESTORE_FUNC_CAP(name) \ 3195 func_caps->common_cap.name = cached_caps.name 3196 3197 /* restore cached values */ 3198 ICE_RESTORE_FUNC_CAP(valid_functions); 3199 ICE_RESTORE_FUNC_CAP(txq_first_id); 3200 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3201 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3202 ICE_RESTORE_FUNC_CAP(max_mtu); 3203 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3204 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3205 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3206 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3207 3208 /* one Tx and one Rx queue in safe mode */ 3209 func_caps->common_cap.num_rxq = 1; 3210 func_caps->common_cap.num_txq = 1; 3211 3212 /* two MSIX vectors, one for traffic and one for misc causes */ 3213 func_caps->common_cap.num_msix_vectors = 2; 3214 func_caps->guar_num_vsi = 1; 3215 3216 /* cache some dev_caps values that should be restored after memset */ 3217 cached_caps = dev_caps->common_cap; 3218 num_funcs = dev_caps->num_funcs; 3219 3220 /* unset dev capabilities */ 3221 memset(dev_caps, 0, sizeof(*dev_caps)); 3222 3223 #define ICE_RESTORE_DEV_CAP(name) \ 3224 dev_caps->common_cap.name = cached_caps.name 3225 3226 /* restore cached values */ 3227 ICE_RESTORE_DEV_CAP(valid_functions); 3228 ICE_RESTORE_DEV_CAP(txq_first_id); 3229 ICE_RESTORE_DEV_CAP(rxq_first_id); 3230 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3231 ICE_RESTORE_DEV_CAP(max_mtu); 3232 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3233 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3234 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3235 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3236 dev_caps->num_funcs = num_funcs; 3237 3238 /* one Tx and one Rx queue per function in safe mode */ 3239 dev_caps->common_cap.num_rxq = num_funcs; 3240 dev_caps->common_cap.num_txq = num_funcs; 3241 3242 /* two MSIX vectors per function */ 3243 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3244 } 3245 3246 /** 3247 * ice_get_caps - get info about the HW 3248 * @hw: pointer to the hardware structure 3249 */ 3250 int ice_get_caps(struct ice_hw *hw) 3251 { 3252 int status; 3253 3254 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3255 if (status) 3256 return status; 3257 3258 return ice_discover_func_caps(hw, &hw->func_caps); 3259 } 3260 3261 /** 3262 * ice_aq_manage_mac_write - manage MAC address write command 3263 * @hw: pointer to the HW struct 3264 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3265 * @flags: flags to control write behavior 3266 * @cd: pointer to command details structure or NULL 3267 * 3268 * This function is used to write MAC address to the NVM (0x0108). 3269 */ 3270 int 3271 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3272 struct ice_sq_cd *cd) 3273 { 3274 struct ice_aqc_manage_mac_write *cmd; 3275 struct libie_aq_desc desc; 3276 3277 cmd = libie_aq_raw(&desc); 3278 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3279 3280 cmd->flags = flags; 3281 ether_addr_copy(cmd->mac_addr, mac_addr); 3282 3283 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3284 } 3285 3286 /** 3287 * ice_aq_clear_pxe_mode 3288 * @hw: pointer to the HW struct 3289 * 3290 * Tell the firmware that the driver is taking over from PXE (0x0110). 3291 */ 3292 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3293 { 3294 struct ice_aqc_clear_pxe *cmd; 3295 struct libie_aq_desc desc; 3296 3297 cmd = libie_aq_raw(&desc); 3298 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3299 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3300 3301 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3302 } 3303 3304 /** 3305 * ice_clear_pxe_mode - clear pxe operations mode 3306 * @hw: pointer to the HW struct 3307 * 3308 * Make sure all PXE mode settings are cleared, including things 3309 * like descriptor fetch/write-back mode. 3310 */ 3311 void ice_clear_pxe_mode(struct ice_hw *hw) 3312 { 3313 if (ice_check_sq_alive(hw, &hw->adminq)) 3314 ice_aq_clear_pxe_mode(hw); 3315 } 3316 3317 /** 3318 * ice_aq_set_port_params - set physical port parameters. 3319 * @pi: pointer to the port info struct 3320 * @double_vlan: if set double VLAN is enabled 3321 * @cd: pointer to command details structure or NULL 3322 * 3323 * Set Physical port parameters (0x0203) 3324 */ 3325 int 3326 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3327 struct ice_sq_cd *cd) 3328 3329 { 3330 struct ice_aqc_set_port_params *cmd; 3331 struct ice_hw *hw = pi->hw; 3332 struct libie_aq_desc desc; 3333 u16 cmd_flags = 0; 3334 3335 cmd = libie_aq_raw(&desc); 3336 3337 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3338 if (double_vlan) 3339 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3340 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3341 3342 cmd->local_fwd_mode = pi->local_fwd_mode | 3343 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3344 3345 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3346 } 3347 3348 /** 3349 * ice_is_100m_speed_supported 3350 * @hw: pointer to the HW struct 3351 * 3352 * returns true if 100M speeds are supported by the device, 3353 * false otherwise. 3354 */ 3355 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3356 { 3357 switch (hw->device_id) { 3358 case ICE_DEV_ID_E822C_SGMII: 3359 case ICE_DEV_ID_E822L_SGMII: 3360 case ICE_DEV_ID_E823L_1GBE: 3361 case ICE_DEV_ID_E823C_SGMII: 3362 case ICE_DEV_ID_E825C_SGMII: 3363 return true; 3364 default: 3365 return false; 3366 } 3367 } 3368 3369 /** 3370 * ice_get_link_speed_based_on_phy_type - returns link speed 3371 * @phy_type_low: lower part of phy_type 3372 * @phy_type_high: higher part of phy_type 3373 * 3374 * This helper function will convert an entry in PHY type structure 3375 * [phy_type_low, phy_type_high] to its corresponding link speed. 3376 * Note: In the structure of [phy_type_low, phy_type_high], there should 3377 * be one bit set, as this function will convert one PHY type to its 3378 * speed. 3379 * 3380 * Return: 3381 * * PHY speed for recognized PHY type 3382 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3383 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3384 */ 3385 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3386 { 3387 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3388 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3389 3390 switch (phy_type_low) { 3391 case ICE_PHY_TYPE_LOW_100BASE_TX: 3392 case ICE_PHY_TYPE_LOW_100M_SGMII: 3393 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3394 break; 3395 case ICE_PHY_TYPE_LOW_1000BASE_T: 3396 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3397 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3398 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3399 case ICE_PHY_TYPE_LOW_1G_SGMII: 3400 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3401 break; 3402 case ICE_PHY_TYPE_LOW_2500BASE_T: 3403 case ICE_PHY_TYPE_LOW_2500BASE_X: 3404 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3405 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3406 break; 3407 case ICE_PHY_TYPE_LOW_5GBASE_T: 3408 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3409 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3410 break; 3411 case ICE_PHY_TYPE_LOW_10GBASE_T: 3412 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3413 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3414 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3415 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3416 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3417 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3418 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3419 break; 3420 case ICE_PHY_TYPE_LOW_25GBASE_T: 3421 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3422 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3423 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3424 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3425 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3426 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3427 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3428 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3429 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3430 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3431 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3432 break; 3433 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3434 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3435 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3436 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3437 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3438 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3439 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3440 break; 3441 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3442 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3443 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3444 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3445 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3446 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3447 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3448 case ICE_PHY_TYPE_LOW_50G_AUI2: 3449 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3450 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3451 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3452 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3453 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3454 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3455 case ICE_PHY_TYPE_LOW_50G_AUI1: 3456 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3457 break; 3458 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3459 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3460 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3461 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3462 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3463 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3464 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3465 case ICE_PHY_TYPE_LOW_100G_AUI4: 3466 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3467 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3468 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3469 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3470 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3471 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3472 break; 3473 default: 3474 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3475 break; 3476 } 3477 3478 switch (phy_type_high) { 3479 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3480 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3481 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3482 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3483 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3484 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3485 break; 3486 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3487 case ICE_PHY_TYPE_HIGH_200G_SR4: 3488 case ICE_PHY_TYPE_HIGH_200G_FR4: 3489 case ICE_PHY_TYPE_HIGH_200G_LR4: 3490 case ICE_PHY_TYPE_HIGH_200G_DR4: 3491 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3492 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3493 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3494 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3495 break; 3496 default: 3497 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3498 break; 3499 } 3500 3501 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3502 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3503 return ICE_AQ_LINK_SPEED_UNKNOWN; 3504 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3505 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3506 return ICE_AQ_LINK_SPEED_UNKNOWN; 3507 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3508 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3509 return speed_phy_type_low; 3510 else 3511 return speed_phy_type_high; 3512 } 3513 3514 /** 3515 * ice_update_phy_type 3516 * @phy_type_low: pointer to the lower part of phy_type 3517 * @phy_type_high: pointer to the higher part of phy_type 3518 * @link_speeds_bitmap: targeted link speeds bitmap 3519 * 3520 * Note: For the link_speeds_bitmap structure, you can check it at 3521 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3522 * link_speeds_bitmap include multiple speeds. 3523 * 3524 * Each entry in this [phy_type_low, phy_type_high] structure will 3525 * present a certain link speed. This helper function will turn on bits 3526 * in [phy_type_low, phy_type_high] structure based on the value of 3527 * link_speeds_bitmap input parameter. 3528 */ 3529 void 3530 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3531 u16 link_speeds_bitmap) 3532 { 3533 u64 pt_high; 3534 u64 pt_low; 3535 int index; 3536 u16 speed; 3537 3538 /* We first check with low part of phy_type */ 3539 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3540 pt_low = BIT_ULL(index); 3541 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3542 3543 if (link_speeds_bitmap & speed) 3544 *phy_type_low |= BIT_ULL(index); 3545 } 3546 3547 /* We then check with high part of phy_type */ 3548 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3549 pt_high = BIT_ULL(index); 3550 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3551 3552 if (link_speeds_bitmap & speed) 3553 *phy_type_high |= BIT_ULL(index); 3554 } 3555 } 3556 3557 /** 3558 * ice_aq_set_phy_cfg 3559 * @hw: pointer to the HW struct 3560 * @pi: port info structure of the interested logical port 3561 * @cfg: structure with PHY configuration data to be set 3562 * @cd: pointer to command details structure or NULL 3563 * 3564 * Set the various PHY configuration parameters supported on the Port. 3565 * One or more of the Set PHY config parameters may be ignored in an MFP 3566 * mode as the PF may not have the privilege to set some of the PHY Config 3567 * parameters. This status will be indicated by the command response (0x0601). 3568 */ 3569 int 3570 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3571 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3572 { 3573 struct ice_aqc_set_phy_cfg *cmd; 3574 struct libie_aq_desc desc; 3575 int status; 3576 3577 if (!cfg) 3578 return -EINVAL; 3579 3580 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3581 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3582 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3583 cfg->caps); 3584 3585 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3586 } 3587 3588 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3589 cmd = libie_aq_raw(&desc); 3590 cmd->lport_num = pi->lport; 3591 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3592 3593 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3594 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3595 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3596 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3597 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3598 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3599 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3600 cfg->low_power_ctrl_an); 3601 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3602 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3603 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3604 cfg->link_fec_opt); 3605 3606 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3607 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3608 status = 0; 3609 3610 if (!status) 3611 pi->phy.curr_user_phy_cfg = *cfg; 3612 3613 return status; 3614 } 3615 3616 /** 3617 * ice_update_link_info - update status of the HW network link 3618 * @pi: port info structure of the interested logical port 3619 */ 3620 int ice_update_link_info(struct ice_port_info *pi) 3621 { 3622 struct ice_link_status *li; 3623 int status; 3624 3625 if (!pi) 3626 return -EINVAL; 3627 3628 li = &pi->phy.link_info; 3629 3630 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3631 if (status) 3632 return status; 3633 3634 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3635 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3636 3637 pcaps = kzalloc_obj(*pcaps); 3638 if (!pcaps) 3639 return -ENOMEM; 3640 3641 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3642 pcaps, NULL); 3643 } 3644 3645 return status; 3646 } 3647 3648 /** 3649 * ice_aq_get_phy_equalization - function to read serdes equaliser 3650 * value from firmware using admin queue command. 3651 * @hw: pointer to the HW struct 3652 * @data_in: represents the serdes equalization parameter requested 3653 * @op_code: represents the serdes number and flag to represent tx or rx 3654 * @serdes_num: represents the serdes number 3655 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3656 * 3657 * Return: non-zero status on error and 0 on success. 3658 */ 3659 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3660 u8 serdes_num, int *output) 3661 { 3662 struct ice_aqc_dnl_call_command *cmd; 3663 struct ice_aqc_dnl_call buf = {}; 3664 struct libie_aq_desc desc; 3665 int err; 3666 3667 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3668 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3669 cpu_to_le16(op_code | (serdes_num & 0xF)); 3670 cmd = libie_aq_raw(&desc); 3671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3672 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3673 LIBIE_AQ_FLAG_RD | 3674 LIBIE_AQ_FLAG_SI); 3675 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3676 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3677 3678 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3679 NULL); 3680 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3681 3682 return err; 3683 } 3684 3685 #define FEC_REG_PORT(port) { \ 3686 FEC_CORR_LOW_REG_PORT##port, \ 3687 FEC_CORR_HIGH_REG_PORT##port, \ 3688 FEC_UNCORR_LOW_REG_PORT##port, \ 3689 FEC_UNCORR_HIGH_REG_PORT##port, \ 3690 } 3691 3692 static const u32 fec_reg[][ICE_FEC_MAX] = { 3693 FEC_REG_PORT(0), 3694 FEC_REG_PORT(1), 3695 FEC_REG_PORT(2), 3696 FEC_REG_PORT(3) 3697 }; 3698 3699 /** 3700 * ice_aq_get_fec_stats - reads fec stats from phy 3701 * @hw: pointer to the HW struct 3702 * @pcs_quad: represents pcsquad of user input serdes 3703 * @pcs_port: represents the pcs port number part of above pcs quad 3704 * @fec_type: represents FEC stats type 3705 * @output: pointer to the caller-supplied buffer to return requested fec stats 3706 * 3707 * Return: non-zero status on error and 0 on success. 3708 */ 3709 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3710 enum ice_fec_stats_types fec_type, u32 *output) 3711 { 3712 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3713 struct ice_sbq_msg_input msg = {}; 3714 u32 receiver_id, reg_offset; 3715 int err; 3716 3717 if (pcs_port > 3) 3718 return -EINVAL; 3719 3720 reg_offset = fec_reg[pcs_port][fec_type]; 3721 3722 if (pcs_quad == 0) 3723 receiver_id = FEC_RECEIVER_ID_PCS0; 3724 else if (pcs_quad == 1) 3725 receiver_id = FEC_RECEIVER_ID_PCS1; 3726 else 3727 return -EINVAL; 3728 3729 msg.msg_addr_low = lower_16_bits(reg_offset); 3730 msg.msg_addr_high = receiver_id; 3731 msg.opcode = ice_sbq_msg_rd; 3732 msg.dest_dev = ice_sbq_dev_phy_0; 3733 3734 err = ice_sbq_rw_reg(hw, &msg, flag); 3735 if (err) 3736 return err; 3737 3738 *output = msg.data; 3739 return 0; 3740 } 3741 3742 /** 3743 * ice_cache_phy_user_req 3744 * @pi: port information structure 3745 * @cache_data: PHY logging data 3746 * @cache_mode: PHY logging mode 3747 * 3748 * Log the user request on (FC, FEC, SPEED) for later use. 3749 */ 3750 static void 3751 ice_cache_phy_user_req(struct ice_port_info *pi, 3752 struct ice_phy_cache_mode_data cache_data, 3753 enum ice_phy_cache_mode cache_mode) 3754 { 3755 if (!pi) 3756 return; 3757 3758 switch (cache_mode) { 3759 case ICE_FC_MODE: 3760 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3761 break; 3762 case ICE_SPEED_MODE: 3763 pi->phy.curr_user_speed_req = 3764 cache_data.data.curr_user_speed_req; 3765 break; 3766 case ICE_FEC_MODE: 3767 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3768 break; 3769 default: 3770 break; 3771 } 3772 } 3773 3774 /** 3775 * ice_caps_to_fc_mode 3776 * @caps: PHY capabilities 3777 * 3778 * Convert PHY FC capabilities to ice FC mode 3779 */ 3780 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3781 { 3782 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3783 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3784 return ICE_FC_FULL; 3785 3786 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3787 return ICE_FC_TX_PAUSE; 3788 3789 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3790 return ICE_FC_RX_PAUSE; 3791 3792 return ICE_FC_NONE; 3793 } 3794 3795 /** 3796 * ice_caps_to_fec_mode 3797 * @caps: PHY capabilities 3798 * @fec_options: Link FEC options 3799 * 3800 * Convert PHY FEC capabilities to ice FEC mode 3801 */ 3802 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3803 { 3804 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3805 return ICE_FEC_AUTO; 3806 3807 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3808 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3809 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3810 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3811 return ICE_FEC_BASER; 3812 3813 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3814 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3815 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3816 return ICE_FEC_RS; 3817 3818 return ICE_FEC_NONE; 3819 } 3820 3821 /** 3822 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3823 * @pi: port information structure 3824 * @cfg: PHY configuration data to set FC mode 3825 * @req_mode: FC mode to configure 3826 */ 3827 int 3828 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3829 enum ice_fc_mode req_mode) 3830 { 3831 struct ice_phy_cache_mode_data cache_data; 3832 u8 pause_mask = 0x0; 3833 3834 if (!pi || !cfg) 3835 return -EINVAL; 3836 3837 switch (req_mode) { 3838 case ICE_FC_FULL: 3839 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3840 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3841 break; 3842 case ICE_FC_RX_PAUSE: 3843 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3844 break; 3845 case ICE_FC_TX_PAUSE: 3846 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3847 break; 3848 default: 3849 break; 3850 } 3851 3852 /* clear the old pause settings */ 3853 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3854 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3855 3856 /* set the new capabilities */ 3857 cfg->caps |= pause_mask; 3858 3859 /* Cache user FC request */ 3860 cache_data.data.curr_user_fc_req = req_mode; 3861 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3862 3863 return 0; 3864 } 3865 3866 /** 3867 * ice_set_fc 3868 * @pi: port information structure 3869 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3870 * @ena_auto_link_update: enable automatic link update 3871 * 3872 * Set the requested flow control mode. 3873 */ 3874 int 3875 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3876 { 3877 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3878 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3879 struct ice_hw *hw; 3880 int status; 3881 3882 if (!pi || !aq_failures) 3883 return -EINVAL; 3884 3885 hw = pi->hw; 3886 3887 pcaps = kzalloc_obj(*pcaps); 3888 if (!pcaps) 3889 return -ENOMEM; 3890 3891 /* Get the current PHY config */ 3892 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3893 pcaps, NULL); 3894 if (status) { 3895 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3896 goto out; 3897 } 3898 3899 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3900 3901 /* Configure the set PHY data */ 3902 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3903 if (status) 3904 goto out; 3905 3906 /* If the capabilities have changed, then set the new config */ 3907 if (cfg.caps != pcaps->caps) { 3908 int retry_count, retry_max = 10; 3909 3910 /* Auto restart link so settings take effect */ 3911 if (ena_auto_link_update) 3912 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3913 3914 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3915 if (status) { 3916 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3917 goto out; 3918 } 3919 3920 /* Update the link info 3921 * It sometimes takes a really long time for link to 3922 * come back from the atomic reset. Thus, we wait a 3923 * little bit. 3924 */ 3925 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3926 status = ice_update_link_info(pi); 3927 3928 if (!status) 3929 break; 3930 3931 mdelay(100); 3932 } 3933 3934 if (status) 3935 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3936 } 3937 3938 out: 3939 return status; 3940 } 3941 3942 /** 3943 * ice_phy_caps_equals_cfg 3944 * @phy_caps: PHY capabilities 3945 * @phy_cfg: PHY configuration 3946 * 3947 * Helper function to determine if PHY capabilities matches PHY 3948 * configuration 3949 */ 3950 bool 3951 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3952 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3953 { 3954 u8 caps_mask, cfg_mask; 3955 3956 if (!phy_caps || !phy_cfg) 3957 return false; 3958 3959 /* These bits are not common between capabilities and configuration. 3960 * Do not use them to determine equality. 3961 */ 3962 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3963 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3964 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3965 3966 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3967 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3968 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3969 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3970 phy_caps->eee_cap != phy_cfg->eee_cap || 3971 phy_caps->eeer_value != phy_cfg->eeer_value || 3972 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3973 return false; 3974 3975 return true; 3976 } 3977 3978 /** 3979 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3980 * @pi: port information structure 3981 * @caps: PHY ability structure to copy date from 3982 * @cfg: PHY configuration structure to copy data to 3983 * 3984 * Helper function to copy AQC PHY get ability data to PHY set configuration 3985 * data structure 3986 */ 3987 void 3988 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3989 struct ice_aqc_get_phy_caps_data *caps, 3990 struct ice_aqc_set_phy_cfg_data *cfg) 3991 { 3992 if (!pi || !caps || !cfg) 3993 return; 3994 3995 memset(cfg, 0, sizeof(*cfg)); 3996 cfg->phy_type_low = caps->phy_type_low; 3997 cfg->phy_type_high = caps->phy_type_high; 3998 cfg->caps = caps->caps; 3999 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4000 cfg->eee_cap = caps->eee_cap; 4001 cfg->eeer_value = caps->eeer_value; 4002 cfg->link_fec_opt = caps->link_fec_options; 4003 cfg->module_compliance_enforcement = 4004 caps->module_compliance_enforcement; 4005 } 4006 4007 /** 4008 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4009 * @pi: port information structure 4010 * @cfg: PHY configuration data to set FEC mode 4011 * @fec: FEC mode to configure 4012 */ 4013 int 4014 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4015 enum ice_fec_mode fec) 4016 { 4017 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4018 struct ice_hw *hw; 4019 int status; 4020 4021 if (!pi || !cfg) 4022 return -EINVAL; 4023 4024 hw = pi->hw; 4025 4026 pcaps = kzalloc_obj(*pcaps); 4027 if (!pcaps) 4028 return -ENOMEM; 4029 4030 status = ice_aq_get_phy_caps(pi, false, 4031 (ice_fw_supports_report_dflt_cfg(hw) ? 4032 ICE_AQC_REPORT_DFLT_CFG : 4033 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4034 if (status) 4035 goto out; 4036 4037 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4038 cfg->link_fec_opt = pcaps->link_fec_options; 4039 4040 switch (fec) { 4041 case ICE_FEC_BASER: 4042 /* Clear RS bits, and AND BASE-R ability 4043 * bits and OR request bits. 4044 */ 4045 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4046 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4047 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4048 ICE_AQC_PHY_FEC_25G_KR_REQ; 4049 break; 4050 case ICE_FEC_RS: 4051 /* Clear BASE-R bits, and AND RS ability 4052 * bits and OR request bits. 4053 */ 4054 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4055 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4056 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4057 break; 4058 case ICE_FEC_NONE: 4059 /* Clear all FEC option bits. */ 4060 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4061 break; 4062 case ICE_FEC_AUTO: 4063 /* AND auto FEC bit, and all caps bits. */ 4064 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4065 cfg->link_fec_opt |= pcaps->link_fec_options; 4066 break; 4067 default: 4068 status = -EINVAL; 4069 break; 4070 } 4071 4072 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4073 !ice_fw_supports_report_dflt_cfg(hw)) { 4074 struct ice_link_default_override_tlv tlv = { 0 }; 4075 4076 status = ice_get_link_default_override(&tlv, pi); 4077 if (status) 4078 goto out; 4079 4080 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4081 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4082 cfg->link_fec_opt = tlv.fec_options; 4083 } 4084 4085 out: 4086 return status; 4087 } 4088 4089 /** 4090 * ice_get_link_status - get status of the HW network link 4091 * @pi: port information structure 4092 * @link_up: pointer to bool (true/false = linkup/linkdown) 4093 * 4094 * Variable link_up is true if link is up, false if link is down. 4095 * The variable link_up is invalid if status is non zero. As a 4096 * result of this call, link status reporting becomes enabled 4097 */ 4098 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4099 { 4100 struct ice_phy_info *phy_info; 4101 int status = 0; 4102 4103 if (!pi || !link_up) 4104 return -EINVAL; 4105 4106 phy_info = &pi->phy; 4107 4108 if (phy_info->get_link_info) { 4109 status = ice_update_link_info(pi); 4110 4111 if (status) 4112 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4113 status); 4114 } 4115 4116 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4117 4118 return status; 4119 } 4120 4121 /** 4122 * ice_aq_set_link_restart_an 4123 * @pi: pointer to the port information structure 4124 * @ena_link: if true: enable link, if false: disable link 4125 * @cd: pointer to command details structure or NULL 4126 * @refclk: the new TX reference clock, 0 if no change 4127 * 4128 * Sets up the link and restarts the Auto-Negotiation over the link. 4129 */ 4130 int 4131 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4132 struct ice_sq_cd *cd, u8 refclk) 4133 { 4134 struct ice_aqc_restart_an *cmd; 4135 struct libie_aq_desc desc; 4136 4137 cmd = libie_aq_raw(&desc); 4138 4139 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4140 4141 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4142 cmd->lport_num = pi->lport; 4143 if (ena_link) 4144 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4145 else 4146 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4147 4148 cmd->cmd_flags |= FIELD_PREP(ICE_AQC_RESTART_AN_REFCLK_M, refclk); 4149 4150 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4151 } 4152 4153 /** 4154 * ice_aq_set_event_mask 4155 * @hw: pointer to the HW struct 4156 * @port_num: port number of the physical function 4157 * @mask: event mask to be set 4158 * @cd: pointer to command details structure or NULL 4159 * 4160 * Set event mask (0x0613) 4161 */ 4162 int 4163 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4164 struct ice_sq_cd *cd) 4165 { 4166 struct ice_aqc_set_event_mask *cmd; 4167 struct libie_aq_desc desc; 4168 4169 cmd = libie_aq_raw(&desc); 4170 4171 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4172 4173 cmd->lport_num = port_num; 4174 4175 cmd->event_mask = cpu_to_le16(mask); 4176 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4177 } 4178 4179 /** 4180 * ice_aq_set_mac_loopback 4181 * @hw: pointer to the HW struct 4182 * @ena_lpbk: Enable or Disable loopback 4183 * @cd: pointer to command details structure or NULL 4184 * 4185 * Enable/disable loopback on a given port 4186 */ 4187 int 4188 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4189 { 4190 struct ice_aqc_set_mac_lb *cmd; 4191 struct libie_aq_desc desc; 4192 4193 cmd = libie_aq_raw(&desc); 4194 4195 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4196 if (ena_lpbk) 4197 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4198 4199 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4200 } 4201 4202 /** 4203 * ice_aq_set_port_id_led 4204 * @pi: pointer to the port information 4205 * @is_orig_mode: is this LED set to original mode (by the net-list) 4206 * @cd: pointer to command details structure or NULL 4207 * 4208 * Set LED value for the given port (0x06e9) 4209 */ 4210 int 4211 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4212 struct ice_sq_cd *cd) 4213 { 4214 struct ice_aqc_set_port_id_led *cmd; 4215 struct ice_hw *hw = pi->hw; 4216 struct libie_aq_desc desc; 4217 4218 cmd = libie_aq_raw(&desc); 4219 4220 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4221 4222 if (is_orig_mode) 4223 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4224 else 4225 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4226 4227 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4228 } 4229 4230 /** 4231 * ice_aq_get_port_options 4232 * @hw: pointer to the HW struct 4233 * @options: buffer for the resultant port options 4234 * @option_count: input - size of the buffer in port options structures, 4235 * output - number of returned port options 4236 * @lport: logical port to call the command with (optional) 4237 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4238 * when PF owns more than 1 port it must be true 4239 * @active_option_idx: index of active port option in returned buffer 4240 * @active_option_valid: active option in returned buffer is valid 4241 * @pending_option_idx: index of pending port option in returned buffer 4242 * @pending_option_valid: pending option in returned buffer is valid 4243 * 4244 * Calls Get Port Options AQC (0x06ea) and verifies result. 4245 */ 4246 int 4247 ice_aq_get_port_options(struct ice_hw *hw, 4248 struct ice_aqc_get_port_options_elem *options, 4249 u8 *option_count, u8 lport, bool lport_valid, 4250 u8 *active_option_idx, bool *active_option_valid, 4251 u8 *pending_option_idx, bool *pending_option_valid) 4252 { 4253 struct ice_aqc_get_port_options *cmd; 4254 struct libie_aq_desc desc; 4255 int status; 4256 u8 i; 4257 4258 /* options buffer shall be able to hold max returned options */ 4259 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4260 return -EINVAL; 4261 4262 cmd = libie_aq_raw(&desc); 4263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4264 4265 if (lport_valid) 4266 cmd->lport_num = lport; 4267 cmd->lport_num_valid = lport_valid; 4268 4269 status = ice_aq_send_cmd(hw, &desc, options, 4270 *option_count * sizeof(*options), NULL); 4271 if (status) 4272 return status; 4273 4274 /* verify direct FW response & set output parameters */ 4275 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4276 cmd->port_options_count); 4277 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4278 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4279 cmd->port_options); 4280 if (*active_option_valid) { 4281 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4282 cmd->port_options); 4283 if (*active_option_idx > (*option_count - 1)) 4284 return -EIO; 4285 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4286 *active_option_idx); 4287 } 4288 4289 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4290 cmd->pending_port_option_status); 4291 if (*pending_option_valid) { 4292 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4293 cmd->pending_port_option_status); 4294 if (*pending_option_idx > (*option_count - 1)) 4295 return -EIO; 4296 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4297 *pending_option_idx); 4298 } 4299 4300 /* mask output options fields */ 4301 for (i = 0; i < *option_count; i++) { 4302 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4303 options[i].pmd); 4304 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4305 options[i].max_lane_speed); 4306 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4307 options[i].pmd, options[i].max_lane_speed); 4308 } 4309 4310 return 0; 4311 } 4312 4313 /** 4314 * ice_aq_set_port_option 4315 * @hw: pointer to the HW struct 4316 * @lport: logical port to call the command with 4317 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4318 * when PF owns more than 1 port it must be true 4319 * @new_option: new port option to be written 4320 * 4321 * Calls Set Port Options AQC (0x06eb). 4322 */ 4323 int 4324 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4325 u8 new_option) 4326 { 4327 struct ice_aqc_set_port_option *cmd; 4328 struct libie_aq_desc desc; 4329 4330 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4331 return -EINVAL; 4332 4333 cmd = libie_aq_raw(&desc); 4334 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4335 4336 if (lport_valid) 4337 cmd->lport_num = lport; 4338 4339 cmd->lport_num_valid = lport_valid; 4340 cmd->selected_port_option = new_option; 4341 4342 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4343 } 4344 4345 /** 4346 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4347 * @hw: pointer to the hw struct 4348 * 4349 * Return: PHY lane number on success, negative error code otherwise. 4350 */ 4351 int ice_get_phy_lane_number(struct ice_hw *hw) 4352 { 4353 struct ice_aqc_get_port_options_elem *options; 4354 unsigned int lport = 0; 4355 unsigned int lane; 4356 int err; 4357 4358 /* E82X does not have sequential IDs, lane number is PF ID. 4359 * For E825 device, the exception is the variant with external 4360 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4361 * mapping. 4362 */ 4363 if (hw->mac_type == ICE_MAC_GENERIC || 4364 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4365 return hw->pf_id; 4366 4367 options = kzalloc_objs(*options, ICE_AQC_PORT_OPT_MAX); 4368 if (!options) 4369 return -ENOMEM; 4370 4371 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4372 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4373 u8 speed, active_idx, pending_idx; 4374 bool active_valid, pending_valid; 4375 4376 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4377 true, &active_idx, &active_valid, 4378 &pending_idx, &pending_valid); 4379 if (err) 4380 goto err; 4381 4382 if (!active_valid) 4383 continue; 4384 4385 speed = options[active_idx].max_lane_speed; 4386 /* If we don't get speed for this lane, it's unoccupied */ 4387 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4388 continue; 4389 4390 if (hw->pf_id == lport) { 4391 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4392 ice_is_dual(hw) && !ice_is_primary(hw)) 4393 lane += ICE_PORTS_PER_QUAD; 4394 kfree(options); 4395 return lane; 4396 } 4397 lport++; 4398 } 4399 4400 /* PHY lane not found */ 4401 err = -ENXIO; 4402 err: 4403 kfree(options); 4404 return err; 4405 } 4406 4407 /** 4408 * ice_aq_sff_eeprom 4409 * @hw: pointer to the HW struct 4410 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4411 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4412 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4413 * @page: QSFP page 4414 * @set_page: set or ignore the page 4415 * @data: pointer to data buffer to be read/written to the I2C device. 4416 * @length: 1-16 for read, 1 for write. 4417 * @write: 0 read, 1 for write. 4418 * @cd: pointer to command details structure or NULL 4419 * 4420 * Read/Write SFF EEPROM (0x06EE) 4421 */ 4422 int 4423 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4424 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4425 bool write, struct ice_sq_cd *cd) 4426 { 4427 struct ice_aqc_sff_eeprom *cmd; 4428 struct libie_aq_desc desc; 4429 u16 i2c_bus_addr; 4430 int status; 4431 4432 if (!data || (mem_addr & 0xff00)) 4433 return -EINVAL; 4434 4435 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4436 cmd = libie_aq_raw(&desc); 4437 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4438 cmd->lport_num = (u8)(lport & 0xff); 4439 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4440 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4441 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4442 if (write) 4443 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4444 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4445 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4446 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4447 4448 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4449 return status; 4450 } 4451 4452 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4453 { 4454 switch (type) { 4455 case ICE_LUT_VSI: 4456 return ICE_LUT_VSI_SIZE; 4457 case ICE_LUT_GLOBAL: 4458 return ICE_LUT_GLOBAL_SIZE; 4459 case ICE_LUT_PF: 4460 return ICE_LUT_PF_SIZE; 4461 } 4462 WARN_ONCE(1, "incorrect type passed"); 4463 return ICE_LUT_VSI_SIZE; 4464 } 4465 4466 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4467 { 4468 switch (size) { 4469 case ICE_LUT_VSI_SIZE: 4470 return ICE_AQC_LUT_SIZE_SMALL; 4471 case ICE_LUT_GLOBAL_SIZE: 4472 return ICE_AQC_LUT_SIZE_512; 4473 case ICE_LUT_PF_SIZE: 4474 return ICE_AQC_LUT_SIZE_2K; 4475 } 4476 WARN_ONCE(1, "incorrect size passed"); 4477 return 0; 4478 } 4479 4480 /** 4481 * __ice_aq_get_set_rss_lut 4482 * @hw: pointer to the hardware structure 4483 * @params: RSS LUT parameters 4484 * @set: set true to set the table, false to get the table 4485 * 4486 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4487 */ 4488 static int 4489 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4490 struct ice_aq_get_set_rss_lut_params *params, bool set) 4491 { 4492 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4493 enum ice_lut_type lut_type = params->lut_type; 4494 struct ice_aqc_get_set_rss_lut *desc_params; 4495 enum ice_aqc_lut_flags flags; 4496 enum ice_lut_size lut_size; 4497 struct libie_aq_desc desc; 4498 u8 *lut = params->lut; 4499 4500 4501 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4502 return -EINVAL; 4503 4504 lut_size = ice_lut_type_to_size(lut_type); 4505 if (lut_size > params->lut_size) 4506 return -EINVAL; 4507 else if (set && lut_size != params->lut_size) 4508 return -EINVAL; 4509 4510 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4511 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4512 if (set) 4513 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4514 4515 desc_params = libie_aq_raw(&desc); 4516 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4517 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4518 4519 if (lut_type == ICE_LUT_GLOBAL) 4520 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4521 params->global_lut_id); 4522 4523 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4524 desc_params->flags = cpu_to_le16(flags); 4525 4526 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4527 } 4528 4529 /** 4530 * ice_aq_get_rss_lut 4531 * @hw: pointer to the hardware structure 4532 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4533 * 4534 * get the RSS lookup table, PF or VSI type 4535 */ 4536 int 4537 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4538 { 4539 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4540 } 4541 4542 /** 4543 * ice_aq_set_rss_lut 4544 * @hw: pointer to the hardware structure 4545 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4546 * 4547 * set the RSS lookup table, PF or VSI type 4548 */ 4549 int 4550 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4551 { 4552 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4553 } 4554 4555 /** 4556 * __ice_aq_get_set_rss_key 4557 * @hw: pointer to the HW struct 4558 * @vsi_id: VSI FW index 4559 * @key: pointer to key info struct 4560 * @set: set true to set the key, false to get the key 4561 * 4562 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4563 */ 4564 static int 4565 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4566 struct ice_aqc_get_set_rss_keys *key, bool set) 4567 { 4568 struct ice_aqc_get_set_rss_key *desc_params; 4569 u16 key_size = sizeof(*key); 4570 struct libie_aq_desc desc; 4571 4572 if (set) { 4573 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4574 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4575 } else { 4576 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4577 } 4578 4579 desc_params = libie_aq_raw(&desc); 4580 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4581 4582 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4583 } 4584 4585 /** 4586 * ice_aq_get_rss_key 4587 * @hw: pointer to the HW struct 4588 * @vsi_handle: software VSI handle 4589 * @key: pointer to key info struct 4590 * 4591 * get the RSS key per VSI 4592 */ 4593 int 4594 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4595 struct ice_aqc_get_set_rss_keys *key) 4596 { 4597 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4598 return -EINVAL; 4599 4600 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4601 key, false); 4602 } 4603 4604 /** 4605 * ice_aq_set_rss_key 4606 * @hw: pointer to the HW struct 4607 * @vsi_handle: software VSI handle 4608 * @keys: pointer to key info struct 4609 * 4610 * set the RSS key per VSI 4611 */ 4612 int 4613 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4614 struct ice_aqc_get_set_rss_keys *keys) 4615 { 4616 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4617 return -EINVAL; 4618 4619 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4620 keys, true); 4621 } 4622 4623 /** 4624 * ice_aq_add_lan_txq 4625 * @hw: pointer to the hardware structure 4626 * @num_qgrps: Number of added queue groups 4627 * @qg_list: list of queue groups to be added 4628 * @buf_size: size of buffer for indirect command 4629 * @cd: pointer to command details structure or NULL 4630 * 4631 * Add Tx LAN queue (0x0C30) 4632 * 4633 * NOTE: 4634 * Prior to calling add Tx LAN queue: 4635 * Initialize the following as part of the Tx queue context: 4636 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4637 * Cache profile and Packet shaper profile. 4638 * 4639 * After add Tx LAN queue AQ command is completed: 4640 * Interrupts should be associated with specific queues, 4641 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4642 * flow. 4643 */ 4644 static int 4645 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4646 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4647 struct ice_sq_cd *cd) 4648 { 4649 struct ice_aqc_add_tx_qgrp *list; 4650 struct ice_aqc_add_txqs *cmd; 4651 struct libie_aq_desc desc; 4652 u16 i, sum_size = 0; 4653 4654 cmd = libie_aq_raw(&desc); 4655 4656 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4657 4658 if (!qg_list) 4659 return -EINVAL; 4660 4661 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4662 return -EINVAL; 4663 4664 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4665 sum_size += struct_size(list, txqs, list->num_txqs); 4666 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4667 list->num_txqs); 4668 } 4669 4670 if (buf_size != sum_size) 4671 return -EINVAL; 4672 4673 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4674 4675 cmd->num_qgrps = num_qgrps; 4676 4677 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4678 } 4679 4680 /** 4681 * ice_aq_dis_lan_txq 4682 * @hw: pointer to the hardware structure 4683 * @num_qgrps: number of groups in the list 4684 * @qg_list: the list of groups to disable 4685 * @buf_size: the total size of the qg_list buffer in bytes 4686 * @rst_src: if called due to reset, specifies the reset source 4687 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4688 * @cd: pointer to command details structure or NULL 4689 * 4690 * Disable LAN Tx queue (0x0C31) 4691 */ 4692 static int 4693 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4694 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4695 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4696 struct ice_sq_cd *cd) 4697 { 4698 struct ice_aqc_dis_txq_item *item; 4699 struct ice_aqc_dis_txqs *cmd; 4700 struct libie_aq_desc desc; 4701 u16 vmvf_and_timeout; 4702 u16 i, sz = 0; 4703 int status; 4704 4705 cmd = libie_aq_raw(&desc); 4706 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4707 4708 /* qg_list can be NULL only in VM/VF reset flow */ 4709 if (!qg_list && !rst_src) 4710 return -EINVAL; 4711 4712 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4713 return -EINVAL; 4714 4715 cmd->num_entries = num_qgrps; 4716 4717 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4718 4719 switch (rst_src) { 4720 case ICE_VM_RESET: 4721 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4722 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4723 break; 4724 case ICE_VF_RESET: 4725 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4726 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4727 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4728 ICE_AQC_Q_DIS_VMVF_NUM_M; 4729 break; 4730 case ICE_NO_RESET: 4731 default: 4732 break; 4733 } 4734 4735 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4736 4737 /* flush pipe on time out */ 4738 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4739 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4740 if (!qg_list) 4741 goto do_aq; 4742 4743 /* set RD bit to indicate that command buffer is provided by the driver 4744 * and it needs to be read by the firmware 4745 */ 4746 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4747 4748 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4749 u16 item_size = struct_size(item, q_id, item->num_qs); 4750 4751 /* If the num of queues is even, add 2 bytes of padding */ 4752 if ((item->num_qs % 2) == 0) 4753 item_size += 2; 4754 4755 sz += item_size; 4756 4757 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4758 } 4759 4760 if (buf_size != sz) 4761 return -EINVAL; 4762 4763 do_aq: 4764 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4765 if (status) { 4766 if (!qg_list) 4767 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4768 vmvf_num, hw->adminq.sq_last_status); 4769 else 4770 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4771 le16_to_cpu(qg_list[0].q_id[0]), 4772 hw->adminq.sq_last_status); 4773 } 4774 return status; 4775 } 4776 4777 /** 4778 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4779 * @hw: pointer to the hardware structure 4780 * @buf: buffer for command 4781 * @buf_size: size of buffer in bytes 4782 * @num_qs: number of queues being configured 4783 * @oldport: origination lport 4784 * @newport: destination lport 4785 * @mode: cmd_type for move to use 4786 * @cd: pointer to command details structure or NULL 4787 * 4788 * Move/Configure LAN Tx queue (0x0C32) 4789 * 4790 * Return: Zero on success, associated error code on failure. 4791 */ 4792 int 4793 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4794 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4795 u8 mode, struct ice_sq_cd *cd) 4796 { 4797 struct ice_aqc_cfg_txqs *cmd; 4798 struct libie_aq_desc desc; 4799 int status; 4800 4801 cmd = libie_aq_raw(&desc); 4802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4803 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4804 4805 if (!buf) 4806 return -EINVAL; 4807 4808 cmd->cmd_type = mode; 4809 cmd->num_qs = num_qs; 4810 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4811 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4812 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4813 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4814 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4815 cmd->blocked_cgds = 0; 4816 4817 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4818 if (status) 4819 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4820 hw->adminq.sq_last_status); 4821 return status; 4822 } 4823 4824 /** 4825 * ice_aq_add_rdma_qsets 4826 * @hw: pointer to the hardware structure 4827 * @num_qset_grps: Number of RDMA Qset groups 4828 * @qset_list: list of Qset groups to be added 4829 * @buf_size: size of buffer for indirect command 4830 * @cd: pointer to command details structure or NULL 4831 * 4832 * Add Tx RDMA Qsets (0x0C33) 4833 */ 4834 static int 4835 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4836 struct ice_aqc_add_rdma_qset_data *qset_list, 4837 u16 buf_size, struct ice_sq_cd *cd) 4838 { 4839 struct ice_aqc_add_rdma_qset_data *list; 4840 struct ice_aqc_add_rdma_qset *cmd; 4841 struct libie_aq_desc desc; 4842 u16 i, sum_size = 0; 4843 4844 cmd = libie_aq_raw(&desc); 4845 4846 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4847 4848 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4849 return -EINVAL; 4850 4851 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4852 u16 num_qsets = le16_to_cpu(list->num_qsets); 4853 4854 sum_size += struct_size(list, rdma_qsets, num_qsets); 4855 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4856 num_qsets); 4857 } 4858 4859 if (buf_size != sum_size) 4860 return -EINVAL; 4861 4862 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4863 4864 cmd->num_qset_grps = num_qset_grps; 4865 4866 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4867 } 4868 4869 /** 4870 * ice_aq_set_txtimeq - set Tx time queues 4871 * @hw: pointer to the hardware structure 4872 * @txtimeq: first Tx time queue id to configure 4873 * @q_count: number of queues to configure 4874 * @txtime_qg: queue group to be set 4875 * @buf_size: size of buffer for indirect command 4876 * @cd: pointer to command details structure or NULL 4877 * 4878 * Set Tx Time queue (0x0C35) 4879 * Return: 0 on success or negative value on failure. 4880 */ 4881 int 4882 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4883 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4884 struct ice_sq_cd *cd) 4885 { 4886 struct ice_aqc_set_txtimeqs *cmd; 4887 struct libie_aq_desc desc; 4888 u16 size; 4889 4890 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4891 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4892 return -EINVAL; 4893 4894 size = struct_size(txtime_qg, txtimeqs, q_count); 4895 if (buf_size != size) 4896 return -EINVAL; 4897 4898 cmd = libie_aq_raw(&desc); 4899 4900 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4901 4902 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4903 4904 cmd->q_id = cpu_to_le16(txtimeq); 4905 cmd->q_amount = cpu_to_le16(q_count); 4906 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4907 } 4908 4909 /* End of FW Admin Queue command wrappers */ 4910 4911 /** 4912 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4913 * @hw: pointer to the HW struct 4914 * @vsi_handle: software VSI handle 4915 * @tc: TC number 4916 * @q_handle: software queue handle 4917 */ 4918 struct ice_q_ctx * 4919 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4920 { 4921 struct ice_vsi_ctx *vsi; 4922 struct ice_q_ctx *q_ctx; 4923 4924 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4925 if (!vsi) 4926 return NULL; 4927 if (q_handle >= vsi->num_lan_q_entries[tc]) 4928 return NULL; 4929 if (!vsi->lan_q_ctx[tc]) 4930 return NULL; 4931 q_ctx = vsi->lan_q_ctx[tc]; 4932 return &q_ctx[q_handle]; 4933 } 4934 4935 /** 4936 * ice_ena_vsi_txq 4937 * @pi: port information structure 4938 * @vsi_handle: software VSI handle 4939 * @tc: TC number 4940 * @q_handle: software queue handle 4941 * @num_qgrps: Number of added queue groups 4942 * @buf: list of queue groups to be added 4943 * @buf_size: size of buffer for indirect command 4944 * @cd: pointer to command details structure or NULL 4945 * 4946 * This function adds one LAN queue 4947 */ 4948 int 4949 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4950 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4951 struct ice_sq_cd *cd) 4952 { 4953 struct ice_aqc_txsched_elem_data node = { 0 }; 4954 struct ice_sched_node *parent; 4955 struct ice_q_ctx *q_ctx; 4956 struct ice_hw *hw; 4957 int status; 4958 4959 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4960 return -EIO; 4961 4962 if (num_qgrps > 1 || buf->num_txqs > 1) 4963 return -ENOSPC; 4964 4965 hw = pi->hw; 4966 4967 if (!ice_is_vsi_valid(hw, vsi_handle)) 4968 return -EINVAL; 4969 4970 mutex_lock(&pi->sched_lock); 4971 4972 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4973 if (!q_ctx) { 4974 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4975 q_handle); 4976 status = -EINVAL; 4977 goto ena_txq_exit; 4978 } 4979 4980 /* find a parent node */ 4981 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4982 ICE_SCHED_NODE_OWNER_LAN); 4983 if (!parent) { 4984 status = -EINVAL; 4985 goto ena_txq_exit; 4986 } 4987 4988 buf->parent_teid = parent->info.node_teid; 4989 node.parent_teid = parent->info.node_teid; 4990 /* Mark that the values in the "generic" section as valid. The default 4991 * value in the "generic" section is zero. This means that : 4992 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4993 * - 0 priority among siblings, indicated by Bit 1-3. 4994 * - WFQ, indicated by Bit 4. 4995 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4996 * Bit 5-6. 4997 * - Bit 7 is reserved. 4998 * Without setting the generic section as valid in valid_sections, the 4999 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5000 */ 5001 buf->txqs[0].info.valid_sections = 5002 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5003 ICE_AQC_ELEM_VALID_EIR; 5004 buf->txqs[0].info.generic = 0; 5005 buf->txqs[0].info.cir_bw.bw_profile_idx = 5006 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5007 buf->txqs[0].info.cir_bw.bw_alloc = 5008 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5009 buf->txqs[0].info.eir_bw.bw_profile_idx = 5010 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5011 buf->txqs[0].info.eir_bw.bw_alloc = 5012 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5013 5014 /* add the LAN queue */ 5015 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5016 if (status) { 5017 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5018 le16_to_cpu(buf->txqs[0].txq_id), 5019 hw->adminq.sq_last_status); 5020 goto ena_txq_exit; 5021 } 5022 5023 node.node_teid = buf->txqs[0].q_teid; 5024 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5025 q_ctx->q_handle = q_handle; 5026 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5027 5028 /* add a leaf node into scheduler tree queue layer */ 5029 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5030 if (!status) 5031 status = ice_sched_replay_q_bw(pi, q_ctx); 5032 5033 ena_txq_exit: 5034 mutex_unlock(&pi->sched_lock); 5035 return status; 5036 } 5037 5038 /** 5039 * ice_dis_vsi_txq 5040 * @pi: port information structure 5041 * @vsi_handle: software VSI handle 5042 * @tc: TC number 5043 * @num_queues: number of queues 5044 * @q_handles: pointer to software queue handle array 5045 * @q_ids: pointer to the q_id array 5046 * @q_teids: pointer to queue node teids 5047 * @rst_src: if called due to reset, specifies the reset source 5048 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5049 * @cd: pointer to command details structure or NULL 5050 * 5051 * This function removes queues and their corresponding nodes in SW DB 5052 */ 5053 int 5054 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5055 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5056 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5057 struct ice_sq_cd *cd) 5058 { 5059 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5060 u16 i, buf_size = __struct_size(qg_list); 5061 struct ice_q_ctx *q_ctx; 5062 int status = -ENOENT; 5063 struct ice_hw *hw; 5064 5065 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5066 return -EIO; 5067 5068 hw = pi->hw; 5069 5070 if (!num_queues) { 5071 /* if queue is disabled already yet the disable queue command 5072 * has to be sent to complete the VF reset, then call 5073 * ice_aq_dis_lan_txq without any queue information 5074 */ 5075 if (rst_src) 5076 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5077 vmvf_num, NULL); 5078 return -EIO; 5079 } 5080 5081 mutex_lock(&pi->sched_lock); 5082 5083 for (i = 0; i < num_queues; i++) { 5084 struct ice_sched_node *node; 5085 5086 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5087 if (!node) 5088 continue; 5089 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5090 if (!q_ctx) { 5091 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5092 q_handles[i]); 5093 continue; 5094 } 5095 if (q_ctx->q_handle != q_handles[i]) { 5096 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5097 q_ctx->q_handle, q_handles[i]); 5098 continue; 5099 } 5100 qg_list->parent_teid = node->info.parent_teid; 5101 qg_list->num_qs = 1; 5102 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5103 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5104 vmvf_num, cd); 5105 5106 if (status) 5107 break; 5108 ice_free_sched_node(pi, node); 5109 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5110 q_ctx->q_teid = ICE_INVAL_TEID; 5111 } 5112 mutex_unlock(&pi->sched_lock); 5113 return status; 5114 } 5115 5116 /** 5117 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5118 * @pi: port information structure 5119 * @vsi_handle: software VSI handle 5120 * @tc_bitmap: TC bitmap 5121 * @maxqs: max queues array per TC 5122 * @owner: LAN or RDMA 5123 * 5124 * This function adds/updates the VSI queues per TC. 5125 */ 5126 static int 5127 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5128 u16 *maxqs, u8 owner) 5129 { 5130 int status = 0; 5131 u8 i; 5132 5133 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5134 return -EIO; 5135 5136 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5137 return -EINVAL; 5138 5139 mutex_lock(&pi->sched_lock); 5140 5141 ice_for_each_traffic_class(i) { 5142 /* configuration is possible only if TC node is present */ 5143 if (!ice_sched_get_tc_node(pi, i)) 5144 continue; 5145 5146 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5147 ice_is_tc_ena(tc_bitmap, i)); 5148 if (status) 5149 break; 5150 } 5151 5152 mutex_unlock(&pi->sched_lock); 5153 return status; 5154 } 5155 5156 /** 5157 * ice_cfg_vsi_lan - configure VSI LAN queues 5158 * @pi: port information structure 5159 * @vsi_handle: software VSI handle 5160 * @tc_bitmap: TC bitmap 5161 * @max_lanqs: max LAN queues array per TC 5162 * 5163 * This function adds/updates the VSI LAN queues per TC. 5164 */ 5165 int 5166 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5167 u16 *max_lanqs) 5168 { 5169 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5170 ICE_SCHED_NODE_OWNER_LAN); 5171 } 5172 5173 /** 5174 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5175 * @pi: port information structure 5176 * @vsi_handle: software VSI handle 5177 * @tc_bitmap: TC bitmap 5178 * @max_rdmaqs: max RDMA queues array per TC 5179 * 5180 * This function adds/updates the VSI RDMA queues per TC. 5181 */ 5182 int 5183 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5184 u16 *max_rdmaqs) 5185 { 5186 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5187 ICE_SCHED_NODE_OWNER_RDMA); 5188 } 5189 5190 /** 5191 * ice_ena_vsi_rdma_qset 5192 * @pi: port information structure 5193 * @vsi_handle: software VSI handle 5194 * @tc: TC number 5195 * @rdma_qset: pointer to RDMA Qset 5196 * @num_qsets: number of RDMA Qsets 5197 * @qset_teid: pointer to Qset node TEIDs 5198 * 5199 * This function adds RDMA Qset 5200 */ 5201 int 5202 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5203 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5204 { 5205 struct ice_aqc_txsched_elem_data node = { 0 }; 5206 struct ice_aqc_add_rdma_qset_data *buf; 5207 struct ice_sched_node *parent; 5208 struct ice_hw *hw; 5209 u16 i, buf_size; 5210 int ret; 5211 5212 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5213 return -EIO; 5214 hw = pi->hw; 5215 5216 if (!ice_is_vsi_valid(hw, vsi_handle)) 5217 return -EINVAL; 5218 5219 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5220 buf = kzalloc(buf_size, GFP_KERNEL); 5221 if (!buf) 5222 return -ENOMEM; 5223 mutex_lock(&pi->sched_lock); 5224 5225 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5226 ICE_SCHED_NODE_OWNER_RDMA); 5227 if (!parent) { 5228 ret = -EINVAL; 5229 goto rdma_error_exit; 5230 } 5231 buf->parent_teid = parent->info.node_teid; 5232 node.parent_teid = parent->info.node_teid; 5233 5234 buf->num_qsets = cpu_to_le16(num_qsets); 5235 for (i = 0; i < num_qsets; i++) { 5236 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5237 buf->rdma_qsets[i].info.valid_sections = 5238 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5239 ICE_AQC_ELEM_VALID_EIR; 5240 buf->rdma_qsets[i].info.generic = 0; 5241 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5242 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5243 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5244 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5245 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5246 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5247 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5248 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5249 } 5250 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5251 if (ret) { 5252 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5253 goto rdma_error_exit; 5254 } 5255 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5256 for (i = 0; i < num_qsets; i++) { 5257 node.node_teid = buf->rdma_qsets[i].qset_teid; 5258 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5259 &node, NULL); 5260 if (ret) 5261 break; 5262 qset_teid[i] = le32_to_cpu(node.node_teid); 5263 } 5264 rdma_error_exit: 5265 mutex_unlock(&pi->sched_lock); 5266 kfree(buf); 5267 return ret; 5268 } 5269 5270 /** 5271 * ice_dis_vsi_rdma_qset - free RDMA resources 5272 * @pi: port_info struct 5273 * @count: number of RDMA Qsets to free 5274 * @qset_teid: TEID of Qset node 5275 * @q_id: list of queue IDs being disabled 5276 */ 5277 int 5278 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5279 u16 *q_id) 5280 { 5281 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5282 u16 qg_size = __struct_size(qg_list); 5283 struct ice_hw *hw; 5284 int status = 0; 5285 int i; 5286 5287 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5288 return -EIO; 5289 5290 hw = pi->hw; 5291 5292 mutex_lock(&pi->sched_lock); 5293 5294 for (i = 0; i < count; i++) { 5295 struct ice_sched_node *node; 5296 5297 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5298 if (!node) 5299 continue; 5300 5301 qg_list->parent_teid = node->info.parent_teid; 5302 qg_list->num_qs = 1; 5303 qg_list->q_id[0] = 5304 cpu_to_le16(q_id[i] | 5305 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5306 5307 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5308 ICE_NO_RESET, 0, NULL); 5309 if (status) 5310 break; 5311 5312 ice_free_sched_node(pi, node); 5313 } 5314 5315 mutex_unlock(&pi->sched_lock); 5316 return status; 5317 } 5318 5319 /** 5320 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5321 * @hw: pointer to the HW struct 5322 * @dpll_idx: index of dpll to be measured 5323 * @meas: array to be filled with results 5324 * @meas_num: max number of results array can hold 5325 * 5326 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5327 * pins on given dpll. 5328 * 5329 * Return: 0 on success or negative value on failure. 5330 */ 5331 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5332 struct ice_cgu_input_measure *meas, 5333 u16 meas_num) 5334 { 5335 struct ice_aqc_get_cgu_input_measure *cmd; 5336 struct libie_aq_desc desc; 5337 5338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5339 cmd = libie_aq_raw(&desc); 5340 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5341 5342 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5343 } 5344 5345 /** 5346 * ice_aq_get_cgu_abilities - get cgu abilities 5347 * @hw: pointer to the HW struct 5348 * @abilities: CGU abilities 5349 * 5350 * Get CGU abilities (0x0C61) 5351 * Return: 0 on success or negative value on failure. 5352 */ 5353 int 5354 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5355 struct ice_aqc_get_cgu_abilities *abilities) 5356 { 5357 struct libie_aq_desc desc; 5358 5359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5360 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5361 } 5362 5363 /** 5364 * ice_aq_set_input_pin_cfg - set input pin config 5365 * @hw: pointer to the HW struct 5366 * @input_idx: Input index 5367 * @flags1: Input flags 5368 * @flags2: Input flags 5369 * @freq: Frequency in Hz 5370 * @phase_delay: Delay in ps 5371 * 5372 * Set CGU input config (0x0C62) 5373 * Return: 0 on success or negative value on failure. 5374 */ 5375 int 5376 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5377 u32 freq, s32 phase_delay) 5378 { 5379 struct ice_aqc_set_cgu_input_config *cmd; 5380 struct libie_aq_desc desc; 5381 5382 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5383 cmd = libie_aq_raw(&desc); 5384 cmd->input_idx = input_idx; 5385 cmd->flags1 = flags1; 5386 cmd->flags2 = flags2; 5387 cmd->freq = cpu_to_le32(freq); 5388 cmd->phase_delay = cpu_to_le32(phase_delay); 5389 5390 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5391 } 5392 5393 /** 5394 * ice_aq_get_input_pin_cfg - get input pin config 5395 * @hw: pointer to the HW struct 5396 * @input_idx: Input index 5397 * @status: Pin status 5398 * @type: Pin type 5399 * @flags1: Input flags 5400 * @flags2: Input flags 5401 * @freq: Frequency in Hz 5402 * @phase_delay: Delay in ps 5403 * 5404 * Get CGU input config (0x0C63) 5405 * Return: 0 on success or negative value on failure. 5406 */ 5407 int 5408 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5409 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5410 { 5411 struct ice_aqc_get_cgu_input_config *cmd; 5412 struct libie_aq_desc desc; 5413 int ret; 5414 5415 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5416 cmd = libie_aq_raw(&desc); 5417 cmd->input_idx = input_idx; 5418 5419 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5420 if (!ret) { 5421 if (status) 5422 *status = cmd->status; 5423 if (type) 5424 *type = cmd->type; 5425 if (flags1) 5426 *flags1 = cmd->flags1; 5427 if (flags2) 5428 *flags2 = cmd->flags2; 5429 if (freq) 5430 *freq = le32_to_cpu(cmd->freq); 5431 if (phase_delay) 5432 *phase_delay = le32_to_cpu(cmd->phase_delay); 5433 } 5434 5435 return ret; 5436 } 5437 5438 /** 5439 * ice_aq_set_output_pin_cfg - set output pin config 5440 * @hw: pointer to the HW struct 5441 * @output_idx: Output index 5442 * @flags: Output flags 5443 * @src_sel: Index of DPLL block 5444 * @freq: Output frequency 5445 * @phase_delay: Output phase compensation 5446 * 5447 * Set CGU output config (0x0C64) 5448 * Return: 0 on success or negative value on failure. 5449 */ 5450 int 5451 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5452 u8 src_sel, u32 freq, s32 phase_delay) 5453 { 5454 struct ice_aqc_set_cgu_output_config *cmd; 5455 struct libie_aq_desc desc; 5456 5457 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5458 cmd = libie_aq_raw(&desc); 5459 cmd->output_idx = output_idx; 5460 cmd->flags = flags; 5461 cmd->src_sel = src_sel; 5462 cmd->freq = cpu_to_le32(freq); 5463 cmd->phase_delay = cpu_to_le32(phase_delay); 5464 5465 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5466 } 5467 5468 /** 5469 * ice_aq_get_output_pin_cfg - get output pin config 5470 * @hw: pointer to the HW struct 5471 * @output_idx: Output index 5472 * @flags: Output flags 5473 * @src_sel: Internal DPLL source 5474 * @freq: Output frequency 5475 * @src_freq: Source frequency 5476 * 5477 * Get CGU output config (0x0C65) 5478 * Return: 0 on success or negative value on failure. 5479 */ 5480 int 5481 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5482 u8 *src_sel, u32 *freq, u32 *src_freq) 5483 { 5484 struct ice_aqc_get_cgu_output_config *cmd; 5485 struct libie_aq_desc desc; 5486 int ret; 5487 5488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5489 cmd = libie_aq_raw(&desc); 5490 cmd->output_idx = output_idx; 5491 5492 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5493 if (!ret) { 5494 if (flags) 5495 *flags = cmd->flags; 5496 if (src_sel) 5497 *src_sel = cmd->src_sel; 5498 if (freq) 5499 *freq = le32_to_cpu(cmd->freq); 5500 if (src_freq) 5501 *src_freq = le32_to_cpu(cmd->src_freq); 5502 } 5503 5504 return ret; 5505 } 5506 5507 /** 5508 * ice_aq_get_cgu_dpll_status - get dpll status 5509 * @hw: pointer to the HW struct 5510 * @dpll_num: DPLL index 5511 * @ref_state: Reference clock state 5512 * @config: current DPLL config 5513 * @dpll_state: current DPLL state 5514 * @phase_offset: Phase offset in ns 5515 * @eec_mode: EEC_mode 5516 * 5517 * Get CGU DPLL status (0x0C66) 5518 * Return: 0 on success or negative value on failure. 5519 */ 5520 int 5521 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5522 u8 *dpll_state, u8 *config, s64 *phase_offset, 5523 u8 *eec_mode) 5524 { 5525 struct ice_aqc_get_cgu_dpll_status *cmd; 5526 struct libie_aq_desc desc; 5527 int status; 5528 5529 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5530 cmd = libie_aq_raw(&desc); 5531 cmd->dpll_num = dpll_num; 5532 5533 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5534 if (!status) { 5535 *ref_state = cmd->ref_state; 5536 *dpll_state = cmd->dpll_state; 5537 *config = cmd->config; 5538 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5539 *phase_offset <<= 32; 5540 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5541 *phase_offset = sign_extend64(*phase_offset, 47); 5542 *eec_mode = cmd->eec_mode; 5543 } 5544 5545 return status; 5546 } 5547 5548 /** 5549 * ice_aq_set_cgu_dpll_config - set dpll config 5550 * @hw: pointer to the HW struct 5551 * @dpll_num: DPLL index 5552 * @ref_state: Reference clock state 5553 * @config: DPLL config 5554 * @eec_mode: EEC mode 5555 * 5556 * Set CGU DPLL config (0x0C67) 5557 * Return: 0 on success or negative value on failure. 5558 */ 5559 int 5560 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5561 u8 config, u8 eec_mode) 5562 { 5563 struct ice_aqc_set_cgu_dpll_config *cmd; 5564 struct libie_aq_desc desc; 5565 5566 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5567 cmd = libie_aq_raw(&desc); 5568 cmd->dpll_num = dpll_num; 5569 cmd->ref_state = ref_state; 5570 cmd->config = config; 5571 cmd->eec_mode = eec_mode; 5572 5573 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5574 } 5575 5576 /** 5577 * ice_aq_set_cgu_ref_prio - set input reference priority 5578 * @hw: pointer to the HW struct 5579 * @dpll_num: DPLL index 5580 * @ref_idx: Reference pin index 5581 * @ref_priority: Reference input priority 5582 * 5583 * Set CGU reference priority (0x0C68) 5584 * Return: 0 on success or negative value on failure. 5585 */ 5586 int 5587 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5588 u8 ref_priority) 5589 { 5590 struct ice_aqc_set_cgu_ref_prio *cmd; 5591 struct libie_aq_desc desc; 5592 5593 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5594 cmd = libie_aq_raw(&desc); 5595 cmd->dpll_num = dpll_num; 5596 cmd->ref_idx = ref_idx; 5597 cmd->ref_priority = ref_priority; 5598 5599 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5600 } 5601 5602 /** 5603 * ice_aq_get_cgu_ref_prio - get input reference priority 5604 * @hw: pointer to the HW struct 5605 * @dpll_num: DPLL index 5606 * @ref_idx: Reference pin index 5607 * @ref_prio: Reference input priority 5608 * 5609 * Get CGU reference priority (0x0C69) 5610 * Return: 0 on success or negative value on failure. 5611 */ 5612 int 5613 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5614 u8 *ref_prio) 5615 { 5616 struct ice_aqc_get_cgu_ref_prio *cmd; 5617 struct libie_aq_desc desc; 5618 int status; 5619 5620 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5621 cmd = libie_aq_raw(&desc); 5622 cmd->dpll_num = dpll_num; 5623 cmd->ref_idx = ref_idx; 5624 5625 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5626 if (!status) 5627 *ref_prio = cmd->ref_priority; 5628 5629 return status; 5630 } 5631 5632 /** 5633 * ice_aq_get_cgu_info - get cgu info 5634 * @hw: pointer to the HW struct 5635 * @cgu_id: CGU ID 5636 * @cgu_cfg_ver: CGU config version 5637 * @cgu_fw_ver: CGU firmware version 5638 * 5639 * Get CGU info (0x0C6A) 5640 * Return: 0 on success or negative value on failure. 5641 */ 5642 int 5643 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5644 u32 *cgu_fw_ver) 5645 { 5646 struct ice_aqc_get_cgu_info *cmd; 5647 struct libie_aq_desc desc; 5648 int status; 5649 5650 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5651 cmd = libie_aq_raw(&desc); 5652 5653 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5654 if (!status) { 5655 *cgu_id = le32_to_cpu(cmd->cgu_id); 5656 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5657 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5658 } 5659 5660 return status; 5661 } 5662 5663 /** 5664 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5665 * @hw: pointer to the HW struct 5666 * @phy_output: PHY reference clock output pin 5667 * @enable: GPIO state to be applied 5668 * @freq: PHY output frequency 5669 * 5670 * Set phy recovered clock as reference (0x0630) 5671 * Return: 0 on success or negative value on failure. 5672 */ 5673 int 5674 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5675 u32 *freq) 5676 { 5677 struct ice_aqc_set_phy_rec_clk_out *cmd; 5678 struct libie_aq_desc desc; 5679 int status; 5680 5681 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5682 cmd = libie_aq_raw(&desc); 5683 cmd->phy_output = phy_output; 5684 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5685 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5686 cmd->freq = cpu_to_le32(*freq); 5687 5688 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5689 if (!status) 5690 *freq = le32_to_cpu(cmd->freq); 5691 5692 return status; 5693 } 5694 5695 /** 5696 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5697 * @hw: pointer to the HW struct 5698 * @phy_output: PHY reference clock output pin 5699 * @port_num: Port number 5700 * @flags: PHY flags 5701 * @node_handle: PHY output frequency 5702 * 5703 * Get PHY recovered clock output info (0x0631) 5704 * Return: 0 on success or negative value on failure. 5705 */ 5706 int 5707 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5708 u8 *flags, u16 *node_handle) 5709 { 5710 struct ice_aqc_get_phy_rec_clk_out *cmd; 5711 struct libie_aq_desc desc; 5712 int status; 5713 5714 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5715 cmd = libie_aq_raw(&desc); 5716 cmd->phy_output = *phy_output; 5717 5718 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5719 if (!status) { 5720 *phy_output = cmd->phy_output; 5721 if (port_num) 5722 *port_num = cmd->port_num; 5723 if (flags) 5724 *flags = cmd->flags; 5725 if (node_handle) 5726 *node_handle = le16_to_cpu(cmd->node_handle); 5727 } 5728 5729 return status; 5730 } 5731 5732 /** 5733 * ice_aq_get_sensor_reading 5734 * @hw: pointer to the HW struct 5735 * @data: pointer to data to be read from the sensor 5736 * 5737 * Get sensor reading (0x0632) 5738 */ 5739 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5740 struct ice_aqc_get_sensor_reading_resp *data) 5741 { 5742 struct ice_aqc_get_sensor_reading *cmd; 5743 struct libie_aq_desc desc; 5744 int status; 5745 5746 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5747 cmd = libie_aq_raw(&desc); 5748 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5749 #define ICE_INTERNAL_TEMP_SENSOR 0 5750 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5751 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5752 5753 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5754 if (!status) 5755 memcpy(data, &desc.params.raw, 5756 sizeof(*data)); 5757 5758 return status; 5759 } 5760 5761 /** 5762 * ice_replay_pre_init - replay pre initialization 5763 * @hw: pointer to the HW struct 5764 * 5765 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5766 */ 5767 static int ice_replay_pre_init(struct ice_hw *hw) 5768 { 5769 struct ice_switch_info *sw = hw->switch_info; 5770 u8 i; 5771 5772 /* Delete old entries from replay filter list head if there is any */ 5773 ice_rm_all_sw_replay_rule_info(hw); 5774 /* In start of replay, move entries into replay_rules list, it 5775 * will allow adding rules entries back to filt_rules list, 5776 * which is operational list. 5777 */ 5778 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5779 list_replace_init(&sw->recp_list[i].filt_rules, 5780 &sw->recp_list[i].filt_replay_rules); 5781 ice_sched_replay_agg_vsi_preinit(hw); 5782 5783 return 0; 5784 } 5785 5786 /** 5787 * ice_replay_vsi - replay VSI configuration 5788 * @hw: pointer to the HW struct 5789 * @vsi_handle: driver VSI handle 5790 * 5791 * Restore all VSI configuration after reset. It is required to call this 5792 * function with main VSI first. 5793 */ 5794 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5795 { 5796 int status; 5797 5798 if (!ice_is_vsi_valid(hw, vsi_handle)) 5799 return -EINVAL; 5800 5801 /* Replay pre-initialization if there is any */ 5802 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5803 status = ice_replay_pre_init(hw); 5804 if (status) 5805 return status; 5806 } 5807 /* Replay per VSI all RSS configurations */ 5808 status = ice_replay_rss_cfg(hw, vsi_handle); 5809 if (status) 5810 return status; 5811 /* Replay per VSI all filters */ 5812 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5813 if (!status) 5814 status = ice_replay_vsi_agg(hw, vsi_handle); 5815 return status; 5816 } 5817 5818 /** 5819 * ice_replay_post - post replay configuration cleanup 5820 * @hw: pointer to the HW struct 5821 * 5822 * Post replay cleanup. 5823 */ 5824 void ice_replay_post(struct ice_hw *hw) 5825 { 5826 /* Delete old entries from replay filter list head */ 5827 ice_rm_all_sw_replay_rule_info(hw); 5828 ice_sched_replay_agg(hw); 5829 } 5830 5831 /** 5832 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5833 * @hw: ptr to the hardware info 5834 * @reg: offset of 64 bit HW register to read from 5835 * @prev_stat_loaded: bool to specify if previous stats are loaded 5836 * @prev_stat: ptr to previous loaded stat value 5837 * @cur_stat: ptr to current stat value 5838 */ 5839 void 5840 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5841 u64 *prev_stat, u64 *cur_stat) 5842 { 5843 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5844 5845 /* device stats are not reset at PFR, they likely will not be zeroed 5846 * when the driver starts. Thus, save the value from the first read 5847 * without adding to the statistic value so that we report stats which 5848 * count up from zero. 5849 */ 5850 if (!prev_stat_loaded) { 5851 *prev_stat = new_data; 5852 return; 5853 } 5854 5855 /* Calculate the difference between the new and old values, and then 5856 * add it to the software stat value. 5857 */ 5858 if (new_data >= *prev_stat) 5859 *cur_stat += new_data - *prev_stat; 5860 else 5861 /* to manage the potential roll-over */ 5862 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5863 5864 /* Update the previously stored value to prepare for next read */ 5865 *prev_stat = new_data; 5866 } 5867 5868 /** 5869 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5870 * @hw: ptr to the hardware info 5871 * @reg: offset of HW register to read from 5872 * @prev_stat_loaded: bool to specify if previous stats are loaded 5873 * @prev_stat: ptr to previous loaded stat value 5874 * @cur_stat: ptr to current stat value 5875 */ 5876 void 5877 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5878 u64 *prev_stat, u64 *cur_stat) 5879 { 5880 u32 new_data; 5881 5882 new_data = rd32(hw, reg); 5883 5884 /* device stats are not reset at PFR, they likely will not be zeroed 5885 * when the driver starts. Thus, save the value from the first read 5886 * without adding to the statistic value so that we report stats which 5887 * count up from zero. 5888 */ 5889 if (!prev_stat_loaded) { 5890 *prev_stat = new_data; 5891 return; 5892 } 5893 5894 /* Calculate the difference between the new and old values, and then 5895 * add it to the software stat value. 5896 */ 5897 if (new_data >= *prev_stat) 5898 *cur_stat += new_data - *prev_stat; 5899 else 5900 /* to manage the potential roll-over */ 5901 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5902 5903 /* Update the previously stored value to prepare for next read */ 5904 *prev_stat = new_data; 5905 } 5906 5907 /** 5908 * ice_sched_query_elem - query element information from HW 5909 * @hw: pointer to the HW struct 5910 * @node_teid: node TEID to be queried 5911 * @buf: buffer to element information 5912 * 5913 * This function queries HW element information 5914 */ 5915 int 5916 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5917 struct ice_aqc_txsched_elem_data *buf) 5918 { 5919 u16 buf_size, num_elem_ret = 0; 5920 int status; 5921 5922 buf_size = sizeof(*buf); 5923 memset(buf, 0, buf_size); 5924 buf->node_teid = cpu_to_le32(node_teid); 5925 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5926 NULL); 5927 if (status || num_elem_ret != 1) 5928 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5929 return status; 5930 } 5931 5932 /** 5933 * ice_aq_read_i2c 5934 * @hw: pointer to the hw struct 5935 * @topo_addr: topology address for a device to communicate with 5936 * @bus_addr: 7-bit I2C bus address 5937 * @addr: I2C memory address (I2C offset) with up to 16 bits 5938 * @params: I2C parameters: bit [7] - Repeated start, 5939 * bits [6:5] data offset size, 5940 * bit [4] - I2C address type, 5941 * bits [3:0] - data size to read (0-16 bytes) 5942 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5943 * @cd: pointer to command details structure or NULL 5944 * 5945 * Read I2C (0x06E2) 5946 */ 5947 int 5948 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5949 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5950 struct ice_sq_cd *cd) 5951 { 5952 struct libie_aq_desc desc = { 0 }; 5953 struct ice_aqc_i2c *cmd; 5954 u8 data_size; 5955 int status; 5956 5957 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5958 cmd = libie_aq_raw(&desc); 5959 5960 if (!data) 5961 return -EINVAL; 5962 5963 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5964 5965 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5966 cmd->topo_addr = topo_addr; 5967 cmd->i2c_params = params; 5968 cmd->i2c_addr = addr; 5969 5970 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5971 if (!status) { 5972 struct ice_aqc_read_i2c_resp *resp; 5973 u8 i; 5974 5975 resp = libie_aq_raw(&desc); 5976 for (i = 0; i < data_size; i++) { 5977 *data = resp->i2c_data[i]; 5978 data++; 5979 } 5980 } 5981 5982 return status; 5983 } 5984 5985 /** 5986 * ice_aq_write_i2c 5987 * @hw: pointer to the hw struct 5988 * @topo_addr: topology address for a device to communicate with 5989 * @bus_addr: 7-bit I2C bus address 5990 * @addr: I2C memory address (I2C offset) with up to 16 bits 5991 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5992 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5993 * @cd: pointer to command details structure or NULL 5994 * 5995 * Write I2C (0x06E3) 5996 * 5997 * * Return: 5998 * * 0 - Successful write to the i2c device 5999 * * -EINVAL - Data size greater than 4 bytes 6000 * * -EIO - FW error 6001 */ 6002 int 6003 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6004 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6005 struct ice_sq_cd *cd) 6006 { 6007 struct libie_aq_desc desc = { 0 }; 6008 struct ice_aqc_i2c *cmd; 6009 u8 data_size; 6010 6011 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6012 cmd = libie_aq_raw(&desc); 6013 6014 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6015 6016 /* data_size limited to 4 */ 6017 if (data_size > 4) 6018 return -EINVAL; 6019 6020 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6021 cmd->topo_addr = topo_addr; 6022 cmd->i2c_params = params; 6023 cmd->i2c_addr = addr; 6024 6025 memcpy(cmd->i2c_data, data, data_size); 6026 6027 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6028 } 6029 6030 /** 6031 * ice_get_pca9575_handle - find and return the PCA9575 controller 6032 * @hw: pointer to the hw struct 6033 * @pca9575_handle: GPIO controller's handle 6034 * 6035 * Find and return the GPIO controller's handle in the netlist. 6036 * When found - the value will be cached in the hw structure and following calls 6037 * will return cached value. 6038 * 6039 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6040 */ 6041 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6042 { 6043 struct ice_aqc_get_link_topo *cmd; 6044 struct libie_aq_desc desc; 6045 int err; 6046 u8 idx; 6047 6048 /* If handle was read previously return cached value */ 6049 if (hw->io_expander_handle) { 6050 *pca9575_handle = hw->io_expander_handle; 6051 return 0; 6052 } 6053 6054 #define SW_PCA9575_SFP_TOPO_IDX 2 6055 #define SW_PCA9575_QSFP_TOPO_IDX 1 6056 6057 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6058 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6059 idx = SW_PCA9575_SFP_TOPO_IDX; 6060 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6061 idx = SW_PCA9575_QSFP_TOPO_IDX; 6062 else 6063 return -ENXIO; 6064 6065 /* If handle was not detected read it from the netlist */ 6066 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6067 cmd = libie_aq_raw(&desc); 6068 cmd->addr.topo_params.node_type_ctx = 6069 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6070 cmd->addr.topo_params.index = idx; 6071 6072 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6073 if (err) 6074 return -ENXIO; 6075 6076 /* Verify if we found the right IO expander type */ 6077 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6078 return -ENXIO; 6079 6080 /* If present save the handle and return it */ 6081 hw->io_expander_handle = 6082 le16_to_cpu(cmd->addr.handle); 6083 *pca9575_handle = hw->io_expander_handle; 6084 6085 return 0; 6086 } 6087 6088 /** 6089 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6090 * @hw: pointer to the hw struct 6091 * @offset: GPIO controller register offset 6092 * @data: pointer to data to be read from the GPIO controller 6093 * 6094 * Return: 0 on success, negative error code otherwise. 6095 */ 6096 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6097 { 6098 struct ice_aqc_link_topo_addr link_topo; 6099 __le16 addr; 6100 u16 handle; 6101 int err; 6102 6103 memset(&link_topo, 0, sizeof(link_topo)); 6104 6105 err = ice_get_pca9575_handle(hw, &handle); 6106 if (err) 6107 return err; 6108 6109 link_topo.handle = cpu_to_le16(handle); 6110 link_topo.topo_params.node_type_ctx = 6111 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6112 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6113 6114 addr = cpu_to_le16((u16)offset); 6115 6116 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6117 } 6118 6119 /** 6120 * ice_aq_set_gpio 6121 * @hw: pointer to the hw struct 6122 * @gpio_ctrl_handle: GPIO controller node handle 6123 * @pin_idx: IO Number of the GPIO that needs to be set 6124 * @value: SW provide IO value to set in the LSB 6125 * @cd: pointer to command details structure or NULL 6126 * 6127 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6128 */ 6129 int 6130 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6131 struct ice_sq_cd *cd) 6132 { 6133 struct libie_aq_desc desc; 6134 struct ice_aqc_gpio *cmd; 6135 6136 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6137 cmd = libie_aq_raw(&desc); 6138 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6139 cmd->gpio_num = pin_idx; 6140 cmd->gpio_val = value ? 1 : 0; 6141 6142 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6143 } 6144 6145 /** 6146 * ice_aq_get_gpio 6147 * @hw: pointer to the hw struct 6148 * @gpio_ctrl_handle: GPIO controller node handle 6149 * @pin_idx: IO Number of the GPIO that needs to be set 6150 * @value: IO value read 6151 * @cd: pointer to command details structure or NULL 6152 * 6153 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6154 * the topology 6155 */ 6156 int 6157 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6158 bool *value, struct ice_sq_cd *cd) 6159 { 6160 struct libie_aq_desc desc; 6161 struct ice_aqc_gpio *cmd; 6162 int status; 6163 6164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6165 cmd = libie_aq_raw(&desc); 6166 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6167 cmd->gpio_num = pin_idx; 6168 6169 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6170 if (status) 6171 return status; 6172 6173 *value = !!cmd->gpio_val; 6174 return 0; 6175 } 6176 6177 /** 6178 * ice_is_fw_api_min_ver 6179 * @hw: pointer to the hardware structure 6180 * @maj: major version 6181 * @min: minor version 6182 * @patch: patch version 6183 * 6184 * Checks if the firmware API is minimum version 6185 */ 6186 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6187 { 6188 if (hw->api_maj_ver == maj) { 6189 if (hw->api_min_ver > min) 6190 return true; 6191 if (hw->api_min_ver == min && hw->api_patch >= patch) 6192 return true; 6193 } else if (hw->api_maj_ver > maj) { 6194 return true; 6195 } 6196 6197 return false; 6198 } 6199 6200 /** 6201 * ice_fw_supports_link_override 6202 * @hw: pointer to the hardware structure 6203 * 6204 * Checks if the firmware supports link override 6205 */ 6206 bool ice_fw_supports_link_override(struct ice_hw *hw) 6207 { 6208 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6209 ICE_FW_API_LINK_OVERRIDE_MIN, 6210 ICE_FW_API_LINK_OVERRIDE_PATCH); 6211 } 6212 6213 /** 6214 * ice_get_link_default_override 6215 * @ldo: pointer to the link default override struct 6216 * @pi: pointer to the port info struct 6217 * 6218 * Gets the link default override for a port 6219 */ 6220 int 6221 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6222 struct ice_port_info *pi) 6223 { 6224 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6225 struct ice_hw *hw = pi->hw; 6226 int status; 6227 6228 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6229 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6230 if (status) { 6231 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6232 return status; 6233 } 6234 6235 /* Each port has its own config; calculate for our port */ 6236 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6237 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6238 6239 /* link options first */ 6240 status = ice_read_sr_word(hw, tlv_start, &buf); 6241 if (status) { 6242 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6243 return status; 6244 } 6245 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6246 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6247 ICE_LINK_OVERRIDE_PHY_CFG_S; 6248 6249 /* link PHY config */ 6250 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6251 status = ice_read_sr_word(hw, offset, &buf); 6252 if (status) { 6253 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6254 return status; 6255 } 6256 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6257 6258 /* PHY types low */ 6259 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6260 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6261 status = ice_read_sr_word(hw, (offset + i), &buf); 6262 if (status) { 6263 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6264 return status; 6265 } 6266 /* shift 16 bits at a time to fill 64 bits */ 6267 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6268 } 6269 6270 /* PHY types high */ 6271 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6272 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6273 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6274 status = ice_read_sr_word(hw, (offset + i), &buf); 6275 if (status) { 6276 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6277 return status; 6278 } 6279 /* shift 16 bits at a time to fill 64 bits */ 6280 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6281 } 6282 6283 return status; 6284 } 6285 6286 /** 6287 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6288 * @caps: get PHY capability data 6289 */ 6290 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6291 { 6292 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6293 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6294 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6295 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6296 return true; 6297 6298 return false; 6299 } 6300 6301 /** 6302 * ice_is_fw_health_report_supported - checks if firmware supports health events 6303 * @hw: pointer to the hardware structure 6304 * 6305 * Return: true if firmware supports health status reports, 6306 * false otherwise 6307 */ 6308 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6309 { 6310 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6311 ICE_FW_API_HEALTH_REPORT_MIN, 6312 ICE_FW_API_HEALTH_REPORT_PATCH); 6313 } 6314 6315 /** 6316 * ice_aq_set_health_status_cfg - Configure FW health events 6317 * @hw: pointer to the HW struct 6318 * @event_source: type of diagnostic events to enable 6319 * 6320 * Configure the health status event types that the firmware will send to this 6321 * PF. The supported event types are: PF-specific, all PFs, and global. 6322 * 6323 * Return: 0 on success, negative error code otherwise. 6324 */ 6325 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6326 { 6327 struct ice_aqc_set_health_status_cfg *cmd; 6328 struct libie_aq_desc desc; 6329 6330 cmd = libie_aq_raw(&desc); 6331 6332 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6333 6334 cmd->event_source = event_source; 6335 6336 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6337 } 6338 6339 /** 6340 * ice_aq_set_lldp_mib - Set the LLDP MIB 6341 * @hw: pointer to the HW struct 6342 * @mib_type: Local, Remote or both Local and Remote MIBs 6343 * @buf: pointer to the caller-supplied buffer to store the MIB block 6344 * @buf_size: size of the buffer (in bytes) 6345 * @cd: pointer to command details structure or NULL 6346 * 6347 * Set the LLDP MIB. (0x0A08) 6348 */ 6349 int 6350 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6351 struct ice_sq_cd *cd) 6352 { 6353 struct ice_aqc_lldp_set_local_mib *cmd; 6354 struct libie_aq_desc desc; 6355 6356 cmd = libie_aq_raw(&desc); 6357 6358 if (buf_size == 0 || !buf) 6359 return -EINVAL; 6360 6361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6362 6363 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6364 desc.datalen = cpu_to_le16(buf_size); 6365 6366 cmd->type = mib_type; 6367 cmd->length = cpu_to_le16(buf_size); 6368 6369 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6370 } 6371 6372 /** 6373 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6374 * @hw: pointer to HW struct 6375 */ 6376 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6377 { 6378 if (hw->mac_type != ICE_MAC_E810) 6379 return false; 6380 6381 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6382 ICE_FW_API_LLDP_FLTR_MIN, 6383 ICE_FW_API_LLDP_FLTR_PATCH); 6384 } 6385 6386 /** 6387 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6388 * @hw: pointer to HW struct 6389 * @vsi: VSI to add the filter to 6390 * @add: boolean for if adding or removing a filter 6391 * 6392 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6393 * with this HW or VSI, otherwise an error corresponding to 6394 * the AQ transaction result. 6395 */ 6396 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6397 { 6398 struct ice_aqc_lldp_filter_ctrl *cmd; 6399 struct libie_aq_desc desc; 6400 6401 if (!ice_fw_supports_lldp_fltr_ctrl(hw)) 6402 return -EOPNOTSUPP; 6403 6404 cmd = libie_aq_raw(&desc); 6405 6406 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6407 6408 if (add) 6409 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6410 else 6411 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6412 6413 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6414 6415 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6416 } 6417 6418 /** 6419 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6420 * @hw: pointer to HW struct 6421 */ 6422 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6423 { 6424 struct libie_aq_desc desc; 6425 6426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6427 6428 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6429 } 6430 6431 /** 6432 * ice_fw_supports_report_dflt_cfg 6433 * @hw: pointer to the hardware structure 6434 * 6435 * Checks if the firmware supports report default configuration 6436 */ 6437 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6438 { 6439 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6440 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6441 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6442 } 6443 6444 /* each of the indexes into the following array match the speed of a return 6445 * value from the list of AQ returned speeds like the range: 6446 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6447 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6448 * array. The array is defined as 15 elements long because the link_speed 6449 * returned by the firmware is a 16 bit * value, but is indexed 6450 * by [fls(speed) - 1] 6451 */ 6452 static const u32 ice_aq_to_link_speed[] = { 6453 SPEED_10, /* BIT(0) */ 6454 SPEED_100, 6455 SPEED_1000, 6456 SPEED_2500, 6457 SPEED_5000, 6458 SPEED_10000, 6459 SPEED_20000, 6460 SPEED_25000, 6461 SPEED_40000, 6462 SPEED_50000, 6463 SPEED_100000, /* BIT(10) */ 6464 SPEED_200000, 6465 }; 6466 6467 /** 6468 * ice_get_link_speed - get integer speed from table 6469 * @index: array index from fls(aq speed) - 1 6470 * 6471 * Returns: u32 value containing integer speed 6472 */ 6473 u32 ice_get_link_speed(u16 index) 6474 { 6475 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6476 return 0; 6477 6478 return ice_aq_to_link_speed[index]; 6479 } 6480 6481 /** 6482 * ice_get_dest_cgu - get destination CGU dev for given HW 6483 * @hw: pointer to the HW struct 6484 * 6485 * Get CGU client id for CGU register read/write operations. 6486 * 6487 * Return: CGU device id to use in SBQ transactions. 6488 */ 6489 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6490 { 6491 /* On dual complex E825 only complex 0 has functional CGU powering all 6492 * the PHYs. 6493 * SBQ destination device cgu points to CGU on a current complex and to 6494 * access primary CGU from the secondary complex, the driver should use 6495 * cgu_peer as a destination device. 6496 */ 6497 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6498 !ice_is_primary(hw)) 6499 return ice_sbq_dev_cgu_peer; 6500 return ice_sbq_dev_cgu; 6501 } 6502 6503 /** 6504 * ice_read_cgu_reg - Read a CGU register 6505 * @hw: Pointer to the HW struct 6506 * @addr: Register address to read 6507 * @val: Storage for register value read 6508 * 6509 * Read the contents of a register of the Clock Generation Unit. Only 6510 * applicable to E82X devices. 6511 * 6512 * Return: 0 on success, other error codes when failed to read from CGU. 6513 */ 6514 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6515 { 6516 struct ice_sbq_msg_input cgu_msg = { 6517 .dest_dev = ice_get_dest_cgu(hw), 6518 .opcode = ice_sbq_msg_rd, 6519 .msg_addr_low = addr 6520 }; 6521 int err; 6522 6523 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6524 if (err) { 6525 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6526 addr, err); 6527 return err; 6528 } 6529 6530 *val = cgu_msg.data; 6531 6532 return 0; 6533 } 6534 6535 /** 6536 * ice_write_cgu_reg - Write a CGU register 6537 * @hw: Pointer to the HW struct 6538 * @addr: Register address to write 6539 * @val: Value to write into the register 6540 * 6541 * Write the specified value to a register of the Clock Generation Unit. Only 6542 * applicable to E82X devices. 6543 * 6544 * Return: 0 on success, other error codes when failed to write to CGU. 6545 */ 6546 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6547 { 6548 struct ice_sbq_msg_input cgu_msg = { 6549 .dest_dev = ice_get_dest_cgu(hw), 6550 .opcode = ice_sbq_msg_wr, 6551 .msg_addr_low = addr, 6552 .data = val 6553 }; 6554 int err; 6555 6556 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6557 if (err) 6558 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6559 addr, err); 6560 6561 return err; 6562 } 6563