1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/cleanup.h>
9 #include <linux/crc8.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/sysfs.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/spi/spi.h>
25 #include <linux/types.h>
26 #include <linux/unaligned.h>
27
28 #include <dt-bindings/iio/addac/adi,ad74413r.h>
29
30 #define AD74413R_CRC_POLYNOMIAL 0x7
31 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
32
33 #define AD74413R_CHANNEL_MAX 4
34
35 #define AD74413R_FRAME_SIZE 4
36
37 struct ad74413r_chip_info {
38 const char *name;
39 bool hart_support;
40 };
41
42 struct ad74413r_channel_config {
43 u32 func;
44 u32 drive_strength;
45 bool gpo_comparator;
46 bool initialized;
47 };
48
49 struct ad74413r_channels {
50 const struct iio_chan_spec *channels;
51 unsigned int num_channels;
52 };
53
54 struct ad74413r_state {
55 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX];
56 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
57 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX];
58 struct gpio_chip gpo_gpiochip;
59 struct gpio_chip comp_gpiochip;
60 struct completion adc_data_completion;
61 unsigned int num_gpo_gpios;
62 unsigned int num_comparator_gpios;
63 u32 sense_resistor_ohms;
64 int refin_reg_uv;
65 /*
66 * Synchronize consecutive operations when doing a one-shot
67 * conversion and when updating the ADC samples SPI message.
68 */
69 struct mutex lock;
70
71 const struct ad74413r_chip_info *chip_info;
72 struct spi_device *spi;
73 struct regmap *regmap;
74 struct device *dev;
75 struct iio_trigger *trig;
76
77 size_t adc_active_channels;
78 struct spi_message adc_samples_msg;
79 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
80
81 /*
82 * DMA (thus cache coherency maintenance) may require the
83 * transfer buffers to live in their own cache lines.
84 */
85 struct {
86 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
87 aligned_s64 timestamp;
88 } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
89
90 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
91 u8 reg_tx_buf[AD74413R_FRAME_SIZE];
92 u8 reg_rx_buf[AD74413R_FRAME_SIZE];
93 };
94
95 #define AD74413R_REG_NOP 0x00
96
97 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
98 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
99
100 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
101 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5)
102 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3)
103 #define AD74413R_ADC_CONFIG_CH_200K_TO_GND BIT(2)
104 #define AD74413R_ADC_RANGE_10V 0b000
105 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
106 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
107 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
108 #define AD74413R_ADC_REJECTION_50_60 0b00
109 #define AD74413R_ADC_REJECTION_NONE 0b01
110 #define AD74413R_ADC_REJECTION_50_60_HART 0b10
111 #define AD74413R_ADC_REJECTION_HART 0b11
112
113 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x))
114 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0)
115 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5)
116 #define AD74413R_DIN_SINK_MASK GENMASK(9, 6)
117
118 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x))
119 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0)
120 #define AD74413R_DAC_VOLTAGE_MAX 11000
121
122 #define AD74413R_REG_GPO_PAR_DATA 0x0d
123 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x))
124 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3)
125 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0)
126 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000
127 #define AD74413R_GPO_CONFIG_LOGIC 0b001
128 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010
129 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011
130 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100
131
132 #define AD74413R_REG_ADC_CONV_CTRL 0x23
133 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8)
134 #define AD74413R_CONV_SEQ_ON 0b00
135 #define AD74413R_CONV_SEQ_SINGLE 0b01
136 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10
137 #define AD74413R_CONV_SEQ_OFF 0b11
138 #define AD74413R_CH_EN_MASK(x) BIT(x)
139
140 #define AD74413R_REG_DIN_COMP_OUT 0x25
141
142 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x))
143 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0)
144
145 #define AD74413R_REG_READ_SELECT 0x41
146
147 #define AD74413R_REG_CMD_KEY 0x44
148 #define AD74413R_CMD_KEY_LDAC 0x953a
149 #define AD74413R_CMD_KEY_RESET1 0x15fa
150 #define AD74413R_CMD_KEY_RESET2 0xaf51
151
152 static const int ad74413r_adc_sampling_rates[] = {
153 20, 4800,
154 };
155
156 static const int ad74413r_adc_sampling_rates_hart[] = {
157 10, 20, 1200, 4800,
158 };
159
ad74413r_crc(u8 * buf)160 static int ad74413r_crc(u8 *buf)
161 {
162 return crc8(ad74413r_crc8_table, buf, 3, 0);
163 }
164
ad74413r_format_reg_write(u8 reg,u16 val,u8 * buf)165 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
166 {
167 buf[0] = reg;
168 put_unaligned_be16(val, &buf[1]);
169 buf[3] = ad74413r_crc(buf);
170 }
171
ad74413r_reg_write(void * context,unsigned int reg,unsigned int val)172 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
173 {
174 struct ad74413r_state *st = context;
175
176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
177
178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
179 }
180
ad74413r_crc_check(struct ad74413r_state * st,u8 * buf)181 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
182 {
183 u8 expected_crc = ad74413r_crc(buf);
184
185 if (buf[3] != expected_crc) {
186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
187 buf[3], buf[0], buf[1], buf[2]);
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
ad74413r_reg_read(void * context,unsigned int reg,unsigned int * val)194 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
195 {
196 struct ad74413r_state *st = context;
197 struct spi_transfer reg_read_xfer[] = {
198 {
199 .tx_buf = st->reg_tx_buf,
200 .len = AD74413R_FRAME_SIZE,
201 .cs_change = 1,
202 },
203 {
204 .rx_buf = st->reg_rx_buf,
205 .len = AD74413R_FRAME_SIZE,
206 },
207 };
208 int ret;
209
210 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
211 st->reg_tx_buf);
212
213 ret = spi_sync_transfer(st->spi, reg_read_xfer,
214 ARRAY_SIZE(reg_read_xfer));
215 if (ret)
216 return ret;
217
218 ret = ad74413r_crc_check(st, st->reg_rx_buf);
219 if (ret)
220 return ret;
221
222 *val = get_unaligned_be16(&st->reg_rx_buf[1]);
223
224 return 0;
225 }
226
227 static const struct regmap_config ad74413r_regmap_config = {
228 .reg_bits = 8,
229 .val_bits = 16,
230 .reg_read = ad74413r_reg_read,
231 .reg_write = ad74413r_reg_write,
232 };
233
ad74413r_set_gpo_config(struct ad74413r_state * st,unsigned int offset,u8 mode)234 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
235 unsigned int offset, u8 mode)
236 {
237 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
238 AD74413R_GPO_CONFIG_SELECT_MASK, mode);
239 }
240
241 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
242 0, 13, 18, 24, 32, 42, 56, 75,
243 100, 130, 180, 240, 320, 420, 560, 750,
244 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500,
245 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
246 };
247
ad74413r_set_comp_debounce(struct ad74413r_state * st,unsigned int offset,unsigned int debounce)248 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
249 unsigned int offset,
250 unsigned int debounce)
251 {
252 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
253 unsigned int i;
254
255 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
256 if (debounce <= ad74413r_debounce_map[i]) {
257 val = i;
258 break;
259 }
260
261 return regmap_update_bits(st->regmap,
262 AD74413R_REG_DIN_CONFIG_X(offset),
263 AD74413R_DIN_DEBOUNCE_MASK,
264 val);
265 }
266
ad74413r_set_comp_drive_strength(struct ad74413r_state * st,unsigned int offset,unsigned int strength)267 static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st,
268 unsigned int offset,
269 unsigned int strength)
270 {
271 strength = min(strength, 1800U);
272
273 return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset),
274 AD74413R_DIN_SINK_MASK,
275 FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120));
276 }
277
278
ad74413r_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)279 static int ad74413r_gpio_set(struct gpio_chip *chip, unsigned int offset,
280 int val)
281 {
282 struct ad74413r_state *st = gpiochip_get_data(chip);
283 unsigned int real_offset = st->gpo_gpio_offsets[offset];
284 int ret;
285
286 ret = ad74413r_set_gpo_config(st, real_offset,
287 AD74413R_GPO_CONFIG_LOGIC);
288 if (ret)
289 return ret;
290
291 return regmap_update_bits(st->regmap,
292 AD74413R_REG_GPO_CONFIG_X(real_offset),
293 AD74413R_GPO_CONFIG_DATA_MASK,
294 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
295 }
296
ad74413r_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)297 static int ad74413r_gpio_set_multiple(struct gpio_chip *chip,
298 unsigned long *mask, unsigned long *bits)
299 {
300 struct ad74413r_state *st = gpiochip_get_data(chip);
301 unsigned long real_mask = 0;
302 unsigned long real_bits = 0;
303 unsigned int offset;
304 int ret;
305
306 for_each_set_bit(offset, mask, chip->ngpio) {
307 unsigned int real_offset = st->gpo_gpio_offsets[offset];
308
309 ret = ad74413r_set_gpo_config(st, real_offset,
310 AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
311 if (ret)
312 return ret;
313
314 real_mask |= BIT(real_offset);
315 if (*bits & offset)
316 real_bits |= BIT(real_offset);
317 }
318
319 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
320 real_mask, real_bits);
321 }
322
ad74413r_gpio_get(struct gpio_chip * chip,unsigned int offset)323 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
324 {
325 struct ad74413r_state *st = gpiochip_get_data(chip);
326 unsigned int real_offset = st->comp_gpio_offsets[offset];
327 unsigned int status;
328 int ret;
329
330 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
331 if (ret)
332 return ret;
333
334 status &= BIT(real_offset);
335
336 return status ? 1 : 0;
337 }
338
ad74413r_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)339 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
340 unsigned long *mask,
341 unsigned long *bits)
342 {
343 struct ad74413r_state *st = gpiochip_get_data(chip);
344 unsigned int offset;
345 unsigned int val;
346 int ret;
347
348 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
349 if (ret)
350 return ret;
351
352 for_each_set_bit(offset, mask, chip->ngpio) {
353 unsigned int real_offset = st->comp_gpio_offsets[offset];
354
355 __assign_bit(offset, bits, val & BIT(real_offset));
356 }
357
358 return ret;
359 }
360
ad74413r_gpio_get_gpo_direction(struct gpio_chip * chip,unsigned int offset)361 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
362 unsigned int offset)
363 {
364 return GPIO_LINE_DIRECTION_OUT;
365 }
366
ad74413r_gpio_get_comp_direction(struct gpio_chip * chip,unsigned int offset)367 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
368 unsigned int offset)
369 {
370 return GPIO_LINE_DIRECTION_IN;
371 }
372
ad74413r_gpio_set_gpo_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)373 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
374 unsigned int offset,
375 unsigned long config)
376 {
377 struct ad74413r_state *st = gpiochip_get_data(chip);
378 unsigned int real_offset = st->gpo_gpio_offsets[offset];
379
380 switch (pinconf_to_config_param(config)) {
381 case PIN_CONFIG_BIAS_PULL_DOWN:
382 return ad74413r_set_gpo_config(st, real_offset,
383 AD74413R_GPO_CONFIG_100K_PULL_DOWN);
384 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
385 return ad74413r_set_gpo_config(st, real_offset,
386 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
387 default:
388 return -ENOTSUPP;
389 }
390 }
391
ad74413r_gpio_set_comp_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)392 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
393 unsigned int offset,
394 unsigned long config)
395 {
396 struct ad74413r_state *st = gpiochip_get_data(chip);
397 unsigned int real_offset = st->comp_gpio_offsets[offset];
398
399 switch (pinconf_to_config_param(config)) {
400 case PIN_CONFIG_INPUT_DEBOUNCE:
401 return ad74413r_set_comp_debounce(st, real_offset,
402 pinconf_to_config_argument(config));
403 default:
404 return -ENOTSUPP;
405 }
406 }
407
ad74413r_reset(struct ad74413r_state * st)408 static int ad74413r_reset(struct ad74413r_state *st)
409 {
410 struct gpio_desc *reset_gpio;
411 int ret;
412
413 reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_HIGH);
414 if (IS_ERR(reset_gpio))
415 return PTR_ERR(reset_gpio);
416
417 if (reset_gpio) {
418 fsleep(50);
419 gpiod_set_value_cansleep(reset_gpio, 0);
420 return 0;
421 }
422
423 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
424 AD74413R_CMD_KEY_RESET1);
425 if (ret)
426 return ret;
427
428 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
429 AD74413R_CMD_KEY_RESET2);
430 }
431
ad74413r_set_channel_dac_code(struct ad74413r_state * st,unsigned int channel,int dac_code)432 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
433 unsigned int channel, int dac_code)
434 {
435 struct reg_sequence reg_seq[2] = {
436 { AD74413R_REG_DAC_CODE_X(channel), dac_code },
437 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
438 };
439
440 return regmap_multi_reg_write(st->regmap, reg_seq, 2);
441 }
442
ad74413r_set_channel_function(struct ad74413r_state * st,unsigned int channel,u8 func)443 static int ad74413r_set_channel_function(struct ad74413r_state *st,
444 unsigned int channel, u8 func)
445 {
446 int ret;
447
448 ret = regmap_update_bits(st->regmap,
449 AD74413R_REG_CH_FUNC_SETUP_X(channel),
450 AD74413R_CH_FUNC_SETUP_MASK,
451 CH_FUNC_HIGH_IMPEDANCE);
452 if (ret)
453 return ret;
454
455 /* Set DAC code to 0 prior to changing channel function */
456 ret = ad74413r_set_channel_dac_code(st, channel, 0);
457 if (ret)
458 return ret;
459
460 /* Delay required before transition to new desired mode */
461 usleep_range(130, 150);
462
463 ret = regmap_update_bits(st->regmap,
464 AD74413R_REG_CH_FUNC_SETUP_X(channel),
465 AD74413R_CH_FUNC_SETUP_MASK, func);
466 if (ret)
467 return ret;
468
469 /* Delay required before updating the new DAC code */
470 usleep_range(150, 170);
471
472 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER)
473 ret = regmap_set_bits(st->regmap,
474 AD74413R_REG_ADC_CONFIG_X(channel),
475 AD74413R_ADC_CONFIG_CH_200K_TO_GND);
476
477 return ret;
478 }
479
ad74413r_set_adc_conv_seq(struct ad74413r_state * st,unsigned int status)480 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
481 unsigned int status)
482 {
483 int ret;
484
485 /*
486 * These bits do not clear when a conversion completes.
487 * To enable a subsequent conversion, repeat the write.
488 */
489 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
490 AD74413R_CONV_SEQ_MASK,
491 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
492 if (ret)
493 return ret;
494
495 /*
496 * Wait 100us before starting conversions.
497 */
498 usleep_range(100, 120);
499
500 return 0;
501 }
502
ad74413r_set_adc_channel_enable(struct ad74413r_state * st,unsigned int channel,bool status)503 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
504 unsigned int channel,
505 bool status)
506 {
507 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
508 AD74413R_CH_EN_MASK(channel),
509 status ? AD74413R_CH_EN_MASK(channel) : 0);
510 }
511
ad74413r_get_adc_range(struct ad74413r_state * st,unsigned int channel,unsigned int * val)512 static int ad74413r_get_adc_range(struct ad74413r_state *st,
513 unsigned int channel,
514 unsigned int *val)
515 {
516 int ret;
517
518 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
519 if (ret)
520 return ret;
521
522 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
523
524 return 0;
525 }
526
ad74413r_get_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int * val)527 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
528 unsigned int channel,
529 unsigned int *val)
530 {
531 int ret;
532
533 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
534 if (ret)
535 return ret;
536
537 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
538
539 return 0;
540 }
541
ad74413r_set_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int val)542 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
543 unsigned int channel,
544 unsigned int val)
545 {
546 return regmap_update_bits(st->regmap,
547 AD74413R_REG_ADC_CONFIG_X(channel),
548 AD74413R_ADC_CONFIG_REJECTION_MASK,
549 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
550 val));
551 }
552
ad74413r_rejection_to_rate(struct ad74413r_state * st,unsigned int rej,int * val)553 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
554 unsigned int rej, int *val)
555 {
556 switch (rej) {
557 case AD74413R_ADC_REJECTION_50_60:
558 *val = 20;
559 return 0;
560 case AD74413R_ADC_REJECTION_NONE:
561 *val = 4800;
562 return 0;
563 case AD74413R_ADC_REJECTION_50_60_HART:
564 *val = 10;
565 return 0;
566 case AD74413R_ADC_REJECTION_HART:
567 *val = 1200;
568 return 0;
569 default:
570 dev_err(st->dev, "ADC rejection invalid\n");
571 return -EINVAL;
572 }
573 }
574
ad74413r_rate_to_rejection(struct ad74413r_state * st,int rate,unsigned int * val)575 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
576 int rate, unsigned int *val)
577 {
578 switch (rate) {
579 case 20:
580 *val = AD74413R_ADC_REJECTION_50_60;
581 return 0;
582 case 4800:
583 *val = AD74413R_ADC_REJECTION_NONE;
584 return 0;
585 case 10:
586 *val = AD74413R_ADC_REJECTION_50_60_HART;
587 return 0;
588 case 1200:
589 *val = AD74413R_ADC_REJECTION_HART;
590 return 0;
591 default:
592 dev_err(st->dev, "ADC rate invalid\n");
593 return -EINVAL;
594 }
595 }
596
ad74413r_range_to_voltage_range(struct ad74413r_state * st,unsigned int range,int * val)597 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
598 unsigned int range, int *val)
599 {
600 switch (range) {
601 case AD74413R_ADC_RANGE_10V:
602 *val = 10000;
603 return 0;
604 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
605 case AD74413R_ADC_RANGE_2P5V_INT_POW:
606 *val = 2500;
607 return 0;
608 case AD74413R_ADC_RANGE_5V_BI_DIR:
609 *val = 5000;
610 return 0;
611 default:
612 dev_err(st->dev, "ADC range invalid\n");
613 return -EINVAL;
614 }
615 }
616
ad74413r_range_to_voltage_offset(struct ad74413r_state * st,unsigned int range,int * val)617 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
618 unsigned int range, int *val)
619 {
620 switch (range) {
621 case AD74413R_ADC_RANGE_10V:
622 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
623 *val = 0;
624 return 0;
625 case AD74413R_ADC_RANGE_2P5V_INT_POW:
626 case AD74413R_ADC_RANGE_5V_BI_DIR:
627 *val = -2500;
628 return 0;
629 default:
630 dev_err(st->dev, "ADC range invalid\n");
631 return -EINVAL;
632 }
633 }
634
ad74413r_range_to_voltage_offset_raw(struct ad74413r_state * st,unsigned int range,int * val)635 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
636 unsigned int range, int *val)
637 {
638 switch (range) {
639 case AD74413R_ADC_RANGE_10V:
640 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
641 *val = 0;
642 return 0;
643 case AD74413R_ADC_RANGE_2P5V_INT_POW:
644 *val = -((int)AD74413R_ADC_RESULT_MAX);
645 return 0;
646 case AD74413R_ADC_RANGE_5V_BI_DIR:
647 *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
648 return 0;
649 default:
650 dev_err(st->dev, "ADC range invalid\n");
651 return -EINVAL;
652 }
653 }
654
ad74413r_get_output_voltage_scale(struct ad74413r_state * st,int * val,int * val2)655 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
656 int *val, int *val2)
657 {
658 *val = AD74413R_DAC_VOLTAGE_MAX;
659 *val2 = AD74413R_DAC_CODE_MAX;
660
661 return IIO_VAL_FRACTIONAL;
662 }
663
ad74413r_get_output_current_scale(struct ad74413r_state * st,int * val,int * val2)664 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
665 int *val, int *val2)
666 {
667 *val = st->refin_reg_uv;
668 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
669
670 return IIO_VAL_FRACTIONAL;
671 }
672
ad74413r_get_input_voltage_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)673 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
674 unsigned int channel,
675 int *val, int *val2)
676 {
677 unsigned int range;
678 int ret;
679
680 ret = ad74413r_get_adc_range(st, channel, &range);
681 if (ret)
682 return ret;
683
684 ret = ad74413r_range_to_voltage_range(st, range, val);
685 if (ret)
686 return ret;
687
688 *val2 = AD74413R_ADC_RESULT_MAX;
689
690 return IIO_VAL_FRACTIONAL;
691 }
692
ad74413r_get_input_voltage_offset(struct ad74413r_state * st,unsigned int channel,int * val)693 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
694 unsigned int channel, int *val)
695 {
696 unsigned int range;
697 int ret;
698
699 ret = ad74413r_get_adc_range(st, channel, &range);
700 if (ret)
701 return ret;
702
703 ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
704 if (ret)
705 return ret;
706
707 return IIO_VAL_INT;
708 }
709
ad74413r_get_input_current_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)710 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
711 unsigned int channel, int *val,
712 int *val2)
713 {
714 unsigned int range;
715 int ret;
716
717 ret = ad74413r_get_adc_range(st, channel, &range);
718 if (ret)
719 return ret;
720
721 ret = ad74413r_range_to_voltage_range(st, range, val);
722 if (ret)
723 return ret;
724
725 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
726
727 return IIO_VAL_FRACTIONAL;
728 }
729
ad74413r_get_input_current_offset(struct ad74413r_state * st,unsigned int channel,int * val)730 static int ad74413r_get_input_current_offset(struct ad74413r_state *st,
731 unsigned int channel, int *val)
732 {
733 unsigned int range;
734 int voltage_range;
735 int voltage_offset;
736 int ret;
737
738 ret = ad74413r_get_adc_range(st, channel, &range);
739 if (ret)
740 return ret;
741
742 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
743 if (ret)
744 return ret;
745
746 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
747 if (ret)
748 return ret;
749
750 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range;
751
752 return IIO_VAL_INT;
753 }
754
ad74413r_get_adc_rate(struct ad74413r_state * st,unsigned int channel,int * val)755 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
756 unsigned int channel, int *val)
757 {
758 unsigned int rejection;
759 int ret;
760
761 ret = ad74413r_get_adc_rejection(st, channel, &rejection);
762 if (ret)
763 return ret;
764
765 ret = ad74413r_rejection_to_rate(st, rejection, val);
766 if (ret)
767 return ret;
768
769 return IIO_VAL_INT;
770 }
771
ad74413r_set_adc_rate(struct ad74413r_state * st,unsigned int channel,int val)772 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
773 unsigned int channel, int val)
774 {
775 unsigned int rejection;
776 int ret;
777
778 ret = ad74413r_rate_to_rejection(st, val, &rejection);
779 if (ret)
780 return ret;
781
782 return ad74413r_set_adc_rejection(st, channel, rejection);
783 }
784
ad74413r_trigger_handler(int irq,void * p)785 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
786 {
787 struct iio_poll_func *pf = p;
788 struct iio_dev *indio_dev = pf->indio_dev;
789 struct ad74413r_state *st = iio_priv(indio_dev);
790 u8 *rx_buf = st->adc_samples_buf.rx_buf;
791 unsigned int i;
792 int ret;
793
794 ret = spi_sync(st->spi, &st->adc_samples_msg);
795 if (ret)
796 goto out;
797
798 for (i = 0; i < st->adc_active_channels; i++)
799 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
800
801 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
802 iio_get_time_ns(indio_dev));
803
804 out:
805 iio_trigger_notify_done(indio_dev->trig);
806
807 return IRQ_HANDLED;
808 }
809
ad74413r_adc_data_interrupt(int irq,void * data)810 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
811 {
812 struct iio_dev *indio_dev = data;
813 struct ad74413r_state *st = iio_priv(indio_dev);
814
815 if (iio_buffer_enabled(indio_dev))
816 iio_trigger_poll(st->trig);
817 else
818 complete(&st->adc_data_completion);
819
820 return IRQ_HANDLED;
821 }
822
_ad74413r_get_single_adc_result(struct ad74413r_state * st,unsigned int channel,int * val)823 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
824 unsigned int channel, int *val)
825 {
826 unsigned int uval;
827 int ret;
828
829 guard(mutex)(&st->lock);
830
831 reinit_completion(&st->adc_data_completion);
832
833 ret = ad74413r_set_adc_channel_enable(st, channel, true);
834 if (ret)
835 return ret;
836
837 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
838 if (ret)
839 return ret;
840
841 if (!wait_for_completion_timeout(&st->adc_data_completion,
842 msecs_to_jiffies(1000)))
843 return -ETIMEDOUT;
844
845 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
846 &uval);
847 if (ret)
848 return ret;
849
850 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
851 if (ret)
852 return ret;
853
854 ret = ad74413r_set_adc_channel_enable(st, channel, false);
855 if (ret)
856 return ret;
857
858 *val = uval;
859
860 return IIO_VAL_INT;
861 }
862
ad74413r_get_single_adc_result(struct iio_dev * indio_dev,unsigned int channel,int * val)863 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
864 unsigned int channel, int *val)
865 {
866 struct ad74413r_state *st = iio_priv(indio_dev);
867 int ret;
868
869 if (!iio_device_claim_direct(indio_dev))
870 return -EBUSY;
871
872 ret = _ad74413r_get_single_adc_result(st, channel, val);
873 iio_device_release_direct(indio_dev);
874 return ret;
875 }
876
ad74413r_adc_to_resistance_result(int adc_result,int * val)877 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
878 {
879 if (adc_result == AD74413R_ADC_RESULT_MAX)
880 adc_result = AD74413R_ADC_RESULT_MAX - 1;
881
882 *val = DIV_ROUND_CLOSEST(adc_result * 2100,
883 AD74413R_ADC_RESULT_MAX - adc_result);
884 }
885
ad74413r_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)886 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
887 const unsigned long *active_scan_mask)
888 {
889 struct ad74413r_state *st = iio_priv(indio_dev);
890 struct spi_transfer *xfer = st->adc_samples_xfer;
891 u8 *rx_buf = st->adc_samples_buf.rx_buf;
892 u8 *tx_buf = st->adc_samples_tx_buf;
893 unsigned int channel;
894 int ret = -EINVAL;
895
896 guard(mutex)(&st->lock);
897
898 spi_message_init(&st->adc_samples_msg);
899 st->adc_active_channels = 0;
900
901 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
902 ret = ad74413r_set_adc_channel_enable(st, channel, false);
903 if (ret)
904 return ret;
905 }
906
907 if (*active_scan_mask == 0)
908 return ret;
909
910 /*
911 * The read select register is used to select which register's value
912 * will be sent by the slave on the next SPI frame.
913 *
914 * Create an SPI message that, on each step, writes to the read select
915 * register to select the ADC result of the next enabled channel, and
916 * reads the ADC result of the previous enabled channel.
917 *
918 * Example:
919 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ]
920 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4]
921 */
922
923 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
924 ret = ad74413r_set_adc_channel_enable(st, channel, true);
925 if (ret)
926 return ret;
927
928 st->adc_active_channels++;
929
930 if (xfer == st->adc_samples_xfer)
931 xfer->rx_buf = NULL;
932 else
933 xfer->rx_buf = rx_buf;
934
935 xfer->tx_buf = tx_buf;
936 xfer->len = AD74413R_FRAME_SIZE;
937 xfer->cs_change = 1;
938
939 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
940 AD74413R_REG_ADC_RESULT_X(channel),
941 tx_buf);
942
943 spi_message_add_tail(xfer, &st->adc_samples_msg);
944
945 tx_buf += AD74413R_FRAME_SIZE;
946 if (xfer != st->adc_samples_xfer)
947 rx_buf += AD74413R_FRAME_SIZE;
948 xfer++;
949 }
950
951 xfer->rx_buf = rx_buf;
952 xfer->tx_buf = NULL;
953 xfer->len = AD74413R_FRAME_SIZE;
954 xfer->cs_change = 0;
955
956 spi_message_add_tail(xfer, &st->adc_samples_msg);
957 return 0;
958 }
959
ad74413r_buffer_postenable(struct iio_dev * indio_dev)960 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
961 {
962 struct ad74413r_state *st = iio_priv(indio_dev);
963
964 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
965 }
966
ad74413r_buffer_predisable(struct iio_dev * indio_dev)967 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
968 {
969 struct ad74413r_state *st = iio_priv(indio_dev);
970
971 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
972 }
973
ad74413r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)974 static int ad74413r_read_raw(struct iio_dev *indio_dev,
975 struct iio_chan_spec const *chan,
976 int *val, int *val2, long info)
977 {
978 struct ad74413r_state *st = iio_priv(indio_dev);
979
980 switch (info) {
981 case IIO_CHAN_INFO_SCALE:
982 switch (chan->type) {
983 case IIO_VOLTAGE:
984 if (chan->output)
985 return ad74413r_get_output_voltage_scale(st,
986 val, val2);
987 else
988 return ad74413r_get_input_voltage_scale(st,
989 chan->channel, val, val2);
990 case IIO_CURRENT:
991 if (chan->output)
992 return ad74413r_get_output_current_scale(st,
993 val, val2);
994 else
995 return ad74413r_get_input_current_scale(st,
996 chan->channel, val, val2);
997 default:
998 return -EINVAL;
999 }
1000 case IIO_CHAN_INFO_OFFSET:
1001 switch (chan->type) {
1002 case IIO_VOLTAGE:
1003 return ad74413r_get_input_voltage_offset(st,
1004 chan->channel, val);
1005 case IIO_CURRENT:
1006 return ad74413r_get_input_current_offset(st,
1007 chan->channel, val);
1008 default:
1009 return -EINVAL;
1010 }
1011 case IIO_CHAN_INFO_RAW:
1012 if (chan->output)
1013 return -EINVAL;
1014
1015 return ad74413r_get_single_adc_result(indio_dev, chan->channel,
1016 val);
1017 case IIO_CHAN_INFO_PROCESSED: {
1018 int ret;
1019
1020 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
1021 val);
1022 if (ret < 0)
1023 return ret;
1024
1025 ad74413r_adc_to_resistance_result(*val, val);
1026
1027 return ret;
1028 }
1029 case IIO_CHAN_INFO_SAMP_FREQ:
1030 return ad74413r_get_adc_rate(st, chan->channel, val);
1031 default:
1032 return -EINVAL;
1033 }
1034 }
1035
ad74413r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1036 static int ad74413r_write_raw(struct iio_dev *indio_dev,
1037 struct iio_chan_spec const *chan,
1038 int val, int val2, long info)
1039 {
1040 struct ad74413r_state *st = iio_priv(indio_dev);
1041
1042 switch (info) {
1043 case IIO_CHAN_INFO_RAW:
1044 if (!chan->output)
1045 return -EINVAL;
1046
1047 if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1048 dev_err(st->dev, "Invalid DAC code\n");
1049 return -EINVAL;
1050 }
1051
1052 return ad74413r_set_channel_dac_code(st, chan->channel, val);
1053 case IIO_CHAN_INFO_SAMP_FREQ:
1054 return ad74413r_set_adc_rate(st, chan->channel, val);
1055 default:
1056 return -EINVAL;
1057 }
1058 }
1059
ad74413r_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1060 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1061 struct iio_chan_spec const *chan,
1062 const int **vals, int *type, int *length,
1063 long info)
1064 {
1065 struct ad74413r_state *st = iio_priv(indio_dev);
1066
1067 switch (info) {
1068 case IIO_CHAN_INFO_SAMP_FREQ:
1069 if (st->chip_info->hart_support) {
1070 *vals = ad74413r_adc_sampling_rates_hart;
1071 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1072 } else {
1073 *vals = ad74413r_adc_sampling_rates;
1074 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1075 }
1076 *type = IIO_VAL_INT;
1077 return IIO_AVAIL_LIST;
1078 default:
1079 return -EINVAL;
1080 }
1081 }
1082
1083 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1084 .postenable = &ad74413r_buffer_postenable,
1085 .predisable = &ad74413r_buffer_predisable,
1086 };
1087
1088 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1089 .validate_device = iio_trigger_validate_own_device,
1090 };
1091
1092 static const struct iio_info ad74413r_info = {
1093 .read_raw = &ad74413r_read_raw,
1094 .write_raw = &ad74413r_write_raw,
1095 .read_avail = &ad74413r_read_avail,
1096 .update_scan_mode = &ad74413r_update_scan_mode,
1097 };
1098
1099 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \
1100 { \
1101 .type = (_type), \
1102 .indexed = 1, \
1103 .output = 1, \
1104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1105 | (extra_mask_separate), \
1106 }
1107
1108 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \
1109 { \
1110 .type = (_type), \
1111 .indexed = 1, \
1112 .output = 0, \
1113 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1114 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
1115 | (extra_mask_separate), \
1116 .info_mask_separate_available = \
1117 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1118 .scan_type = { \
1119 .sign = 'u', \
1120 .realbits = 16, \
1121 .storagebits = 32, \
1122 .shift = 8, \
1123 .endianness = IIO_BE, \
1124 }, \
1125 }
1126
1127 #define AD74413R_ADC_VOLTAGE_CHANNEL \
1128 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \
1129 | BIT(IIO_CHAN_INFO_OFFSET))
1130
1131 #define AD74413R_ADC_CURRENT_CHANNEL \
1132 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \
1133 | BIT(IIO_CHAN_INFO_OFFSET))
1134
1135 static const struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1136 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1137 AD74413R_ADC_CURRENT_CHANNEL,
1138 };
1139
1140 static const struct iio_chan_spec ad74413r_current_output_channels[] = {
1141 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1142 AD74413R_ADC_VOLTAGE_CHANNEL,
1143 };
1144
1145 static const struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1146 AD74413R_ADC_VOLTAGE_CHANNEL,
1147 };
1148
1149 static const struct iio_chan_spec ad74413r_current_input_channels[] = {
1150 AD74413R_ADC_CURRENT_CHANNEL,
1151 };
1152
1153 static const struct iio_chan_spec ad74413r_current_input_loop_channels[] = {
1154 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1155 AD74413R_ADC_CURRENT_CHANNEL,
1156 };
1157
1158 static const struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1159 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1160 };
1161
1162 static const struct iio_chan_spec ad74413r_digital_input_channels[] = {
1163 AD74413R_ADC_VOLTAGE_CHANNEL,
1164 };
1165
1166 #define _AD74413R_CHANNELS(_channels) \
1167 { \
1168 .channels = _channels, \
1169 .num_channels = ARRAY_SIZE(_channels), \
1170 }
1171
1172 #define AD74413R_CHANNELS(name) \
1173 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1174
1175 static const struct ad74413r_channels ad74413r_channels_map[] = {
1176 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1177 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1178 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1179 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1180 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1181 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop),
1182 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1183 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1184 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1185 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1186 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1187 };
1188
ad74413r_parse_channel_config(struct iio_dev * indio_dev,struct fwnode_handle * channel_node)1189 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1190 struct fwnode_handle *channel_node)
1191 {
1192 struct ad74413r_state *st = iio_priv(indio_dev);
1193 struct ad74413r_channel_config *config;
1194 u32 index;
1195 int ret;
1196
1197 ret = fwnode_property_read_u32(channel_node, "reg", &index);
1198 if (ret) {
1199 dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1200 return ret;
1201 }
1202
1203 if (index >= AD74413R_CHANNEL_MAX) {
1204 dev_err(st->dev, "Channel index %u is too large\n", index);
1205 return -EINVAL;
1206 }
1207
1208 config = &st->channel_configs[index];
1209 if (config->initialized) {
1210 dev_err(st->dev, "Channel %u already initialized\n", index);
1211 return -EINVAL;
1212 }
1213
1214 config->func = CH_FUNC_HIGH_IMPEDANCE;
1215 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1216
1217 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1218 dev_err(st->dev, "Invalid channel function %u\n", config->func);
1219 return -EINVAL;
1220 }
1221
1222 if (!st->chip_info->hart_support &&
1223 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1224 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1225 dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1226 return -EINVAL;
1227 }
1228
1229 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1230 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1231 st->num_comparator_gpios++;
1232
1233 config->gpo_comparator = fwnode_property_read_bool(channel_node,
1234 "adi,gpo-comparator");
1235
1236 fwnode_property_read_u32(channel_node, "drive-strength-microamp",
1237 &config->drive_strength);
1238
1239 if (!config->gpo_comparator)
1240 st->num_gpo_gpios++;
1241
1242 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1243
1244 config->initialized = true;
1245
1246 return 0;
1247 }
1248
ad74413r_parse_channel_configs(struct iio_dev * indio_dev)1249 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1250 {
1251 struct ad74413r_state *st = iio_priv(indio_dev);
1252 int ret;
1253
1254 device_for_each_child_node_scoped(st->dev, channel_node) {
1255 ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1256 if (ret)
1257 return ret;
1258 }
1259
1260 return 0;
1261 }
1262
ad74413r_setup_channels(struct iio_dev * indio_dev)1263 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1264 {
1265 struct ad74413r_state *st = iio_priv(indio_dev);
1266 struct ad74413r_channel_config *config;
1267 const struct iio_chan_spec *chans;
1268 struct iio_chan_spec *channels;
1269 unsigned int i, num_chans, chan_i;
1270 int ret;
1271
1272 channels = devm_kcalloc(st->dev, sizeof(*channels),
1273 indio_dev->num_channels, GFP_KERNEL);
1274 if (!channels)
1275 return -ENOMEM;
1276
1277 indio_dev->channels = channels;
1278
1279 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1280 config = &st->channel_configs[i];
1281 chans = ad74413r_channels_map[config->func].channels;
1282 num_chans = ad74413r_channels_map[config->func].num_channels;
1283
1284 memcpy(channels, chans, num_chans * sizeof(*chans));
1285
1286 for (chan_i = 0; chan_i < num_chans; chan_i++) {
1287 struct iio_chan_spec *chan = &channels[chan_i];
1288
1289 chan->channel = i;
1290 if (chan->output)
1291 chan->scan_index = -1;
1292 else
1293 chan->scan_index = i;
1294 }
1295
1296 ret = ad74413r_set_channel_function(st, i, config->func);
1297 if (ret)
1298 return ret;
1299
1300 channels += num_chans;
1301 }
1302
1303 return 0;
1304 }
1305
ad74413r_setup_gpios(struct ad74413r_state * st)1306 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1307 {
1308 struct ad74413r_channel_config *config;
1309 unsigned int comp_gpio_i = 0;
1310 unsigned int gpo_gpio_i = 0;
1311 unsigned int i;
1312 u8 gpo_config;
1313 u32 strength;
1314 int ret;
1315
1316 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1317 config = &st->channel_configs[i];
1318
1319 if (config->gpo_comparator) {
1320 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1321 } else {
1322 gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1323 st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1324 }
1325
1326 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1327 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1328 st->comp_gpio_offsets[comp_gpio_i++] = i;
1329
1330 strength = config->drive_strength;
1331 ret = ad74413r_set_comp_drive_strength(st, i, strength);
1332 if (ret)
1333 return ret;
1334 }
1335
1336 ret = ad74413r_set_gpo_config(st, i, gpo_config);
1337 if (ret)
1338 return ret;
1339 }
1340
1341 return 0;
1342 }
1343
ad74413r_probe(struct spi_device * spi)1344 static int ad74413r_probe(struct spi_device *spi)
1345 {
1346 struct ad74413r_state *st;
1347 struct iio_dev *indio_dev;
1348 int ret;
1349
1350 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1351 if (!indio_dev)
1352 return -ENOMEM;
1353
1354 st = iio_priv(indio_dev);
1355
1356 st->spi = spi;
1357 st->dev = &spi->dev;
1358 st->chip_info = spi_get_device_match_data(spi);
1359 if (!st->chip_info)
1360 return -EINVAL;
1361
1362 ret = devm_mutex_init(st->dev, &st->lock);
1363 if (ret)
1364 return ret;
1365
1366 init_completion(&st->adc_data_completion);
1367
1368 st->regmap = devm_regmap_init(st->dev, NULL, st,
1369 &ad74413r_regmap_config);
1370 if (IS_ERR(st->regmap))
1371 return PTR_ERR(st->regmap);
1372
1373 ret = devm_regulator_get_enable_read_voltage(st->dev, "refin");
1374 if (ret < 0)
1375 return dev_err_probe(st->dev, ret,
1376 "Failed to get refin regulator voltage\n");
1377 st->refin_reg_uv = ret;
1378
1379 st->sense_resistor_ohms = 100000000;
1380 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1381 &st->sense_resistor_ohms);
1382 st->sense_resistor_ohms /= 1000000;
1383
1384 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1385 st->chip_info->name, iio_device_id(indio_dev));
1386 if (!st->trig)
1387 return -ENOMEM;
1388
1389 st->trig->ops = &ad74413r_trigger_ops;
1390 iio_trigger_set_drvdata(st->trig, st);
1391
1392 ret = devm_iio_trigger_register(st->dev, st->trig);
1393 if (ret)
1394 return ret;
1395
1396 indio_dev->name = st->chip_info->name;
1397 indio_dev->modes = INDIO_DIRECT_MODE;
1398 indio_dev->info = &ad74413r_info;
1399 indio_dev->trig = iio_trigger_get(st->trig);
1400
1401 ret = ad74413r_reset(st);
1402 if (ret)
1403 return ret;
1404
1405 ret = ad74413r_parse_channel_configs(indio_dev);
1406 if (ret)
1407 return ret;
1408
1409 ret = ad74413r_setup_channels(indio_dev);
1410 if (ret)
1411 return ret;
1412
1413 ret = ad74413r_setup_gpios(st);
1414 if (ret)
1415 return ret;
1416
1417 if (st->num_gpo_gpios) {
1418 st->gpo_gpiochip.owner = THIS_MODULE;
1419 st->gpo_gpiochip.label = st->chip_info->name;
1420 st->gpo_gpiochip.base = -1;
1421 st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1422 st->gpo_gpiochip.parent = st->dev;
1423 st->gpo_gpiochip.can_sleep = true;
1424 st->gpo_gpiochip.set = ad74413r_gpio_set;
1425 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1426 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1427 st->gpo_gpiochip.get_direction =
1428 ad74413r_gpio_get_gpo_direction;
1429
1430 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 if (st->num_comparator_gpios) {
1436 st->comp_gpiochip.owner = THIS_MODULE;
1437 st->comp_gpiochip.label = st->chip_info->name;
1438 st->comp_gpiochip.base = -1;
1439 st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1440 st->comp_gpiochip.parent = st->dev;
1441 st->comp_gpiochip.can_sleep = true;
1442 st->comp_gpiochip.get = ad74413r_gpio_get;
1443 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1444 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1445 st->comp_gpiochip.get_direction =
1446 ad74413r_gpio_get_comp_direction;
1447
1448 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1449 if (ret)
1450 return ret;
1451 }
1452
1453 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1454 if (ret)
1455 return ret;
1456
1457 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1458 0, st->chip_info->name, indio_dev);
1459 if (ret)
1460 return ret;
1461
1462 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1463 &iio_pollfunc_store_time,
1464 &ad74413r_trigger_handler,
1465 &ad74413r_buffer_ops);
1466 if (ret)
1467 return ret;
1468
1469 return devm_iio_device_register(st->dev, indio_dev);
1470 }
1471
ad74413r_unregister_driver(struct spi_driver * spi)1472 static int ad74413r_unregister_driver(struct spi_driver *spi)
1473 {
1474 spi_unregister_driver(spi);
1475
1476 return 0;
1477 }
1478
ad74413r_register_driver(struct spi_driver * spi)1479 static int __init ad74413r_register_driver(struct spi_driver *spi)
1480 {
1481 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1482
1483 return spi_register_driver(spi);
1484 }
1485
1486 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1487 .hart_support = false,
1488 .name = "ad74412r",
1489 };
1490
1491 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1492 .hart_support = true,
1493 .name = "ad74413r",
1494 };
1495
1496 static const struct of_device_id ad74413r_dt_id[] = {
1497 {
1498 .compatible = "adi,ad74412r",
1499 .data = &ad74412r_chip_info_data,
1500 },
1501 {
1502 .compatible = "adi,ad74413r",
1503 .data = &ad74413r_chip_info_data,
1504 },
1505 { }
1506 };
1507 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1508
1509 static const struct spi_device_id ad74413r_spi_id[] = {
1510 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data },
1511 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data },
1512 { }
1513 };
1514 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id);
1515
1516 static struct spi_driver ad74413r_driver = {
1517 .driver = {
1518 .name = "ad74413r",
1519 .of_match_table = ad74413r_dt_id,
1520 },
1521 .probe = ad74413r_probe,
1522 .id_table = ad74413r_spi_id,
1523 };
1524
1525 module_driver(ad74413r_driver,
1526 ad74413r_register_driver,
1527 ad74413r_unregister_driver);
1528
1529 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1530 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1531 MODULE_LICENSE("GPL v2");
1532