1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Balsam CHIHI <bchihi@baylibre.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/debugfs.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21
22 #include "../thermal_hwmon.h"
23
24 #define LVTS_MONCTL0(__base) (__base + 0x0000)
25 #define LVTS_MONCTL1(__base) (__base + 0x0004)
26 #define LVTS_MONCTL2(__base) (__base + 0x0008)
27 #define LVTS_MONINT(__base) (__base + 0x000C)
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010)
29 #define LVTS_MONIDET0(__base) (__base + 0x0014)
30 #define LVTS_MONIDET1(__base) (__base + 0x0018)
31 #define LVTS_MONIDET2(__base) (__base + 0x001C)
32 #define LVTS_MONIDET3(__base) (__base + 0x0020)
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024)
34 #define LVTS_HTHRE(__base) (__base + 0x0028)
35 #define LVTS_OFFSETH(__base) (__base + 0x0030)
36 #define LVTS_OFFSETL(__base) (__base + 0x0034)
37 #define LVTS_MSRCTL0(__base) (__base + 0x0038)
38 #define LVTS_MSRCTL1(__base) (__base + 0x003C)
39 #define LVTS_TSSEL(__base) (__base + 0x0040)
40 #define LVTS_CALSCALE(__base) (__base + 0x0048)
41 #define LVTS_ID(__base) (__base + 0x004C)
42 #define LVTS_CONFIG(__base) (__base + 0x0050)
43 #define LVTS_EDATA00(__base) (__base + 0x0054)
44 #define LVTS_EDATA01(__base) (__base + 0x0058)
45 #define LVTS_EDATA02(__base) (__base + 0x005C)
46 #define LVTS_EDATA03(__base) (__base + 0x0060)
47 #define LVTS_MSROFT(__base) (__base + 0x006C)
48 #define LVTS_ATP0(__base) (__base + 0x0070)
49 #define LVTS_ATP1(__base) (__base + 0x0074)
50 #define LVTS_ATP2(__base) (__base + 0x0078)
51 #define LVTS_ATP3(__base) (__base + 0x007C)
52 #define LVTS_MSR0(__base) (__base + 0x0090)
53 #define LVTS_MSR1(__base) (__base + 0x0094)
54 #define LVTS_MSR2(__base) (__base + 0x0098)
55 #define LVTS_MSR3(__base) (__base + 0x009C)
56 #define LVTS_IMMD0(__base) (__base + 0x00A0)
57 #define LVTS_IMMD1(__base) (__base + 0x00A4)
58 #define LVTS_IMMD2(__base) (__base + 0x00A8)
59 #define LVTS_IMMD3(__base) (__base + 0x00AC)
60 #define LVTS_PROTCTL(__base) (__base + 0x00C0)
61 #define LVTS_PROTTA(__base) (__base + 0x00C4)
62 #define LVTS_PROTTB(__base) (__base + 0x00C8)
63 #define LVTS_PROTTC(__base) (__base + 0x00CC)
64 #define LVTS_CLKEN(__base) (__base + 0x00E4)
65
66 #define LVTS_PERIOD_UNIT 0
67 #define LVTS_GROUP_INTERVAL 0
68 #define LVTS_FILTER_INTERVAL 0
69 #define LVTS_SENSOR_INTERVAL 0
70 #define LVTS_HW_FILTER 0x0
71 #define LVTS_TSSEL_CONF 0x13121110
72 #define LVTS_CALSCALE_CONF 0x300
73
74 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3)
75 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8)
76 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2 BIT(13)
77 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3 BIT(25)
78 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0 BIT(2)
79 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1 BIT(7)
80 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2 BIT(12)
81 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3 BIT(24)
82
83 #define LVTS_INT_SENSOR0 0x0009001F
84 #define LVTS_INT_SENSOR1 0x001203E0
85 #define LVTS_INT_SENSOR2 0x00247C00
86 #define LVTS_INT_SENSOR3 0x1FC00000
87
88 #define LVTS_SENSOR_MAX 4
89 #define LVTS_GOLDEN_TEMP_MAX 62
90 #define LVTS_GOLDEN_TEMP_DEFAULT 50
91 #define LVTS_COEFF_A_MT8195 -250460
92 #define LVTS_COEFF_B_MT8195 250460
93 #define LVTS_COEFF_A_MT7987 -204650
94 #define LVTS_COEFF_B_MT7987 204650
95 #define LVTS_COEFF_A_MT7988 -204650
96 #define LVTS_COEFF_B_MT7988 204650
97 #define LVTS_COEFF_A_MT8196 391460
98 #define LVTS_COEFF_B_MT8196 -391460
99
100 #define LVTS_MSR_OFFSET_MT8196 -984
101
102 #define LVTS_MSR_READ_TIMEOUT_US 400
103 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
104
105 #define LVTS_MINIMUM_THRESHOLD 20000
106
107 #define LVTS_MAX_CAL_OFFSETS 3
108 #define LVTS_NUM_CAL_OFFSETS_MT7988 3
109 #define LVTS_NUM_CAL_OFFSETS_MT8196 2
110
111 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
112 static int golden_temp_offset;
113
114 enum lvts_msr_mode {
115 LVTS_MSR_IMMEDIATE_MODE,
116 LVTS_MSR_FILTERED_MODE,
117 LVTS_MSR_ATP_MODE,
118 };
119
120 struct lvts_sensor_data {
121 int dt_id;
122 u8 cal_offsets[LVTS_MAX_CAL_OFFSETS];
123 };
124
125 struct lvts_ctrl_data {
126 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
127 u8 valid_sensor_mask;
128 int offset;
129 enum lvts_msr_mode mode;
130 };
131
132 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \
133 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \
134 ((s1) ? BIT(1) : 0) | \
135 ((s2) ? BIT(2) : 0) | \
136 ((s3) ? BIT(3) : 0))
137
138 #define lvts_for_each_valid_sensor(i, lvts_ctrl) \
139 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \
140 if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \
141 continue; \
142 else
143
144 struct lvts_platform_ops {
145 int (*lvts_raw_to_temp)(u32 raw_temp, int temp_factor);
146 u32 (*lvts_temp_to_raw)(int temperature, int temp_factor);
147 };
148
149 struct lvts_data {
150 const struct lvts_ctrl_data *lvts_ctrl;
151 const struct lvts_platform_ops *ops;
152 const u32 *conn_cmd;
153 const u32 *init_cmd;
154 int num_cal_offsets;
155 int num_lvts_ctrl;
156 int num_conn_cmd;
157 int num_init_cmd;
158 int temp_factor;
159 int temp_offset;
160 int gt_calib_bit_offset;
161 unsigned int def_calibration;
162 u16 msr_offset;
163 };
164
165 struct lvts_sensor {
166 struct thermal_zone_device *tz;
167 void __iomem *msr;
168 void __iomem *base;
169 int id;
170 int dt_id;
171 int low_thresh;
172 int high_thresh;
173 };
174
175 struct lvts_ctrl {
176 struct lvts_sensor sensors[LVTS_SENSOR_MAX];
177 const struct lvts_data *lvts_data;
178 u32 calibration[LVTS_SENSOR_MAX];
179 u8 valid_sensor_mask;
180 int mode;
181 void __iomem *base;
182 int low_thresh;
183 int high_thresh;
184 };
185
186 struct lvts_domain {
187 struct lvts_ctrl *lvts_ctrl;
188 struct reset_control *reset;
189 struct clk *clk;
190 int num_lvts_ctrl;
191 void __iomem *base;
192 size_t calib_len;
193 u8 *calib;
194 #ifdef CONFIG_DEBUG_FS
195 struct dentry *dom_dentry;
196 #endif
197 };
198
199 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
200
201 #define LVTS_DEBUG_FS_REGS(__reg) \
202 { \
203 .name = __stringify(__reg), \
204 .offset = __reg(0), \
205 }
206
207 static const struct debugfs_reg32 lvts_regs[] = {
208 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
209 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
210 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
211 LVTS_DEBUG_FS_REGS(LVTS_MONINT),
212 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
213 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
214 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
215 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
216 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
217 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
218 LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
219 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
220 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
221 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
222 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
223 LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
224 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
225 LVTS_DEBUG_FS_REGS(LVTS_ID),
226 LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
227 LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
228 LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
229 LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
230 LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
231 LVTS_DEBUG_FS_REGS(LVTS_MSROFT),
232 LVTS_DEBUG_FS_REGS(LVTS_ATP0),
233 LVTS_DEBUG_FS_REGS(LVTS_ATP1),
234 LVTS_DEBUG_FS_REGS(LVTS_ATP2),
235 LVTS_DEBUG_FS_REGS(LVTS_ATP3),
236 LVTS_DEBUG_FS_REGS(LVTS_MSR0),
237 LVTS_DEBUG_FS_REGS(LVTS_MSR1),
238 LVTS_DEBUG_FS_REGS(LVTS_MSR2),
239 LVTS_DEBUG_FS_REGS(LVTS_MSR3),
240 LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
241 LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
242 LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
243 LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
244 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
245 LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
246 LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
247 LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
248 LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
249 };
250
lvts_debugfs_exit(void * data)251 static void lvts_debugfs_exit(void *data)
252 {
253 struct lvts_domain *lvts_td = data;
254
255 debugfs_remove_recursive(lvts_td->dom_dentry);
256 }
257
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)258 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
259 {
260 struct debugfs_regset32 *regset;
261 struct lvts_ctrl *lvts_ctrl;
262 struct dentry *dentry;
263 char name[64];
264 int i;
265
266 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
267 if (IS_ERR(lvts_td->dom_dentry))
268 return 0;
269
270 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
271
272 lvts_ctrl = &lvts_td->lvts_ctrl[i];
273
274 sprintf(name, "controller%d", i);
275 dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
276 if (IS_ERR(dentry))
277 continue;
278
279 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
280 if (!regset)
281 continue;
282
283 regset->base = lvts_ctrl->base;
284 regset->regs = lvts_regs;
285 regset->nregs = ARRAY_SIZE(lvts_regs);
286
287 debugfs_create_regset32("registers", 0400, dentry, regset);
288 }
289
290 return devm_add_action_or_reset(dev, lvts_debugfs_exit, lvts_td);
291 }
292
293 #else
294
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)295 static inline int lvts_debugfs_init(struct device *dev,
296 struct lvts_domain *lvts_td)
297 {
298 return 0;
299 }
300
301 #endif
302
lvts_raw_to_temp(u32 raw_temp,const struct lvts_data * lvts_data)303 static int lvts_raw_to_temp(u32 raw_temp, const struct lvts_data *lvts_data)
304 {
305 return lvts_data->ops->lvts_raw_to_temp(raw_temp & 0xFFFF, lvts_data->temp_factor);
306 }
307
lvts_temp_to_raw(int temperature,const struct lvts_data * lvts_data)308 static u32 lvts_temp_to_raw(int temperature, const struct lvts_data *lvts_data)
309 {
310 return lvts_data->ops->lvts_temp_to_raw(temperature, lvts_data->temp_factor);
311 }
312
lvts_raw_to_temp_mt7988(u32 raw_temp,int temp_factor)313 static int lvts_raw_to_temp_mt7988(u32 raw_temp, int temp_factor)
314 {
315 int temperature;
316
317 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
318 temperature += golden_temp_offset;
319
320 return temperature;
321 }
322
lvts_temp_to_raw_mt7988(int temperature,int temp_factor)323 static u32 lvts_temp_to_raw_mt7988(int temperature, int temp_factor)
324 {
325 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
326
327 raw_temp = div_s64(raw_temp, -temp_factor);
328
329 return raw_temp;
330 }
331
lvts_temp_to_raw_mt8196(int temperature,int temp_factor)332 static u32 lvts_temp_to_raw_mt8196(int temperature, int temp_factor)
333 {
334 u32 raw_temp;
335
336 raw_temp = temperature - golden_temp_offset;
337
338 return div_s64((s64)temp_factor << 14, raw_temp);
339 }
340
lvts_get_temp(struct thermal_zone_device * tz,int * temp)341 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
342 {
343 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
344 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
345 sensors[lvts_sensor->id]);
346 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
347 void __iomem *msr = lvts_sensor->msr;
348 u32 value;
349 int rc;
350
351 /*
352 * Measurement registers:
353 *
354 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
355 *
356 * Bits:
357 *
358 * 32-17: Unused
359 * 16 : Valid temperature
360 * 15-0 : Raw temperature
361 */
362 rc = readl_poll_timeout(msr, value, value & BIT(16),
363 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
364
365 /*
366 * As the thermal zone temperature will read before the
367 * hardware sensor is fully initialized, we have to check the
368 * validity of the temperature returned when reading the
369 * measurement register. The thermal controller will set the
370 * valid bit temperature only when it is totally initialized.
371 *
372 * Otherwise, we may end up with garbage values out of the
373 * functionning temperature and directly jump to a system
374 * shutdown.
375 */
376 if (rc)
377 return -EAGAIN;
378
379 *temp = lvts_raw_to_temp(value, lvts_data);
380
381 return 0;
382 }
383
lvts_update_irq_mask(struct lvts_ctrl * lvts_ctrl)384 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
385 {
386 static const u32 high_offset_inten_masks[] = {
387 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0,
388 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1,
389 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2,
390 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3,
391 };
392 static const u32 low_offset_inten_masks[] = {
393 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0,
394 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1,
395 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2,
396 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3,
397 };
398 u32 value = 0;
399 int i;
400
401 value = readl(LVTS_MONINT(lvts_ctrl->base));
402
403 lvts_for_each_valid_sensor(i, lvts_ctrl) {
404 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
405 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) {
406 /*
407 * The minimum threshold needs to be configured in the
408 * OFFSETL register to get working interrupts, but we
409 * don't actually want to generate interrupts when
410 * crossing it.
411 */
412 if (lvts_ctrl->low_thresh == -INT_MAX) {
413 value &= ~low_offset_inten_masks[i];
414 value |= high_offset_inten_masks[i];
415 } else {
416 value |= low_offset_inten_masks[i] | high_offset_inten_masks[i];
417 }
418 } else {
419 value &= ~(low_offset_inten_masks[i] | high_offset_inten_masks[i]);
420 }
421 }
422
423 writel(value, LVTS_MONINT(lvts_ctrl->base));
424 }
425
lvts_should_update_thresh(struct lvts_ctrl * lvts_ctrl,int high)426 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
427 {
428 int i;
429
430 if (high > lvts_ctrl->high_thresh)
431 return true;
432
433 lvts_for_each_valid_sensor(i, lvts_ctrl)
434 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
435 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
436 return false;
437
438 return true;
439 }
440
lvts_set_trips(struct thermal_zone_device * tz,int low,int high)441 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
442 {
443 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
444 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
445 sensors[lvts_sensor->id]);
446 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
447 void __iomem *base = lvts_sensor->base;
448 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
449 lvts_data);
450 u32 raw_high = lvts_temp_to_raw(high, lvts_data);
451 bool should_update_thresh;
452
453 lvts_sensor->low_thresh = low;
454 lvts_sensor->high_thresh = high;
455
456 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
457 if (should_update_thresh) {
458 lvts_ctrl->high_thresh = high;
459 lvts_ctrl->low_thresh = low;
460 }
461 lvts_update_irq_mask(lvts_ctrl);
462
463 if (!should_update_thresh)
464 return 0;
465
466 /*
467 * Low offset temperature threshold
468 *
469 * LVTS_OFFSETL
470 *
471 * Bits:
472 *
473 * 14-0 : Raw temperature for threshold
474 */
475 pr_debug("%s: Setting low limit temperature interrupt: %d\n",
476 thermal_zone_device_type(tz), low);
477 writel(raw_low, LVTS_OFFSETL(base));
478
479 /*
480 * High offset temperature threshold
481 *
482 * LVTS_OFFSETH
483 *
484 * Bits:
485 *
486 * 14-0 : Raw temperature for threshold
487 */
488 pr_debug("%s: Setting high limit temperature interrupt: %d\n",
489 thermal_zone_device_type(tz), high);
490 writel(raw_high, LVTS_OFFSETH(base));
491
492 return 0;
493 }
494
lvts_ctrl_irq_handler(struct lvts_ctrl * lvts_ctrl)495 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
496 {
497 irqreturn_t iret = IRQ_NONE;
498 u32 value;
499 static const u32 masks[] = {
500 LVTS_INT_SENSOR0,
501 LVTS_INT_SENSOR1,
502 LVTS_INT_SENSOR2,
503 LVTS_INT_SENSOR3
504 };
505 int i;
506
507 /*
508 * Interrupt monitoring status
509 *
510 * LVTS_MONINTST
511 *
512 * Bits:
513 *
514 * 31 : Interrupt for stage 3
515 * 30 : Interrupt for stage 2
516 * 29 : Interrupt for state 1
517 * 28 : Interrupt using filter on sensor 3
518 *
519 * 27 : Interrupt using immediate on sensor 3
520 * 26 : Interrupt normal to hot on sensor 3
521 * 25 : Interrupt high offset on sensor 3
522 * 24 : Interrupt low offset on sensor 3
523 *
524 * 23 : Interrupt hot threshold on sensor 3
525 * 22 : Interrupt cold threshold on sensor 3
526 * 21 : Interrupt using filter on sensor 2
527 * 20 : Interrupt using filter on sensor 1
528 *
529 * 19 : Interrupt using filter on sensor 0
530 * 18 : Interrupt using immediate on sensor 2
531 * 17 : Interrupt using immediate on sensor 1
532 * 16 : Interrupt using immediate on sensor 0
533 *
534 * 15 : Interrupt device access timeout interrupt
535 * 14 : Interrupt normal to hot on sensor 2
536 * 13 : Interrupt high offset interrupt on sensor 2
537 * 12 : Interrupt low offset interrupt on sensor 2
538 *
539 * 11 : Interrupt hot threshold on sensor 2
540 * 10 : Interrupt cold threshold on sensor 2
541 * 9 : Interrupt normal to hot on sensor 1
542 * 8 : Interrupt high offset interrupt on sensor 1
543 *
544 * 7 : Interrupt low offset interrupt on sensor 1
545 * 6 : Interrupt hot threshold on sensor 1
546 * 5 : Interrupt cold threshold on sensor 1
547 * 4 : Interrupt normal to hot on sensor 0
548 *
549 * 3 : Interrupt high offset interrupt on sensor 0
550 * 2 : Interrupt low offset interrupt on sensor 0
551 * 1 : Interrupt hot threshold on sensor 0
552 * 0 : Interrupt cold threshold on sensor 0
553 *
554 * We are interested in the sensor(s) responsible of the
555 * interrupt event. We update the thermal framework with the
556 * thermal zone associated with the sensor. The framework will
557 * take care of the rest whatever the kind of interrupt, we
558 * are only interested in which sensor raised the interrupt.
559 *
560 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
561 * => 0x1FC00000
562 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
563 * => 0x00247C00
564 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
565 * => 0X001203E0
566 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
567 * => 0x0009001F
568 */
569 value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
570
571 /*
572 * Let's figure out which sensors raised the interrupt
573 *
574 * NOTE: the masks array must be ordered with the index
575 * corresponding to the sensor id eg. index=0, mask for
576 * sensor0.
577 */
578 for (i = 0; i < ARRAY_SIZE(masks); i++) {
579
580 if (!(value & masks[i]))
581 continue;
582
583 thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
584 THERMAL_TRIP_VIOLATED);
585 iret = IRQ_HANDLED;
586 }
587
588 /*
589 * Write back to clear the interrupt status (W1C)
590 */
591 writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
592
593 return iret;
594 }
595
596 /*
597 * Temperature interrupt handler. Even if the driver supports more
598 * interrupt modes, we use the interrupt when the temperature crosses
599 * the hot threshold the way up and the way down (modulo the
600 * hysteresis).
601 *
602 * Each thermal domain has a couple of interrupts, one for hardware
603 * reset and another one for all the thermal events happening on the
604 * different sensors.
605 *
606 * The interrupt is configured for thermal events when crossing the
607 * hot temperature limit. At each interrupt, we check in every
608 * controller if there is an interrupt pending.
609 */
lvts_irq_handler(int irq,void * data)610 static irqreturn_t lvts_irq_handler(int irq, void *data)
611 {
612 struct lvts_domain *lvts_td = data;
613 irqreturn_t aux, iret = IRQ_NONE;
614 int i;
615
616 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
617
618 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
619 if (aux != IRQ_HANDLED)
620 continue;
621
622 iret = IRQ_HANDLED;
623 }
624
625 return iret;
626 }
627
628 static const struct thermal_zone_device_ops lvts_ops = {
629 .get_temp = lvts_get_temp,
630 .set_trips = lvts_set_trips,
631 };
632
lvts_sensor_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data)633 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
634 const struct lvts_ctrl_data *lvts_ctrl_data)
635 {
636 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
637
638 void __iomem *msr_regs[] = {
639 LVTS_MSR0(lvts_ctrl->base),
640 LVTS_MSR1(lvts_ctrl->base),
641 LVTS_MSR2(lvts_ctrl->base),
642 LVTS_MSR3(lvts_ctrl->base)
643 };
644
645 void __iomem *imm_regs[] = {
646 LVTS_IMMD0(lvts_ctrl->base),
647 LVTS_IMMD1(lvts_ctrl->base),
648 LVTS_IMMD2(lvts_ctrl->base),
649 LVTS_IMMD3(lvts_ctrl->base)
650 };
651
652 void __iomem *atp_regs[] = {
653 LVTS_ATP0(lvts_ctrl->base),
654 LVTS_ATP1(lvts_ctrl->base),
655 LVTS_ATP2(lvts_ctrl->base),
656 LVTS_ATP3(lvts_ctrl->base)
657 };
658
659 int i;
660
661 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
662
663 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
664
665 /*
666 * At this point, we don't know which id matches which
667 * sensor. Let's set arbitrally the id from the index.
668 */
669 lvts_sensor[i].id = i;
670
671 /*
672 * The thermal zone registration will set the trip
673 * point interrupt in the thermal controller
674 * register. But this one will be reset in the
675 * initialization after. So we need to post pone the
676 * thermal zone creation after the controller is
677 * setup. For this reason, we store the device tree
678 * node id from the data in the sensor structure
679 */
680 lvts_sensor[i].dt_id = dt_id;
681
682 /*
683 * We assign the base address of the thermal
684 * controller as a back pointer. So it will be
685 * accessible from the different thermal framework ops
686 * as we pass the lvts_sensor pointer as thermal zone
687 * private data.
688 */
689 lvts_sensor[i].base = lvts_ctrl->base;
690
691 /*
692 * Each sensor has its own register address to read from.
693 */
694 switch (lvts_ctrl_data->mode) {
695 case LVTS_MSR_IMMEDIATE_MODE:
696 lvts_sensor[i].msr = imm_regs[i];
697 break;
698 case LVTS_MSR_FILTERED_MODE:
699 lvts_sensor[i].msr = msr_regs[i];
700 break;
701 case LVTS_MSR_ATP_MODE:
702 lvts_sensor[i].msr = atp_regs[i];
703 break;
704 default:
705 lvts_sensor[i].msr = imm_regs[i];
706 break;
707 }
708
709 lvts_sensor[i].low_thresh = INT_MIN;
710 lvts_sensor[i].high_thresh = INT_MIN;
711 }
712
713 lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask;
714
715 return 0;
716 }
717
lvts_decode_sensor_calibration(const struct lvts_sensor_data * sensor,const u8 * efuse_calibration,u32 calib_len,u8 num_offsets,u32 * calib)718 static int lvts_decode_sensor_calibration(const struct lvts_sensor_data *sensor,
719 const u8 *efuse_calibration, u32 calib_len,
720 u8 num_offsets, u32 *calib)
721 {
722 int i;
723 u32 calib_val = 0;
724
725 for (i = 0; i < num_offsets; i++) {
726 u8 offset = sensor->cal_offsets[i];
727
728 if (offset >= calib_len)
729 return -EINVAL;
730 // Pack each calibration byte into the correct position
731 calib_val |= efuse_calibration[offset] << (8 * i);
732 }
733
734 *calib = calib_val;
735 return 0;
736 }
737
738 /*
739 * The efuse blob values follows the sensor enumeration per thermal
740 * controller. The decoding of the stream is as follow:
741 *
742 * MT8192 :
743 * Stream index map for MCU Domain mt8192 :
744 *
745 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
746 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
747 *
748 * <-----sensor#2-----> <-----sensor#3----->
749 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
750 *
751 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
752 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
753 *
754 * Stream index map for AP Domain mt8192 :
755 *
756 * <-----sensor#0-----> <-----sensor#1----->
757 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
758 *
759 * <-----sensor#2-----> <-----sensor#3----->
760 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
761 *
762 * <-----sensor#4-----> <-----sensor#5----->
763 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
764 *
765 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
766 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
767 *
768 * MT8195 :
769 * Stream index map for MCU Domain mt8195 :
770 *
771 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
772 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
773 *
774 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
775 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
776 *
777 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
778 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
779 *
780 * Stream index map for AP Domain mt8195 :
781 *
782 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
783 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
784 *
785 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
786 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
787 *
788 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
789 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
790 *
791 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
792 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
793 *
794 * MT8196 :
795 * Stream index map for MCU Domain mt8196 :
796 *
797 * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
798 * 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
799 *
800 * <-sensor#5--> <-sensor#4--> <-sensor#7--> <-sensor#6-->
801 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
802 *
803 * <-sensor#9--> <-sensor#8--> <-sensor#11-> <-sensor#10->
804 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0X1B
805 *
806 * <-sensor#13-> <-sensor#12-> <-sensor#15-> <-sensor#14->
807 * 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
808 *
809 * Stream index map for APU Domain mt8196 :
810 *
811 * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
812 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
813 *
814 * Stream index map for GPU Domain mt8196 :
815 *
816 * <-sensor#1--> <-sensor#0-->
817 * 0x2C | 0x2D | 0x2E | 0x2F
818 *
819 * Stream index map for AP Domain mt8196 :
820 *
821 * <-sensor#1--> <-sensor#0--> <-sensor#3--> <-sensor#2-->
822 * 0x30 | 0x31 | 0x32 | 0x33 | 0x34 | 0x35 | 0x36 | 0x37
823 *
824 * <-sensor#5--> <-sensor#4--> <-sensor#6--> <-sensor#7-->
825 * 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
826 *
827 * Note: In some cases, values don't strictly follow a little endian ordering.
828 * The data description gives byte offsets constituting each calibration value
829 * for each sensor.
830 */
lvts_calibration_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data,u8 * efuse_calibration,size_t calib_len)831 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
832 const struct lvts_ctrl_data *lvts_ctrl_data,
833 u8 *efuse_calibration,
834 size_t calib_len)
835 {
836 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
837 int i, ret;
838 u32 gt;
839
840 /* A zero value for gt means that device has invalid efuse data */
841 gt = (((u32 *)efuse_calibration)[0] >> lvts_data->gt_calib_bit_offset) & 0xff;
842
843 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
844 const struct lvts_sensor_data *sensor =
845 &lvts_ctrl_data->lvts_sensor[i];
846 u32 calib = 0;
847
848 ret = lvts_decode_sensor_calibration(sensor, efuse_calibration,
849 calib_len,
850 lvts_data->num_cal_offsets,
851 &calib);
852 if (ret)
853 return ret;
854
855 if (gt) {
856 lvts_ctrl->calibration[i] = calib;
857 if (lvts_ctrl->lvts_data->msr_offset)
858 lvts_ctrl->calibration[i] += lvts_ctrl->lvts_data->msr_offset;
859 } else if (lvts_ctrl->lvts_data->def_calibration) {
860 lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration;
861 } else {
862 dev_err(dev, "efuse contains invalid calibration data and no default given.\n");
863 return -ENODATA;
864 }
865 }
866
867 return 0;
868 }
869
870 /*
871 * The efuse bytes stream can be split into different chunk of
872 * nvmems. This function reads and concatenate those into a single
873 * buffer so it can be read sequentially when initializing the
874 * calibration data.
875 */
lvts_calibration_read(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)876 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
877 const struct lvts_data *lvts_data)
878 {
879 struct device_node *np = dev_of_node(dev);
880 struct nvmem_cell *cell;
881 struct property *prop;
882 const char *cell_name;
883
884 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
885 size_t len;
886 u8 *efuse;
887
888 cell = of_nvmem_cell_get(np, cell_name);
889 if (IS_ERR(cell)) {
890 dev_err(dev, "Failed to get cell '%s'\n", cell_name);
891 return PTR_ERR(cell);
892 }
893
894 efuse = nvmem_cell_read(cell, &len);
895
896 nvmem_cell_put(cell);
897
898 if (IS_ERR(efuse)) {
899 dev_err(dev, "Failed to read cell '%s'\n", cell_name);
900 return PTR_ERR(efuse);
901 }
902
903 lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
904 lvts_td->calib_len + len, GFP_KERNEL);
905 if (!lvts_td->calib) {
906 kfree(efuse);
907 return -ENOMEM;
908 }
909
910 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
911
912 lvts_td->calib_len += len;
913
914 kfree(efuse);
915 }
916
917 return 0;
918 }
919
lvts_golden_temp_init(struct device * dev,u8 * calib,const struct lvts_data * lvts_data)920 static int lvts_golden_temp_init(struct device *dev, u8 *calib,
921 const struct lvts_data *lvts_data)
922 {
923 u32 gt;
924
925 /*
926 * The golden temp information is contained in the first 32-bit
927 * word of efuse data at a specific bit offset.
928 */
929 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff;
930
931 /* A zero value for gt means that device has invalid efuse data */
932 if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
933 golden_temp = gt;
934
935 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset;
936
937 dev_info(dev, "%sgolden temp=%d\n", gt ? "" : "fake ", golden_temp);
938
939 return 0;
940 }
941
lvts_ctrl_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)942 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
943 const struct lvts_data *lvts_data)
944 {
945 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
946 struct lvts_ctrl *lvts_ctrl;
947 int i, ret;
948
949 /*
950 * Create the calibration bytes stream from efuse data
951 */
952 ret = lvts_calibration_read(dev, lvts_td, lvts_data);
953 if (ret)
954 return ret;
955
956 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data);
957 if (ret)
958 return ret;
959
960 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
961 if (!lvts_ctrl)
962 return -ENOMEM;
963
964 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
965
966 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
967 lvts_ctrl[i].lvts_data = lvts_data;
968
969 ret = lvts_sensor_init(dev, &lvts_ctrl[i],
970 &lvts_data->lvts_ctrl[i]);
971 if (ret)
972 return ret;
973
974 ret = lvts_calibration_init(dev, &lvts_ctrl[i],
975 &lvts_data->lvts_ctrl[i],
976 lvts_td->calib,
977 lvts_td->calib_len);
978 if (ret)
979 return ret;
980
981 /*
982 * The mode the ctrl will use to read the temperature
983 * (filtered or immediate)
984 */
985 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
986
987 lvts_ctrl[i].low_thresh = INT_MIN;
988 lvts_ctrl[i].high_thresh = INT_MIN;
989 }
990
991 /*
992 * We no longer need the efuse bytes stream, let's free it
993 */
994 devm_kfree(dev, lvts_td->calib);
995
996 lvts_td->lvts_ctrl = lvts_ctrl;
997 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
998
999 return 0;
1000 }
1001
lvts_ctrl_monitor_enable(struct device * dev,struct lvts_ctrl * lvts_ctrl,bool enable)1002 static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_ctrl, bool enable)
1003 {
1004 /*
1005 * Bitmaps to enable each sensor on filtered mode in the MONCTL0
1006 * register.
1007 */
1008 static const u8 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1009 u32 sensor_map = 0;
1010 int i;
1011
1012 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE)
1013 return;
1014
1015 if (enable) {
1016 lvts_for_each_valid_sensor(i, lvts_ctrl)
1017 sensor_map |= sensor_filt_bitmap[i];
1018 }
1019
1020 /*
1021 * Bits:
1022 * 9: Single point access flow
1023 * 0-3: Enable sensing point 0-3
1024 */
1025 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1026 }
1027
1028 /*
1029 * At this point the configuration register is the only place in the
1030 * driver where we write multiple values. Per hardware constraint,
1031 * each write in the configuration register must be separated by a
1032 * delay of 2 us.
1033 */
lvts_write_config(struct lvts_ctrl * lvts_ctrl,const u32 * cmds,int nr_cmds)1034 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int nr_cmds)
1035 {
1036 int i;
1037
1038 /*
1039 * Configuration register
1040 */
1041 for (i = 0; i < nr_cmds; i++) {
1042 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
1043 usleep_range(2, 4);
1044 }
1045 }
1046
lvts_irq_init(struct lvts_ctrl * lvts_ctrl)1047 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
1048 {
1049 /*
1050 * LVTS_PROTCTL : Thermal Protection Sensor Selection
1051 *
1052 * Bits:
1053 *
1054 * 19-18 : Sensor to base the protection on
1055 * 17-16 : Strategy:
1056 * 00 : Average of 4 sensors
1057 * 01 : Max of 4 sensors
1058 * 10 : Selected sensor with bits 19-18
1059 * 11 : Reserved
1060 */
1061
1062 /*
1063 * LVTS_PROTTA : Stage 1 temperature threshold
1064 * LVTS_PROTTB : Stage 2 temperature threshold
1065 * LVTS_PROTTC : Stage 3 temperature threshold
1066 *
1067 * Bits:
1068 *
1069 * 14-0: Raw temperature threshold
1070 *
1071 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
1072 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
1073 * writel(0x0, LVTS_PROTTC(lvts_ctrl->base));
1074 */
1075
1076 /*
1077 * LVTS_MONINT : Interrupt configuration register
1078 *
1079 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
1080 * register, except we set the bits to enable the interrupt.
1081 */
1082 writel(0, LVTS_MONINT(lvts_ctrl->base));
1083
1084 return 0;
1085 }
1086
lvts_domain_reset(struct device * dev,struct reset_control * reset)1087 static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
1088 {
1089 int ret;
1090
1091 ret = reset_control_assert(reset);
1092 if (ret)
1093 return ret;
1094
1095 return reset_control_deassert(reset);
1096 }
1097
1098 /*
1099 * Enable or disable the clocks of a specified thermal controller
1100 */
lvts_ctrl_set_enable(struct lvts_ctrl * lvts_ctrl,int enable)1101 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
1102 {
1103 /*
1104 * LVTS_CLKEN : Internal LVTS clock
1105 *
1106 * Bits:
1107 *
1108 * 0 : enable / disable clock
1109 */
1110 writel(enable, LVTS_CLKEN(lvts_ctrl->base));
1111
1112 return 0;
1113 }
1114
lvts_ctrl_connect(struct device * dev,struct lvts_ctrl * lvts_ctrl)1115 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1116 {
1117 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
1118 u32 id;
1119
1120 lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd);
1121
1122 /*
1123 * LVTS_ID : Get ID and status of the thermal controller
1124 *
1125 * Bits:
1126 *
1127 * 0-5 : thermal controller id
1128 * 7 : thermal controller connection is valid
1129 */
1130 id = readl(LVTS_ID(lvts_ctrl->base));
1131 if (!(id & BIT(7)))
1132 return -EIO;
1133
1134 return 0;
1135 }
1136
lvts_ctrl_initialize(struct device * dev,struct lvts_ctrl * lvts_ctrl)1137 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1138 {
1139 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
1140
1141 lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd);
1142
1143 return 0;
1144 }
1145
lvts_ctrl_calibrate(struct device * dev,struct lvts_ctrl * lvts_ctrl)1146 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1147 {
1148 int i;
1149 void __iomem *lvts_edata[] = {
1150 LVTS_EDATA00(lvts_ctrl->base),
1151 LVTS_EDATA01(lvts_ctrl->base),
1152 LVTS_EDATA02(lvts_ctrl->base),
1153 LVTS_EDATA03(lvts_ctrl->base)
1154 };
1155
1156 /*
1157 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
1158 *
1159 * Bits:
1160 *
1161 * 20-0 : Efuse value for normalization data
1162 */
1163 for (i = 0; i < LVTS_SENSOR_MAX; i++)
1164 writel(lvts_ctrl->calibration[i], lvts_edata[i]);
1165
1166 /* LVTS_MSROFT : Constant offset applied to MSR values
1167 * for post-processing
1168 *
1169 * Bits:
1170 *
1171 * 20-0 : Constant data added to MSR values
1172 */
1173 if (lvts_ctrl->lvts_data->msr_offset)
1174 writel(lvts_ctrl->lvts_data->msr_offset,
1175 LVTS_MSROFT(lvts_ctrl->base));
1176
1177 return 0;
1178 }
1179
lvts_ctrl_configure(struct device * dev,struct lvts_ctrl * lvts_ctrl)1180 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1181 {
1182 u32 value;
1183
1184 /*
1185 * LVTS_TSSEL : Sensing point index numbering
1186 *
1187 * Bits:
1188 *
1189 * 31-24: ADC Sense 3
1190 * 23-16: ADC Sense 2
1191 * 15-8 : ADC Sense 1
1192 * 7-0 : ADC Sense 0
1193 */
1194 value = LVTS_TSSEL_CONF;
1195 writel(value, LVTS_TSSEL(lvts_ctrl->base));
1196
1197 /*
1198 * LVTS_CALSCALE : ADC voltage round
1199 */
1200 value = 0x300;
1201 value = LVTS_CALSCALE_CONF;
1202
1203 /*
1204 * LVTS_MSRCTL0 : Sensor filtering strategy
1205 *
1206 * Filters:
1207 *
1208 * 000 : One sample
1209 * 001 : Avg 2 samples
1210 * 010 : 4 samples, drop min and max, avg 2 samples
1211 * 011 : 6 samples, drop min and max, avg 4 samples
1212 * 100 : 10 samples, drop min and max, avg 8 samples
1213 * 101 : 18 samples, drop min and max, avg 16 samples
1214 *
1215 * Bits:
1216 *
1217 * 0-2 : Sensor0 filter
1218 * 3-5 : Sensor1 filter
1219 * 6-8 : Sensor2 filter
1220 * 9-11 : Sensor3 filter
1221 */
1222 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
1223 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
1224 writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
1225
1226 /*
1227 * LVTS_MONCTL1 : Period unit and group interval configuration
1228 *
1229 * The clock source of LVTS thermal controller is 26MHz.
1230 *
1231 * The period unit is a time base for all the interval delays
1232 * specified in the registers. By default we use 12. The time
1233 * conversion is done by multiplying by 256 and 1/26.10^6
1234 *
1235 * An interval delay multiplied by the period unit gives the
1236 * duration in seconds.
1237 *
1238 * - Filter interval delay is a delay between two samples of
1239 * the same sensor.
1240 *
1241 * - Sensor interval delay is a delay between two samples of
1242 * different sensors.
1243 *
1244 * - Group interval delay is a delay between different rounds.
1245 *
1246 * For example:
1247 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
1248 * and two sensors, TS1 and TS2, are in a LVTS thermal controller
1249 * and then
1250 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
1251 * Filter interval delay = 1 * Period unit = 118.149us
1252 * Sensor interval delay = 2 * Period unit = 236.298us
1253 * Group interval delay = 1 * Period unit = 118.149us
1254 *
1255 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
1256 * <--> Filter interval delay
1257 * <--> Sensor interval delay
1258 * <--> Group interval delay
1259 * Bits:
1260 * 29 - 20 : Group interval
1261 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1262 * or an interrupt everytime the hot threshold is crossed (0)
1263 * 9 - 0 : Period unit
1264 *
1265 */
1266 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1267 writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1268
1269 /*
1270 * LVTS_MONCTL2 : Filtering and sensor interval
1271 *
1272 * Bits:
1273 *
1274 * 25-16 : Interval unit in PERIOD_UNIT between sample on
1275 * the same sensor, filter interval
1276 * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1277 *
1278 */
1279 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1280 writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1281
1282 return lvts_irq_init(lvts_ctrl);
1283 }
1284
lvts_ctrl_start(struct device * dev,struct lvts_ctrl * lvts_ctrl)1285 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1286 {
1287 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1288 struct thermal_zone_device *tz;
1289 u32 sensor_map = 0;
1290 int i;
1291 /*
1292 * Bitmaps to enable each sensor on immediate and filtered modes, as
1293 * described in MSRCTL1 and MONCTL0 registers below, respectively.
1294 */
1295 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
1296 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1297
1298 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
1299 sensor_imm_bitmap : sensor_filt_bitmap;
1300
1301 lvts_for_each_valid_sensor(i, lvts_ctrl) {
1302
1303 int dt_id = lvts_sensors[i].dt_id;
1304
1305 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1306 &lvts_ops);
1307 if (IS_ERR(tz)) {
1308 /*
1309 * This thermal zone is not described in the
1310 * device tree. It is not an error from the
1311 * thermal OF code POV, we just continue.
1312 */
1313 if (PTR_ERR(tz) == -ENODEV)
1314 continue;
1315
1316 return PTR_ERR(tz);
1317 }
1318
1319 devm_thermal_add_hwmon_sysfs(dev, tz);
1320
1321 /*
1322 * The thermal zone pointer will be needed in the
1323 * interrupt handler, we store it in the sensor
1324 * structure. The thermal domain structure will be
1325 * passed to the interrupt handler private data as the
1326 * interrupt is shared for all the controller
1327 * belonging to the thermal domain.
1328 */
1329 lvts_sensors[i].tz = tz;
1330
1331 /*
1332 * This sensor was correctly associated with a thermal
1333 * zone, let's set the corresponding bit in the sensor
1334 * map, so we can enable the temperature monitoring in
1335 * the hardware thermal controller.
1336 */
1337 sensor_map |= sensor_bitmap[i];
1338 }
1339
1340 /*
1341 * The initialization of the thermal zones give us
1342 * which sensor point to enable. If any thermal zone
1343 * was not described in the device tree, it won't be
1344 * enabled here in the sensor map.
1345 */
1346 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
1347 /*
1348 * LVTS_MSRCTL1 : Measurement control
1349 *
1350 * Bits:
1351 *
1352 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
1353 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
1354 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
1355 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
1356 *
1357 * That configuration will ignore the filtering and the delays
1358 * introduced in MONCTL1 and MONCTL2
1359 */
1360 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
1361 } else {
1362 /*
1363 * Bits:
1364 * 9: Single point access flow
1365 * 0-3: Enable sensing point 0-3
1366 */
1367 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1368 }
1369
1370 return 0;
1371 }
1372
lvts_domain_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)1373 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1374 const struct lvts_data *lvts_data)
1375 {
1376 struct lvts_ctrl *lvts_ctrl;
1377 int i, ret;
1378
1379 ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1380 if (ret)
1381 return ret;
1382
1383 ret = lvts_domain_reset(dev, lvts_td->reset);
1384 if (ret) {
1385 dev_dbg(dev, "Failed to reset domain");
1386 return ret;
1387 }
1388
1389 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1390
1391 lvts_ctrl = &lvts_td->lvts_ctrl[i];
1392
1393 /*
1394 * Initialization steps:
1395 *
1396 * - Enable the clock
1397 * - Connect to the LVTS
1398 * - Initialize the LVTS
1399 * - Prepare the calibration data
1400 * - Select monitored sensors
1401 * [ Configure sampling ]
1402 * [ Configure the interrupt ]
1403 * - Start measurement
1404 */
1405 ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1406 if (ret) {
1407 dev_dbg(dev, "Failed to enable LVTS clock");
1408 return ret;
1409 }
1410
1411 ret = lvts_ctrl_connect(dev, lvts_ctrl);
1412 if (ret) {
1413 dev_dbg(dev, "Failed to connect to LVTS controller");
1414 return ret;
1415 }
1416
1417 ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1418 if (ret) {
1419 dev_dbg(dev, "Failed to initialize controller");
1420 return ret;
1421 }
1422
1423 ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1424 if (ret) {
1425 dev_dbg(dev, "Failed to calibrate controller");
1426 return ret;
1427 }
1428
1429 ret = lvts_ctrl_configure(dev, lvts_ctrl);
1430 if (ret) {
1431 dev_dbg(dev, "Failed to configure controller");
1432 return ret;
1433 }
1434
1435 ret = lvts_ctrl_start(dev, lvts_ctrl);
1436 if (ret) {
1437 dev_dbg(dev, "Failed to start controller");
1438 return ret;
1439 }
1440 }
1441
1442 return lvts_debugfs_init(dev, lvts_td);
1443 }
1444
lvts_probe(struct platform_device * pdev)1445 static int lvts_probe(struct platform_device *pdev)
1446 {
1447 const struct lvts_data *lvts_data;
1448 struct lvts_domain *lvts_td;
1449 struct device *dev = &pdev->dev;
1450 struct resource *res;
1451 int irq, ret;
1452
1453 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1454 if (!lvts_td)
1455 return -ENOMEM;
1456
1457 lvts_data = of_device_get_match_data(dev);
1458 if (!lvts_data)
1459 return -ENODEV;
1460
1461 lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1462 if (IS_ERR(lvts_td->clk))
1463 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1464
1465 res = platform_get_mem_or_io(pdev, 0);
1466 if (!res)
1467 return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1468
1469 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1470 if (IS_ERR(lvts_td->base))
1471 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1472
1473 /*
1474 * Depending on the SoC+Firmware combination, the LVTS hardware may be
1475 * may be actively used by one or even multiple concurrent MCUs!
1476 * In this case, resetting it may produce either a severe slowdown of
1477 * the entire system, or even a thermal protection AP reset, as some
1478 * MCU(s) may be reading a very high or very low temperature while the
1479 * LVTS is being reset.
1480 *
1481 * On those, don't fail if no reset is found as that may be omitted on
1482 * purpose, but still check if there's one, because some board(s) may
1483 * be running on a different bootchain with reduced firmwares or using
1484 * firmwares with reduced functionality.
1485 */
1486 lvts_td->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1487 if (IS_ERR(lvts_td->reset))
1488 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1489
1490 irq = platform_get_irq(pdev, 0);
1491 if (irq < 0)
1492 return irq;
1493
1494 golden_temp_offset = lvts_data->temp_offset;
1495
1496 ret = lvts_domain_init(dev, lvts_td, lvts_data);
1497 if (ret)
1498 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1499
1500 /*
1501 * At this point the LVTS is initialized and enabled. We can
1502 * safely enable the interrupt.
1503 */
1504 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1505 IRQF_ONESHOT, dev_name(dev), lvts_td);
1506 if (ret)
1507 return ret;
1508
1509 platform_set_drvdata(pdev, lvts_td);
1510
1511 return 0;
1512 }
1513
lvts_remove(struct platform_device * pdev)1514 static void lvts_remove(struct platform_device *pdev)
1515 {
1516 struct lvts_domain *lvts_td;
1517 int i;
1518
1519 lvts_td = platform_get_drvdata(pdev);
1520
1521 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1522 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1523 }
1524
1525 static const struct lvts_ctrl_data mt7987_lvts_ap_data_ctrl[] = {
1526 {
1527 .lvts_sensor = {
1528 { .dt_id = MT7987_CPU,
1529 .cal_offsets = { 0x04, 0x05, 0x06 } },
1530 { .dt_id = MT7987_ETH2P5G,
1531 .cal_offsets = { 0x08, 0x09, 0x0a } },
1532 },
1533 VALID_SENSOR_MAP(1, 1, 0, 0),
1534 .offset = 0x0,
1535 .mode = LVTS_MSR_FILTERED_MODE,
1536 },
1537 };
1538
1539 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
1540 {
1541 .lvts_sensor = {
1542 { .dt_id = MT7988_CPU_0,
1543 .cal_offsets = { 0x00, 0x01, 0x02 } },
1544 { .dt_id = MT7988_CPU_1,
1545 .cal_offsets = { 0x04, 0x05, 0x06 } },
1546 { .dt_id = MT7988_ETH2P5G_0,
1547 .cal_offsets = { 0x08, 0x09, 0x0a } },
1548 { .dt_id = MT7988_ETH2P5G_1,
1549 .cal_offsets = { 0x0c, 0x0d, 0x0e } }
1550 },
1551 VALID_SENSOR_MAP(1, 1, 1, 1),
1552 .offset = 0x0,
1553 },
1554 {
1555 .lvts_sensor = {
1556 { .dt_id = MT7988_TOPS_0,
1557 .cal_offsets = { 0x14, 0x15, 0x16 } },
1558 { .dt_id = MT7988_TOPS_1,
1559 .cal_offsets = { 0x18, 0x19, 0x1a } },
1560 { .dt_id = MT7988_ETHWARP_0,
1561 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1562 { .dt_id = MT7988_ETHWARP_1,
1563 .cal_offsets = { 0x20, 0x21, 0x22 } }
1564 },
1565 VALID_SENSOR_MAP(1, 1, 1, 1),
1566 .offset = 0x100,
1567 }
1568 };
1569
lvts_suspend(struct device * dev)1570 static int lvts_suspend(struct device *dev)
1571 {
1572 struct lvts_domain *lvts_td;
1573 int i;
1574
1575 lvts_td = dev_get_drvdata(dev);
1576
1577 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1578 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], false);
1579 usleep_range(100, 200);
1580 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1581 }
1582
1583 clk_disable_unprepare(lvts_td->clk);
1584
1585 return 0;
1586 }
1587
lvts_resume(struct device * dev)1588 static int lvts_resume(struct device *dev)
1589 {
1590 struct lvts_domain *lvts_td;
1591 int i, ret;
1592
1593 lvts_td = dev_get_drvdata(dev);
1594
1595 ret = clk_prepare_enable(lvts_td->clk);
1596 if (ret)
1597 return ret;
1598
1599 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1600 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
1601 usleep_range(100, 200);
1602 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], true);
1603 }
1604
1605 return 0;
1606 }
1607
1608 static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
1609 static const u32 mt7988_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 };
1610
1611 /*
1612 * Write device mask: 0xC1030000
1613 */
1614 static const u32 default_init_cmds[] = {
1615 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
1616 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
1617 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
1618 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
1619 };
1620
1621 static const u32 mt7987_init_cmds[] = {
1622 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC10308C7,
1623 0xC103098D, 0xC1030C7C, 0xC1030AA8, 0xC10308CE, 0xC10308C7,
1624 0xC1030B04, 0xC1030E01, 0xC10306B8
1625 };
1626
1627 static const u32 mt7988_init_cmds[] = {
1628 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC,
1629 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01,
1630 0xC10306B8
1631 };
1632
1633 /*
1634 * The MT8186 calibration data is stored as packed 3-byte little-endian
1635 * values using a weird layout that makes sense only when viewed as a 32-bit
1636 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and
1637 * y = byte number where the LSB is y=0. We then have:
1638 *
1639 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0]
1640 *
1641 * However, when considering a byte stream, those appear as follows:
1642 *
1643 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0]
1644 *
1645 * Hence the rather confusing offsets provided below.
1646 */
1647 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = {
1648 {
1649 .lvts_sensor = {
1650 { .dt_id = MT8186_LITTLE_CPU0,
1651 .cal_offsets = { 5, 6, 7 } },
1652 { .dt_id = MT8186_LITTLE_CPU1,
1653 .cal_offsets = { 10, 11, 4 } },
1654 { .dt_id = MT8186_LITTLE_CPU2,
1655 .cal_offsets = { 15, 8, 9 } },
1656 { .dt_id = MT8186_CAM,
1657 .cal_offsets = { 12, 13, 14 } }
1658 },
1659 VALID_SENSOR_MAP(1, 1, 1, 1),
1660 .offset = 0x0,
1661 },
1662 {
1663 .lvts_sensor = {
1664 { .dt_id = MT8186_BIG_CPU0,
1665 .cal_offsets = { 22, 23, 16 } },
1666 { .dt_id = MT8186_BIG_CPU1,
1667 .cal_offsets = { 27, 20, 21 } }
1668 },
1669 VALID_SENSOR_MAP(1, 1, 0, 0),
1670 .offset = 0x100,
1671 },
1672 {
1673 .lvts_sensor = {
1674 { .dt_id = MT8186_NNA,
1675 .cal_offsets = { 29, 30, 31 } },
1676 { .dt_id = MT8186_ADSP,
1677 .cal_offsets = { 34, 35, 28 } },
1678 { .dt_id = MT8186_GPU,
1679 .cal_offsets = { 39, 32, 33 } }
1680 },
1681 VALID_SENSOR_MAP(1, 1, 1, 0),
1682 .offset = 0x200,
1683 }
1684 };
1685
1686 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = {
1687 {
1688 .lvts_sensor = {
1689 { .dt_id = MT8188_MCU_LITTLE_CPU0,
1690 .cal_offsets = { 22, 23, 24 } },
1691 { .dt_id = MT8188_MCU_LITTLE_CPU1,
1692 .cal_offsets = { 25, 26, 27 } },
1693 { .dt_id = MT8188_MCU_LITTLE_CPU2,
1694 .cal_offsets = { 28, 29, 30 } },
1695 { .dt_id = MT8188_MCU_LITTLE_CPU3,
1696 .cal_offsets = { 31, 32, 33 } },
1697 },
1698 VALID_SENSOR_MAP(1, 1, 1, 1),
1699 .offset = 0x0,
1700 },
1701 {
1702 .lvts_sensor = {
1703 { .dt_id = MT8188_MCU_BIG_CPU0,
1704 .cal_offsets = { 34, 35, 36 } },
1705 { .dt_id = MT8188_MCU_BIG_CPU1,
1706 .cal_offsets = { 37, 38, 39 } },
1707 },
1708 VALID_SENSOR_MAP(1, 1, 0, 0),
1709 .offset = 0x100,
1710 }
1711 };
1712
1713 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = {
1714 {
1715 .lvts_sensor = {
1716
1717 { /* unused */ },
1718 { .dt_id = MT8188_AP_APU,
1719 .cal_offsets = { 40, 41, 42 } },
1720 },
1721 VALID_SENSOR_MAP(0, 1, 0, 0),
1722 .offset = 0x0,
1723 },
1724 {
1725 .lvts_sensor = {
1726 { .dt_id = MT8188_AP_GPU0,
1727 .cal_offsets = { 43, 44, 45 } },
1728 { .dt_id = MT8188_AP_GPU1,
1729 .cal_offsets = { 46, 47, 48 } },
1730 { .dt_id = MT8188_AP_ADSP,
1731 .cal_offsets = { 49, 50, 51 } },
1732 },
1733 VALID_SENSOR_MAP(1, 1, 1, 0),
1734 .offset = 0x100,
1735 },
1736 {
1737 .lvts_sensor = {
1738 { .dt_id = MT8188_AP_VDO,
1739 .cal_offsets = { 52, 53, 54 } },
1740 { .dt_id = MT8188_AP_INFRA,
1741 .cal_offsets = { 55, 56, 57 } },
1742 },
1743 VALID_SENSOR_MAP(1, 1, 0, 0),
1744 .offset = 0x200,
1745 },
1746 {
1747 .lvts_sensor = {
1748 { .dt_id = MT8188_AP_CAM1,
1749 .cal_offsets = { 58, 59, 60 } },
1750 { .dt_id = MT8188_AP_CAM2,
1751 .cal_offsets = { 61, 62, 63 } },
1752 },
1753 VALID_SENSOR_MAP(1, 1, 0, 0),
1754 .offset = 0x300,
1755 }
1756 };
1757
1758 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
1759 {
1760 .lvts_sensor = {
1761 { .dt_id = MT8192_MCU_BIG_CPU0,
1762 .cal_offsets = { 0x04, 0x05, 0x06 } },
1763 { .dt_id = MT8192_MCU_BIG_CPU1,
1764 .cal_offsets = { 0x08, 0x09, 0x0a } }
1765 },
1766 VALID_SENSOR_MAP(1, 1, 0, 0),
1767 .offset = 0x0,
1768 .mode = LVTS_MSR_FILTERED_MODE,
1769 },
1770 {
1771 .lvts_sensor = {
1772 { .dt_id = MT8192_MCU_BIG_CPU2,
1773 .cal_offsets = { 0x0c, 0x0d, 0x0e } },
1774 { .dt_id = MT8192_MCU_BIG_CPU3,
1775 .cal_offsets = { 0x10, 0x11, 0x12 } }
1776 },
1777 VALID_SENSOR_MAP(1, 1, 0, 0),
1778 .offset = 0x100,
1779 .mode = LVTS_MSR_FILTERED_MODE,
1780 },
1781 {
1782 .lvts_sensor = {
1783 { .dt_id = MT8192_MCU_LITTLE_CPU0,
1784 .cal_offsets = { 0x14, 0x15, 0x16 } },
1785 { .dt_id = MT8192_MCU_LITTLE_CPU1,
1786 .cal_offsets = { 0x18, 0x19, 0x1a } },
1787 { .dt_id = MT8192_MCU_LITTLE_CPU2,
1788 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1789 { .dt_id = MT8192_MCU_LITTLE_CPU3,
1790 .cal_offsets = { 0x20, 0x21, 0x22 } }
1791 },
1792 VALID_SENSOR_MAP(1, 1, 1, 1),
1793 .offset = 0x200,
1794 .mode = LVTS_MSR_FILTERED_MODE,
1795 }
1796 };
1797
1798 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
1799 {
1800 .lvts_sensor = {
1801 { .dt_id = MT8192_AP_VPU0,
1802 .cal_offsets = { 0x24, 0x25, 0x26 } },
1803 { .dt_id = MT8192_AP_VPU1,
1804 .cal_offsets = { 0x28, 0x29, 0x2a } }
1805 },
1806 VALID_SENSOR_MAP(1, 1, 0, 0),
1807 .offset = 0x0,
1808 },
1809 {
1810 .lvts_sensor = {
1811 { .dt_id = MT8192_AP_GPU0,
1812 .cal_offsets = { 0x2c, 0x2d, 0x2e } },
1813 { .dt_id = MT8192_AP_GPU1,
1814 .cal_offsets = { 0x30, 0x31, 0x32 } }
1815 },
1816 VALID_SENSOR_MAP(1, 1, 0, 0),
1817 .offset = 0x100,
1818 },
1819 {
1820 .lvts_sensor = {
1821 { .dt_id = MT8192_AP_INFRA,
1822 .cal_offsets = { 0x34, 0x35, 0x36 } },
1823 { .dt_id = MT8192_AP_CAM,
1824 .cal_offsets = { 0x38, 0x39, 0x3a } },
1825 },
1826 VALID_SENSOR_MAP(1, 1, 0, 0),
1827 .offset = 0x200,
1828 },
1829 {
1830 .lvts_sensor = {
1831 { .dt_id = MT8192_AP_MD0,
1832 .cal_offsets = { 0x3c, 0x3d, 0x3e } },
1833 { .dt_id = MT8192_AP_MD1,
1834 .cal_offsets = { 0x40, 0x41, 0x42 } },
1835 { .dt_id = MT8192_AP_MD2,
1836 .cal_offsets = { 0x44, 0x45, 0x46 } }
1837 },
1838 VALID_SENSOR_MAP(1, 1, 1, 0),
1839 .offset = 0x300,
1840 }
1841 };
1842
1843 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
1844 {
1845 .lvts_sensor = {
1846 { .dt_id = MT8195_MCU_BIG_CPU0,
1847 .cal_offsets = { 0x04, 0x05, 0x06 } },
1848 { .dt_id = MT8195_MCU_BIG_CPU1,
1849 .cal_offsets = { 0x07, 0x08, 0x09 } }
1850 },
1851 VALID_SENSOR_MAP(1, 1, 0, 0),
1852 .offset = 0x0,
1853 },
1854 {
1855 .lvts_sensor = {
1856 { .dt_id = MT8195_MCU_BIG_CPU2,
1857 .cal_offsets = { 0x0d, 0x0e, 0x0f } },
1858 { .dt_id = MT8195_MCU_BIG_CPU3,
1859 .cal_offsets = { 0x10, 0x11, 0x12 } }
1860 },
1861 VALID_SENSOR_MAP(1, 1, 0, 0),
1862 .offset = 0x100,
1863 },
1864 {
1865 .lvts_sensor = {
1866 { .dt_id = MT8195_MCU_LITTLE_CPU0,
1867 .cal_offsets = { 0x16, 0x17, 0x18 } },
1868 { .dt_id = MT8195_MCU_LITTLE_CPU1,
1869 .cal_offsets = { 0x19, 0x1a, 0x1b } },
1870 { .dt_id = MT8195_MCU_LITTLE_CPU2,
1871 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1872 { .dt_id = MT8195_MCU_LITTLE_CPU3,
1873 .cal_offsets = { 0x1f, 0x20, 0x21 } }
1874 },
1875 VALID_SENSOR_MAP(1, 1, 1, 1),
1876 .offset = 0x200,
1877 }
1878 };
1879
1880 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
1881 {
1882 .lvts_sensor = {
1883 { .dt_id = MT8195_AP_VPU0,
1884 .cal_offsets = { 0x25, 0x26, 0x27 } },
1885 { .dt_id = MT8195_AP_VPU1,
1886 .cal_offsets = { 0x28, 0x29, 0x2a } }
1887 },
1888 VALID_SENSOR_MAP(1, 1, 0, 0),
1889 .offset = 0x0,
1890 },
1891 {
1892 .lvts_sensor = {
1893 { .dt_id = MT8195_AP_GPU0,
1894 .cal_offsets = { 0x2e, 0x2f, 0x30 } },
1895 { .dt_id = MT8195_AP_GPU1,
1896 .cal_offsets = { 0x31, 0x32, 0x33 } }
1897 },
1898 VALID_SENSOR_MAP(1, 1, 0, 0),
1899 .offset = 0x100,
1900 },
1901 {
1902 .lvts_sensor = {
1903 { .dt_id = MT8195_AP_VDEC,
1904 .cal_offsets = { 0x37, 0x38, 0x39 } },
1905 { .dt_id = MT8195_AP_IMG,
1906 .cal_offsets = { 0x3a, 0x3b, 0x3c } },
1907 { .dt_id = MT8195_AP_INFRA,
1908 .cal_offsets = { 0x3d, 0x3e, 0x3f } }
1909 },
1910 VALID_SENSOR_MAP(1, 1, 1, 0),
1911 .offset = 0x200,
1912 },
1913 {
1914 .lvts_sensor = {
1915 { .dt_id = MT8195_AP_CAM0,
1916 .cal_offsets = { 0x43, 0x44, 0x45 } },
1917 { .dt_id = MT8195_AP_CAM1,
1918 .cal_offsets = { 0x46, 0x47, 0x48 } }
1919 },
1920 VALID_SENSOR_MAP(1, 1, 0, 0),
1921 .offset = 0x300,
1922 }
1923 };
1924
1925 static const struct lvts_ctrl_data mt8196_lvts_mcu_data_ctrl[] = {
1926 {
1927 .lvts_sensor = {
1928 { .dt_id = MT8196_MCU_MEDIUM_CPU6_0,
1929 .cal_offsets = { 0x06, 0x07 } },
1930 { .dt_id = MT8196_MCU_MEDIUM_CPU6_1,
1931 .cal_offsets = { 0x04, 0x05 } },
1932 { .dt_id = MT8196_MCU_DSU2,
1933 .cal_offsets = { 0x0A, 0x0B } },
1934 { .dt_id = MT8196_MCU_DSU3,
1935 .cal_offsets = { 0x08, 0x09 } }
1936 },
1937 VALID_SENSOR_MAP(1, 1, 1, 1),
1938 .offset = 0x0,
1939 .mode = LVTS_MSR_ATP_MODE,
1940 },
1941 {
1942 .lvts_sensor = {
1943 { .dt_id = MT8196_MCU_LITTLE_CPU3,
1944 .cal_offsets = { 0x0E, 0x0F } },
1945 { .dt_id = MT8196_MCU_LITTLE_CPU0,
1946 .cal_offsets = { 0x0C, 0x0D } },
1947 { .dt_id = MT8196_MCU_LITTLE_CPU1,
1948 .cal_offsets = { 0x12, 0x13 } },
1949 { .dt_id = MT8196_MCU_LITTLE_CPU2,
1950 .cal_offsets = { 0x10, 0x11 } }
1951 },
1952 VALID_SENSOR_MAP(1, 1, 1, 1),
1953 .offset = 0x100,
1954 .mode = LVTS_MSR_ATP_MODE,
1955 },
1956 {
1957 .lvts_sensor = {
1958 { .dt_id = MT8196_MCU_MEDIUM_CPU4_0,
1959 .cal_offsets = { 0x16, 0x17 } },
1960 { .dt_id = MT8196_MCU_MEDIUM_CPU4_1,
1961 .cal_offsets = { 0x14, 0x15 } },
1962 { .dt_id = MT8196_MCU_MEDIUM_CPU5_0,
1963 .cal_offsets = { 0x1A, 0x1B } },
1964 { .dt_id = MT8196_MCU_MEDIUM_CPU5_1,
1965 .cal_offsets = { 0x18, 0x19 } }
1966 },
1967 VALID_SENSOR_MAP(1, 1, 1, 1),
1968 .offset = 0x200,
1969 .mode = LVTS_MSR_ATP_MODE,
1970 },
1971 {
1972 .lvts_sensor = {
1973 { .dt_id = MT8196_MCU_DSU0,
1974 .cal_offsets = { 0x1E, 0x1F } },
1975 { .dt_id = MT8196_MCU_DSU1,
1976 .cal_offsets = { 0x1C, 0x1D } },
1977 { .dt_id = MT8196_MCU_BIG_CPU7_0,
1978 .cal_offsets = { 0x22, 0x23 } },
1979 { .dt_id = MT8196_MCU_BIG_CPU7_1,
1980 .cal_offsets = { 0x20, 0x21 } }
1981 },
1982 VALID_SENSOR_MAP(1, 1, 1, 1),
1983 .offset = 0x300,
1984 .mode = LVTS_MSR_ATP_MODE,
1985 }
1986 };
1987
1988 static const struct lvts_ctrl_data mt8196_lvts_ap_data_ctrl[] = {
1989 {
1990 .lvts_sensor = {
1991 { .dt_id = MT8196_AP_TOP0,
1992 .cal_offsets = { 0x32, 0x33 } },
1993 { .dt_id = MT8196_AP_TOP1,
1994 .cal_offsets = { 0x30, 0x31 } },
1995 { .dt_id = MT8196_AP_TOP2,
1996 .cal_offsets = { 0x36, 0x37 } },
1997 { .dt_id = MT8196_AP_TOP3,
1998 .cal_offsets = { 0x34, 0x35 } }
1999 },
2000 VALID_SENSOR_MAP(1, 1, 1, 1),
2001 .offset = 0x0,
2002 .mode = LVTS_MSR_ATP_MODE,
2003 },
2004 {
2005 .lvts_sensor = {
2006 { .dt_id = MT8196_AP_BOT0,
2007 .cal_offsets = { 0x3A, 0x3B } },
2008 { .dt_id = MT8196_AP_BOT1,
2009 .cal_offsets = { 0x38, 0x39 } },
2010 { .dt_id = MT8196_AP_BOT2,
2011 .cal_offsets = { 0x3E, 0x3F } },
2012 { .dt_id = MT8196_AP_BOT3,
2013 .cal_offsets = { 0x3C, 0x3D } }
2014 },
2015 VALID_SENSOR_MAP(1, 1, 1, 1),
2016 .offset = 0x100,
2017 .mode = LVTS_MSR_ATP_MODE,
2018 }
2019 };
2020
2021 static const struct lvts_platform_ops lvts_platform_ops_mt7988 = {
2022 .lvts_raw_to_temp = lvts_raw_to_temp_mt7988,
2023 .lvts_temp_to_raw = lvts_temp_to_raw_mt7988,
2024 };
2025
2026 static const struct lvts_platform_ops lvts_platform_ops_mt8196 = {
2027 .lvts_raw_to_temp = lvts_raw_to_temp_mt7988,
2028 .lvts_temp_to_raw = lvts_temp_to_raw_mt8196,
2029 };
2030
2031 static const struct lvts_data mt7987_lvts_ap_data = {
2032 .lvts_ctrl = mt7987_lvts_ap_data_ctrl,
2033 .num_lvts_ctrl = ARRAY_SIZE(mt7987_lvts_ap_data_ctrl),
2034 .conn_cmd = mt7988_conn_cmds,
2035 .init_cmd = mt7987_init_cmds,
2036 .num_conn_cmd = ARRAY_SIZE(mt7988_conn_cmds),
2037 .num_init_cmd = ARRAY_SIZE(mt7987_init_cmds),
2038 .temp_factor = LVTS_COEFF_A_MT7987,
2039 .temp_offset = LVTS_COEFF_B_MT7987,
2040 .gt_calib_bit_offset = 32,
2041 .def_calibration = 19380,
2042 };
2043
2044 static const struct lvts_data mt7988_lvts_ap_data = {
2045 .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
2046 .conn_cmd = mt7988_conn_cmds,
2047 .init_cmd = mt7988_init_cmds,
2048 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
2049 .num_conn_cmd = ARRAY_SIZE(mt7988_conn_cmds),
2050 .num_init_cmd = ARRAY_SIZE(mt7988_init_cmds),
2051 .temp_factor = LVTS_COEFF_A_MT7988,
2052 .temp_offset = LVTS_COEFF_B_MT7988,
2053 .gt_calib_bit_offset = 24,
2054 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2055 .ops = &lvts_platform_ops_mt7988,
2056 };
2057
2058 static const struct lvts_data mt8186_lvts_data = {
2059 .lvts_ctrl = mt8186_lvts_data_ctrl,
2060 .conn_cmd = default_conn_cmds,
2061 .init_cmd = default_init_cmds,
2062 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
2063 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2064 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2065 .temp_factor = LVTS_COEFF_A_MT7988,
2066 .temp_offset = LVTS_COEFF_B_MT7988,
2067 .gt_calib_bit_offset = 24,
2068 .def_calibration = 19000,
2069 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2070 .ops = &lvts_platform_ops_mt7988,
2071 };
2072
2073 static const struct lvts_data mt8188_lvts_mcu_data = {
2074 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl,
2075 .conn_cmd = default_conn_cmds,
2076 .init_cmd = default_init_cmds,
2077 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
2078 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2079 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2080 .temp_factor = LVTS_COEFF_A_MT8195,
2081 .temp_offset = LVTS_COEFF_B_MT8195,
2082 .gt_calib_bit_offset = 20,
2083 .def_calibration = 35000,
2084 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2085 .ops = &lvts_platform_ops_mt7988,
2086 };
2087
2088 static const struct lvts_data mt8188_lvts_ap_data = {
2089 .lvts_ctrl = mt8188_lvts_ap_data_ctrl,
2090 .conn_cmd = default_conn_cmds,
2091 .init_cmd = default_init_cmds,
2092 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
2093 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2094 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2095 .temp_factor = LVTS_COEFF_A_MT8195,
2096 .temp_offset = LVTS_COEFF_B_MT8195,
2097 .gt_calib_bit_offset = 20,
2098 .def_calibration = 35000,
2099 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2100 .ops = &lvts_platform_ops_mt7988,
2101 };
2102
2103 static const struct lvts_data mt8192_lvts_mcu_data = {
2104 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
2105 .conn_cmd = default_conn_cmds,
2106 .init_cmd = default_init_cmds,
2107 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
2108 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2109 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2110 .temp_factor = LVTS_COEFF_A_MT8195,
2111 .temp_offset = LVTS_COEFF_B_MT8195,
2112 .gt_calib_bit_offset = 24,
2113 .def_calibration = 35000,
2114 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2115 .ops = &lvts_platform_ops_mt7988,
2116 };
2117
2118 static const struct lvts_data mt8192_lvts_ap_data = {
2119 .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
2120 .conn_cmd = default_conn_cmds,
2121 .init_cmd = default_init_cmds,
2122 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
2123 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2124 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2125 .temp_factor = LVTS_COEFF_A_MT8195,
2126 .temp_offset = LVTS_COEFF_B_MT8195,
2127 .gt_calib_bit_offset = 24,
2128 .def_calibration = 35000,
2129 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2130 .ops = &lvts_platform_ops_mt7988,
2131 };
2132
2133 static const struct lvts_data mt8195_lvts_mcu_data = {
2134 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
2135 .conn_cmd = default_conn_cmds,
2136 .init_cmd = default_init_cmds,
2137 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
2138 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2139 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2140 .temp_factor = LVTS_COEFF_A_MT8195,
2141 .temp_offset = LVTS_COEFF_B_MT8195,
2142 .gt_calib_bit_offset = 24,
2143 .def_calibration = 35000,
2144 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2145 .ops = &lvts_platform_ops_mt7988,
2146 };
2147
2148 static const struct lvts_data mt8195_lvts_ap_data = {
2149 .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
2150 .conn_cmd = default_conn_cmds,
2151 .init_cmd = default_init_cmds,
2152 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
2153 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
2154 .num_init_cmd = ARRAY_SIZE(default_init_cmds),
2155 .temp_factor = LVTS_COEFF_A_MT8195,
2156 .temp_offset = LVTS_COEFF_B_MT8195,
2157 .gt_calib_bit_offset = 24,
2158 .def_calibration = 35000,
2159 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT7988,
2160 .ops = &lvts_platform_ops_mt7988,
2161 };
2162
2163 static const struct lvts_data mt8196_lvts_mcu_data = {
2164 .lvts_ctrl = mt8196_lvts_mcu_data_ctrl,
2165 .num_lvts_ctrl = ARRAY_SIZE(mt8196_lvts_mcu_data_ctrl),
2166 .temp_factor = LVTS_COEFF_A_MT8196,
2167 .temp_offset = LVTS_COEFF_B_MT8196,
2168 .gt_calib_bit_offset = 0,
2169 .def_calibration = 14437,
2170 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT8196,
2171 .msr_offset = LVTS_MSR_OFFSET_MT8196,
2172 .ops = &lvts_platform_ops_mt8196,
2173 };
2174
2175 static const struct lvts_data mt8196_lvts_ap_data = {
2176 .lvts_ctrl = mt8196_lvts_ap_data_ctrl,
2177 .num_lvts_ctrl = ARRAY_SIZE(mt8196_lvts_ap_data_ctrl),
2178 .temp_factor = LVTS_COEFF_A_MT8196,
2179 .temp_offset = LVTS_COEFF_B_MT8196,
2180 .gt_calib_bit_offset = 0,
2181 .def_calibration = 14437,
2182 .num_cal_offsets = LVTS_NUM_CAL_OFFSETS_MT8196,
2183 .msr_offset = LVTS_MSR_OFFSET_MT8196,
2184 .ops = &lvts_platform_ops_mt8196,
2185 };
2186
2187 static const struct of_device_id lvts_of_match[] = {
2188 { .compatible = "mediatek,mt7987-lvts-ap", .data = &mt7987_lvts_ap_data },
2189 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
2190 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data },
2191 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data },
2192 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data },
2193 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
2194 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
2195 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
2196 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
2197 { .compatible = "mediatek,mt8196-lvts-mcu", .data = &mt8196_lvts_mcu_data },
2198 { .compatible = "mediatek,mt8196-lvts-ap", .data = &mt8196_lvts_ap_data },
2199 {},
2200 };
2201 MODULE_DEVICE_TABLE(of, lvts_of_match);
2202
2203 static const struct dev_pm_ops lvts_pm_ops = {
2204 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
2205 };
2206
2207 static struct platform_driver lvts_driver = {
2208 .probe = lvts_probe,
2209 .remove = lvts_remove,
2210 .driver = {
2211 .name = "mtk-lvts-thermal",
2212 .of_match_table = lvts_of_match,
2213 .pm = &lvts_pm_ops,
2214 },
2215 };
2216 module_platform_driver(lvts_driver);
2217
2218 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
2219 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
2220 MODULE_LICENSE("GPL");
2221