1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-a100-ccu.h> 8#include <dt-bindings/clock/sun50i-a100-r-ccu.h> 9#include <dt-bindings/reset/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 clocks = <&ccu CLK_CPUX>; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <0x1>; 33 enable-method = "psci"; 34 clocks = <&ccu CLK_CPUX>; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <0x2>; 41 enable-method = "psci"; 42 clocks = <&ccu CLK_CPUX>; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <0x3>; 49 enable-method = "psci"; 50 clocks = <&ccu CLK_CPUX>; 51 }; 52 }; 53 54 pmu { 55 compatible = "arm,cortex-a53-pmu"; 56 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 dcxo24M: dcxo24M-clk { 69 compatible = "fixed-clock"; 70 clock-frequency = <24000000>; 71 clock-output-names = "dcxo24M"; 72 #clock-cells = <0>; 73 }; 74 75 iosc: internal-osc-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <16000000>; 78 clock-accuracy = <300000000>; 79 clock-output-names = "iosc"; 80 #clock-cells = <0>; 81 }; 82 83 osc32k: osc32k-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 clock-output-names = "osc32k"; 87 #clock-cells = <0>; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 14 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 11 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 10 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0 0 0x3fffffff>; 107 108 syscon: syscon@3000000 { 109 compatible = "allwinner,sun50i-a100-system-control", 110 "allwinner,sun50i-a64-system-control"; 111 reg = <0x03000000 0x1000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges; 115 116 sram_a1: sram@20000 { 117 compatible = "mmio-sram"; 118 reg = <0x00020000 0x4000>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0 0x00020000 0x4000>; 122 }; 123 124 sram_c: sram@24000 { 125 compatible = "mmio-sram"; 126 reg = <0x024000 0x21000>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0 0x024000 0x21000>; 130 }; 131 132 sram_a2: sram@100000 { 133 compatible = "mmio-sram"; 134 reg = <0x0100000 0x14000>; 135 #address-cells = <1>; 136 #size-cells = <1>; 137 ranges = <0 0x0100000 0x14000>; 138 }; 139 }; 140 141 ccu: clock@3001000 { 142 compatible = "allwinner,sun50i-a100-ccu"; 143 reg = <0x03001000 0x1000>; 144 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 145 clock-names = "hosc", "losc", "iosc"; 146 #clock-cells = <1>; 147 #reset-cells = <1>; 148 }; 149 150 dma: dma-controller@3002000 { 151 compatible = "allwinner,sun50i-a100-dma"; 152 reg = <0x03002000 0x1000>; 153 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 155 clock-names = "bus", "mbus"; 156 resets = <&ccu RST_BUS_DMA>; 157 dma-channels = <8>; 158 dma-requests = <52>; 159 #dma-cells = <1>; 160 }; 161 162 gic: interrupt-controller@3021000 { 163 compatible = "arm,gic-400"; 164 reg = <0x03021000 0x1000>, <0x03022000 0x2000>, 165 <0x03024000 0x2000>, <0x03026000 0x2000>; 166 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 167 IRQ_TYPE_LEVEL_HIGH)>; 168 interrupt-controller; 169 #interrupt-cells = <3>; 170 }; 171 172 efuse@3006000 { 173 compatible = "allwinner,sun50i-a100-sid", 174 "allwinner,sun50i-a64-sid"; 175 reg = <0x03006000 0x1000>; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 179 ths_calibration: calib@14 { 180 reg = <0x14 8>; 181 }; 182 183 cpu_speed_grade: cpu-speed-grade@1c { 184 reg = <0x1c 0x2>; 185 }; 186 }; 187 188 watchdog@30090a0 { 189 compatible = "allwinner,sun50i-a100-wdt", 190 "allwinner,sun6i-a31-wdt"; 191 reg = <0x030090a0 0x20>; 192 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&dcxo24M>; 194 }; 195 196 pio: pinctrl@300b000 { 197 compatible = "allwinner,sun50i-a100-pinctrl"; 198 reg = <0x0300b000 0x400>; 199 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 207 clock-names = "apb", "hosc", "losc"; 208 gpio-controller; 209 #gpio-cells = <3>; 210 interrupt-controller; 211 #interrupt-cells = <3>; 212 213 mmc0_pins: mmc0-pins { 214 pins = "PF0", "PF1", "PF2", "PF3", 215 "PF4", "PF5"; 216 function = "mmc0"; 217 drive-strength = <30>; 218 bias-pull-up; 219 }; 220 221 /omit-if-no-ref/ 222 mmc1_pins: mmc1-pins { 223 pins = "PG0", "PG1", "PG2", "PG3", 224 "PG4", "PG5"; 225 function = "mmc1"; 226 drive-strength = <30>; 227 bias-pull-up; 228 }; 229 230 mmc2_pins: mmc2-pins { 231 pins = "PC0", "PC1", "PC5", "PC6", 232 "PC8", "PC9", "PC10", "PC11", 233 "PC13", "PC14", "PC15", "PC16"; 234 function = "mmc2"; 235 drive-strength = <30>; 236 bias-pull-up; 237 }; 238 239 rgmii0_pins: rgmii0-pins { 240 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 241 "PH5", "PH6", "PH7", "PH9", "PH10", 242 "PH14", "PH15", "PH16", "PH17", "PH18"; 243 function = "emac0"; 244 drive-strength = <40>; 245 }; 246 247 rmii0_pins: rmii0-pins { 248 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 249 "PH5", "PH6", "PH7", "PH9", "PH10"; 250 function = "emac0"; 251 drive-strength = <40>; 252 }; 253 254 uart0_pb_pins: uart0-pb-pins { 255 pins = "PB9", "PB10"; 256 function = "uart0"; 257 }; 258 }; 259 260 mmc0: mmc@4020000 { 261 compatible = "allwinner,sun50i-a100-mmc"; 262 reg = <0x04020000 0x1000>; 263 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 264 clock-names = "ahb", "mmc"; 265 resets = <&ccu RST_BUS_MMC0>; 266 reset-names = "ahb"; 267 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&mmc0_pins>; 270 max-frequency = <150000000>; 271 status = "disabled"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 }; 275 276 mmc1: mmc@4021000 { 277 compatible = "allwinner,sun50i-a100-mmc"; 278 reg = <0x04021000 0x1000>; 279 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 280 clock-names = "ahb", "mmc"; 281 resets = <&ccu RST_BUS_MMC1>; 282 reset-names = "ahb"; 283 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&mmc1_pins>; 286 max-frequency = <150000000>; 287 status = "disabled"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 }; 291 292 mmc2: mmc@4022000 { 293 compatible = "allwinner,sun50i-a100-emmc"; 294 reg = <0x04022000 0x1000>; 295 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 296 clock-names = "ahb", "mmc"; 297 resets = <&ccu RST_BUS_MMC2>; 298 reset-names = "ahb"; 299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&mmc2_pins>; 302 max-frequency = <150000000>; 303 status = "disabled"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 }; 307 308 uart0: serial@5000000 { 309 compatible = "snps,dw-apb-uart"; 310 reg = <0x05000000 0x400>; 311 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 clocks = <&ccu CLK_BUS_UART0>; 315 resets = <&ccu RST_BUS_UART0>; 316 status = "disabled"; 317 }; 318 319 uart1: serial@5000400 { 320 compatible = "snps,dw-apb-uart"; 321 reg = <0x05000400 0x400>; 322 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 323 reg-shift = <2>; 324 reg-io-width = <4>; 325 clocks = <&ccu CLK_BUS_UART1>; 326 resets = <&ccu RST_BUS_UART1>; 327 status = "disabled"; 328 }; 329 330 uart2: serial@5000800 { 331 compatible = "snps,dw-apb-uart"; 332 reg = <0x05000800 0x400>; 333 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 334 reg-shift = <2>; 335 reg-io-width = <4>; 336 clocks = <&ccu CLK_BUS_UART2>; 337 resets = <&ccu RST_BUS_UART2>; 338 status = "disabled"; 339 }; 340 341 uart3: serial@5000c00 { 342 compatible = "snps,dw-apb-uart"; 343 reg = <0x05000c00 0x400>; 344 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 clocks = <&ccu CLK_BUS_UART3>; 348 resets = <&ccu RST_BUS_UART3>; 349 status = "disabled"; 350 }; 351 352 uart4: serial@5001000 { 353 compatible = "snps,dw-apb-uart"; 354 reg = <0x05001000 0x400>; 355 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 356 reg-shift = <2>; 357 reg-io-width = <4>; 358 clocks = <&ccu CLK_BUS_UART4>; 359 resets = <&ccu RST_BUS_UART4>; 360 status = "disabled"; 361 }; 362 363 i2c0: i2c@5002000 { 364 compatible = "allwinner,sun50i-a100-i2c", 365 "allwinner,sun8i-v536-i2c", 366 "allwinner,sun6i-a31-i2c"; 367 reg = <0x05002000 0x400>; 368 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&ccu CLK_BUS_I2C0>; 370 resets = <&ccu RST_BUS_I2C0>; 371 dmas = <&dma 43>, <&dma 43>; 372 dma-names = "rx", "tx"; 373 status = "disabled"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 }; 377 378 i2c1: i2c@5002400 { 379 compatible = "allwinner,sun50i-a100-i2c", 380 "allwinner,sun8i-v536-i2c", 381 "allwinner,sun6i-a31-i2c"; 382 reg = <0x05002400 0x400>; 383 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&ccu CLK_BUS_I2C1>; 385 resets = <&ccu RST_BUS_I2C1>; 386 dmas = <&dma 44>, <&dma 44>; 387 dma-names = "rx", "tx"; 388 status = "disabled"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 }; 392 393 i2c2: i2c@5002800 { 394 compatible = "allwinner,sun50i-a100-i2c", 395 "allwinner,sun8i-v536-i2c", 396 "allwinner,sun6i-a31-i2c"; 397 reg = <0x05002800 0x400>; 398 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&ccu CLK_BUS_I2C2>; 400 resets = <&ccu RST_BUS_I2C2>; 401 dmas = <&dma 45>, <&dma 45>; 402 dma-names = "rx", "tx"; 403 status = "disabled"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 }; 407 408 i2c3: i2c@5002c00 { 409 compatible = "allwinner,sun50i-a100-i2c", 410 "allwinner,sun8i-v536-i2c", 411 "allwinner,sun6i-a31-i2c"; 412 reg = <0x05002c00 0x400>; 413 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&ccu CLK_BUS_I2C3>; 415 resets = <&ccu RST_BUS_I2C3>; 416 dmas = <&dma 46>, <&dma 46>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 }; 422 423 emac0: ethernet@5020000 { 424 compatible = "allwinner,sun50i-a100-emac", 425 "allwinner,sun50i-a64-emac"; 426 reg = <0x5020000 0x10000>; 427 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "macirq"; 429 clocks = <&ccu CLK_BUS_EMAC>; 430 clock-names = "stmmaceth"; 431 resets = <&ccu RST_BUS_EMAC>; 432 reset-names = "stmmaceth"; 433 syscon = <&syscon>; 434 status = "disabled"; 435 436 mdio0: mdio { 437 compatible = "snps,dwmac-mdio"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 }; 442 443 ths: thermal-sensor@5070400 { 444 compatible = "allwinner,sun50i-a100-ths"; 445 reg = <0x05070400 0x100>; 446 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&ccu CLK_BUS_THS>; 448 clock-names = "bus"; 449 resets = <&ccu RST_BUS_THS>; 450 nvmem-cells = <&ths_calibration>; 451 nvmem-cell-names = "calibration"; 452 #thermal-sensor-cells = <1>; 453 }; 454 455 usb_otg: usb@5100000 { 456 compatible = "allwinner,sun50i-a100-musb", 457 "allwinner,sun8i-a33-musb"; 458 reg = <0x05100000 0x0400>; 459 clocks = <&ccu CLK_BUS_OTG>; 460 resets = <&ccu RST_BUS_OTG>; 461 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "mc"; 463 phys = <&usbphy 0>; 464 phy-names = "usb"; 465 extcon = <&usbphy 0>; 466 status = "disabled"; 467 }; 468 469 usbphy: phy@5100400 { 470 compatible = "allwinner,sun50i-a100-usb-phy", 471 "allwinner,sun20i-d1-usb-phy"; 472 reg = <0x05100400 0x100>, 473 <0x05101800 0x100>, 474 <0x05200800 0x100>; 475 reg-names = "phy_ctrl", 476 "pmu0", 477 "pmu1"; 478 clocks = <&ccu CLK_USB_PHY0>, 479 <&ccu CLK_USB_PHY1>; 480 clock-names = "usb0_phy", 481 "usb1_phy"; 482 resets = <&ccu RST_USB_PHY0>, 483 <&ccu RST_USB_PHY1>; 484 reset-names = "usb0_reset", 485 "usb1_reset"; 486 status = "disabled"; 487 #phy-cells = <1>; 488 }; 489 490 ehci0: usb@5101000 { 491 compatible = "allwinner,sun50i-a100-ehci", 492 "generic-ehci"; 493 reg = <0x05101000 0x100>; 494 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&ccu CLK_BUS_OHCI0>, 496 <&ccu CLK_BUS_EHCI0>, 497 <&ccu CLK_USB_OHCI0>; 498 resets = <&ccu RST_BUS_OHCI0>, 499 <&ccu RST_BUS_EHCI0>; 500 phys = <&usbphy 0>; 501 phy-names = "usb"; 502 status = "disabled"; 503 }; 504 505 ohci0: usb@5101400 { 506 compatible = "allwinner,sun50i-a100-ohci", 507 "generic-ohci"; 508 reg = <0x05101400 0x100>; 509 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&ccu CLK_BUS_OHCI0>, 511 <&ccu CLK_USB_OHCI0>; 512 resets = <&ccu RST_BUS_OHCI0>; 513 phys = <&usbphy 0>; 514 phy-names = "usb"; 515 status = "disabled"; 516 }; 517 518 ehci1: usb@5200000 { 519 compatible = "allwinner,sun50i-a100-ehci", 520 "generic-ehci"; 521 reg = <0x05200000 0x100>; 522 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&ccu CLK_BUS_OHCI1>, 524 <&ccu CLK_BUS_EHCI1>, 525 <&ccu CLK_USB_OHCI1>; 526 resets = <&ccu RST_BUS_OHCI1>, 527 <&ccu RST_BUS_EHCI1>; 528 phys = <&usbphy 1>; 529 phy-names = "usb"; 530 status = "disabled"; 531 }; 532 533 ohci1: usb@5200400 { 534 compatible = "allwinner,sun50i-a100-ohci", 535 "generic-ohci"; 536 reg = <0x05200400 0x100>; 537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_BUS_OHCI1>, 539 <&ccu CLK_USB_OHCI1>; 540 resets = <&ccu RST_BUS_OHCI1>; 541 phys = <&usbphy 1>; 542 phy-names = "usb"; 543 status = "disabled"; 544 }; 545 546 r_ccu: clock@7010000 { 547 compatible = "allwinner,sun50i-a100-r-ccu"; 548 reg = <0x07010000 0x300>; 549 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 550 <&ccu CLK_PLL_PERIPH0>; 551 clock-names = "hosc", "losc", "iosc", "pll-periph"; 552 #clock-cells = <1>; 553 #reset-cells = <1>; 554 }; 555 556 r_intc: interrupt-controller@7010320 { 557 compatible = "allwinner,sun50i-a100-nmi", 558 "allwinner,sun9i-a80-nmi"; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 reg = <0x07010320 0xc>; 562 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 563 }; 564 565 r_pio: pinctrl@7022000 { 566 compatible = "allwinner,sun50i-a100-r-pinctrl"; 567 reg = <0x07022000 0x400>; 568 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 570 clock-names = "apb", "hosc", "losc"; 571 gpio-controller; 572 #gpio-cells = <3>; 573 interrupt-controller; 574 #interrupt-cells = <3>; 575 576 r_i2c0_pins: r-i2c0-pins { 577 pins = "PL0", "PL1"; 578 function = "s_i2c0"; 579 }; 580 581 r_i2c1_pins: r-i2c1-pins { 582 pins = "PL8", "PL9"; 583 function = "s_i2c1"; 584 }; 585 }; 586 587 r_uart: serial@7080000 { 588 compatible = "snps,dw-apb-uart"; 589 reg = <0x07080000 0x400>; 590 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 591 reg-shift = <2>; 592 reg-io-width = <4>; 593 clocks = <&r_ccu CLK_R_APB2_UART>; 594 resets = <&r_ccu RST_R_APB2_UART>; 595 status = "disabled"; 596 }; 597 598 r_i2c0: i2c@7081400 { 599 compatible = "allwinner,sun50i-a100-i2c", 600 "allwinner,sun8i-v536-i2c", 601 "allwinner,sun6i-a31-i2c"; 602 reg = <0x07081400 0x400>; 603 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&r_ccu CLK_R_APB2_I2C0>; 605 resets = <&r_ccu RST_R_APB2_I2C0>; 606 dmas = <&dma 50>, <&dma 50>; 607 dma-names = "rx", "tx"; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&r_i2c0_pins>; 610 status = "disabled"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 }; 614 615 r_i2c1: i2c@7081800 { 616 compatible = "allwinner,sun50i-a100-i2c", 617 "allwinner,sun8i-v536-i2c", 618 "allwinner,sun6i-a31-i2c"; 619 reg = <0x07081800 0x400>; 620 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&r_ccu CLK_R_APB2_I2C1>; 622 resets = <&r_ccu RST_R_APB2_I2C1>; 623 dmas = <&dma 51>, <&dma 51>; 624 dma-names = "rx", "tx"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&r_i2c1_pins>; 627 status = "disabled"; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 }; 631 }; 632 633 thermal-zones { 634 cpu-thermal { 635 polling-delay-passive = <0>; 636 polling-delay = <0>; 637 thermal-sensors = <&ths 0>; 638 }; 639 640 ddr-thermal { 641 polling-delay-passive = <0>; 642 polling-delay = <0>; 643 thermal-sensors = <&ths 2>; 644 }; 645 646 gpu-thermal { 647 polling-delay-passive = <0>; 648 polling-delay = <0>; 649 thermal-sensors = <&ths 1>; 650 }; 651 }; 652}; 653