1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9
10 #include "pinctrl-msm.h"
11
12 #define REG_SIZE 0x1000
13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
14 { \
15 .grp = PINCTRL_PINGROUP("gpio" #id, \
16 gpio##id##_pins, \
17 ARRAY_SIZE(gpio##id##_pins)), \
18 .ctl_reg = REG_SIZE * id, \
19 .io_reg = 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
21 .intr_status_reg = 0xc + REG_SIZE * id, \
22 .mux_bit = 2, \
23 .pull_bit = 0, \
24 .drv_bit = 6, \
25 .oe_bit = 9, \
26 .in_bit = 0, \
27 .out_bit = 1, \
28 .intr_enable_bit = 0, \
29 .intr_status_bit = 0, \
30 .intr_target_bit = 5, \
31 .intr_target_kpss_val = 3, \
32 .intr_raw_status_bit = 4, \
33 .intr_polarity_bit = 1, \
34 .intr_detection_bit = 2, \
35 .intr_detection_width = 2, \
36 .funcs = (int[]){ \
37 msm_mux_gpio, /* gpio mode */ \
38 msm_mux_##f1, \
39 msm_mux_##f2, \
40 msm_mux_##f3, \
41 msm_mux_##f4, \
42 msm_mux_##f5, \
43 msm_mux_##f6, \
44 msm_mux_##f7, \
45 msm_mux_##f8, \
46 msm_mux_##f9, \
47 }, \
48 .nfuncs = 10, \
49 }
50
51 static const struct pinctrl_pin_desc ipq9650_pins[] = {
52 PINCTRL_PIN(0, "GPIO_0"),
53 PINCTRL_PIN(1, "GPIO_1"),
54 PINCTRL_PIN(2, "GPIO_2"),
55 PINCTRL_PIN(3, "GPIO_3"),
56 PINCTRL_PIN(4, "GPIO_4"),
57 PINCTRL_PIN(5, "GPIO_5"),
58 PINCTRL_PIN(6, "GPIO_6"),
59 PINCTRL_PIN(7, "GPIO_7"),
60 PINCTRL_PIN(8, "GPIO_8"),
61 PINCTRL_PIN(9, "GPIO_9"),
62 PINCTRL_PIN(10, "GPIO_10"),
63 PINCTRL_PIN(11, "GPIO_11"),
64 PINCTRL_PIN(12, "GPIO_12"),
65 PINCTRL_PIN(13, "GPIO_13"),
66 PINCTRL_PIN(14, "GPIO_14"),
67 PINCTRL_PIN(15, "GPIO_15"),
68 PINCTRL_PIN(16, "GPIO_16"),
69 PINCTRL_PIN(17, "GPIO_17"),
70 PINCTRL_PIN(18, "GPIO_18"),
71 PINCTRL_PIN(19, "GPIO_19"),
72 PINCTRL_PIN(20, "GPIO_20"),
73 PINCTRL_PIN(21, "GPIO_21"),
74 PINCTRL_PIN(22, "GPIO_22"),
75 PINCTRL_PIN(23, "GPIO_23"),
76 PINCTRL_PIN(24, "GPIO_24"),
77 PINCTRL_PIN(25, "GPIO_25"),
78 PINCTRL_PIN(26, "GPIO_26"),
79 PINCTRL_PIN(27, "GPIO_27"),
80 PINCTRL_PIN(28, "GPIO_28"),
81 PINCTRL_PIN(29, "GPIO_29"),
82 PINCTRL_PIN(30, "GPIO_30"),
83 PINCTRL_PIN(31, "GPIO_31"),
84 PINCTRL_PIN(32, "GPIO_32"),
85 PINCTRL_PIN(33, "GPIO_33"),
86 PINCTRL_PIN(34, "GPIO_34"),
87 PINCTRL_PIN(35, "GPIO_35"),
88 PINCTRL_PIN(36, "GPIO_36"),
89 PINCTRL_PIN(37, "GPIO_37"),
90 PINCTRL_PIN(38, "GPIO_38"),
91 PINCTRL_PIN(39, "GPIO_39"),
92 PINCTRL_PIN(40, "GPIO_40"),
93 PINCTRL_PIN(41, "GPIO_41"),
94 PINCTRL_PIN(42, "GPIO_42"),
95 PINCTRL_PIN(43, "GPIO_43"),
96 PINCTRL_PIN(44, "GPIO_44"),
97 PINCTRL_PIN(45, "GPIO_45"),
98 PINCTRL_PIN(46, "GPIO_46"),
99 PINCTRL_PIN(47, "GPIO_47"),
100 PINCTRL_PIN(48, "GPIO_48"),
101 PINCTRL_PIN(49, "GPIO_49"),
102 PINCTRL_PIN(50, "GPIO_50"),
103 PINCTRL_PIN(51, "GPIO_51"),
104 PINCTRL_PIN(52, "GPIO_52"),
105 PINCTRL_PIN(53, "GPIO_53"),
106 };
107
108 #define DECLARE_MSM_GPIO_PINS(pin) \
109 static const unsigned int gpio##pin##_pins[] = { pin }
110 DECLARE_MSM_GPIO_PINS(0);
111 DECLARE_MSM_GPIO_PINS(1);
112 DECLARE_MSM_GPIO_PINS(2);
113 DECLARE_MSM_GPIO_PINS(3);
114 DECLARE_MSM_GPIO_PINS(4);
115 DECLARE_MSM_GPIO_PINS(5);
116 DECLARE_MSM_GPIO_PINS(6);
117 DECLARE_MSM_GPIO_PINS(7);
118 DECLARE_MSM_GPIO_PINS(8);
119 DECLARE_MSM_GPIO_PINS(9);
120 DECLARE_MSM_GPIO_PINS(10);
121 DECLARE_MSM_GPIO_PINS(11);
122 DECLARE_MSM_GPIO_PINS(12);
123 DECLARE_MSM_GPIO_PINS(13);
124 DECLARE_MSM_GPIO_PINS(14);
125 DECLARE_MSM_GPIO_PINS(15);
126 DECLARE_MSM_GPIO_PINS(16);
127 DECLARE_MSM_GPIO_PINS(17);
128 DECLARE_MSM_GPIO_PINS(18);
129 DECLARE_MSM_GPIO_PINS(19);
130 DECLARE_MSM_GPIO_PINS(20);
131 DECLARE_MSM_GPIO_PINS(21);
132 DECLARE_MSM_GPIO_PINS(22);
133 DECLARE_MSM_GPIO_PINS(23);
134 DECLARE_MSM_GPIO_PINS(24);
135 DECLARE_MSM_GPIO_PINS(25);
136 DECLARE_MSM_GPIO_PINS(26);
137 DECLARE_MSM_GPIO_PINS(27);
138 DECLARE_MSM_GPIO_PINS(28);
139 DECLARE_MSM_GPIO_PINS(29);
140 DECLARE_MSM_GPIO_PINS(30);
141 DECLARE_MSM_GPIO_PINS(31);
142 DECLARE_MSM_GPIO_PINS(32);
143 DECLARE_MSM_GPIO_PINS(33);
144 DECLARE_MSM_GPIO_PINS(34);
145 DECLARE_MSM_GPIO_PINS(35);
146 DECLARE_MSM_GPIO_PINS(36);
147 DECLARE_MSM_GPIO_PINS(37);
148 DECLARE_MSM_GPIO_PINS(38);
149 DECLARE_MSM_GPIO_PINS(39);
150 DECLARE_MSM_GPIO_PINS(40);
151 DECLARE_MSM_GPIO_PINS(41);
152 DECLARE_MSM_GPIO_PINS(42);
153 DECLARE_MSM_GPIO_PINS(43);
154 DECLARE_MSM_GPIO_PINS(44);
155 DECLARE_MSM_GPIO_PINS(45);
156 DECLARE_MSM_GPIO_PINS(46);
157 DECLARE_MSM_GPIO_PINS(47);
158 DECLARE_MSM_GPIO_PINS(48);
159 DECLARE_MSM_GPIO_PINS(49);
160 DECLARE_MSM_GPIO_PINS(50);
161 DECLARE_MSM_GPIO_PINS(51);
162 DECLARE_MSM_GPIO_PINS(52);
163 DECLARE_MSM_GPIO_PINS(53);
164
165 enum ipq9650_functions {
166 msm_mux_atest_char_start,
167 msm_mux_atest_char_status0,
168 msm_mux_atest_char_status1,
169 msm_mux_atest_char_status2,
170 msm_mux_atest_char_status3,
171 msm_mux_atest_tic_en,
172 msm_mux_audio_pri_mclk_in0,
173 msm_mux_audio_pri_mclk_out0,
174 msm_mux_audio_pri_mclk_in1,
175 msm_mux_audio_pri_mclk_out1,
176 msm_mux_audio_pri,
177 msm_mux_audio_sec,
178 msm_mux_audio_sec_mclk_in0,
179 msm_mux_audio_sec_mclk_out0,
180 msm_mux_audio_sec_mclk_in1,
181 msm_mux_audio_sec_mclk_out1,
182 msm_mux_core_voltage_0,
183 msm_mux_core_voltage_1,
184 msm_mux_core_voltage_2,
185 msm_mux_core_voltage_3,
186 msm_mux_core_voltage_4,
187 msm_mux_cri_rng0,
188 msm_mux_cri_rng1,
189 msm_mux_cri_rng2,
190 msm_mux_dbg_out_clk,
191 msm_mux_gcc_plltest_bypassnl,
192 msm_mux_gcc_plltest_resetn,
193 msm_mux_gcc_tlmm,
194 msm_mux_gpio,
195 msm_mux_mdc_mst,
196 msm_mux_mdc_slv0,
197 msm_mux_mdc_slv1,
198 msm_mux_mdio_mst,
199 msm_mux_mdio_slv,
200 msm_mux_mdio_slv0,
201 msm_mux_mdio_slv1,
202 msm_mux_pcie0_clk_req_n,
203 msm_mux_pcie0_wake,
204 msm_mux_pcie1_clk_req_n,
205 msm_mux_pcie1_wake,
206 msm_mux_pcie2_clk_req_n,
207 msm_mux_pcie2_wake,
208 msm_mux_pcie3_clk_req_n,
209 msm_mux_pcie3_wake,
210 msm_mux_pcie4_clk_req_n,
211 msm_mux_pcie4_wake,
212 msm_mux_pll_bist_sync,
213 msm_mux_pll_test,
214 msm_mux_pwm,
215 msm_mux_qdss_cti_trig_in_a0,
216 msm_mux_qdss_cti_trig_in_a1,
217 msm_mux_qdss_cti_trig_in_b0,
218 msm_mux_qdss_cti_trig_in_b1,
219 msm_mux_qdss_cti_trig_out_a0,
220 msm_mux_qdss_cti_trig_out_a1,
221 msm_mux_qdss_cti_trig_out_b0,
222 msm_mux_qdss_cti_trig_out_b1,
223 msm_mux_qdss_traceclk_a,
224 msm_mux_qdss_tracectl_a,
225 msm_mux_qdss_tracedata_a,
226 msm_mux_qspi_data,
227 msm_mux_qspi_clk,
228 msm_mux_qspi_cs_n,
229 msm_mux_qup_se0,
230 msm_mux_qup_se1,
231 msm_mux_qup_se2,
232 msm_mux_qup_se3,
233 msm_mux_qup_se4,
234 msm_mux_qup_se5,
235 msm_mux_qup_se6,
236 msm_mux_qup_se7,
237 msm_mux_resout,
238 msm_mux_rx_los0,
239 msm_mux_rx_los1,
240 msm_mux_rx_los2,
241 msm_mux_sdc_clk,
242 msm_mux_sdc_cmd,
243 msm_mux_sdc_data,
244 msm_mux_tsens_max,
245 msm_mux_tsn,
246 msm_mux__,
247 };
248
249 static const char *const gpio_groups[] = {
250 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
251 "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
252 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
253 "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
254 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
255 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
256 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
257 "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
258 };
259
260 static const char *const atest_char_start_groups[] = {
261 "gpio21",
262 };
263
264 static const char *const atest_char_status0_groups[] = {
265 "gpio33",
266 };
267
268 static const char *const atest_char_status1_groups[] = {
269 "gpio35",
270 };
271
272 static const char *const atest_char_status2_groups[] = {
273 "gpio22",
274 };
275
276 static const char *const atest_char_status3_groups[] = {
277 "gpio23",
278 };
279
280 static const char *const atest_tic_en_groups[] = {
281 "gpio53",
282 };
283
284 static const char *const audio_pri_mclk_in0_groups[] = {
285 "gpio53",
286 };
287
288 static const char *const audio_pri_mclk_out0_groups[] = {
289 "gpio53",
290 };
291
292 static const char *const audio_pri_mclk_in1_groups[] = {
293 "gpio51",
294 };
295
296 static const char *const audio_pri_mclk_out1_groups[] = {
297 "gpio51",
298 };
299
300 static const char *const audio_pri_groups[] = {
301 "gpio36", "gpio37", "gpio38", "gpio39",
302 };
303
304 static const char *const audio_sec_mclk_in0_groups[] = {
305 "gpio37",
306 };
307
308 static const char *const audio_sec_mclk_out0_groups[] = {
309 "gpio37",
310 };
311
312 static const char *const audio_sec_mclk_in1_groups[] = {
313 "gpio39",
314 };
315
316 static const char *const audio_sec_mclk_out1_groups[] = {
317 "gpio39",
318 };
319
320 static const char *const audio_sec_groups[] = {
321 "gpio45", "gpio46", "gpio47", "gpio48",
322 };
323
324 static const char *const core_voltage_0_groups[] = {
325 "gpio16",
326 };
327
328 static const char *const core_voltage_1_groups[] = {
329 "gpio17",
330 };
331
332 static const char *const core_voltage_2_groups[] = {
333 "gpio33",
334 };
335
336 static const char *const core_voltage_3_groups[] = {
337 "gpio34",
338 };
339
340 static const char *const core_voltage_4_groups[] = {
341 "gpio35",
342 };
343
344 static const char *const cri_rng0_groups[] = {
345 "gpio6",
346 };
347
348 static const char *const cri_rng1_groups[] = {
349 "gpio7",
350 };
351
352 static const char *const cri_rng2_groups[] = {
353 "gpio8",
354 };
355
356 static const char *const dbg_out_clk_groups[] = {
357 "gpio46",
358 };
359
360 static const char *const gcc_plltest_bypassnl_groups[] = {
361 "gpio33",
362 };
363
364 static const char *const gcc_plltest_resetn_groups[] = {
365 "gpio35",
366 };
367
368 static const char *const gcc_tlmm_groups[] = {
369 "gpio34",
370 };
371
372 static const char *const mdc_mst_groups[] = {
373 "gpio22",
374 };
375
376 static const char *const mdc_slv0_groups[] = {
377 "gpio20",
378 };
379
380 static const char *const mdc_slv1_groups[] = {
381 "gpio14",
382 };
383
384 static const char *const mdio_mst_groups[] = {
385 "gpio23",
386 };
387
388 static const char *const mdio_slv_groups[] = {
389 "gpio46",
390 "gpio47",
391 };
392
393 static const char *const mdio_slv0_groups[] = {
394 "gpio21",
395 };
396
397 static const char *const mdio_slv1_groups[] = {
398 "gpio15",
399 };
400
401 static const char *const pcie0_clk_req_n_groups[] = {
402 "gpio24",
403 };
404
405 static const char *const pcie0_wake_groups[] = {
406 "gpio26",
407 };
408
409 static const char *const pcie1_clk_req_n_groups[] = {
410 "gpio27",
411 };
412
413 static const char *const pcie1_wake_groups[] = {
414 "gpio29",
415 };
416
417 static const char *const pcie2_clk_req_n_groups[] = {
418 "gpio51",
419 };
420
421 static const char *const pcie2_wake_groups[] = {
422 "gpio53",
423 };
424
425 static const char *const pcie3_clk_req_n_groups[] = {
426 "gpio40",
427 };
428
429 static const char *const pcie3_wake_groups[] = {
430 "gpio42",
431 };
432
433 static const char *const pcie4_clk_req_n_groups[] = {
434 "gpio30",
435 };
436
437 static const char *const pcie4_wake_groups[] = {
438 "gpio32",
439 };
440
441 static const char *const pll_bist_sync_groups[] = {
442 "gpio47",
443 };
444
445 static const char *const pll_test_groups[] = {
446 "gpio39",
447 };
448
449 static const char *const pwm_groups[] = {
450 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16",
451 "gpio17", "gpio33", "gpio34", "gpio35", "gpio43", "gpio44", "gpio45",
452 "gpio46", "gpio47", "gpio48",
453 };
454
455 static const char *const qdss_cti_trig_in_a0_groups[] = {
456 "gpio53",
457 };
458
459 static const char *const qdss_cti_trig_in_a1_groups[] = {
460 "gpio29",
461 };
462
463 static const char *const qdss_cti_trig_in_b0_groups[] = {
464 "gpio42",
465 };
466
467 static const char *const qdss_cti_trig_in_b1_groups[] = {
468 "gpio43",
469 };
470
471 static const char *const qdss_cti_trig_out_a0_groups[] = {
472 "gpio51",
473 };
474
475 static const char *const qdss_cti_trig_out_a1_groups[] = {
476 "gpio27",
477 };
478
479 static const char *const qdss_cti_trig_out_b0_groups[] = {
480 "gpio40",
481 };
482
483 static const char *const qdss_cti_trig_out_b1_groups[] = {
484 "gpio44",
485 };
486
487 static const char *const qdss_traceclk_a_groups[] = {
488 "gpio45",
489 };
490
491 static const char *const qdss_tracectl_a_groups[] = {
492 "gpio46",
493 };
494
495 static const char *const qdss_tracedata_a_groups[] = {
496 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
497 "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21",
498 "gpio36", "gpio37", "gpio38", "gpio39",
499 };
500
501 static const char *const qspi_data_groups[] = {
502 "gpio0", "gpio1", "gpio2", "gpio3",
503 };
504
505 static const char *const qspi_clk_groups[] = {
506 "gpio5",
507 };
508
509 static const char *const qspi_cs_n_groups[] = {
510 "gpio4",
511 };
512
513 static const char *const qup_se0_groups[] = {
514 "gpio6", "gpio7", "gpio8", "gpio9", "gpio51", "gpio53",
515 };
516
517 static const char *const qup_se1_groups[] = {
518 "gpio10", "gpio11", "gpio12", "gpio13", "gpio27", "gpio29",
519 };
520
521 static const char *const qup_se2_groups[] = {
522 "gpio27", "gpio29", "gpio33", "gpio34",
523 };
524
525 static const char *const qup_se3_groups[] = {
526 "gpio16", "gpio17", "gpio20", "gpio21",
527 };
528
529 static const char *const qup_se4_groups[] = {
530 "gpio14", "gpio15", "gpio40", "gpio42", "gpio43", "gpio44",
531 };
532
533 static const char *const qup_se5_groups[] = {
534 "gpio40", "gpio42", "gpio45", "gpio46", "gpio47", "gpio48",
535 };
536
537 static const char *const qup_se6_groups[] = {
538 "gpio43", "gpio44", "gpio51", "gpio53",
539 };
540
541 static const char *const qup_se7_groups[] = {
542 "gpio36", "gpio37", "gpio38", "gpio39",
543 };
544
545 static const char *const resout_groups[] = {
546 "gpio49",
547 };
548
549 static const char *const rx_los0_groups[] = {
550 "gpio39", "gpio47", "gpio50",
551 };
552
553 static const char *const rx_los1_groups[] = {
554 "gpio38", "gpio46",
555 };
556
557 static const char *const rx_los2_groups[] = {
558 "gpio37", "gpio45",
559 };
560
561 static const char *const sdc_clk_groups[] = {
562 "gpio5",
563 };
564
565 static const char *const sdc_cmd_groups[] = {
566 "gpio4",
567 };
568
569 static const char *const sdc_data_groups[] = {
570 "gpio0", "gpio1", "gpio2", "gpio3",
571 };
572
573 static const char *const tsens_max_groups[] = {
574 "gpio14",
575 };
576
577 static const char *const tsn_groups[] = {
578 "gpio50",
579 };
580
581 static const struct pinfunction ipq9650_functions[] = {
582 MSM_PIN_FUNCTION(atest_char_start),
583 MSM_PIN_FUNCTION(atest_char_status0),
584 MSM_PIN_FUNCTION(atest_char_status1),
585 MSM_PIN_FUNCTION(atest_char_status2),
586 MSM_PIN_FUNCTION(atest_char_status3),
587 MSM_PIN_FUNCTION(atest_tic_en),
588 MSM_PIN_FUNCTION(audio_pri_mclk_in0),
589 MSM_PIN_FUNCTION(audio_pri_mclk_out0),
590 MSM_PIN_FUNCTION(audio_pri_mclk_in1),
591 MSM_PIN_FUNCTION(audio_pri_mclk_out1),
592 MSM_PIN_FUNCTION(audio_pri),
593 MSM_PIN_FUNCTION(audio_sec),
594 MSM_PIN_FUNCTION(audio_sec_mclk_in0),
595 MSM_PIN_FUNCTION(audio_sec_mclk_out0),
596 MSM_PIN_FUNCTION(audio_sec_mclk_in1),
597 MSM_PIN_FUNCTION(audio_sec_mclk_out1),
598 MSM_PIN_FUNCTION(core_voltage_0),
599 MSM_PIN_FUNCTION(core_voltage_1),
600 MSM_PIN_FUNCTION(core_voltage_2),
601 MSM_PIN_FUNCTION(core_voltage_3),
602 MSM_PIN_FUNCTION(core_voltage_4),
603 MSM_PIN_FUNCTION(cri_rng0),
604 MSM_PIN_FUNCTION(cri_rng1),
605 MSM_PIN_FUNCTION(cri_rng2),
606 MSM_PIN_FUNCTION(dbg_out_clk),
607 MSM_PIN_FUNCTION(gcc_plltest_bypassnl),
608 MSM_PIN_FUNCTION(gcc_plltest_resetn),
609 MSM_PIN_FUNCTION(gcc_tlmm),
610 MSM_GPIO_PIN_FUNCTION(gpio),
611 MSM_PIN_FUNCTION(mdc_mst),
612 MSM_PIN_FUNCTION(mdc_slv0),
613 MSM_PIN_FUNCTION(mdc_slv1),
614 MSM_PIN_FUNCTION(mdio_mst),
615 MSM_PIN_FUNCTION(mdio_slv),
616 MSM_PIN_FUNCTION(mdio_slv0),
617 MSM_PIN_FUNCTION(mdio_slv1),
618 MSM_PIN_FUNCTION(pcie0_clk_req_n),
619 MSM_PIN_FUNCTION(pcie0_wake),
620 MSM_PIN_FUNCTION(pcie1_clk_req_n),
621 MSM_PIN_FUNCTION(pcie1_wake),
622 MSM_PIN_FUNCTION(pcie2_clk_req_n),
623 MSM_PIN_FUNCTION(pcie2_wake),
624 MSM_PIN_FUNCTION(pcie3_clk_req_n),
625 MSM_PIN_FUNCTION(pcie3_wake),
626 MSM_PIN_FUNCTION(pcie4_clk_req_n),
627 MSM_PIN_FUNCTION(pcie4_wake),
628 MSM_PIN_FUNCTION(pll_bist_sync),
629 MSM_PIN_FUNCTION(pll_test),
630 MSM_PIN_FUNCTION(pwm),
631 MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
632 MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
633 MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
634 MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
635 MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
636 MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
637 MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
638 MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
639 MSM_PIN_FUNCTION(qdss_traceclk_a),
640 MSM_PIN_FUNCTION(qdss_tracectl_a),
641 MSM_PIN_FUNCTION(qdss_tracedata_a),
642 MSM_PIN_FUNCTION(qspi_data),
643 MSM_PIN_FUNCTION(qspi_clk),
644 MSM_PIN_FUNCTION(qspi_cs_n),
645 MSM_PIN_FUNCTION(qup_se0),
646 MSM_PIN_FUNCTION(qup_se1),
647 MSM_PIN_FUNCTION(qup_se2),
648 MSM_PIN_FUNCTION(qup_se3),
649 MSM_PIN_FUNCTION(qup_se4),
650 MSM_PIN_FUNCTION(qup_se5),
651 MSM_PIN_FUNCTION(qup_se6),
652 MSM_PIN_FUNCTION(qup_se7),
653 MSM_PIN_FUNCTION(resout),
654 MSM_PIN_FUNCTION(rx_los0),
655 MSM_PIN_FUNCTION(rx_los1),
656 MSM_PIN_FUNCTION(rx_los2),
657 MSM_PIN_FUNCTION(sdc_clk),
658 MSM_PIN_FUNCTION(sdc_cmd),
659 MSM_PIN_FUNCTION(sdc_data),
660 MSM_PIN_FUNCTION(tsens_max),
661 MSM_PIN_FUNCTION(tsn),
662 };
663
664 static const struct msm_pingroup ipq9650_groups[] = {
665 [0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _),
666 [1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _),
667 [2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _),
668 [3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _),
669 [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),
670 [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
671 [6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _),
672 [7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _),
673 [8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _),
674 [9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _),
675 [10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),
676 [11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _),
677 [12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),
678 [13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _),
679 [14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _),
680 [15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _),
681 [16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _),
682 [17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _),
683 [18] = PINGROUP(18, _, _, _, _, _, _, _, _, _),
684 [19] = PINGROUP(19, _, _, _, _, _, _, _, _, _),
685 [20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _),
686 [21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _),
687 [22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _),
688 [23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _),
689 [24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _),
690 [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
691 [26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _),
692 [27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _),
693 [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _),
694 [29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _),
695 [30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _),
696 [31] = PINGROUP(31, _, _, _, _, _, _, _, _, _),
697 [32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _),
698 [33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _),
699 [34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _),
700 [35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _),
701 [36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _),
702 [37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _),
703 [38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _),
704 [39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _),
705 [40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _),
706 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
707 [42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _),
708 [43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _),
709 [44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _),
710 [45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _),
711 [46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _),
712 [47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _),
713 [48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _),
714 [49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _),
715 [50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _),
716 [51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _),
717 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
718 [53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _),
719 };
720
721 static const struct msm_pinctrl_soc_data ipq9650_tlmm = {
722 .pins = ipq9650_pins,
723 .npins = ARRAY_SIZE(ipq9650_pins),
724 .functions = ipq9650_functions,
725 .nfunctions = ARRAY_SIZE(ipq9650_functions),
726 .groups = ipq9650_groups,
727 .ngroups = ARRAY_SIZE(ipq9650_groups),
728 .ngpios = 54,
729 };
730
731 static const struct of_device_id ipq9650_tlmm_of_match[] = {
732 { .compatible = "qcom,ipq9650-tlmm", },
733 {},
734 };
735
ipq9650_tlmm_probe(struct platform_device * pdev)736 static int ipq9650_tlmm_probe(struct platform_device *pdev)
737 {
738 return msm_pinctrl_probe(pdev, &ipq9650_tlmm);
739 }
740
741 static struct platform_driver ipq9650_tlmm_driver = {
742 .driver = {
743 .name = "ipq9650-tlmm",
744 .of_match_table = ipq9650_tlmm_of_match,
745 },
746 .probe = ipq9650_tlmm_probe,
747 };
748
ipq9650_tlmm_init(void)749 static int __init ipq9650_tlmm_init(void)
750 {
751 return platform_driver_register(&ipq9650_tlmm_driver);
752 }
753 arch_initcall(ipq9650_tlmm_init);
754
ipq9650_tlmm_exit(void)755 static void __exit ipq9650_tlmm_exit(void)
756 {
757 platform_driver_unregister(&ipq9650_tlmm_driver);
758 }
759 module_exit(ipq9650_tlmm_exit);
760
761 MODULE_DESCRIPTION("QTI IPQ9650 TLMM driver");
762 MODULE_LICENSE("GPL");
763