1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 13#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 14#include <dt-bindings/clock/qcom,sm8350-videocc.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc8280xp.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sm8350-videocc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6afe.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 clocks { 36 xo_board_clk: xo-board-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32764>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a78c"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <981>; 59 dynamic-power-coefficient = <549>; 60 next-level-cache = <&l2_0>; 61 power-domains = <&cpu_pd0>; 62 power-domain-names = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 66 #cooling-cells = <2>; 67 l2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 next-level-cache = <&l3_0>; 72 l3_0: l3-cache { 73 compatible = "cache"; 74 cache-level = <3>; 75 cache-unified; 76 }; 77 }; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a78c"; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <981>; 87 dynamic-power-coefficient = <549>; 88 next-level-cache = <&l2_100>; 89 power-domains = <&cpu_pd1>; 90 power-domain-names = "psci"; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 94 #cooling-cells = <2>; 95 l2_100: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a78c"; 106 reg = <0x0 0x200>; 107 clocks = <&cpufreq_hw 0>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <981>; 110 dynamic-power-coefficient = <549>; 111 next-level-cache = <&l2_200>; 112 power-domains = <&cpu_pd2>; 113 power-domain-names = "psci"; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 117 #cooling-cells = <2>; 118 l2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a78c"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <981>; 133 dynamic-power-coefficient = <549>; 134 next-level-cache = <&l2_300>; 135 power-domains = <&cpu_pd3>; 136 power-domain-names = "psci"; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 #cooling-cells = <2>; 141 l2_300: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-unified; 145 next-level-cache = <&l3_0>; 146 }; 147 }; 148 149 cpu4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-x1c"; 152 reg = <0x0 0x400>; 153 clocks = <&cpufreq_hw 1>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1024>; 156 dynamic-power-coefficient = <590>; 157 next-level-cache = <&l2_400>; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 operating-points-v2 = <&cpu4_opp_table>; 162 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 163 #cooling-cells = <2>; 164 l2_400: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu5: cpu@500 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-x1c"; 175 reg = <0x0 0x500>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 dynamic-power-coefficient = <590>; 180 next-level-cache = <&l2_500>; 181 power-domains = <&cpu_pd5>; 182 power-domain-names = "psci"; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 186 #cooling-cells = <2>; 187 l2_500: l2-cache { 188 compatible = "cache"; 189 cache-level = <2>; 190 cache-unified; 191 next-level-cache = <&l3_0>; 192 }; 193 }; 194 195 cpu6: cpu@600 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-x1c"; 198 reg = <0x0 0x600>; 199 clocks = <&cpufreq_hw 1>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1024>; 202 dynamic-power-coefficient = <590>; 203 next-level-cache = <&l2_600>; 204 power-domains = <&cpu_pd6>; 205 power-domain-names = "psci"; 206 qcom,freq-domain = <&cpufreq_hw 1>; 207 operating-points-v2 = <&cpu4_opp_table>; 208 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 209 #cooling-cells = <2>; 210 l2_600: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&l3_0>; 215 }; 216 }; 217 218 cpu7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-x1c"; 221 reg = <0x0 0x700>; 222 clocks = <&cpufreq_hw 1>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <590>; 226 next-level-cache = <&l2_700>; 227 power-domains = <&cpu_pd7>; 228 power-domain-names = "psci"; 229 qcom,freq-domain = <&cpufreq_hw 1>; 230 operating-points-v2 = <&cpu4_opp_table>; 231 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 232 #cooling-cells = <2>; 233 l2_700: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&l3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&cpu0>; 245 }; 246 247 core1 { 248 cpu = <&cpu1>; 249 }; 250 251 core2 { 252 cpu = <&cpu2>; 253 }; 254 255 core3 { 256 cpu = <&cpu3>; 257 }; 258 259 core4 { 260 cpu = <&cpu4>; 261 }; 262 263 core5 { 264 cpu = <&cpu5>; 265 }; 266 267 core6 { 268 cpu = <&cpu6>; 269 }; 270 271 core7 { 272 cpu = <&cpu7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 little_cpu_sleep_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "little-rail-power-collapse"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <355>; 285 exit-latency-us = <909>; 286 min-residency-us = <3934>; 287 local-timer-stop; 288 }; 289 290 big_cpu_sleep_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "big-rail-power-collapse"; 293 arm,psci-suspend-param = <0x40000004>; 294 entry-latency-us = <241>; 295 exit-latency-us = <1461>; 296 min-residency-us = <4488>; 297 local-timer-stop; 298 }; 299 }; 300 301 domain-idle-states { 302 cluster_sleep_0: cluster-sleep-0 { 303 compatible = "domain-idle-state"; 304 arm,psci-suspend-param = <0x4100c344>; 305 entry-latency-us = <3263>; 306 exit-latency-us = <6562>; 307 min-residency-us = <9987>; 308 }; 309 }; 310 }; 311 312 firmware { 313 scm: scm { 314 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 315 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 316 qcom,dload-mode = <&tcsr 0x13000>; 317 }; 318 }; 319 320 clk_virt: interconnect-clk-virt { 321 compatible = "qcom,sc8280xp-clk-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 mc_virt: interconnect-mc-virt { 327 compatible = "qcom,sc8280xp-mc-virt"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 memory@80000000 { 333 device_type = "memory"; 334 /* We expect the bootloader to fill in the size */ 335 reg = <0x0 0x80000000 0x0 0x0>; 336 }; 337 338 cpu0_opp_table: opp-table-cpu0 { 339 compatible = "operating-points-v2"; 340 opp-shared; 341 342 opp-300000000 { 343 opp-hz = /bits/ 64 <300000000>; 344 opp-peak-kBps = <(300000 * 32)>; 345 }; 346 opp-403200000 { 347 opp-hz = /bits/ 64 <403200000>; 348 opp-peak-kBps = <(384000 * 32)>; 349 }; 350 opp-499200000 { 351 opp-hz = /bits/ 64 <499200000>; 352 opp-peak-kBps = <(480000 * 32)>; 353 }; 354 opp-595200000 { 355 opp-hz = /bits/ 64 <595200000>; 356 opp-peak-kBps = <(576000 * 32)>; 357 }; 358 opp-691200000 { 359 opp-hz = /bits/ 64 <691200000>; 360 opp-peak-kBps = <(672000 * 32)>; 361 }; 362 opp-806400000 { 363 opp-hz = /bits/ 64 <806400000>; 364 opp-peak-kBps = <(768000 * 32)>; 365 }; 366 opp-902400000 { 367 opp-hz = /bits/ 64 <902400000>; 368 opp-peak-kBps = <(864000 * 32)>; 369 }; 370 opp-1017600000 { 371 opp-hz = /bits/ 64 <1017600000>; 372 opp-peak-kBps = <(960000 * 32)>; 373 }; 374 opp-1113600000 { 375 opp-hz = /bits/ 64 <1113600000>; 376 opp-peak-kBps = <(1075200 * 32)>; 377 }; 378 opp-1209600000 { 379 opp-hz = /bits/ 64 <1209600000>; 380 opp-peak-kBps = <(1171200 * 32)>; 381 }; 382 opp-1324800000 { 383 opp-hz = /bits/ 64 <1324800000>; 384 opp-peak-kBps = <(1267200 * 32)>; 385 }; 386 opp-1440000000 { 387 opp-hz = /bits/ 64 <1440000000>; 388 opp-peak-kBps = <(1363200 * 32)>; 389 }; 390 opp-1555200000 { 391 opp-hz = /bits/ 64 <1555200000>; 392 opp-peak-kBps = <(1536000 * 32)>; 393 }; 394 opp-1670400000 { 395 opp-hz = /bits/ 64 <1670400000>; 396 opp-peak-kBps = <(1612800 * 32)>; 397 }; 398 opp-1785600000 { 399 opp-hz = /bits/ 64 <1785600000>; 400 opp-peak-kBps = <(1689600 * 32)>; 401 }; 402 opp-1881600000 { 403 opp-hz = /bits/ 64 <1881600000>; 404 opp-peak-kBps = <(1689600 * 32)>; 405 }; 406 opp-1996800000 { 407 opp-hz = /bits/ 64 <1996800000>; 408 opp-peak-kBps = <(1689600 * 32)>; 409 }; 410 opp-2112000000 { 411 opp-hz = /bits/ 64 <2112000000>; 412 opp-peak-kBps = <(1689600 * 32)>; 413 }; 414 opp-2227200000 { 415 opp-hz = /bits/ 64 <2227200000>; 416 opp-peak-kBps = <(1689600 * 32)>; 417 }; 418 opp-2342400000 { 419 opp-hz = /bits/ 64 <2342400000>; 420 opp-peak-kBps = <(1689600 * 32)>; 421 }; 422 opp-2438400000 { 423 opp-hz = /bits/ 64 <2438400000>; 424 opp-peak-kBps = <(1689600 * 32)>; 425 }; 426 }; 427 428 cpu4_opp_table: opp-table-cpu4 { 429 compatible = "operating-points-v2"; 430 opp-shared; 431 432 opp-825600000 { 433 opp-hz = /bits/ 64 <825600000>; 434 opp-peak-kBps = <(768000 * 32)>; 435 }; 436 opp-940800000 { 437 opp-hz = /bits/ 64 <940800000>; 438 opp-peak-kBps = <(864000 * 32)>; 439 }; 440 opp-1056000000 { 441 opp-hz = /bits/ 64 <1056000000>; 442 opp-peak-kBps = <(960000 * 32)>; 443 }; 444 opp-1171200000 { 445 opp-hz = /bits/ 64 <1171200000>; 446 opp-peak-kBps = <(1171200 * 32)>; 447 }; 448 opp-1286400000 { 449 opp-hz = /bits/ 64 <1286400000>; 450 opp-peak-kBps = <(1267200 * 32)>; 451 }; 452 opp-1401600000 { 453 opp-hz = /bits/ 64 <1401600000>; 454 opp-peak-kBps = <(1363200 * 32)>; 455 }; 456 opp-1516800000 { 457 opp-hz = /bits/ 64 <1516800000>; 458 opp-peak-kBps = <(1459200 * 32)>; 459 }; 460 opp-1632000000 { 461 opp-hz = /bits/ 64 <1632000000>; 462 opp-peak-kBps = <(1612800 * 32)>; 463 }; 464 opp-1747200000 { 465 opp-hz = /bits/ 64 <1747200000>; 466 opp-peak-kBps = <(1689600 * 32)>; 467 }; 468 opp-1862400000 { 469 opp-hz = /bits/ 64 <1862400000>; 470 opp-peak-kBps = <(1689600 * 32)>; 471 }; 472 opp-1977600000 { 473 opp-hz = /bits/ 64 <1977600000>; 474 opp-peak-kBps = <(1689600 * 32)>; 475 }; 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(1689600 * 32)>; 479 }; 480 opp-2169600000 { 481 opp-hz = /bits/ 64 <2169600000>; 482 opp-peak-kBps = <(1689600 * 32)>; 483 }; 484 opp-2284800000 { 485 opp-hz = /bits/ 64 <2284800000>; 486 opp-peak-kBps = <(1689600 * 32)>; 487 }; 488 opp-2400000000 { 489 opp-hz = /bits/ 64 <2400000000>; 490 opp-peak-kBps = <(1689600 * 32)>; 491 }; 492 opp-2496000000 { 493 opp-hz = /bits/ 64 <2496000000>; 494 opp-peak-kBps = <(1689600 * 32)>; 495 }; 496 opp-2592000000 { 497 opp-hz = /bits/ 64 <2592000000>; 498 opp-peak-kBps = <(1689600 * 32)>; 499 }; 500 opp-2688000000 { 501 opp-hz = /bits/ 64 <2688000000>; 502 opp-peak-kBps = <(1689600 * 32)>; 503 }; 504 opp-2803200000 { 505 opp-hz = /bits/ 64 <2803200000>; 506 opp-peak-kBps = <(1689600 * 32)>; 507 }; 508 opp-2899200000 { 509 opp-hz = /bits/ 64 <2899200000>; 510 opp-peak-kBps = <(1689600 * 32)>; 511 }; 512 opp-2995200000 { 513 opp-hz = /bits/ 64 <2995200000>; 514 opp-peak-kBps = <(1689600 * 32)>; 515 }; 516 }; 517 518 qup_opp_table_100mhz: opp-table-qup100mhz { 519 compatible = "operating-points-v2"; 520 521 opp-75000000 { 522 opp-hz = /bits/ 64 <75000000>; 523 required-opps = <&rpmhpd_opp_low_svs>; 524 }; 525 526 opp-100000000 { 527 opp-hz = /bits/ 64 <100000000>; 528 required-opps = <&rpmhpd_opp_svs>; 529 }; 530 }; 531 532 pmu { 533 compatible = "arm,armv8-pmuv3"; 534 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 535 }; 536 537 psci { 538 compatible = "arm,psci-1.0"; 539 method = "smc"; 540 541 cpu_pd0: power-domain-cpu0 { 542 #power-domain-cells = <0>; 543 power-domains = <&cluster_pd>; 544 domain-idle-states = <&little_cpu_sleep_0>; 545 }; 546 547 cpu_pd1: power-domain-cpu1 { 548 #power-domain-cells = <0>; 549 power-domains = <&cluster_pd>; 550 domain-idle-states = <&little_cpu_sleep_0>; 551 }; 552 553 cpu_pd2: power-domain-cpu2 { 554 #power-domain-cells = <0>; 555 power-domains = <&cluster_pd>; 556 domain-idle-states = <&little_cpu_sleep_0>; 557 }; 558 559 cpu_pd3: power-domain-cpu3 { 560 #power-domain-cells = <0>; 561 power-domains = <&cluster_pd>; 562 domain-idle-states = <&little_cpu_sleep_0>; 563 }; 564 565 cpu_pd4: power-domain-cpu4 { 566 #power-domain-cells = <0>; 567 power-domains = <&cluster_pd>; 568 domain-idle-states = <&big_cpu_sleep_0>; 569 }; 570 571 cpu_pd5: power-domain-cpu5 { 572 #power-domain-cells = <0>; 573 power-domains = <&cluster_pd>; 574 domain-idle-states = <&big_cpu_sleep_0>; 575 }; 576 577 cpu_pd6: power-domain-cpu6 { 578 #power-domain-cells = <0>; 579 power-domains = <&cluster_pd>; 580 domain-idle-states = <&big_cpu_sleep_0>; 581 }; 582 583 cpu_pd7: power-domain-cpu7 { 584 #power-domain-cells = <0>; 585 power-domains = <&cluster_pd>; 586 domain-idle-states = <&big_cpu_sleep_0>; 587 }; 588 589 cluster_pd: power-domain-cpu-cluster0 { 590 #power-domain-cells = <0>; 591 domain-idle-states = <&cluster_sleep_0>; 592 }; 593 }; 594 595 reserved-memory { 596 #address-cells = <2>; 597 #size-cells = <2>; 598 ranges; 599 600 reserved-region@80000000 { 601 reg = <0 0x80000000 0 0x860000>; 602 no-map; 603 }; 604 605 cmd_db: cmd-db-region@80860000 { 606 compatible = "qcom,cmd-db"; 607 reg = <0 0x80860000 0 0x20000>; 608 no-map; 609 }; 610 611 reserved-region@80880000 { 612 reg = <0 0x80880000 0 0x80000>; 613 no-map; 614 }; 615 616 smem_mem: smem-region@80900000 { 617 compatible = "qcom,smem"; 618 reg = <0 0x80900000 0 0x200000>; 619 no-map; 620 hwlocks = <&tcsr_mutex 3>; 621 }; 622 623 reserved-region@80b00000 { 624 reg = <0 0x80b00000 0 0x100000>; 625 no-map; 626 }; 627 628 reserved-region@83b00000 { 629 reg = <0 0x83b00000 0 0x1700000>; 630 no-map; 631 }; 632 633 reserved-region@85b00000 { 634 reg = <0 0x85b00000 0 0xc00000>; 635 no-map; 636 }; 637 638 pil_video_mem: video-region@86700000 { 639 reg = <0 0x86700000 0 0x500000>; 640 no-map; 641 }; 642 643 pil_adsp_mem: adsp-region@86c00000 { 644 reg = <0 0x86c00000 0 0x2000000>; 645 no-map; 646 }; 647 648 pil_slpi_mem: slpi-region@88c00000 { 649 reg = <0 0x88c00000 0 0x1500000>; 650 no-map; 651 }; 652 653 pil_nsp0_mem: cdsp0-region@8a100000 { 654 reg = <0 0x8a100000 0 0x1e00000>; 655 no-map; 656 }; 657 658 pil_gpu_mem: gpu-mem@8bf00000 { 659 reg = <0 0x8bf00000 0 0x2000>; 660 no-map; 661 }; 662 663 pil_nsp1_mem: cdsp1-region@8c600000 { 664 reg = <0 0x8c600000 0 0x1e00000>; 665 no-map; 666 }; 667 668 reserved-region@aeb00000 { 669 reg = <0 0xaeb00000 0 0x16600000>; 670 no-map; 671 }; 672 }; 673 674 smp2p-adsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <443>, <429>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_LPASS 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <2>; 685 686 smp2p_adsp_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 smp2p_adsp_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-nsp0 { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <94>, <432>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <5>; 709 710 smp2p_nsp0_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 smp2p_nsp0_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 }; 721 722 smp2p-nsp1 { 723 compatible = "qcom,smp2p"; 724 qcom,smem = <617>, <616>; 725 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 726 IPCC_MPROC_SIGNAL_SMP2P 727 IRQ_TYPE_EDGE_RISING>; 728 mboxes = <&ipcc IPCC_CLIENT_NSP1 729 IPCC_MPROC_SIGNAL_SMP2P>; 730 731 qcom,local-pid = <0>; 732 qcom,remote-pid = <12>; 733 734 smp2p_nsp1_out: master-kernel { 735 qcom,entry-name = "master-kernel"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 smp2p_nsp1_in: slave-kernel { 740 qcom,entry-name = "slave-kernel"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 }; 745 746 smp2p-slpi { 747 compatible = "qcom,smp2p"; 748 qcom,smem = <481>, <430>; 749 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 mboxes = <&ipcc IPCC_CLIENT_SLPI 753 IPCC_MPROC_SIGNAL_SMP2P>; 754 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <3>; 757 758 smp2p_slpi_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 smp2p_slpi_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 }; 769 770 soc: soc@0 { 771 compatible = "simple-bus"; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges = <0 0 0 0 0x10 0>; 775 dma-ranges = <0 0 0 0 0x10 0>; 776 777 ethernet0: ethernet@20000 { 778 compatible = "qcom,sc8280xp-ethqos"; 779 reg = <0x0 0x00020000 0x0 0x10000>, 780 <0x0 0x00036000 0x0 0x100>; 781 reg-names = "stmmaceth", "rgmii"; 782 783 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 784 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 785 <&gcc GCC_EMAC0_PTP_CLK>, 786 <&gcc GCC_EMAC0_RGMII_CLK>; 787 clock-names = "stmmaceth", 788 "pclk", 789 "ptp_ref", 790 "rgmii"; 791 792 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-names = "macirq", "eth_lpi"; 795 796 iommus = <&apps_smmu 0x4c0 0xf>; 797 power-domains = <&gcc EMAC_0_GDSC>; 798 799 snps,tso; 800 snps,pbl = <32>; 801 rx-fifo-depth = <4096>; 802 tx-fifo-depth = <4096>; 803 804 status = "disabled"; 805 }; 806 807 gcc: clock-controller@100000 { 808 compatible = "qcom,gcc-sc8280xp"; 809 reg = <0x0 0x00100000 0x0 0x1f0000>; 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 clocks = <&rpmhcc RPMH_CXO_CLK>, 814 <&sleep_clk>, 815 <0>, 816 <0>, 817 <0>, 818 <0>, 819 <0>, 820 <0>, 821 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <&pcie2a_phy>, 840 <&pcie2b_phy>, 841 <&pcie3a_phy>, 842 <&pcie3b_phy>, 843 <&pcie4_phy>, 844 <0>, 845 <0>; 846 power-domains = <&rpmhpd SC8280XP_CX>; 847 }; 848 849 ipcc: mailbox@408000 { 850 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 851 reg = <0 0x00408000 0 0x1000>; 852 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-controller; 854 #interrupt-cells = <3>; 855 #mbox-cells = <2>; 856 }; 857 858 qfprom: efuse@784000 { 859 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 860 reg = <0 0x00784000 0 0x3000>; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 864 gpu_speed_bin: gpu-speed-bin@18b { 865 reg = <0x18b 0x1>; 866 bits = <5 3>; 867 }; 868 }; 869 870 gpi_dma2: dma-controller@800000 { 871 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 872 reg = <0 0x00800000 0 0x60000>; 873 874 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 886 887 dma-channels = <12>; 888 #dma-cells = <3>; 889 890 iommus = <&apps_smmu 0xb6 0x0>; 891 892 status = "disabled"; 893 }; 894 895 qup2: geniqup@8c0000 { 896 compatible = "qcom,geni-se-qup"; 897 reg = <0 0x008c0000 0 0x2000>; 898 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 899 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 900 clock-names = "m-ahb", "s-ahb"; 901 iommus = <&apps_smmu 0xa3 0>; 902 903 #address-cells = <2>; 904 #size-cells = <2>; 905 ranges; 906 907 status = "disabled"; 908 909 i2c16: i2c@880000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0 0x00880000 0 0x4000>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 915 clock-names = "se"; 916 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 917 power-domains = <&rpmhpd SC8280XP_CX>; 918 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 920 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 921 interconnect-names = "qup-core", "qup-config", "qup-memory"; 922 923 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 924 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 925 dma-names = "tx", 926 "rx"; 927 928 status = "disabled"; 929 }; 930 931 spi16: spi@880000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0 0x00880000 0 0x4000>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 937 clock-names = "se"; 938 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 939 power-domains = <&rpmhpd SC8280XP_CX>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 942 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 943 interconnect-names = "qup-core", "qup-config", "qup-memory"; 944 945 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 946 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 947 dma-names = "tx", 948 "rx"; 949 950 status = "disabled"; 951 }; 952 953 i2c17: i2c@884000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00884000 0 0x4000>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 959 clock-names = "se"; 960 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 961 power-domains = <&rpmhpd SC8280XP_CX>; 962 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 963 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 964 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 965 interconnect-names = "qup-core", "qup-config", "qup-memory"; 966 967 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 968 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 969 dma-names = "tx", 970 "rx"; 971 972 status = "disabled"; 973 }; 974 975 spi17: spi@884000 { 976 compatible = "qcom,geni-spi"; 977 reg = <0 0x00884000 0 0x4000>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 981 clock-names = "se"; 982 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 983 power-domains = <&rpmhpd SC8280XP_CX>; 984 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 985 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 986 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 987 interconnect-names = "qup-core", "qup-config", "qup-memory"; 988 989 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 990 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 991 dma-names = "tx", 992 "rx"; 993 994 status = "disabled"; 995 }; 996 997 uart17: serial@884000 { 998 compatible = "qcom,geni-uart"; 999 reg = <0 0x00884000 0 0x4000>; 1000 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1001 clock-names = "se"; 1002 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1003 operating-points-v2 = <&qup_opp_table_100mhz>; 1004 power-domains = <&rpmhpd SC8280XP_CX>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1007 interconnect-names = "qup-core", "qup-config"; 1008 status = "disabled"; 1009 }; 1010 1011 i2c18: i2c@888000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00888000 0 0x4000>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 clock-names = "se"; 1018 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1019 power-domains = <&rpmhpd SC8280XP_CX>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1022 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1023 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1024 1025 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1026 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1027 dma-names = "tx", 1028 "rx"; 1029 1030 status = "disabled"; 1031 }; 1032 1033 spi18: spi@888000 { 1034 compatible = "qcom,geni-spi"; 1035 reg = <0 0x00888000 0 0x4000>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1039 clock-names = "se"; 1040 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&rpmhpd SC8280XP_CX>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1043 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1044 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1045 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1046 1047 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1048 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1049 dma-names = "tx", 1050 "rx"; 1051 1052 status = "disabled"; 1053 }; 1054 1055 uart18: serial@888000 { 1056 compatible = "qcom,geni-uart"; 1057 reg = <0 0x00888000 0 0x4000>; 1058 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1059 clock-names = "se"; 1060 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1061 operating-points-v2 = <&qup_opp_table_100mhz>; 1062 power-domains = <&rpmhpd SC8280XP_CX>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 1067 pinctrl-0 = <&qup_uart18_default>; 1068 pinctrl-names = "default"; 1069 1070 status = "disabled"; 1071 }; 1072 1073 i2c19: i2c@88c000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0 0x0088c000 0 0x4000>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1079 clock-names = "se"; 1080 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1081 power-domains = <&rpmhpd SC8280XP_CX>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1084 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1086 1087 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1089 dma-names = "tx", 1090 "rx"; 1091 1092 status = "disabled"; 1093 }; 1094 1095 spi19: spi@88c000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x0088c000 0 0x4000>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1101 clock-names = "se"; 1102 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1103 power-domains = <&rpmhpd SC8280XP_CX>; 1104 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1105 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1106 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1107 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1108 1109 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1110 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1111 dma-names = "tx", 1112 "rx"; 1113 1114 status = "disabled"; 1115 }; 1116 1117 i2c20: i2c@890000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0 0x00890000 0 0x4000>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1123 clock-names = "se"; 1124 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC8280XP_CX>; 1126 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1128 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1129 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1130 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1132 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1133 dma-names = "tx", 1134 "rx"; 1135 1136 status = "disabled"; 1137 }; 1138 1139 spi20: spi@890000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x00890000 0 0x4000>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1145 clock-names = "se"; 1146 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1147 power-domains = <&rpmhpd SC8280XP_CX>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1150 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1151 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1152 1153 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1154 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1155 dma-names = "tx", 1156 "rx"; 1157 1158 status = "disabled"; 1159 }; 1160 1161 i2c21: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1166 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 power-domains = <&rpmhpd SC8280XP_CX>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1173 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1174 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 1180 status = "disabled"; 1181 }; 1182 1183 spi21: spi@894000 { 1184 compatible = "qcom,geni-spi"; 1185 reg = <0 0x00894000 0 0x4000>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1189 clock-names = "se"; 1190 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1191 power-domains = <&rpmhpd SC8280XP_CX>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1195 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1196 1197 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1198 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1199 dma-names = "tx", 1200 "rx"; 1201 1202 status = "disabled"; 1203 }; 1204 1205 i2c22: i2c@898000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x00898000 0 0x4000>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1212 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1213 power-domains = <&rpmhpd SC8280XP_CX>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1216 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1217 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1218 1219 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1220 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1221 dma-names = "tx", 1222 "rx"; 1223 1224 status = "disabled"; 1225 }; 1226 1227 spi22: spi@898000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0 0x00898000 0 0x4000>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1233 clock-names = "se"; 1234 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC8280XP_CX>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1238 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1240 1241 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1242 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1243 dma-names = "tx", 1244 "rx"; 1245 1246 status = "disabled"; 1247 }; 1248 1249 i2c23: i2c@89c000 { 1250 compatible = "qcom,geni-i2c"; 1251 reg = <0 0x0089c000 0 0x4000>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1256 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1257 power-domains = <&rpmhpd SC8280XP_CX>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1260 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1261 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1262 1263 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1264 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1265 dma-names = "tx", 1266 "rx"; 1267 1268 status = "disabled"; 1269 }; 1270 1271 spi23: spi@89c000 { 1272 compatible = "qcom,geni-spi"; 1273 reg = <0 0x0089c000 0 0x4000>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1277 clock-names = "se"; 1278 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1279 power-domains = <&rpmhpd SC8280XP_CX>; 1280 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1281 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1282 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1283 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1284 1285 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1286 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1287 dma-names = "tx", 1288 "rx"; 1289 1290 status = "disabled"; 1291 }; 1292 }; 1293 1294 gpi_dma0: dma-controller@900000 { 1295 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1296 reg = <0 0x00900000 0 0x60000>; 1297 1298 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1311 1312 dma-channels = <13>; 1313 #dma-cells = <3>; 1314 1315 iommus = <&apps_smmu 0x576 0x0>; 1316 1317 status = "disabled"; 1318 }; 1319 1320 qup0: geniqup@9c0000 { 1321 compatible = "qcom,geni-se-qup"; 1322 reg = <0 0x009c0000 0 0x6000>; 1323 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1324 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1325 clock-names = "m-ahb", "s-ahb"; 1326 iommus = <&apps_smmu 0x563 0>; 1327 1328 #address-cells = <2>; 1329 #size-cells = <2>; 1330 ranges; 1331 1332 status = "disabled"; 1333 1334 i2c0: i2c@980000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00980000 0 0x4000>; 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1341 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1342 power-domains = <&rpmhpd SC8280XP_CX>; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1344 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1345 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1346 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1347 1348 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1349 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1350 dma-names = "tx", 1351 "rx"; 1352 1353 status = "disabled"; 1354 }; 1355 1356 spi0: spi@980000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00980000 0 0x4000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1362 clock-names = "se"; 1363 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1364 power-domains = <&rpmhpd SC8280XP_CX>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1367 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1368 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1369 1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1371 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 1375 status = "disabled"; 1376 }; 1377 1378 i2c1: i2c@984000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00984000 0 0x4000>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 clock-names = "se"; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1385 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1386 power-domains = <&rpmhpd SC8280XP_CX>; 1387 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1388 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1389 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1390 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1391 1392 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1393 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1394 dma-names = "tx", 1395 "rx"; 1396 1397 status = "disabled"; 1398 }; 1399 1400 spi1: spi@984000 { 1401 compatible = "qcom,geni-spi"; 1402 reg = <0 0x00984000 0 0x4000>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1406 clock-names = "se"; 1407 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1408 power-domains = <&rpmhpd SC8280XP_CX>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1410 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1411 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 1414 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1415 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1416 dma-names = "tx", 1417 "rx"; 1418 1419 status = "disabled"; 1420 }; 1421 1422 i2c2: i2c@988000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00988000 0 0x4000>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1429 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1430 power-domains = <&rpmhpd SC8280XP_CX>; 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1433 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1435 1436 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1437 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1438 dma-names = "tx", 1439 "rx"; 1440 1441 status = "disabled"; 1442 }; 1443 1444 spi2: spi@988000 { 1445 compatible = "qcom,geni-spi"; 1446 reg = <0 0x00988000 0 0x4000>; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1450 clock-names = "se"; 1451 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1452 power-domains = <&rpmhpd SC8280XP_CX>; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1455 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1456 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1457 1458 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1459 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1460 dma-names = "tx", 1461 "rx"; 1462 1463 status = "disabled"; 1464 }; 1465 1466 uart2: serial@988000 { 1467 compatible = "qcom,geni-uart"; 1468 reg = <0 0x00988000 0 0x4000>; 1469 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1470 clock-names = "se"; 1471 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1472 operating-points-v2 = <&qup_opp_table_100mhz>; 1473 power-domains = <&rpmhpd SC8280XP_CX>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1476 interconnect-names = "qup-core", "qup-config"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c3: i2c@98c000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x0098c000 0 0x4000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 clock-names = "se"; 1486 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1487 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1488 power-domains = <&rpmhpd SC8280XP_CX>; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1491 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1493 1494 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1495 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1496 dma-names = "tx", 1497 "rx"; 1498 1499 status = "disabled"; 1500 }; 1501 1502 spi3: spi@98c000 { 1503 compatible = "qcom,geni-spi"; 1504 reg = <0 0x0098c000 0 0x4000>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1508 clock-names = "se"; 1509 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC8280XP_CX>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1513 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1515 1516 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1517 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1518 dma-names = "tx", 1519 "rx"; 1520 1521 status = "disabled"; 1522 }; 1523 1524 i2c4: i2c@990000 { 1525 compatible = "qcom,geni-i2c"; 1526 reg = <0 0x00990000 0 0x4000>; 1527 clock-names = "se"; 1528 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1529 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 power-domains = <&rpmhpd SC8280XP_CX>; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1534 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1535 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1536 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1537 1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1539 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1540 dma-names = "tx", 1541 "rx"; 1542 1543 status = "disabled"; 1544 }; 1545 1546 spi4: spi@990000 { 1547 compatible = "qcom,geni-spi"; 1548 reg = <0 0x00990000 0 0x4000>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1552 clock-names = "se"; 1553 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SC8280XP_CX>; 1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1556 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1557 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1558 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1559 1560 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1561 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1562 dma-names = "tx", 1563 "rx"; 1564 1565 status = "disabled"; 1566 }; 1567 1568 i2c5: i2c@994000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00994000 0 0x4000>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 clock-names = "se"; 1574 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1575 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1576 power-domains = <&rpmhpd SC8280XP_CX>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1579 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1581 1582 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1583 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1584 dma-names = "tx", 1585 "rx"; 1586 1587 status = "disabled"; 1588 }; 1589 1590 spi5: spi@994000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00994000 0 0x4000>; 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1596 clock-names = "se"; 1597 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1598 power-domains = <&rpmhpd SC8280XP_CX>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1600 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1601 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1602 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1603 1604 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1605 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1606 dma-names = "tx", 1607 "rx"; 1608 1609 status = "disabled"; 1610 }; 1611 1612 i2c6: i2c@998000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0 0x00998000 0 0x4000>; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 clock-names = "se"; 1618 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1619 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC8280XP_CX>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1623 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1624 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1625 1626 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1627 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1628 dma-names = "tx", 1629 "rx"; 1630 1631 status = "disabled"; 1632 }; 1633 1634 spi6: spi@998000 { 1635 compatible = "qcom,geni-spi"; 1636 reg = <0 0x00998000 0 0x4000>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1640 clock-names = "se"; 1641 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1642 power-domains = <&rpmhpd SC8280XP_CX>; 1643 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1644 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1645 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1646 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1647 1648 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1649 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1650 dma-names = "tx", 1651 "rx"; 1652 1653 status = "disabled"; 1654 }; 1655 1656 i2c7: i2c@99c000 { 1657 compatible = "qcom,geni-i2c"; 1658 reg = <0 0x0099c000 0 0x4000>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 clock-names = "se"; 1662 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1663 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1664 power-domains = <&rpmhpd SC8280XP_CX>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1667 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1668 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1669 1670 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1671 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1672 dma-names = "tx", 1673 "rx"; 1674 1675 status = "disabled"; 1676 }; 1677 1678 spi7: spi@99c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x0099c000 0 0x4000>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1684 clock-names = "se"; 1685 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1686 power-domains = <&rpmhpd SC8280XP_CX>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1689 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1690 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1691 1692 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1693 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1694 dma-names = "tx", 1695 "rx"; 1696 1697 status = "disabled"; 1698 }; 1699 }; 1700 1701 gpi_dma1: dma-controller@a00000 { 1702 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1703 reg = <0 0x00a00000 0 0x60000>; 1704 1705 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1717 1718 dma-channels = <12>; 1719 #dma-cells = <3>; 1720 1721 iommus = <&apps_smmu 0x96 0x0>; 1722 1723 status = "disabled"; 1724 }; 1725 1726 qup1: geniqup@ac0000 { 1727 compatible = "qcom,geni-se-qup"; 1728 reg = <0 0x00ac0000 0 0x6000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1730 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1731 clock-names = "m-ahb", "s-ahb"; 1732 iommus = <&apps_smmu 0x83 0>; 1733 1734 #address-cells = <2>; 1735 #size-cells = <2>; 1736 ranges; 1737 1738 status = "disabled"; 1739 1740 i2c8: i2c@a80000 { 1741 compatible = "qcom,geni-i2c"; 1742 reg = <0 0x00a80000 0 0x4000>; 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1746 clock-names = "se"; 1747 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1748 power-domains = <&rpmhpd SC8280XP_CX>; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1750 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1751 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1752 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1753 1754 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1755 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1756 dma-names = "tx", 1757 "rx"; 1758 1759 status = "disabled"; 1760 }; 1761 1762 spi8: spi@a80000 { 1763 compatible = "qcom,geni-spi"; 1764 reg = <0 0x00a80000 0 0x4000>; 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1768 clock-names = "se"; 1769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1770 power-domains = <&rpmhpd SC8280XP_CX>; 1771 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1772 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1773 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1774 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1775 1776 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1777 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1778 dma-names = "tx", 1779 "rx"; 1780 1781 status = "disabled"; 1782 }; 1783 1784 i2c9: i2c@a84000 { 1785 compatible = "qcom,geni-i2c"; 1786 reg = <0 0x00a84000 0 0x4000>; 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1790 clock-names = "se"; 1791 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1792 power-domains = <&rpmhpd SC8280XP_CX>; 1793 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1795 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1796 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1797 1798 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1800 dma-names = "tx", 1801 "rx"; 1802 1803 status = "disabled"; 1804 }; 1805 1806 spi9: spi@a84000 { 1807 compatible = "qcom,geni-spi"; 1808 reg = <0 0x00a84000 0 0x4000>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1812 clock-names = "se"; 1813 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1814 power-domains = <&rpmhpd SC8280XP_CX>; 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1816 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1817 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1818 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1819 1820 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1821 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1822 dma-names = "tx", 1823 "rx"; 1824 1825 status = "disabled"; 1826 }; 1827 1828 i2c10: i2c@a88000 { 1829 compatible = "qcom,geni-i2c"; 1830 reg = <0 0x00a88000 0 0x4000>; 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1834 clock-names = "se"; 1835 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1836 power-domains = <&rpmhpd SC8280XP_CX>; 1837 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1839 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1840 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1841 1842 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1843 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1844 dma-names = "tx", 1845 "rx"; 1846 1847 status = "disabled"; 1848 }; 1849 1850 spi10: spi@a88000 { 1851 compatible = "qcom,geni-spi"; 1852 reg = <0 0x00a88000 0 0x4000>; 1853 #address-cells = <1>; 1854 #size-cells = <0>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1856 clock-names = "se"; 1857 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1858 power-domains = <&rpmhpd SC8280XP_CX>; 1859 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1860 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1861 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1862 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1863 1864 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1865 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1866 dma-names = "tx", 1867 "rx"; 1868 1869 status = "disabled"; 1870 }; 1871 1872 i2c11: i2c@a8c000 { 1873 compatible = "qcom,geni-i2c"; 1874 reg = <0 0x00a8c000 0 0x4000>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1878 clock-names = "se"; 1879 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1880 power-domains = <&rpmhpd SC8280XP_CX>; 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1882 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1883 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1884 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1885 1886 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1887 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1888 dma-names = "tx", 1889 "rx"; 1890 1891 status = "disabled"; 1892 }; 1893 1894 spi11: spi@a8c000 { 1895 compatible = "qcom,geni-spi"; 1896 reg = <0 0x00a8c000 0 0x4000>; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1900 clock-names = "se"; 1901 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1902 power-domains = <&rpmhpd SC8280XP_CX>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1905 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1906 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1907 1908 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1909 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1910 dma-names = "tx", 1911 "rx"; 1912 1913 status = "disabled"; 1914 }; 1915 1916 i2c12: i2c@a90000 { 1917 compatible = "qcom,geni-i2c"; 1918 reg = <0 0x00a90000 0 0x4000>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1922 clock-names = "se"; 1923 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1924 power-domains = <&rpmhpd SC8280XP_CX>; 1925 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1927 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1928 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1929 1930 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1931 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1932 dma-names = "tx", 1933 "rx"; 1934 1935 status = "disabled"; 1936 }; 1937 1938 spi12: spi@a90000 { 1939 compatible = "qcom,geni-spi"; 1940 reg = <0 0x00a90000 0 0x4000>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1944 clock-names = "se"; 1945 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1946 power-domains = <&rpmhpd SC8280XP_CX>; 1947 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1949 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1951 1952 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1953 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1954 dma-names = "tx", 1955 "rx"; 1956 1957 status = "disabled"; 1958 }; 1959 1960 i2c13: i2c@a94000 { 1961 compatible = "qcom,geni-i2c"; 1962 reg = <0 0x00a94000 0 0x4000>; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1966 clock-names = "se"; 1967 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1968 power-domains = <&rpmhpd SC8280XP_CX>; 1969 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1970 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1971 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1973 1974 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1975 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1976 dma-names = "tx", 1977 "rx"; 1978 1979 status = "disabled"; 1980 }; 1981 1982 spi13: spi@a94000 { 1983 compatible = "qcom,geni-spi"; 1984 reg = <0 0x00a94000 0 0x4000>; 1985 #address-cells = <1>; 1986 #size-cells = <0>; 1987 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1988 clock-names = "se"; 1989 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1990 power-domains = <&rpmhpd SC8280XP_CX>; 1991 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1993 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1994 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1995 1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1997 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1998 dma-names = "tx", 1999 "rx"; 2000 2001 status = "disabled"; 2002 }; 2003 2004 i2c14: i2c@a98000 { 2005 compatible = "qcom,geni-i2c"; 2006 reg = <0 0x00a98000 0 0x4000>; 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2010 clock-names = "se"; 2011 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2012 power-domains = <&rpmhpd SC8280XP_CX>; 2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2015 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2017 2018 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2019 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2020 dma-names = "tx", 2021 "rx"; 2022 2023 status = "disabled"; 2024 }; 2025 2026 spi14: spi@a98000 { 2027 compatible = "qcom,geni-spi"; 2028 reg = <0 0x00a98000 0 0x4000>; 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2032 clock-names = "se"; 2033 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2034 power-domains = <&rpmhpd SC8280XP_CX>; 2035 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2037 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2039 2040 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2041 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2042 dma-names = "tx", 2043 "rx"; 2044 2045 status = "disabled"; 2046 }; 2047 2048 i2c15: i2c@a9c000 { 2049 compatible = "qcom,geni-i2c"; 2050 reg = <0 0x00a9c000 0 0x4000>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2054 clock-names = "se"; 2055 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2056 power-domains = <&rpmhpd SC8280XP_CX>; 2057 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2058 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2059 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2060 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2061 2062 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2063 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2064 dma-names = "tx", 2065 "rx"; 2066 2067 status = "disabled"; 2068 }; 2069 2070 spi15: spi@a9c000 { 2071 compatible = "qcom,geni-spi"; 2072 reg = <0 0x00a9c000 0 0x4000>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2076 clock-names = "se"; 2077 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2078 power-domains = <&rpmhpd SC8280XP_CX>; 2079 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2081 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2082 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2083 2084 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2085 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2086 dma-names = "tx", 2087 "rx"; 2088 2089 status = "disabled"; 2090 }; 2091 }; 2092 2093 rng: rng@10d3000 { 2094 compatible = "qcom,prng-ee"; 2095 reg = <0 0x010d3000 0 0x1000>; 2096 clocks = <&rpmhcc RPMH_HWKM_CLK>; 2097 clock-names = "core"; 2098 }; 2099 2100 config_noc: interconnect@1500000 { 2101 compatible = "qcom,sc8280xp-config-noc"; 2102 reg = <0 0x01500000 0 0x2c000>; 2103 2104 #interconnect-cells = <2>; 2105 qcom,bcm-voters = <&apps_bcm_voter>; 2106 }; 2107 2108 system_noc: interconnect@1680000 { 2109 compatible = "qcom,sc8280xp-system-noc"; 2110 reg = <0 0x01680000 0 0x1a400>; 2111 2112 #interconnect-cells = <2>; 2113 qcom,bcm-voters = <&apps_bcm_voter>; 2114 }; 2115 2116 aggre1_noc: interconnect@16c0000 { 2117 compatible = "qcom,sc8280xp-aggre1-noc"; 2118 reg = <0 0x016c0000 0 0x3af80>; 2119 2120 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2121 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2122 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2123 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2124 <&gcc GCC_AGGRE_USB4_AXI_CLK>, 2125 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, 2126 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 2127 <&rpmhcc RPMH_IPA_CLK>; 2128 2129 #interconnect-cells = <2>; 2130 qcom,bcm-voters = <&apps_bcm_voter>; 2131 }; 2132 2133 aggre2_noc: interconnect@1700000 { 2134 compatible = "qcom,sc8280xp-aggre2-noc"; 2135 reg = <0 0x01700000 0 0x3af80>; 2136 2137 clocks = <&gcc GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK>, 2138 <&gcc GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK>, 2139 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2140 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2141 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2142 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2143 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2144 2145 #interconnect-cells = <2>; 2146 qcom,bcm-voters = <&apps_bcm_voter>; 2147 }; 2148 2149 mmss_noc: interconnect@1740000 { 2150 compatible = "qcom,sc8280xp-mmss-noc"; 2151 reg = <0 0x01740000 0 0x1fa80>; 2152 2153 #interconnect-cells = <2>; 2154 qcom,bcm-voters = <&apps_bcm_voter>; 2155 }; 2156 2157 pcie4: pcie@1c00000 { 2158 device_type = "pci"; 2159 compatible = "qcom,pcie-sc8280xp"; 2160 reg = <0x0 0x01c00000 0x0 0x3000>, 2161 <0x0 0x30000000 0x0 0xf1d>, 2162 <0x0 0x30000f20 0x0 0xa8>, 2163 <0x0 0x30001000 0x0 0x1000>, 2164 <0x0 0x30100000 0x0 0x100000>, 2165 <0x0 0x01c03000 0x0 0x1000>; 2166 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2167 #address-cells = <3>; 2168 #size-cells = <2>; 2169 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 2170 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 2171 bus-range = <0x00 0xff>; 2172 2173 dma-coherent; 2174 2175 linux,pci-domain = <6>; 2176 num-lanes = <1>; 2177 2178 msi-map = <0x0 &its 0xe0000 0x10000>; 2179 2180 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2184 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2185 2186 #interrupt-cells = <1>; 2187 interrupt-map-mask = <0 0 0 0x7>; 2188 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2189 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2190 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2191 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2192 2193 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2194 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2195 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2196 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2197 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2198 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2199 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2200 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2201 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 2202 clock-names = "aux", 2203 "cfg", 2204 "bus_master", 2205 "bus_slave", 2206 "slave_q2a", 2207 "ddrss_sf_tbu", 2208 "noc_aggr_4", 2209 "noc_aggr_south_sf", 2210 "cnoc_qx"; 2211 2212 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2213 assigned-clock-rates = <19200000>; 2214 2215 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 2216 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 2217 interconnect-names = "pcie-mem", "cpu-pcie"; 2218 2219 resets = <&gcc GCC_PCIE_4_BCR>; 2220 reset-names = "pci"; 2221 2222 power-domains = <&gcc PCIE_4_GDSC>; 2223 required-opps = <&rpmhpd_opp_nom>; 2224 2225 status = "disabled"; 2226 2227 pcie4_port0: pcie@0 { 2228 device_type = "pci"; 2229 reg = <0x0 0x0 0x0 0x0 0x0>; 2230 bus-range = <0x01 0xff>; 2231 2232 phys = <&pcie4_phy>; 2233 2234 #address-cells = <3>; 2235 #size-cells = <2>; 2236 ranges; 2237 }; 2238 }; 2239 2240 pcie4_phy: phy@1c06000 { 2241 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 2242 reg = <0x0 0x01c06000 0x0 0x2000>; 2243 2244 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2245 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2246 <&gcc GCC_PCIE_4_CLKREF_CLK>, 2247 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 2248 <&gcc GCC_PCIE_4_PIPE_CLK>, 2249 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 2250 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2251 "pipe", "pipediv2"; 2252 2253 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 2254 assigned-clock-rates = <100000000>; 2255 2256 power-domains = <&gcc PCIE_4_GDSC>; 2257 2258 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2259 reset-names = "phy"; 2260 2261 #clock-cells = <0>; 2262 clock-output-names = "pcie_4_pipe_clk"; 2263 2264 #phy-cells = <0>; 2265 2266 status = "disabled"; 2267 }; 2268 2269 pcie3b: pcie@1c08000 { 2270 device_type = "pci"; 2271 compatible = "qcom,pcie-sc8280xp"; 2272 reg = <0x0 0x01c08000 0x0 0x3000>, 2273 <0x0 0x32000000 0x0 0xf1d>, 2274 <0x0 0x32000f20 0x0 0xa8>, 2275 <0x0 0x32001000 0x0 0x1000>, 2276 <0x0 0x32100000 0x0 0x100000>, 2277 <0x0 0x01c0b000 0x0 0x1000>; 2278 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2279 #address-cells = <3>; 2280 #size-cells = <2>; 2281 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 2282 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 2283 bus-range = <0x00 0xff>; 2284 2285 dma-coherent; 2286 2287 linux,pci-domain = <5>; 2288 num-lanes = <2>; 2289 2290 msi-map = <0x0 &its 0xd0000 0x10000>; 2291 2292 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2296 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2297 2298 #interrupt-cells = <1>; 2299 interrupt-map-mask = <0 0 0 0x7>; 2300 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 2301 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2302 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 2303 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 2304 2305 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2306 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2307 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 2308 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 2309 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 2310 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2311 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2312 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2313 clock-names = "aux", 2314 "cfg", 2315 "bus_master", 2316 "bus_slave", 2317 "slave_q2a", 2318 "ddrss_sf_tbu", 2319 "noc_aggr_4", 2320 "noc_aggr_south_sf"; 2321 2322 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 2323 assigned-clock-rates = <19200000>; 2324 2325 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 2326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 2327 interconnect-names = "pcie-mem", "cpu-pcie"; 2328 2329 resets = <&gcc GCC_PCIE_3B_BCR>; 2330 reset-names = "pci"; 2331 2332 power-domains = <&gcc PCIE_3B_GDSC>; 2333 required-opps = <&rpmhpd_opp_nom>; 2334 2335 status = "disabled"; 2336 2337 pcie3b_port0: pcie@0 { 2338 device_type = "pci"; 2339 reg = <0x0 0x0 0x0 0x0 0x0>; 2340 bus-range = <0x01 0xff>; 2341 2342 phys = <&pcie3b_phy>; 2343 2344 #address-cells = <3>; 2345 #size-cells = <2>; 2346 ranges; 2347 }; 2348 }; 2349 2350 pcie3b_phy: phy@1c0e000 { 2351 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2352 reg = <0x0 0x01c0e000 0x0 0x2000>; 2353 2354 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2355 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2356 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2357 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 2358 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2359 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 2360 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2361 "pipe", "pipediv2"; 2362 2363 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 2364 assigned-clock-rates = <100000000>; 2365 2366 power-domains = <&gcc PCIE_3B_GDSC>; 2367 2368 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 2369 reset-names = "phy"; 2370 2371 #clock-cells = <0>; 2372 clock-output-names = "pcie_3b_pipe_clk"; 2373 2374 #phy-cells = <0>; 2375 2376 status = "disabled"; 2377 }; 2378 2379 pcie3a: pcie@1c10000 { 2380 device_type = "pci"; 2381 compatible = "qcom,pcie-sc8280xp"; 2382 reg = <0x0 0x01c10000 0x0 0x3000>, 2383 <0x0 0x34000000 0x0 0xf1d>, 2384 <0x0 0x34000f20 0x0 0xa8>, 2385 <0x0 0x34001000 0x0 0x1000>, 2386 <0x0 0x34100000 0x0 0x100000>, 2387 <0x0 0x01c13000 0x0 0x1000>; 2388 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2389 #address-cells = <3>; 2390 #size-cells = <2>; 2391 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2392 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2393 bus-range = <0x00 0xff>; 2394 2395 dma-coherent; 2396 2397 linux,pci-domain = <4>; 2398 num-lanes = <4>; 2399 2400 msi-map = <0x0 &its 0xc0000 0x10000>; 2401 2402 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2406 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2407 2408 #interrupt-cells = <1>; 2409 interrupt-map-mask = <0 0 0 0x7>; 2410 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2411 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2412 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2413 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2414 2415 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2416 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2417 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2418 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2419 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2420 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2421 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2422 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2423 clock-names = "aux", 2424 "cfg", 2425 "bus_master", 2426 "bus_slave", 2427 "slave_q2a", 2428 "ddrss_sf_tbu", 2429 "noc_aggr_4", 2430 "noc_aggr_south_sf"; 2431 2432 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2433 assigned-clock-rates = <19200000>; 2434 2435 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2436 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2437 interconnect-names = "pcie-mem", "cpu-pcie"; 2438 2439 resets = <&gcc GCC_PCIE_3A_BCR>; 2440 reset-names = "pci"; 2441 2442 power-domains = <&gcc PCIE_3A_GDSC>; 2443 required-opps = <&rpmhpd_opp_nom>; 2444 2445 status = "disabled"; 2446 2447 pcie3a_port0: pcie@0 { 2448 device_type = "pci"; 2449 reg = <0x0 0x0 0x0 0x0 0x0>; 2450 bus-range = <0x01 0xff>; 2451 2452 phys = <&pcie3a_phy>; 2453 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 ranges; 2457 }; 2458 }; 2459 2460 pcie3a_phy: phy@1c14000 { 2461 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2462 reg = <0x0 0x01c14000 0x0 0x2000>, 2463 <0x0 0x01c16000 0x0 0x2000>; 2464 2465 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2466 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2467 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2468 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2469 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2470 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2471 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2472 "pipe", "pipediv2"; 2473 2474 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2475 assigned-clock-rates = <100000000>; 2476 2477 power-domains = <&gcc PCIE_3A_GDSC>; 2478 2479 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2480 reset-names = "phy"; 2481 2482 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2483 2484 #clock-cells = <0>; 2485 clock-output-names = "pcie_3a_pipe_clk"; 2486 2487 #phy-cells = <0>; 2488 2489 status = "disabled"; 2490 }; 2491 2492 pcie2b: pcie@1c18000 { 2493 device_type = "pci"; 2494 compatible = "qcom,pcie-sc8280xp"; 2495 reg = <0x0 0x01c18000 0x0 0x3000>, 2496 <0x0 0x38000000 0x0 0xf1d>, 2497 <0x0 0x38000f20 0x0 0xa8>, 2498 <0x0 0x38001000 0x0 0x1000>, 2499 <0x0 0x38100000 0x0 0x100000>, 2500 <0x0 0x01c1b000 0x0 0x1000>; 2501 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2502 #address-cells = <3>; 2503 #size-cells = <2>; 2504 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2505 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2506 bus-range = <0x00 0xff>; 2507 2508 dma-coherent; 2509 2510 linux,pci-domain = <3>; 2511 num-lanes = <2>; 2512 2513 msi-map = <0x0 &its 0xb0000 0x10000>; 2514 2515 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2519 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2520 2521 #interrupt-cells = <1>; 2522 interrupt-map-mask = <0 0 0 0x7>; 2523 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2524 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2525 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2526 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2527 2528 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2529 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2530 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2531 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2532 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2533 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2534 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2535 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2536 clock-names = "aux", 2537 "cfg", 2538 "bus_master", 2539 "bus_slave", 2540 "slave_q2a", 2541 "ddrss_sf_tbu", 2542 "noc_aggr_4", 2543 "noc_aggr_south_sf"; 2544 2545 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2546 assigned-clock-rates = <19200000>; 2547 2548 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2549 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2550 interconnect-names = "pcie-mem", "cpu-pcie"; 2551 2552 resets = <&gcc GCC_PCIE_2B_BCR>; 2553 reset-names = "pci"; 2554 2555 power-domains = <&gcc PCIE_2B_GDSC>; 2556 required-opps = <&rpmhpd_opp_nom>; 2557 2558 status = "disabled"; 2559 2560 pcie2b_port0: pcie@0 { 2561 device_type = "pci"; 2562 reg = <0x0 0x0 0x0 0x0 0x0>; 2563 bus-range = <0x01 0xff>; 2564 2565 phys = <&pcie2b_phy>; 2566 2567 #address-cells = <3>; 2568 #size-cells = <2>; 2569 ranges; 2570 }; 2571 }; 2572 2573 pcie2b_phy: phy@1c1e000 { 2574 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2575 reg = <0x0 0x01c1e000 0x0 0x2000>; 2576 2577 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2578 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2579 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2580 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2581 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2582 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2583 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2584 "pipe", "pipediv2"; 2585 2586 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2587 assigned-clock-rates = <100000000>; 2588 2589 power-domains = <&gcc PCIE_2B_GDSC>; 2590 2591 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2592 reset-names = "phy"; 2593 2594 #clock-cells = <0>; 2595 clock-output-names = "pcie_2b_pipe_clk"; 2596 2597 #phy-cells = <0>; 2598 2599 status = "disabled"; 2600 }; 2601 2602 pcie2a: pcie@1c20000 { 2603 device_type = "pci"; 2604 compatible = "qcom,pcie-sc8280xp"; 2605 reg = <0x0 0x01c20000 0x0 0x3000>, 2606 <0x0 0x3c000000 0x0 0xf1d>, 2607 <0x0 0x3c000f20 0x0 0xa8>, 2608 <0x0 0x3c001000 0x0 0x1000>, 2609 <0x0 0x3c100000 0x0 0x100000>, 2610 <0x0 0x01c23000 0x0 0x1000>; 2611 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2612 #address-cells = <3>; 2613 #size-cells = <2>; 2614 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2615 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2616 bus-range = <0x00 0xff>; 2617 2618 dma-coherent; 2619 2620 linux,pci-domain = <2>; 2621 num-lanes = <4>; 2622 2623 msi-map = <0x0 &its 0xa0000 0x10000>; 2624 2625 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2629 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2630 2631 #interrupt-cells = <1>; 2632 interrupt-map-mask = <0 0 0 0x7>; 2633 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2634 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2635 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2636 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2637 2638 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2639 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2640 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2641 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2642 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2643 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2644 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2645 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2646 clock-names = "aux", 2647 "cfg", 2648 "bus_master", 2649 "bus_slave", 2650 "slave_q2a", 2651 "ddrss_sf_tbu", 2652 "noc_aggr_4", 2653 "noc_aggr_south_sf"; 2654 2655 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2656 assigned-clock-rates = <19200000>; 2657 2658 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2659 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2660 interconnect-names = "pcie-mem", "cpu-pcie"; 2661 2662 resets = <&gcc GCC_PCIE_2A_BCR>; 2663 reset-names = "pci"; 2664 2665 power-domains = <&gcc PCIE_2A_GDSC>; 2666 required-opps = <&rpmhpd_opp_nom>; 2667 2668 status = "disabled"; 2669 2670 pcie2a_port0: pcie@0 { 2671 device_type = "pci"; 2672 reg = <0x0 0x0 0x0 0x0 0x0>; 2673 bus-range = <0x01 0xff>; 2674 2675 phys = <&pcie2a_phy>; 2676 2677 #address-cells = <3>; 2678 #size-cells = <2>; 2679 ranges; 2680 }; 2681 }; 2682 2683 pcie2a_phy: phy@1c24000 { 2684 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2685 reg = <0x0 0x01c24000 0x0 0x2000>, 2686 <0x0 0x01c26000 0x0 0x2000>; 2687 2688 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2689 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2690 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2691 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2692 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2693 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2694 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2695 "pipe", "pipediv2"; 2696 2697 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2698 assigned-clock-rates = <100000000>; 2699 2700 power-domains = <&gcc PCIE_2A_GDSC>; 2701 2702 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2703 reset-names = "phy"; 2704 2705 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2706 2707 #clock-cells = <0>; 2708 clock-output-names = "pcie_2a_pipe_clk"; 2709 2710 #phy-cells = <0>; 2711 2712 status = "disabled"; 2713 }; 2714 2715 ufs_mem_hc: ufshc@1d84000 { 2716 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2717 "jedec,ufs-2.0"; 2718 reg = <0 0x01d84000 0 0x3000>; 2719 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2720 phys = <&ufs_mem_phy>; 2721 phy-names = "ufsphy"; 2722 lanes-per-direction = <2>; 2723 #reset-cells = <1>; 2724 resets = <&gcc GCC_UFS_PHY_BCR>; 2725 reset-names = "rst"; 2726 2727 power-domains = <&gcc UFS_PHY_GDSC>; 2728 required-opps = <&rpmhpd_opp_nom>; 2729 2730 iommus = <&apps_smmu 0xe0 0x0>; 2731 dma-coherent; 2732 2733 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2734 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2735 <&gcc GCC_UFS_PHY_AHB_CLK>, 2736 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2737 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2738 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2739 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2740 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2741 clock-names = "core_clk", 2742 "bus_aggr_clk", 2743 "iface_clk", 2744 "core_clk_unipro", 2745 "ref_clk", 2746 "tx_lane0_sync_clk", 2747 "rx_lane0_sync_clk", 2748 "rx_lane1_sync_clk"; 2749 freq-table-hz = <75000000 300000000>, 2750 <0 0>, 2751 <0 0>, 2752 <75000000 300000000>, 2753 <0 0>, 2754 <0 0>, 2755 <0 0>, 2756 <0 0>; 2757 status = "disabled"; 2758 }; 2759 2760 ufs_mem_phy: phy@1d87000 { 2761 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2762 reg = <0 0x01d87000 0 0x1000>; 2763 2764 clocks = <&rpmhcc RPMH_CXO_CLK>, 2765 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2766 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2767 clock-names = "ref", 2768 "ref_aux", 2769 "qref"; 2770 2771 power-domains = <&gcc UFS_PHY_GDSC>; 2772 2773 resets = <&ufs_mem_hc 0>; 2774 reset-names = "ufsphy"; 2775 2776 #phy-cells = <0>; 2777 2778 status = "disabled"; 2779 }; 2780 2781 ufs_card_hc: ufshc@1da4000 { 2782 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2783 "jedec,ufs-2.0"; 2784 reg = <0 0x01da4000 0 0x3000>; 2785 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2786 phys = <&ufs_card_phy>; 2787 phy-names = "ufsphy"; 2788 lanes-per-direction = <2>; 2789 #reset-cells = <1>; 2790 resets = <&gcc GCC_UFS_CARD_BCR>; 2791 reset-names = "rst"; 2792 2793 power-domains = <&gcc UFS_CARD_GDSC>; 2794 2795 iommus = <&apps_smmu 0x4a0 0x0>; 2796 dma-coherent; 2797 2798 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2799 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2800 <&gcc GCC_UFS_CARD_AHB_CLK>, 2801 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2802 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2803 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2804 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2805 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2806 clock-names = "core_clk", 2807 "bus_aggr_clk", 2808 "iface_clk", 2809 "core_clk_unipro", 2810 "ref_clk", 2811 "tx_lane0_sync_clk", 2812 "rx_lane0_sync_clk", 2813 "rx_lane1_sync_clk"; 2814 freq-table-hz = <75000000 300000000>, 2815 <0 0>, 2816 <0 0>, 2817 <75000000 300000000>, 2818 <0 0>, 2819 <0 0>, 2820 <0 0>, 2821 <0 0>; 2822 status = "disabled"; 2823 }; 2824 2825 ufs_card_phy: phy@1da7000 { 2826 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2827 reg = <0 0x01da7000 0 0x1000>; 2828 2829 clocks = <&rpmhcc RPMH_CXO_CLK>, 2830 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2831 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2832 clock-names = "ref", 2833 "ref_aux", 2834 "qref"; 2835 2836 power-domains = <&gcc UFS_CARD_GDSC>; 2837 2838 resets = <&ufs_card_hc 0>; 2839 reset-names = "ufsphy"; 2840 2841 #phy-cells = <0>; 2842 2843 status = "disabled"; 2844 }; 2845 2846 tcsr_mutex: hwlock@1f40000 { 2847 compatible = "qcom,tcsr-mutex"; 2848 reg = <0x0 0x01f40000 0x0 0x20000>; 2849 #hwlock-cells = <1>; 2850 }; 2851 2852 tcsr: syscon@1fc0000 { 2853 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2854 reg = <0x0 0x01fc0000 0x0 0x30000>; 2855 }; 2856 2857 remoteproc_slpi: remoteproc@2400000 { 2858 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2859 reg = <0 0x02400000 0 0x10000>; 2860 2861 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2862 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2863 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2864 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2865 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2866 interrupt-names = "wdog", 2867 "fatal", 2868 "ready", 2869 "handover", 2870 "stop-ack"; 2871 2872 clocks = <&rpmhcc RPMH_CXO_CLK>; 2873 clock-names = "xo"; 2874 2875 power-domains = <&rpmhpd SC8280XP_LCX>, 2876 <&rpmhpd SC8280XP_LMX>; 2877 power-domain-names = "lcx", "lmx"; 2878 2879 memory-region = <&pil_slpi_mem>; 2880 2881 qcom,qmp = <&aoss_qmp>; 2882 2883 qcom,smem-states = <&smp2p_slpi_out 0>; 2884 qcom,smem-state-names = "stop"; 2885 2886 status = "disabled"; 2887 2888 glink-edge { 2889 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2890 IPCC_MPROC_SIGNAL_GLINK_QMP 2891 IRQ_TYPE_EDGE_RISING>; 2892 mboxes = <&ipcc IPCC_CLIENT_SLPI 2893 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2894 2895 label = "slpi"; 2896 qcom,remote-pid = <3>; 2897 2898 fastrpc { 2899 compatible = "qcom,fastrpc"; 2900 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2901 label = "sdsp"; 2902 qcom,non-secure-domain; 2903 #address-cells = <1>; 2904 #size-cells = <0>; 2905 2906 compute-cb@1 { 2907 compatible = "qcom,fastrpc-compute-cb"; 2908 reg = <1>; 2909 iommus = <&apps_smmu 0x0521 0x0>; 2910 dma-coherent; 2911 }; 2912 2913 compute-cb@2 { 2914 compatible = "qcom,fastrpc-compute-cb"; 2915 reg = <2>; 2916 iommus = <&apps_smmu 0x0522 0x0>; 2917 dma-coherent; 2918 }; 2919 2920 compute-cb@3 { 2921 compatible = "qcom,fastrpc-compute-cb"; 2922 reg = <3>; 2923 iommus = <&apps_smmu 0x0523 0x0>; 2924 dma-coherent; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 remoteproc_adsp: remoteproc@3000000 { 2931 compatible = "qcom,sc8280xp-adsp-pas"; 2932 reg = <0 0x03000000 0 0x10000>; 2933 2934 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2935 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2936 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2937 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2938 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2939 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2940 interrupt-names = "wdog", "fatal", "ready", 2941 "handover", "stop-ack", "shutdown-ack"; 2942 2943 clocks = <&rpmhcc RPMH_CXO_CLK>; 2944 clock-names = "xo"; 2945 2946 power-domains = <&rpmhpd SC8280XP_LCX>, 2947 <&rpmhpd SC8280XP_LMX>; 2948 power-domain-names = "lcx", "lmx"; 2949 2950 memory-region = <&pil_adsp_mem>; 2951 2952 qcom,qmp = <&aoss_qmp>; 2953 2954 qcom,smem-states = <&smp2p_adsp_out 0>; 2955 qcom,smem-state-names = "stop"; 2956 2957 status = "disabled"; 2958 2959 glink-edge { 2960 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2961 IPCC_MPROC_SIGNAL_GLINK_QMP 2962 IRQ_TYPE_EDGE_RISING>; 2963 mboxes = <&ipcc IPCC_CLIENT_LPASS 2964 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2965 2966 label = "lpass"; 2967 qcom,remote-pid = <2>; 2968 2969 fastrpc { 2970 compatible = "qcom,fastrpc"; 2971 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2972 label = "adsp"; 2973 qcom,non-secure-domain; 2974 #address-cells = <1>; 2975 #size-cells = <0>; 2976 2977 compute-cb@3 { 2978 compatible = "qcom,fastrpc-compute-cb"; 2979 reg = <3>; 2980 iommus = <&apps_smmu 0x0c03 0x0>; 2981 dma-coherent; 2982 }; 2983 2984 compute-cb@4 { 2985 compatible = "qcom,fastrpc-compute-cb"; 2986 reg = <4>; 2987 iommus = <&apps_smmu 0x0c04 0x0>; 2988 dma-coherent; 2989 }; 2990 2991 compute-cb@5 { 2992 compatible = "qcom,fastrpc-compute-cb"; 2993 reg = <5>; 2994 iommus = <&apps_smmu 0x0c05 0x0>; 2995 dma-coherent; 2996 }; 2997 }; 2998 2999 gpr { 3000 compatible = "qcom,gpr"; 3001 qcom,glink-channels = "adsp_apps"; 3002 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3003 qcom,intents = <512 20>; 3004 #address-cells = <1>; 3005 #size-cells = <0>; 3006 3007 q6apm: service@1 { 3008 compatible = "qcom,q6apm"; 3009 reg = <GPR_APM_MODULE_IID>; 3010 #sound-dai-cells = <0>; 3011 qcom,protection-domain = "avs/audio", 3012 "msm/adsp/audio_pd"; 3013 q6apmdai: dais { 3014 compatible = "qcom,q6apm-dais"; 3015 iommus = <&apps_smmu 0x0c01 0x0>; 3016 }; 3017 3018 q6apmbedai: bedais { 3019 compatible = "qcom,q6apm-lpass-dais"; 3020 #sound-dai-cells = <1>; 3021 }; 3022 }; 3023 3024 q6prm: service@2 { 3025 compatible = "qcom,q6prm"; 3026 reg = <GPR_PRM_MODULE_IID>; 3027 qcom,protection-domain = "avs/audio", 3028 "msm/adsp/audio_pd"; 3029 q6prmcc: clock-controller { 3030 compatible = "qcom,q6prm-lpass-clocks"; 3031 #clock-cells = <2>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 rxmacro: rxmacro@3200000 { 3039 compatible = "qcom,sc8280xp-lpass-rx-macro"; 3040 reg = <0 0x03200000 0 0x1000>; 3041 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3042 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3043 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3044 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3045 <&vamacro>; 3046 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3047 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3048 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3049 assigned-clock-rates = <19200000>, <19200000>; 3050 3051 clock-output-names = "mclk"; 3052 #clock-cells = <0>; 3053 #sound-dai-cells = <1>; 3054 3055 pinctrl-names = "default"; 3056 pinctrl-0 = <&rx_swr_default>; 3057 3058 status = "disabled"; 3059 }; 3060 3061 swr1: soundwire@3210000 { 3062 compatible = "qcom,soundwire-v1.6.0"; 3063 reg = <0 0x03210000 0 0x2000>; 3064 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3065 clocks = <&rxmacro>; 3066 clock-names = "iface"; 3067 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3068 reset-names = "swr_audio_cgcr"; 3069 label = "RX"; 3070 3071 qcom,din-ports = <0>; 3072 qcom,dout-ports = <5>; 3073 3074 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 3075 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 3076 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 3077 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 3078 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 3079 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 3080 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 3081 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 3082 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3083 3084 #sound-dai-cells = <1>; 3085 #address-cells = <2>; 3086 #size-cells = <0>; 3087 3088 status = "disabled"; 3089 }; 3090 3091 txmacro: txmacro@3220000 { 3092 compatible = "qcom,sc8280xp-lpass-tx-macro"; 3093 reg = <0 0x03220000 0 0x1000>; 3094 pinctrl-names = "default"; 3095 pinctrl-0 = <&tx_swr_default>; 3096 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3097 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3098 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3099 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3100 <&vamacro>; 3101 3102 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3103 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3104 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3105 assigned-clock-rates = <19200000>, <19200000>; 3106 clock-output-names = "mclk"; 3107 3108 #clock-cells = <0>; 3109 #sound-dai-cells = <1>; 3110 3111 status = "disabled"; 3112 }; 3113 3114 wsamacro: codec@3240000 { 3115 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 3116 reg = <0 0x03240000 0 0x1000>; 3117 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3118 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3119 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3120 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3121 <&vamacro>; 3122 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3123 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3124 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3125 assigned-clock-rates = <19200000>, <19200000>; 3126 3127 #clock-cells = <0>; 3128 clock-output-names = "mclk"; 3129 #sound-dai-cells = <1>; 3130 3131 pinctrl-names = "default"; 3132 pinctrl-0 = <&wsa_swr_default>; 3133 3134 status = "disabled"; 3135 }; 3136 3137 swr0: soundwire@3250000 { 3138 reg = <0 0x03250000 0 0x2000>; 3139 compatible = "qcom,soundwire-v1.6.0"; 3140 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3141 clocks = <&wsamacro>; 3142 clock-names = "iface"; 3143 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3144 reset-names = "swr_audio_cgcr"; 3145 label = "WSA"; 3146 3147 qcom,din-ports = <2>; 3148 qcom,dout-ports = <6>; 3149 3150 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3151 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3152 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3153 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3154 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3155 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3156 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3157 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3158 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3159 3160 #sound-dai-cells = <1>; 3161 #address-cells = <2>; 3162 #size-cells = <0>; 3163 3164 status = "disabled"; 3165 }; 3166 3167 lpass_audiocc: clock-controller@32a9000 { 3168 compatible = "qcom,sc8280xp-lpassaudiocc"; 3169 reg = <0 0x032a9000 0 0x1000>; 3170 #clock-cells = <1>; 3171 #reset-cells = <1>; 3172 }; 3173 3174 swr2: soundwire@3330000 { 3175 compatible = "qcom,soundwire-v1.6.0"; 3176 reg = <0 0x03330000 0 0x2000>; 3177 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3179 interrupt-names = "core", "wakeup"; 3180 3181 clocks = <&txmacro>; 3182 clock-names = "iface"; 3183 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3184 reset-names = "swr_audio_cgcr"; 3185 label = "TX"; 3186 #sound-dai-cells = <1>; 3187 #address-cells = <2>; 3188 #size-cells = <0>; 3189 3190 qcom,din-ports = <4>; 3191 qcom,dout-ports = <0>; 3192 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3193 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 3194 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3195 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3196 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3197 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3198 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3199 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3200 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 3201 3202 status = "disabled"; 3203 }; 3204 3205 vamacro: codec@3370000 { 3206 compatible = "qcom,sc8280xp-lpass-va-macro"; 3207 reg = <0 0x03370000 0 0x1000>; 3208 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3209 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3210 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3211 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3212 clock-names = "mclk", "macro", "dcodec", "npl"; 3213 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3214 assigned-clock-rates = <19200000>; 3215 3216 #clock-cells = <0>; 3217 clock-output-names = "fsgen"; 3218 #sound-dai-cells = <1>; 3219 3220 status = "disabled"; 3221 }; 3222 3223 lpass_tlmm: pinctrl@33c0000 { 3224 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3225 reg = <0 0x33c0000 0x0 0x20000>, 3226 <0 0x3550000 0x0 0x10000>; 3227 gpio-controller; 3228 #gpio-cells = <2>; 3229 gpio-ranges = <&lpass_tlmm 0 0 19>; 3230 3231 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3232 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3233 clock-names = "core", "audio"; 3234 3235 status = "disabled"; 3236 3237 tx_swr_default: tx-swr-default-state { 3238 clk-pins { 3239 pins = "gpio0"; 3240 function = "swr_tx_clk"; 3241 drive-strength = <2>; 3242 slew-rate = <1>; 3243 bias-disable; 3244 }; 3245 3246 data-pins { 3247 pins = "gpio1", "gpio2"; 3248 function = "swr_tx_data"; 3249 drive-strength = <2>; 3250 slew-rate = <1>; 3251 bias-bus-hold; 3252 }; 3253 }; 3254 3255 rx_swr_default: rx-swr-default-state { 3256 clk-pins { 3257 pins = "gpio3"; 3258 function = "swr_rx_clk"; 3259 drive-strength = <2>; 3260 slew-rate = <1>; 3261 bias-disable; 3262 }; 3263 3264 data-pins { 3265 pins = "gpio4", "gpio5"; 3266 function = "swr_rx_data"; 3267 drive-strength = <2>; 3268 slew-rate = <1>; 3269 bias-bus-hold; 3270 }; 3271 }; 3272 3273 dmic01_default: dmic01-default-state { 3274 clk-pins { 3275 pins = "gpio6"; 3276 function = "dmic1_clk"; 3277 drive-strength = <8>; 3278 output-high; 3279 }; 3280 3281 data-pins { 3282 pins = "gpio7"; 3283 function = "dmic1_data"; 3284 drive-strength = <8>; 3285 input-enable; 3286 }; 3287 }; 3288 3289 dmic01_sleep: dmic01-sleep-state { 3290 clk-pins { 3291 pins = "gpio6"; 3292 function = "dmic1_clk"; 3293 drive-strength = <2>; 3294 bias-disable; 3295 output-low; 3296 }; 3297 3298 data-pins { 3299 pins = "gpio7"; 3300 function = "dmic1_data"; 3301 drive-strength = <2>; 3302 bias-pull-down; 3303 input-enable; 3304 }; 3305 }; 3306 3307 dmic23_default: dmic23-default-state { 3308 clk-pins { 3309 pins = "gpio8"; 3310 function = "dmic2_clk"; 3311 drive-strength = <8>; 3312 output-high; 3313 }; 3314 3315 data-pins { 3316 pins = "gpio9"; 3317 function = "dmic2_data"; 3318 drive-strength = <8>; 3319 input-enable; 3320 }; 3321 }; 3322 3323 dmic23_sleep: dmic23-sleep-state { 3324 clk-pins { 3325 pins = "gpio8"; 3326 function = "dmic2_clk"; 3327 drive-strength = <2>; 3328 bias-disable; 3329 output-low; 3330 }; 3331 3332 data-pins { 3333 pins = "gpio9"; 3334 function = "dmic2_data"; 3335 drive-strength = <2>; 3336 bias-pull-down; 3337 input-enable; 3338 }; 3339 }; 3340 3341 wsa_swr_default: wsa-swr-default-state { 3342 clk-pins { 3343 pins = "gpio10"; 3344 function = "wsa_swr_clk"; 3345 drive-strength = <2>; 3346 slew-rate = <1>; 3347 bias-disable; 3348 }; 3349 3350 data-pins { 3351 pins = "gpio11"; 3352 function = "wsa_swr_data"; 3353 drive-strength = <2>; 3354 slew-rate = <1>; 3355 bias-bus-hold; 3356 }; 3357 }; 3358 3359 wsa2_swr_default: wsa2-swr-default-state { 3360 clk-pins { 3361 pins = "gpio15"; 3362 function = "wsa2_swr_clk"; 3363 drive-strength = <2>; 3364 slew-rate = <1>; 3365 bias-disable; 3366 }; 3367 3368 data-pins { 3369 pins = "gpio16"; 3370 function = "wsa2_swr_data"; 3371 drive-strength = <2>; 3372 slew-rate = <1>; 3373 bias-bus-hold; 3374 }; 3375 }; 3376 }; 3377 3378 lpasscc: clock-controller@33e0000 { 3379 compatible = "qcom,sc8280xp-lpasscc"; 3380 reg = <0 0x033e0000 0 0x12000>; 3381 #clock-cells = <1>; 3382 #reset-cells = <1>; 3383 }; 3384 3385 lpass_noc: interconnect@3c40000 { 3386 compatible = "qcom,sc8280xp-lpass-ag-noc"; 3387 reg = <0 0x03c40000 0 0xf080>; 3388 3389 #interconnect-cells = <2>; 3390 qcom,bcm-voters = <&apps_bcm_voter>; 3391 }; 3392 3393 gpu: gpu@3d00000 { 3394 compatible = "qcom,adreno-690.0", "qcom,adreno"; 3395 3396 reg = <0 0x03d00000 0 0x40000>, 3397 <0 0x03d9e000 0 0x1000>, 3398 <0 0x03d61000 0 0x800>; 3399 reg-names = "kgsl_3d0_reg_memory", 3400 "cx_mem", 3401 "cx_dbgc"; 3402 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3403 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 3404 operating-points-v2 = <&gpu_opp_table>; 3405 3406 qcom,gmu = <&gmu>; 3407 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3408 interconnect-names = "gfx-mem"; 3409 #cooling-cells = <2>; 3410 3411 status = "disabled"; 3412 3413 gpu_zap_shader: zap-shader { 3414 memory-region = <&pil_gpu_mem>; 3415 }; 3416 3417 gpu_opp_table: opp-table { 3418 compatible = "operating-points-v2"; 3419 3420 opp-270000000 { 3421 opp-hz = /bits/ 64 <270000000>; 3422 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3423 opp-peak-kBps = <451000>; 3424 }; 3425 3426 opp-410000000 { 3427 opp-hz = /bits/ 64 <410000000>; 3428 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3429 opp-peak-kBps = <1555000>; 3430 }; 3431 3432 opp-500000000 { 3433 opp-hz = /bits/ 64 <500000000>; 3434 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3435 opp-peak-kBps = <1555000>; 3436 }; 3437 3438 opp-547000000 { 3439 opp-hz = /bits/ 64 <547000000>; 3440 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3441 opp-peak-kBps = <1555000>; 3442 }; 3443 3444 opp-606000000 { 3445 opp-hz = /bits/ 64 <606000000>; 3446 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3447 opp-peak-kBps = <2736000>; 3448 }; 3449 3450 opp-640000000 { 3451 opp-hz = /bits/ 64 <640000000>; 3452 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3453 opp-peak-kBps = <2736000>; 3454 }; 3455 3456 opp-655000000 { 3457 opp-hz = /bits/ 64 <655000000>; 3458 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3459 opp-peak-kBps = <2736000>; 3460 }; 3461 3462 opp-690000000 { 3463 opp-hz = /bits/ 64 <690000000>; 3464 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3465 opp-peak-kBps = <2736000>; 3466 }; 3467 }; 3468 }; 3469 3470 gmu: gmu@3d6a000 { 3471 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3472 reg = <0 0x03d6a000 0 0x34000>, 3473 <0 0x03de0000 0 0x10000>, 3474 <0 0x0b290000 0 0x10000>; 3475 reg-names = "gmu", "rscc", "gmu_pdc"; 3476 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3478 interrupt-names = "hfi", "gmu"; 3479 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3480 <&gpucc GPU_CC_CXO_CLK>, 3481 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3482 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3483 <&gpucc GPU_CC_AHB_CLK>, 3484 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3485 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3486 clock-names = "gmu", 3487 "cxo", 3488 "axi", 3489 "memnoc", 3490 "ahb", 3491 "hub", 3492 "smmu_vote"; 3493 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3494 <&gpucc GPU_CC_GX_GDSC>; 3495 power-domain-names = "cx", 3496 "gx"; 3497 iommus = <&gpu_smmu 5 0xc00>; 3498 operating-points-v2 = <&gmu_opp_table>; 3499 3500 gmu_opp_table: opp-table { 3501 compatible = "operating-points-v2"; 3502 3503 opp-200000000 { 3504 opp-hz = /bits/ 64 <200000000>; 3505 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3506 }; 3507 3508 opp-500000000 { 3509 opp-hz = /bits/ 64 <500000000>; 3510 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3511 }; 3512 }; 3513 }; 3514 3515 gpucc: clock-controller@3d90000 { 3516 compatible = "qcom,sc8280xp-gpucc"; 3517 reg = <0 0x03d90000 0 0x9000>; 3518 clocks = <&rpmhcc RPMH_CXO_CLK>, 3519 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3520 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3521 clock-names = "bi_tcxo", 3522 "gcc_gpu_gpll0_clk_src", 3523 "gcc_gpu_gpll0_div_clk_src"; 3524 3525 power-domains = <&rpmhpd SC8280XP_GFX>; 3526 #clock-cells = <1>; 3527 #reset-cells = <1>; 3528 #power-domain-cells = <1>; 3529 }; 3530 3531 gpu_smmu: iommu@3da0000 { 3532 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3533 "qcom,smmu-500", "arm,mmu-500"; 3534 reg = <0 0x03da0000 0 0x20000>; 3535 #iommu-cells = <2>; 3536 #global-interrupts = <2>; 3537 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3551 3552 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3553 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3554 <&gpucc GPU_CC_AHB_CLK>, 3555 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3556 <&gpucc GPU_CC_CX_GMU_CLK>, 3557 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3558 <&gpucc GPU_CC_HUB_AON_CLK>; 3559 clock-names = "gcc_gpu_memnoc_gfx_clk", 3560 "gcc_gpu_snoc_dvm_gfx_clk", 3561 "gpu_cc_ahb_clk", 3562 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3563 "gpu_cc_cx_gmu_clk", 3564 "gpu_cc_hub_cx_int_clk", 3565 "gpu_cc_hub_aon_clk"; 3566 3567 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3568 dma-coherent; 3569 }; 3570 3571 sdc2: mmc@8804000 { 3572 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3573 reg = <0 0x08804000 0 0x1000>; 3574 3575 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3577 interrupt-names = "hc_irq", "pwr_irq"; 3578 3579 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3580 <&gcc GCC_SDCC2_APPS_CLK>, 3581 <&rpmhcc RPMH_CXO_CLK>; 3582 clock-names = "iface", "core", "xo"; 3583 resets = <&gcc GCC_SDCC2_BCR>; 3584 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3586 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3587 iommus = <&apps_smmu 0x4e0 0x0>; 3588 power-domains = <&rpmhpd SC8280XP_CX>; 3589 operating-points-v2 = <&sdc2_opp_table>; 3590 bus-width = <4>; 3591 dma-coherent; 3592 3593 status = "disabled"; 3594 3595 sdc2_opp_table: opp-table { 3596 compatible = "operating-points-v2"; 3597 3598 opp-100000000 { 3599 opp-hz = /bits/ 64 <100000000>; 3600 required-opps = <&rpmhpd_opp_low_svs>; 3601 opp-peak-kBps = <1800000 400000>; 3602 opp-avg-kBps = <100000 0>; 3603 }; 3604 3605 opp-202000000 { 3606 opp-hz = /bits/ 64 <202000000>; 3607 required-opps = <&rpmhpd_opp_svs_l1>; 3608 opp-peak-kBps = <5400000 1600000>; 3609 opp-avg-kBps = <200000 0>; 3610 }; 3611 }; 3612 }; 3613 3614 usb_0_hsphy: phy@88e5000 { 3615 compatible = "qcom,sc8280xp-usb-hs-phy", 3616 "qcom,usb-snps-hs-5nm-phy"; 3617 reg = <0 0x088e5000 0 0x400>; 3618 clocks = <&rpmhcc RPMH_CXO_CLK>; 3619 clock-names = "ref"; 3620 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3621 3622 #phy-cells = <0>; 3623 3624 status = "disabled"; 3625 }; 3626 3627 usb_2_hsphy0: phy@88e7000 { 3628 compatible = "qcom,sc8280xp-usb-hs-phy", 3629 "qcom,usb-snps-hs-5nm-phy"; 3630 reg = <0 0x088e7000 0 0x400>; 3631 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3632 clock-names = "ref"; 3633 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3634 3635 #phy-cells = <0>; 3636 3637 status = "disabled"; 3638 }; 3639 3640 usb_2_hsphy1: phy@88e8000 { 3641 compatible = "qcom,sc8280xp-usb-hs-phy", 3642 "qcom,usb-snps-hs-5nm-phy"; 3643 reg = <0 0x088e8000 0 0x400>; 3644 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3645 clock-names = "ref"; 3646 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3647 3648 #phy-cells = <0>; 3649 3650 status = "disabled"; 3651 }; 3652 3653 usb_2_hsphy2: phy@88e9000 { 3654 compatible = "qcom,sc8280xp-usb-hs-phy", 3655 "qcom,usb-snps-hs-5nm-phy"; 3656 reg = <0 0x088e9000 0 0x400>; 3657 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3658 clock-names = "ref"; 3659 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3660 3661 #phy-cells = <0>; 3662 3663 status = "disabled"; 3664 }; 3665 3666 usb_2_hsphy3: phy@88ea000 { 3667 compatible = "qcom,sc8280xp-usb-hs-phy", 3668 "qcom,usb-snps-hs-5nm-phy"; 3669 reg = <0 0x088ea000 0 0x400>; 3670 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3671 clock-names = "ref"; 3672 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3673 3674 #phy-cells = <0>; 3675 3676 status = "disabled"; 3677 }; 3678 3679 usb_0_qmpphy: phy@88eb000 { 3680 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3681 reg = <0 0x088eb000 0 0x4000>; 3682 3683 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3684 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3685 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3686 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3687 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3688 3689 power-domains = <&gcc USB30_PRIM_GDSC>; 3690 3691 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3692 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3693 reset-names = "phy", "common"; 3694 3695 #clock-cells = <1>; 3696 #phy-cells = <1>; 3697 3698 status = "disabled"; 3699 3700 ports { 3701 #address-cells = <1>; 3702 #size-cells = <0>; 3703 3704 port@0 { 3705 reg = <0>; 3706 3707 usb_0_qmpphy_out: endpoint {}; 3708 }; 3709 3710 port@1 { 3711 reg = <1>; 3712 3713 usb_0_qmpphy_usb_ss_in: endpoint { 3714 remote-endpoint = <&usb_0_dwc3_ss>; 3715 }; 3716 }; 3717 3718 port@2 { 3719 reg = <2>; 3720 3721 usb_0_qmpphy_dp_in: endpoint {}; 3722 }; 3723 }; 3724 }; 3725 3726 usb_2_qmpphy0: phy@88ef000 { 3727 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3728 reg = <0 0x088ef000 0 0x2000>; 3729 3730 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3731 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3732 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3733 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3734 clock-names = "aux", "ref", "com_aux", "pipe"; 3735 3736 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3737 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3738 reset-names = "phy", "phy_phy"; 3739 3740 power-domains = <&gcc USB30_MP_GDSC>; 3741 3742 #clock-cells = <0>; 3743 clock-output-names = "usb2_phy0_pipe_clk"; 3744 3745 #phy-cells = <0>; 3746 3747 status = "disabled"; 3748 }; 3749 3750 usb_2_qmpphy1: phy@88f1000 { 3751 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3752 reg = <0 0x088f1000 0 0x2000>; 3753 3754 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3755 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3756 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3757 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3758 clock-names = "aux", "ref", "com_aux", "pipe"; 3759 3760 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3761 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3762 reset-names = "phy", "phy_phy"; 3763 3764 power-domains = <&gcc USB30_MP_GDSC>; 3765 3766 #clock-cells = <0>; 3767 clock-output-names = "usb2_phy1_pipe_clk"; 3768 3769 #phy-cells = <0>; 3770 3771 status = "disabled"; 3772 }; 3773 3774 refgen: regulator@8900000 { 3775 compatible = "qcom,sc8280xp-refgen-regulator", 3776 "qcom,sm8250-refgen-regulator"; 3777 reg = <0x0 0x08900000 0x0 0x96>; 3778 }; 3779 3780 usb_1_hsphy: phy@8902000 { 3781 compatible = "qcom,sc8280xp-usb-hs-phy", 3782 "qcom,usb-snps-hs-5nm-phy"; 3783 reg = <0 0x08902000 0 0x400>; 3784 #phy-cells = <0>; 3785 3786 clocks = <&rpmhcc RPMH_CXO_CLK>; 3787 clock-names = "ref"; 3788 3789 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3790 3791 status = "disabled"; 3792 }; 3793 3794 usb_1_qmpphy: phy@8903000 { 3795 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3796 reg = <0 0x08903000 0 0x4000>; 3797 3798 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3799 <&gcc GCC_USB4_CLKREF_CLK>, 3800 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3801 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3802 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3803 3804 power-domains = <&gcc USB30_SEC_GDSC>; 3805 3806 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3807 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3808 reset-names = "phy", "common"; 3809 3810 #clock-cells = <1>; 3811 #phy-cells = <1>; 3812 3813 status = "disabled"; 3814 3815 ports { 3816 #address-cells = <1>; 3817 #size-cells = <0>; 3818 3819 port@0 { 3820 reg = <0>; 3821 3822 usb_1_qmpphy_out: endpoint {}; 3823 }; 3824 3825 port@1 { 3826 reg = <1>; 3827 3828 usb_1_qmpphy_usb_ss_in: endpoint { 3829 remote-endpoint = <&usb_1_dwc3_ss>; 3830 }; 3831 }; 3832 3833 port@2 { 3834 reg = <2>; 3835 3836 usb_1_qmpphy_dp_in: endpoint {}; 3837 }; 3838 }; 3839 }; 3840 3841 mdss1_dp0_phy: phy@8909a00 { 3842 compatible = "qcom,sc8280xp-dp-phy"; 3843 reg = <0 0x08909a00 0 0x19c>, 3844 <0 0x08909200 0 0xec>, 3845 <0 0x08909600 0 0xec>, 3846 <0 0x08909000 0 0x1c8>; 3847 3848 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3849 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3850 clock-names = "aux", "cfg_ahb"; 3851 power-domains = <&rpmhpd SC8280XP_MX>; 3852 3853 #clock-cells = <1>; 3854 #phy-cells = <0>; 3855 3856 status = "disabled"; 3857 }; 3858 3859 mdss1_dp1_phy: phy@890ca00 { 3860 compatible = "qcom,sc8280xp-dp-phy"; 3861 reg = <0 0x0890ca00 0 0x19c>, 3862 <0 0x0890c200 0 0xec>, 3863 <0 0x0890c600 0 0xec>, 3864 <0 0x0890c000 0 0x1c8>; 3865 3866 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3867 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3868 clock-names = "aux", "cfg_ahb"; 3869 power-domains = <&rpmhpd SC8280XP_MX>; 3870 3871 #clock-cells = <1>; 3872 #phy-cells = <0>; 3873 3874 status = "disabled"; 3875 }; 3876 3877 pmu@9091000 { 3878 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3879 reg = <0 0x09091000 0 0x1000>; 3880 3881 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3882 3883 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3884 3885 operating-points-v2 = <&llcc_bwmon_opp_table>; 3886 3887 llcc_bwmon_opp_table: opp-table { 3888 compatible = "operating-points-v2"; 3889 3890 opp-0 { 3891 opp-peak-kBps = <762000>; 3892 }; 3893 opp-1 { 3894 opp-peak-kBps = <1720000>; 3895 }; 3896 opp-2 { 3897 opp-peak-kBps = <2086000>; 3898 }; 3899 opp-3 { 3900 opp-peak-kBps = <2597000>; 3901 }; 3902 opp-4 { 3903 opp-peak-kBps = <2929000>; 3904 }; 3905 opp-5 { 3906 opp-peak-kBps = <3879000>; 3907 }; 3908 opp-6 { 3909 opp-peak-kBps = <5161000>; 3910 }; 3911 opp-7 { 3912 opp-peak-kBps = <5931000>; 3913 }; 3914 opp-8 { 3915 opp-peak-kBps = <6515000>; 3916 }; 3917 opp-9 { 3918 opp-peak-kBps = <7980000>; 3919 }; 3920 opp-10 { 3921 opp-peak-kBps = <8136000>; 3922 }; 3923 opp-11 { 3924 opp-peak-kBps = <10437000>; 3925 }; 3926 opp-12 { 3927 opp-peak-kBps = <12191000>; 3928 }; 3929 }; 3930 }; 3931 3932 pmu@90b6400 { 3933 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3934 reg = <0 0x090b6400 0 0x600>; 3935 3936 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3937 3938 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3939 operating-points-v2 = <&cpu_bwmon_opp_table>; 3940 3941 cpu_bwmon_opp_table: opp-table { 3942 compatible = "operating-points-v2"; 3943 3944 opp-0 { 3945 opp-peak-kBps = <2288000>; 3946 }; 3947 opp-1 { 3948 opp-peak-kBps = <4577000>; 3949 }; 3950 opp-2 { 3951 opp-peak-kBps = <7110000>; 3952 }; 3953 opp-3 { 3954 opp-peak-kBps = <9155000>; 3955 }; 3956 opp-4 { 3957 opp-peak-kBps = <12298000>; 3958 }; 3959 opp-5 { 3960 opp-peak-kBps = <14236000>; 3961 }; 3962 opp-6 { 3963 opp-peak-kBps = <15258001>; 3964 }; 3965 }; 3966 }; 3967 3968 dc_noc: interconnect@90e0000 { 3969 compatible = "qcom,sc8280xp-dc-noc"; 3970 reg = <0 0x090e0000 0 0x5080>; 3971 3972 #interconnect-cells = <2>; 3973 qcom,bcm-voters = <&apps_bcm_voter>; 3974 }; 3975 3976 gem_noc: interconnect@9100000 { 3977 compatible = "qcom,sc8280xp-gem-noc"; 3978 reg = <0 0x09100000 0 0xb8400>; 3979 3980 #interconnect-cells = <2>; 3981 qcom,bcm-voters = <&apps_bcm_voter>; 3982 }; 3983 3984 system-cache-controller@9200000 { 3985 compatible = "qcom,sc8280xp-llcc"; 3986 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3987 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3988 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3989 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3990 <0 0x09600000 0 0x58000>; 3991 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3992 "llcc3_base", "llcc4_base", "llcc5_base", 3993 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3994 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3995 }; 3996 3997 usb_2: usb@a4f8800 { 3998 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3999 reg = <0 0x0a4f8800 0 0x400>; 4000 #address-cells = <2>; 4001 #size-cells = <2>; 4002 ranges; 4003 4004 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4005 <&gcc GCC_USB30_MP_MASTER_CLK>, 4006 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4007 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4008 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4009 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4010 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4011 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4012 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4013 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4014 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4015 4016 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4017 <&gcc GCC_USB30_MP_MASTER_CLK>; 4018 assigned-clock-rates = <19200000>, <200000000>; 4019 4020 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4021 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4022 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 4023 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4024 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4025 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4026 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 4027 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 4028 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 4029 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 4030 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 4031 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 4032 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 4033 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 4034 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 4035 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 4036 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 4037 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4038 4039 interrupt-names = "pwr_event_1", "pwr_event_2", 4040 "pwr_event_3", "pwr_event_4", 4041 "hs_phy_1", "hs_phy_2", 4042 "hs_phy_3", "hs_phy_4", 4043 "dp_hs_phy_1", "dm_hs_phy_1", 4044 "dp_hs_phy_2", "dm_hs_phy_2", 4045 "dp_hs_phy_3", "dm_hs_phy_3", 4046 "dp_hs_phy_4", "dm_hs_phy_4", 4047 "ss_phy_1", "ss_phy_2"; 4048 4049 power-domains = <&gcc USB30_MP_GDSC>; 4050 required-opps = <&rpmhpd_opp_nom>; 4051 4052 resets = <&gcc GCC_USB30_MP_BCR>; 4053 4054 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 4055 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 4056 interconnect-names = "usb-ddr", "apps-usb"; 4057 4058 wakeup-source; 4059 4060 status = "disabled"; 4061 4062 usb_2_dwc3: usb@a400000 { 4063 compatible = "snps,dwc3"; 4064 reg = <0 0x0a400000 0 0xcd00>; 4065 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4066 iommus = <&apps_smmu 0x800 0x0>; 4067 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 4068 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 4069 <&usb_2_hsphy2>, 4070 <&usb_2_hsphy3>; 4071 phy-names = "usb2-0", "usb3-0", 4072 "usb2-1", "usb3-1", 4073 "usb2-2", 4074 "usb2-3"; 4075 dr_mode = "host"; 4076 snps,dis-u1-entry-quirk; 4077 snps,dis-u2-entry-quirk; 4078 }; 4079 }; 4080 4081 usb_0: usb@a6f8800 { 4082 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4083 reg = <0 0x0a6f8800 0 0x400>; 4084 #address-cells = <2>; 4085 #size-cells = <2>; 4086 ranges; 4087 4088 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4089 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4090 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4091 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4092 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4093 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4094 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4095 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4096 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4097 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4098 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4099 4100 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4101 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4102 assigned-clock-rates = <19200000>, <200000000>; 4103 4104 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4105 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4106 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4107 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4108 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 4109 interrupt-names = "pwr_event", 4110 "hs_phy_irq", 4111 "dp_hs_phy_irq", 4112 "dm_hs_phy_irq", 4113 "ss_phy_irq"; 4114 4115 power-domains = <&gcc USB30_PRIM_GDSC>; 4116 required-opps = <&rpmhpd_opp_nom>; 4117 4118 resets = <&gcc GCC_USB30_PRIM_BCR>; 4119 4120 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4121 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4122 interconnect-names = "usb-ddr", "apps-usb"; 4123 4124 wakeup-source; 4125 4126 status = "disabled"; 4127 4128 usb_0_dwc3: usb@a600000 { 4129 compatible = "snps,dwc3"; 4130 reg = <0 0x0a600000 0 0xcd00>; 4131 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 4132 iommus = <&apps_smmu 0x820 0x0>; 4133 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4134 phy-names = "usb2-phy", "usb3-phy"; 4135 snps,dis-u1-entry-quirk; 4136 snps,dis-u2-entry-quirk; 4137 4138 ports { 4139 #address-cells = <1>; 4140 #size-cells = <0>; 4141 4142 port@0 { 4143 reg = <0>; 4144 4145 usb_0_dwc3_hs: endpoint { 4146 }; 4147 }; 4148 4149 port@1 { 4150 reg = <1>; 4151 4152 usb_0_dwc3_ss: endpoint { 4153 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4154 }; 4155 }; 4156 }; 4157 }; 4158 }; 4159 4160 usb_1: usb@a8f8800 { 4161 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4162 reg = <0 0x0a8f8800 0 0x400>; 4163 #address-cells = <2>; 4164 #size-cells = <2>; 4165 ranges; 4166 4167 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4168 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4169 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4170 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4171 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4172 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4173 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4174 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4175 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4176 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4177 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4178 4179 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4180 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4181 assigned-clock-rates = <19200000>, <200000000>; 4182 4183 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4184 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4185 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4186 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4187 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 4188 interrupt-names = "pwr_event", 4189 "hs_phy_irq", 4190 "dp_hs_phy_irq", 4191 "dm_hs_phy_irq", 4192 "ss_phy_irq"; 4193 4194 power-domains = <&gcc USB30_SEC_GDSC>; 4195 required-opps = <&rpmhpd_opp_nom>; 4196 4197 resets = <&gcc GCC_USB30_SEC_BCR>; 4198 4199 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4200 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4201 interconnect-names = "usb-ddr", "apps-usb"; 4202 4203 wakeup-source; 4204 4205 status = "disabled"; 4206 4207 usb_1_dwc3: usb@a800000 { 4208 compatible = "snps,dwc3"; 4209 reg = <0 0x0a800000 0 0xcd00>; 4210 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 4211 iommus = <&apps_smmu 0x860 0x0>; 4212 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4213 phy-names = "usb2-phy", "usb3-phy"; 4214 snps,dis-u1-entry-quirk; 4215 snps,dis-u2-entry-quirk; 4216 4217 ports { 4218 #address-cells = <1>; 4219 #size-cells = <0>; 4220 4221 port@0 { 4222 reg = <0>; 4223 4224 usb_1_dwc3_hs: endpoint { 4225 }; 4226 }; 4227 4228 port@1 { 4229 reg = <1>; 4230 4231 usb_1_dwc3_ss: endpoint { 4232 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4233 }; 4234 }; 4235 }; 4236 }; 4237 }; 4238 4239 iris: video-codec@aa00000 { 4240 compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus"; 4241 reg = <0x0 0x0aa00000 0x0 0x100000>; 4242 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4243 4244 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4245 <&videocc VIDEO_CC_MVS0C_CLK>, 4246 <&videocc VIDEO_CC_MVS0_CLK>; 4247 clock-names = "iface", 4248 "core", 4249 "vcodec0_core"; 4250 power-domains = <&videocc MVS0C_GDSC>, 4251 <&videocc MVS0_GDSC>, 4252 <&rpmhpd SC8280XP_MX>, 4253 <&rpmhpd SC8280XP_MMCX>; 4254 power-domain-names = "venus", 4255 "vcodec0", 4256 "mx", 4257 "mmcx"; 4258 4259 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4260 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4261 reset-names = "bus", "core"; 4262 4263 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4264 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4265 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4267 interconnect-names = "cpu-cfg", 4268 "video-mem"; 4269 4270 operating-points-v2 = <&iris_opp_table>; 4271 iommus = <&apps_smmu 0x2a00 0x400>; 4272 memory-region = <&pil_video_mem>; 4273 4274 status = "disabled"; 4275 4276 iris_opp_table: opp-table { 4277 compatible = "operating-points-v2"; 4278 4279 opp-240000000 { 4280 opp-hz = /bits/ 64 <240000000>; 4281 required-opps = <&rpmhpd_opp_svs>, 4282 <&rpmhpd_opp_low_svs>; 4283 }; 4284 4285 opp-338000000 { 4286 opp-hz = /bits/ 64 <338000000>; 4287 required-opps = <&rpmhpd_opp_svs>, 4288 <&rpmhpd_opp_svs>; 4289 }; 4290 4291 opp-366000000 { 4292 opp-hz = /bits/ 64 <366000000>; 4293 required-opps = <&rpmhpd_opp_svs_l1>, 4294 <&rpmhpd_opp_svs_l1>; 4295 }; 4296 4297 opp-444000000 { 4298 opp-hz = /bits/ 64 <444000000>; 4299 required-opps = <&rpmhpd_opp_svs_l1>, 4300 <&rpmhpd_opp_nom>; 4301 }; 4302 4303 opp-533000000 { 4304 opp-hz = /bits/ 64 <533000000>; 4305 required-opps = <&rpmhpd_opp_nom>, 4306 <&rpmhpd_opp_turbo>; 4307 }; 4308 4309 opp-560000000 { 4310 opp-hz = /bits/ 64 <560000000>; 4311 required-opps = <&rpmhpd_opp_nom>, 4312 <&rpmhpd_opp_turbo_l1>; 4313 }; 4314 }; 4315 }; 4316 4317 videocc: clock-controller@abf0000 { 4318 compatible = "qcom,sc8280xp-videocc"; 4319 reg = <0 0x0abf0000 0 0x10000>; 4320 clocks = <&rpmhcc RPMH_CXO_CLK>, 4321 <&rpmhcc RPMH_CXO_CLK_A>, 4322 <&sleep_clk>; 4323 power-domains = <&rpmhpd SC8280XP_MMCX>; 4324 required-opps = <&rpmhpd_opp_low_svs>; 4325 #clock-cells = <1>; 4326 #reset-cells = <1>; 4327 #power-domain-cells = <1>; 4328 }; 4329 4330 cci0: cci@ac4a000 { 4331 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4332 reg = <0 0x0ac4a000 0 0x1000>; 4333 4334 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4335 4336 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4337 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4338 <&camcc CAMCC_CPAS_AHB_CLK>, 4339 <&camcc CAMCC_CCI_0_CLK>; 4340 clock-names = "camnoc_axi", 4341 "slow_ahb_src", 4342 "cpas_ahb", 4343 "cci"; 4344 4345 power-domains = <&camcc TITAN_TOP_GDSC>; 4346 4347 pinctrl-0 = <&cci0_default>; 4348 pinctrl-1 = <&cci0_sleep>; 4349 pinctrl-names = "default", "sleep"; 4350 4351 #address-cells = <1>; 4352 #size-cells = <0>; 4353 4354 status = "disabled"; 4355 4356 cci0_i2c0: i2c-bus@0 { 4357 reg = <0>; 4358 clock-frequency = <1000000>; 4359 #address-cells = <1>; 4360 #size-cells = <0>; 4361 }; 4362 4363 cci0_i2c1: i2c-bus@1 { 4364 reg = <1>; 4365 clock-frequency = <1000000>; 4366 #address-cells = <1>; 4367 #size-cells = <0>; 4368 }; 4369 }; 4370 4371 cci1: cci@ac4b000 { 4372 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4373 reg = <0 0x0ac4b000 0 0x1000>; 4374 4375 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4376 4377 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4378 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4379 <&camcc CAMCC_CPAS_AHB_CLK>, 4380 <&camcc CAMCC_CCI_1_CLK>; 4381 clock-names = "camnoc_axi", 4382 "slow_ahb_src", 4383 "cpas_ahb", 4384 "cci"; 4385 4386 power-domains = <&camcc TITAN_TOP_GDSC>; 4387 4388 pinctrl-0 = <&cci1_default>; 4389 pinctrl-1 = <&cci1_sleep>; 4390 pinctrl-names = "default", "sleep"; 4391 4392 #address-cells = <1>; 4393 #size-cells = <0>; 4394 4395 status = "disabled"; 4396 4397 cci1_i2c0: i2c-bus@0 { 4398 reg = <0>; 4399 clock-frequency = <1000000>; 4400 #address-cells = <1>; 4401 #size-cells = <0>; 4402 }; 4403 4404 cci1_i2c1: i2c-bus@1 { 4405 reg = <1>; 4406 clock-frequency = <1000000>; 4407 #address-cells = <1>; 4408 #size-cells = <0>; 4409 }; 4410 }; 4411 4412 cci2: cci@ac4c000 { 4413 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4414 reg = <0 0x0ac4c000 0 0x1000>; 4415 4416 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4417 4418 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4419 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4420 <&camcc CAMCC_CPAS_AHB_CLK>, 4421 <&camcc CAMCC_CCI_2_CLK>; 4422 clock-names = "camnoc_axi", 4423 "slow_ahb_src", 4424 "cpas_ahb", 4425 "cci"; 4426 power-domains = <&camcc TITAN_TOP_GDSC>; 4427 4428 pinctrl-0 = <&cci2_default>; 4429 pinctrl-1 = <&cci2_sleep>; 4430 pinctrl-names = "default", "sleep"; 4431 4432 #address-cells = <1>; 4433 #size-cells = <0>; 4434 4435 status = "disabled"; 4436 4437 cci2_i2c0: i2c-bus@0 { 4438 reg = <0>; 4439 clock-frequency = <1000000>; 4440 #address-cells = <1>; 4441 #size-cells = <0>; 4442 }; 4443 4444 cci2_i2c1: i2c-bus@1 { 4445 reg = <1>; 4446 clock-frequency = <1000000>; 4447 #address-cells = <1>; 4448 #size-cells = <0>; 4449 }; 4450 }; 4451 4452 cci3: cci@ac4d000 { 4453 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4454 reg = <0 0x0ac4d000 0 0x1000>; 4455 4456 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 4457 4458 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4459 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4460 <&camcc CAMCC_CPAS_AHB_CLK>, 4461 <&camcc CAMCC_CCI_3_CLK>; 4462 clock-names = "camnoc_axi", 4463 "slow_ahb_src", 4464 "cpas_ahb", 4465 "cci"; 4466 4467 power-domains = <&camcc TITAN_TOP_GDSC>; 4468 4469 pinctrl-0 = <&cci3_default>; 4470 pinctrl-1 = <&cci3_sleep>; 4471 pinctrl-names = "default", "sleep"; 4472 4473 #address-cells = <1>; 4474 #size-cells = <0>; 4475 4476 status = "disabled"; 4477 4478 cci3_i2c0: i2c-bus@0 { 4479 reg = <0>; 4480 clock-frequency = <1000000>; 4481 #address-cells = <1>; 4482 #size-cells = <0>; 4483 }; 4484 4485 cci3_i2c1: i2c-bus@1 { 4486 reg = <1>; 4487 clock-frequency = <1000000>; 4488 #address-cells = <1>; 4489 #size-cells = <0>; 4490 }; 4491 }; 4492 4493 camss: camss@ac5a000 { 4494 compatible = "qcom,sc8280xp-camss"; 4495 4496 reg = <0 0x0ac5a000 0 0x2000>, 4497 <0 0x0ac5c000 0 0x2000>, 4498 <0 0x0ac65000 0 0x2000>, 4499 <0 0x0ac67000 0 0x2000>, 4500 <0 0x0acaf000 0 0x4000>, 4501 <0 0x0acb3000 0 0x1000>, 4502 <0 0x0acb6000 0 0x4000>, 4503 <0 0x0acba000 0 0x1000>, 4504 <0 0x0acbd000 0 0x4000>, 4505 <0 0x0acc1000 0 0x1000>, 4506 <0 0x0acc4000 0 0x4000>, 4507 <0 0x0acc8000 0 0x1000>, 4508 <0 0x0accb000 0 0x4000>, 4509 <0 0x0accf000 0 0x1000>, 4510 <0 0x0acd2000 0 0x4000>, 4511 <0 0x0acd6000 0 0x1000>, 4512 <0 0x0acd9000 0 0x4000>, 4513 <0 0x0acdd000 0 0x1000>, 4514 <0 0x0ace0000 0 0x4000>, 4515 <0 0x0ace4000 0 0x1000>; 4516 reg-names = "csiphy2", 4517 "csiphy3", 4518 "csiphy0", 4519 "csiphy1", 4520 "vfe0", 4521 "csid0", 4522 "vfe1", 4523 "csid1", 4524 "vfe2", 4525 "csid2", 4526 "vfe_lite0", 4527 "csid0_lite", 4528 "vfe_lite1", 4529 "csid1_lite", 4530 "vfe_lite2", 4531 "csid2_lite", 4532 "vfe_lite3", 4533 "csid3_lite", 4534 "vfe3", 4535 "csid3"; 4536 4537 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4538 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4539 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4540 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4541 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4542 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4543 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4544 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4545 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4546 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4547 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4548 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4549 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4550 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4551 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4552 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4553 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4554 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4555 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4556 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4557 interrupt-names = "csid1_lite", 4558 "vfe_lite1", 4559 "csiphy3", 4560 "csid0", 4561 "vfe0", 4562 "csid1", 4563 "vfe1", 4564 "csid0_lite", 4565 "vfe_lite0", 4566 "csiphy0", 4567 "csiphy1", 4568 "csiphy2", 4569 "csid2", 4570 "vfe2", 4571 "csid3_lite", 4572 "csid2_lite", 4573 "vfe_lite3", 4574 "vfe_lite2", 4575 "csid3", 4576 "vfe3"; 4577 4578 power-domains = <&camcc IFE_0_GDSC>, 4579 <&camcc IFE_1_GDSC>, 4580 <&camcc IFE_2_GDSC>, 4581 <&camcc IFE_3_GDSC>, 4582 <&camcc TITAN_TOP_GDSC>; 4583 power-domain-names = "ife0", 4584 "ife1", 4585 "ife2", 4586 "ife3", 4587 "top"; 4588 4589 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4590 <&camcc CAMCC_CPAS_AHB_CLK>, 4591 <&camcc CAMCC_CSIPHY0_CLK>, 4592 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4593 <&camcc CAMCC_CSIPHY1_CLK>, 4594 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4595 <&camcc CAMCC_CSIPHY2_CLK>, 4596 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4597 <&camcc CAMCC_CSIPHY3_CLK>, 4598 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4599 <&camcc CAMCC_IFE_0_AXI_CLK>, 4600 <&camcc CAMCC_IFE_0_CLK>, 4601 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4602 <&camcc CAMCC_IFE_0_CSID_CLK>, 4603 <&camcc CAMCC_IFE_1_AXI_CLK>, 4604 <&camcc CAMCC_IFE_1_CLK>, 4605 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4606 <&camcc CAMCC_IFE_1_CSID_CLK>, 4607 <&camcc CAMCC_IFE_2_AXI_CLK>, 4608 <&camcc CAMCC_IFE_2_CLK>, 4609 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4610 <&camcc CAMCC_IFE_2_CSID_CLK>, 4611 <&camcc CAMCC_IFE_3_AXI_CLK>, 4612 <&camcc CAMCC_IFE_3_CLK>, 4613 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4614 <&camcc CAMCC_IFE_3_CSID_CLK>, 4615 <&camcc CAMCC_IFE_LITE_0_CLK>, 4616 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4617 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4618 <&camcc CAMCC_IFE_LITE_1_CLK>, 4619 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4620 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4621 <&camcc CAMCC_IFE_LITE_2_CLK>, 4622 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4623 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4624 <&camcc CAMCC_IFE_LITE_3_CLK>, 4625 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4626 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4627 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4628 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4629 clock-names = "camnoc_axi", 4630 "cpas_ahb", 4631 "csiphy0", 4632 "csiphy0_timer", 4633 "csiphy1", 4634 "csiphy1_timer", 4635 "csiphy2", 4636 "csiphy2_timer", 4637 "csiphy3", 4638 "csiphy3_timer", 4639 "vfe0_axi", 4640 "vfe0", 4641 "vfe0_cphy_rx", 4642 "vfe0_csid", 4643 "vfe1_axi", 4644 "vfe1", 4645 "vfe1_cphy_rx", 4646 "vfe1_csid", 4647 "vfe2_axi", 4648 "vfe2", 4649 "vfe2_cphy_rx", 4650 "vfe2_csid", 4651 "vfe3_axi", 4652 "vfe3", 4653 "vfe3_cphy_rx", 4654 "vfe3_csid", 4655 "vfe_lite0", 4656 "vfe_lite0_cphy_rx", 4657 "vfe_lite0_csid", 4658 "vfe_lite1", 4659 "vfe_lite1_cphy_rx", 4660 "vfe_lite1_csid", 4661 "vfe_lite2", 4662 "vfe_lite2_cphy_rx", 4663 "vfe_lite2_csid", 4664 "vfe_lite3", 4665 "vfe_lite3_cphy_rx", 4666 "vfe_lite3_csid", 4667 "gcc_axi_hf", 4668 "gcc_axi_sf"; 4669 4670 iommus = <&apps_smmu 0x2000 0x4e0>, 4671 <&apps_smmu 0x2020 0x4e0>, 4672 <&apps_smmu 0x2040 0x4e0>, 4673 <&apps_smmu 0x2060 0x4e0>, 4674 <&apps_smmu 0x2080 0x4e0>, 4675 <&apps_smmu 0x20e0 0x4e0>, 4676 <&apps_smmu 0x20c0 0x4e0>, 4677 <&apps_smmu 0x20a0 0x4e0>, 4678 <&apps_smmu 0x2400 0x4e0>, 4679 <&apps_smmu 0x2420 0x4e0>, 4680 <&apps_smmu 0x2440 0x4e0>, 4681 <&apps_smmu 0x2460 0x4e0>, 4682 <&apps_smmu 0x2480 0x4e0>, 4683 <&apps_smmu 0x24e0 0x4e0>, 4684 <&apps_smmu 0x24c0 0x4e0>, 4685 <&apps_smmu 0x24a0 0x4e0>; 4686 4687 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4688 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4689 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4690 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4691 interconnect-names = "cam_ahb", 4692 "cam_hf_mnoc", 4693 "cam_sf_mnoc", 4694 "cam_sf_icp_mnoc"; 4695 4696 status = "disabled"; 4697 4698 ports { 4699 #address-cells = <1>; 4700 #size-cells = <0>; 4701 4702 port@0 { 4703 reg = <0>; 4704 #address-cells = <1>; 4705 #size-cells = <0>; 4706 }; 4707 4708 port@1 { 4709 reg = <1>; 4710 #address-cells = <1>; 4711 #size-cells = <0>; 4712 }; 4713 4714 port@2 { 4715 reg = <2>; 4716 #address-cells = <1>; 4717 #size-cells = <0>; 4718 }; 4719 4720 port@3 { 4721 reg = <3>; 4722 #address-cells = <1>; 4723 #size-cells = <0>; 4724 }; 4725 }; 4726 }; 4727 4728 camcc: clock-controller@ad00000 { 4729 compatible = "qcom,sc8280xp-camcc"; 4730 reg = <0 0x0ad00000 0 0x20000>; 4731 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4732 <&rpmhcc RPMH_CXO_CLK>, 4733 <&rpmhcc RPMH_CXO_CLK_A>, 4734 <&sleep_clk>; 4735 power-domains = <&rpmhpd SC8280XP_MMCX>; 4736 required-opps = <&rpmhpd_opp_low_svs>; 4737 #clock-cells = <1>; 4738 #reset-cells = <1>; 4739 #power-domain-cells = <1>; 4740 }; 4741 4742 mdss0: display-subsystem@ae00000 { 4743 compatible = "qcom,sc8280xp-mdss"; 4744 reg = <0 0x0ae00000 0 0x1000>; 4745 reg-names = "mdss"; 4746 4747 clocks = <&gcc GCC_DISP_AHB_CLK>, 4748 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4749 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4750 clock-names = "iface", 4751 "ahb", 4752 "core"; 4753 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4754 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4755 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4756 interconnect-names = "mdp0-mem", "mdp1-mem"; 4757 iommus = <&apps_smmu 0x1000 0x402>; 4758 power-domains = <&dispcc0 MDSS_GDSC>; 4759 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4760 4761 interrupt-controller; 4762 #interrupt-cells = <1>; 4763 #address-cells = <2>; 4764 #size-cells = <2>; 4765 ranges; 4766 4767 status = "disabled"; 4768 4769 mdss0_mdp: display-controller@ae01000 { 4770 compatible = "qcom,sc8280xp-dpu"; 4771 reg = <0 0x0ae01000 0 0x8f000>, 4772 <0 0x0aeb0000 0 0x3000>; 4773 reg-names = "mdp", "vbif"; 4774 4775 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4776 <&gcc GCC_DISP_SF_AXI_CLK>, 4777 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4778 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4779 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4780 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4781 clock-names = "bus", 4782 "nrt_bus", 4783 "iface", 4784 "lut", 4785 "core", 4786 "vsync"; 4787 interrupt-parent = <&mdss0>; 4788 interrupts = <0>; 4789 power-domains = <&rpmhpd SC8280XP_MMCX>; 4790 4791 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4792 assigned-clock-rates = <19200000>; 4793 operating-points-v2 = <&mdss0_mdp_opp_table>; 4794 4795 ports { 4796 #address-cells = <1>; 4797 #size-cells = <0>; 4798 4799 port@0 { 4800 reg = <0>; 4801 4802 mdss0_intf0_out: endpoint { 4803 remote-endpoint = <&mdss0_dp0_in>; 4804 }; 4805 }; 4806 4807 port@1 { 4808 reg = <1>; 4809 4810 mdss0_intf1_out: endpoint { 4811 remote-endpoint = <&mdss0_dsi0_in>; 4812 }; 4813 }; 4814 4815 port@2 { 4816 reg = <2>; 4817 4818 mdss0_intf2_out: endpoint { 4819 remote-endpoint = <&mdss0_dsi1_in>; 4820 }; 4821 }; 4822 4823 port@4 { 4824 reg = <4>; 4825 4826 mdss0_intf4_out: endpoint { 4827 remote-endpoint = <&mdss0_dp1_in>; 4828 }; 4829 }; 4830 4831 port@5 { 4832 reg = <5>; 4833 4834 mdss0_intf5_out: endpoint { 4835 remote-endpoint = <&mdss0_dp3_in>; 4836 }; 4837 }; 4838 4839 port@6 { 4840 reg = <6>; 4841 4842 mdss0_intf6_out: endpoint { 4843 remote-endpoint = <&mdss0_dp2_in>; 4844 }; 4845 }; 4846 }; 4847 4848 mdss0_mdp_opp_table: opp-table { 4849 compatible = "operating-points-v2"; 4850 4851 opp-200000000 { 4852 opp-hz = /bits/ 64 <200000000>; 4853 required-opps = <&rpmhpd_opp_low_svs>; 4854 }; 4855 4856 opp-300000000 { 4857 opp-hz = /bits/ 64 <300000000>; 4858 required-opps = <&rpmhpd_opp_svs>; 4859 }; 4860 4861 opp-375000000 { 4862 opp-hz = /bits/ 64 <375000000>; 4863 required-opps = <&rpmhpd_opp_svs_l1>; 4864 }; 4865 4866 opp-500000000 { 4867 opp-hz = /bits/ 64 <500000000>; 4868 required-opps = <&rpmhpd_opp_nom>; 4869 }; 4870 opp-600000000 { 4871 opp-hz = /bits/ 64 <600000000>; 4872 required-opps = <&rpmhpd_opp_turbo_l1>; 4873 }; 4874 }; 4875 }; 4876 4877 mdss0_dp0: displayport-controller@ae90000 { 4878 compatible = "qcom,sc8280xp-dp"; 4879 reg = <0 0xae90000 0 0x200>, 4880 <0 0xae90200 0 0x200>, 4881 <0 0xae90400 0 0x600>, 4882 <0 0xae91000 0 0x400>, 4883 <0 0xae91400 0 0x400>; 4884 interrupt-parent = <&mdss0>; 4885 interrupts = <12>; 4886 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4887 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4888 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4889 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4890 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4891 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4892 clock-names = "core_iface", "core_aux", 4893 "ctrl_link", 4894 "ctrl_link_iface", 4895 "stream_pixel", 4896 "stream_1_pixel"; 4897 4898 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4899 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4900 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4901 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4902 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4903 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4904 4905 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4906 phy-names = "dp"; 4907 4908 #sound-dai-cells = <0>; 4909 4910 operating-points-v2 = <&mdss0_dp0_opp_table>; 4911 power-domains = <&rpmhpd SC8280XP_MMCX>; 4912 4913 status = "disabled"; 4914 4915 ports { 4916 #address-cells = <1>; 4917 #size-cells = <0>; 4918 4919 port@0 { 4920 reg = <0>; 4921 4922 mdss0_dp0_in: endpoint { 4923 remote-endpoint = <&mdss0_intf0_out>; 4924 }; 4925 }; 4926 4927 port@1 { 4928 reg = <1>; 4929 4930 mdss0_dp0_out: endpoint { 4931 }; 4932 }; 4933 }; 4934 4935 mdss0_dp0_opp_table: opp-table { 4936 compatible = "operating-points-v2"; 4937 4938 opp-162000000 { 4939 opp-hz = /bits/ 64 <162000000>; 4940 required-opps = <&rpmhpd_opp_low_svs>; 4941 }; 4942 4943 opp-270000000 { 4944 opp-hz = /bits/ 64 <270000000>; 4945 required-opps = <&rpmhpd_opp_svs>; 4946 }; 4947 4948 opp-540000000 { 4949 opp-hz = /bits/ 64 <540000000>; 4950 required-opps = <&rpmhpd_opp_svs_l1>; 4951 }; 4952 4953 opp-810000000 { 4954 opp-hz = /bits/ 64 <810000000>; 4955 required-opps = <&rpmhpd_opp_nom>; 4956 }; 4957 }; 4958 }; 4959 4960 mdss0_dsi0: dsi@ae94000 { 4961 compatible = "qcom,sc8280xp-dsi-ctrl", 4962 "qcom,sa8775p-dsi-ctrl", 4963 "qcom,mdss-dsi-ctrl"; 4964 reg = <0 0x0ae94000 0 0x400>; 4965 reg-names = "dsi_ctrl"; 4966 4967 interrupt-parent = <&mdss0>; 4968 interrupts = <4>; 4969 4970 clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, 4971 <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, 4972 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, 4973 <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, 4974 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4975 <&gcc GCC_DISP_HF_AXI_CLK>; 4976 clock-names = "byte", 4977 "byte_intf", 4978 "pixel", 4979 "core", 4980 "iface", 4981 "bus"; 4982 4983 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, 4984 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; 4985 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4986 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4987 4988 operating-points-v2 = <&dsi_opp_table>; 4989 power-domains = <&rpmhpd SC8280XP_MMCX>; 4990 4991 refgen-supply = <&refgen>; 4992 4993 phys = <&mdss0_dsi0_phy>; 4994 phy-names = "dsi"; 4995 4996 #address-cells = <1>; 4997 #size-cells = <0>; 4998 4999 status = "disabled"; 5000 5001 ports { 5002 #address-cells = <1>; 5003 #size-cells = <0>; 5004 5005 port@0 { 5006 reg = <0>; 5007 5008 mdss0_dsi0_in: endpoint { 5009 remote-endpoint = <&mdss0_intf1_out>; 5010 }; 5011 }; 5012 5013 port@1 { 5014 reg = <1>; 5015 5016 mdss0_dsi0_out: endpoint { 5017 }; 5018 }; 5019 }; 5020 5021 dsi_opp_table: opp-table { 5022 compatible = "operating-points-v2"; 5023 5024 opp-187500000 { 5025 opp-hz = /bits/ 64 <187500000>; 5026 required-opps = <&rpmhpd_opp_low_svs>; 5027 }; 5028 5029 opp-300000000 { 5030 opp-hz = /bits/ 64 <300000000>; 5031 required-opps = <&rpmhpd_opp_svs>; 5032 }; 5033 5034 opp-358000000 { 5035 opp-hz = /bits/ 64 <358000000>; 5036 required-opps = <&rpmhpd_opp_svs_l1>; 5037 }; 5038 }; 5039 }; 5040 5041 mdss0_dsi0_phy: phy@ae94400 { 5042 compatible = "qcom,sc8280xp-dsi-phy-5nm", 5043 "qcom,sa8775p-dsi-phy-5nm"; 5044 reg = <0 0x0ae94400 0 0x200>, 5045 <0 0x0ae94600 0 0x280>, 5046 <0 0x0ae94900 0 0x280>; 5047 reg-names = "dsi_phy", 5048 "dsi_phy_lane", 5049 "dsi_pll"; 5050 5051 #clock-cells = <1>; 5052 #phy-cells = <0>; 5053 5054 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5055 <&rpmhcc RPMH_CXO_CLK>; 5056 clock-names = "iface", "ref"; 5057 5058 status = "disabled"; 5059 }; 5060 5061 mdss0_dsi1: dsi@ae96000 { 5062 compatible = "qcom,sc8280xp-dsi-ctrl", 5063 "qcom,sa8775p-dsi-ctrl", 5064 "qcom,mdss-dsi-ctrl"; 5065 reg = <0 0x0ae96000 0 0x400>; 5066 reg-names = "dsi_ctrl"; 5067 5068 interrupt-parent = <&mdss0>; 5069 interrupts = <5>; 5070 5071 clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, 5072 <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, 5073 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, 5074 <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, 5075 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5076 <&gcc GCC_DISP_HF_AXI_CLK>; 5077 clock-names = "byte", 5078 "byte_intf", 5079 "pixel", 5080 "core", 5081 "iface", 5082 "bus"; 5083 5084 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, 5085 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; 5086 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5087 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5088 5089 operating-points-v2 = <&dsi_opp_table>; 5090 power-domains = <&rpmhpd SC8280XP_MMCX>; 5091 5092 refgen-supply = <&refgen>; 5093 5094 phys = <&mdss0_dsi1_phy>; 5095 phy-names = "dsi"; 5096 5097 #address-cells = <1>; 5098 #size-cells = <0>; 5099 5100 status = "disabled"; 5101 5102 ports { 5103 #address-cells = <1>; 5104 #size-cells = <0>; 5105 5106 port@0 { 5107 reg = <0>; 5108 5109 mdss0_dsi1_in: endpoint { 5110 remote-endpoint = <&mdss0_intf2_out>; 5111 }; 5112 }; 5113 5114 port@1 { 5115 reg = <1>; 5116 5117 mdss0_dsi1_out: endpoint { 5118 }; 5119 }; 5120 }; 5121 }; 5122 5123 mdss0_dsi1_phy: phy@ae96400 { 5124 compatible = "qcom,sc8280xp-dsi-phy-5nm", 5125 "qcom,sa8775p-dsi-phy-5nm"; 5126 reg = <0 0x0ae96400 0 0x200>, 5127 <0 0x0ae96600 0 0x280>, 5128 <0 0x0ae96900 0 0x280>; 5129 reg-names = "dsi_phy", 5130 "dsi_phy_lane", 5131 "dsi_pll"; 5132 5133 #clock-cells = <1>; 5134 #phy-cells = <0>; 5135 5136 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5137 <&rpmhcc RPMH_CXO_CLK>; 5138 clock-names = "iface", "ref"; 5139 5140 status = "disabled"; 5141 }; 5142 5143 mdss0_dp1: displayport-controller@ae98000 { 5144 compatible = "qcom,sc8280xp-dp"; 5145 reg = <0 0xae98000 0 0x200>, 5146 <0 0xae98200 0 0x200>, 5147 <0 0xae98400 0 0x600>, 5148 <0 0xae99000 0 0x400>, 5149 <0 0xae99400 0 0x400>; 5150 interrupt-parent = <&mdss0>; 5151 interrupts = <13>; 5152 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5153 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5154 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5155 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5156 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5157 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5158 clock-names = "core_iface", "core_aux", 5159 "ctrl_link", 5160 "ctrl_link_iface", "stream_pixel", 5161 "stream_1_pixel"; 5162 5163 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5164 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5165 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5166 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5167 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5168 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5169 5170 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5171 phy-names = "dp"; 5172 5173 #sound-dai-cells = <0>; 5174 5175 operating-points-v2 = <&mdss0_dp1_opp_table>; 5176 power-domains = <&rpmhpd SC8280XP_MMCX>; 5177 5178 status = "disabled"; 5179 5180 ports { 5181 #address-cells = <1>; 5182 #size-cells = <0>; 5183 5184 port@0 { 5185 reg = <0>; 5186 5187 mdss0_dp1_in: endpoint { 5188 remote-endpoint = <&mdss0_intf4_out>; 5189 }; 5190 }; 5191 5192 port@1 { 5193 reg = <1>; 5194 5195 mdss0_dp1_out: endpoint { 5196 }; 5197 }; 5198 }; 5199 5200 mdss0_dp1_opp_table: opp-table { 5201 compatible = "operating-points-v2"; 5202 5203 opp-162000000 { 5204 opp-hz = /bits/ 64 <162000000>; 5205 required-opps = <&rpmhpd_opp_low_svs>; 5206 }; 5207 5208 opp-270000000 { 5209 opp-hz = /bits/ 64 <270000000>; 5210 required-opps = <&rpmhpd_opp_svs>; 5211 }; 5212 5213 opp-540000000 { 5214 opp-hz = /bits/ 64 <540000000>; 5215 required-opps = <&rpmhpd_opp_svs_l1>; 5216 }; 5217 5218 opp-810000000 { 5219 opp-hz = /bits/ 64 <810000000>; 5220 required-opps = <&rpmhpd_opp_nom>; 5221 }; 5222 }; 5223 }; 5224 5225 mdss0_dp2: displayport-controller@ae9a000 { 5226 compatible = "qcom,sc8280xp-dp"; 5227 reg = <0 0xae9a000 0 0x200>, 5228 <0 0xae9a200 0 0x200>, 5229 <0 0xae9a400 0 0x600>, 5230 <0 0xae9b000 0 0x400>, 5231 <0 0xae9b400 0 0x400>; 5232 5233 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5234 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5235 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5236 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5237 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5238 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5239 clock-names = "core_iface", "core_aux", 5240 "ctrl_link", 5241 "ctrl_link_iface", "stream_pixel", 5242 "stream_1_pixel"; 5243 interrupt-parent = <&mdss0>; 5244 interrupts = <14>; 5245 phys = <&mdss0_dp2_phy>; 5246 phy-names = "dp"; 5247 power-domains = <&rpmhpd SC8280XP_MMCX>; 5248 5249 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5250 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5251 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5252 assigned-clock-parents = <&mdss0_dp2_phy 0>, 5253 <&mdss0_dp2_phy 1>, 5254 <&mdss0_dp2_phy 1>; 5255 operating-points-v2 = <&mdss0_dp2_opp_table>; 5256 5257 #sound-dai-cells = <0>; 5258 5259 status = "disabled"; 5260 5261 ports { 5262 #address-cells = <1>; 5263 #size-cells = <0>; 5264 5265 port@0 { 5266 reg = <0>; 5267 mdss0_dp2_in: endpoint { 5268 remote-endpoint = <&mdss0_intf6_out>; 5269 }; 5270 }; 5271 5272 port@1 { 5273 reg = <1>; 5274 5275 mdss0_dp2_out: endpoint { 5276 }; 5277 }; 5278 }; 5279 5280 mdss0_dp2_opp_table: opp-table { 5281 compatible = "operating-points-v2"; 5282 5283 opp-162000000 { 5284 opp-hz = /bits/ 64 <162000000>; 5285 required-opps = <&rpmhpd_opp_low_svs>; 5286 }; 5287 5288 opp-270000000 { 5289 opp-hz = /bits/ 64 <270000000>; 5290 required-opps = <&rpmhpd_opp_svs>; 5291 }; 5292 5293 opp-540000000 { 5294 opp-hz = /bits/ 64 <540000000>; 5295 required-opps = <&rpmhpd_opp_svs_l1>; 5296 }; 5297 5298 opp-810000000 { 5299 opp-hz = /bits/ 64 <810000000>; 5300 required-opps = <&rpmhpd_opp_nom>; 5301 }; 5302 }; 5303 }; 5304 5305 mdss0_dp3: displayport-controller@aea0000 { 5306 compatible = "qcom,sc8280xp-dp"; 5307 reg = <0 0xaea0000 0 0x200>, 5308 <0 0xaea0200 0 0x200>, 5309 <0 0xaea0400 0 0x600>, 5310 <0 0xaea1000 0 0x400>, 5311 <0 0xaea1400 0 0x400>; 5312 5313 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5314 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5315 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5316 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5317 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5318 clock-names = "core_iface", "core_aux", 5319 "ctrl_link", 5320 "ctrl_link_iface", "stream_pixel"; 5321 interrupt-parent = <&mdss0>; 5322 interrupts = <15>; 5323 phys = <&mdss0_dp3_phy>; 5324 phy-names = "dp"; 5325 power-domains = <&rpmhpd SC8280XP_MMCX>; 5326 5327 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5328 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5329 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 5330 operating-points-v2 = <&mdss0_dp3_opp_table>; 5331 5332 #sound-dai-cells = <0>; 5333 5334 status = "disabled"; 5335 5336 ports { 5337 #address-cells = <1>; 5338 #size-cells = <0>; 5339 5340 port@0 { 5341 reg = <0>; 5342 mdss0_dp3_in: endpoint { 5343 remote-endpoint = <&mdss0_intf5_out>; 5344 }; 5345 }; 5346 5347 port@1 { 5348 reg = <1>; 5349 5350 mdss0_dp3_out: endpoint { 5351 }; 5352 }; 5353 }; 5354 5355 mdss0_dp3_opp_table: opp-table { 5356 compatible = "operating-points-v2"; 5357 5358 opp-162000000 { 5359 opp-hz = /bits/ 64 <162000000>; 5360 required-opps = <&rpmhpd_opp_low_svs>; 5361 }; 5362 5363 opp-270000000 { 5364 opp-hz = /bits/ 64 <270000000>; 5365 required-opps = <&rpmhpd_opp_svs>; 5366 }; 5367 5368 opp-540000000 { 5369 opp-hz = /bits/ 64 <540000000>; 5370 required-opps = <&rpmhpd_opp_svs_l1>; 5371 }; 5372 5373 opp-810000000 { 5374 opp-hz = /bits/ 64 <810000000>; 5375 required-opps = <&rpmhpd_opp_nom>; 5376 }; 5377 }; 5378 }; 5379 }; 5380 5381 mdss0_dp2_phy: phy@aec2a00 { 5382 compatible = "qcom,sc8280xp-dp-phy"; 5383 reg = <0 0x0aec2a00 0 0x19c>, 5384 <0 0x0aec2200 0 0xec>, 5385 <0 0x0aec2600 0 0xec>, 5386 <0 0x0aec2000 0 0x1c8>; 5387 5388 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5389 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5390 clock-names = "aux", "cfg_ahb"; 5391 power-domains = <&rpmhpd SC8280XP_MX>; 5392 5393 #clock-cells = <1>; 5394 #phy-cells = <0>; 5395 5396 status = "disabled"; 5397 }; 5398 5399 mdss0_dp3_phy: phy@aec5a00 { 5400 compatible = "qcom,sc8280xp-dp-phy"; 5401 reg = <0 0x0aec5a00 0 0x19c>, 5402 <0 0x0aec5200 0 0xec>, 5403 <0 0x0aec5600 0 0xec>, 5404 <0 0x0aec5000 0 0x1c8>; 5405 5406 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5407 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5408 clock-names = "aux", "cfg_ahb"; 5409 power-domains = <&rpmhpd SC8280XP_MX>; 5410 5411 #clock-cells = <1>; 5412 #phy-cells = <0>; 5413 5414 status = "disabled"; 5415 }; 5416 5417 dispcc0: clock-controller@af00000 { 5418 compatible = "qcom,sc8280xp-dispcc0"; 5419 reg = <0 0x0af00000 0 0x20000>; 5420 5421 clocks = <&gcc GCC_DISP_AHB_CLK>, 5422 <&rpmhcc RPMH_CXO_CLK>, 5423 <&sleep_clk>, 5424 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5425 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5426 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5427 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5428 <&mdss0_dp2_phy 0>, 5429 <&mdss0_dp2_phy 1>, 5430 <&mdss0_dp3_phy 0>, 5431 <&mdss0_dp3_phy 1>, 5432 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5433 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5434 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5435 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5436 power-domains = <&rpmhpd SC8280XP_MMCX>; 5437 5438 #clock-cells = <1>; 5439 #power-domain-cells = <1>; 5440 #reset-cells = <1>; 5441 5442 status = "disabled"; 5443 }; 5444 5445 pdc: interrupt-controller@b220000 { 5446 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 5447 reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>; 5448 qcom,pdc-ranges = <0 480 40>, 5449 <40 140 14>, 5450 <54 263 1>, 5451 <55 306 4>, 5452 <59 312 3>, 5453 <62 374 2>, 5454 <64 434 2>, 5455 <66 438 3>, 5456 <69 86 1>, 5457 <70 520 54>, 5458 <124 609 28>, 5459 <159 638 1>, 5460 <160 720 8>, 5461 <168 801 1>, 5462 <169 728 30>, 5463 <199 416 2>, 5464 <201 449 1>, 5465 <202 89 1>, 5466 <203 451 1>, 5467 <204 462 1>, 5468 <205 264 1>, 5469 <206 579 1>, 5470 <207 653 1>, 5471 <208 656 1>, 5472 <209 659 1>, 5473 <210 122 1>, 5474 <211 699 1>, 5475 <212 705 1>, 5476 <213 450 1>, 5477 <214 643 2>, 5478 <216 646 5>, 5479 <221 390 5>, 5480 <226 700 3>, 5481 <229 240 3>, 5482 <232 269 1>, 5483 <233 377 1>, 5484 <234 372 1>, 5485 <235 138 1>, 5486 <236 857 1>, 5487 <237 860 1>, 5488 <238 137 1>, 5489 <239 668 1>, 5490 <240 366 1>, 5491 <241 949 1>, 5492 <242 815 5>, 5493 <247 769 1>, 5494 <248 768 1>, 5495 <249 663 1>, 5496 <250 799 2>, 5497 <252 798 1>, 5498 <253 765 1>, 5499 <254 763 1>, 5500 <255 454 3>, 5501 <258 139 1>, 5502 <259 786 2>, 5503 <261 370 2>, 5504 <263 158 2>; 5505 #interrupt-cells = <2>; 5506 interrupt-parent = <&intc>; 5507 interrupt-controller; 5508 }; 5509 5510 tsens2: thermal-sensor@c251000 { 5511 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5512 reg = <0 0x0c251000 0 0x1ff>, 5513 <0 0x0c224000 0 0x8>; 5514 #qcom,sensors = <11>; 5515 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 5516 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 5517 interrupt-names = "uplow", "critical"; 5518 #thermal-sensor-cells = <1>; 5519 }; 5520 5521 tsens3: thermal-sensor@c252000 { 5522 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5523 reg = <0 0x0c252000 0 0x1ff>, 5524 <0 0x0c225000 0 0x8>; 5525 #qcom,sensors = <5>; 5526 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 5527 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 5528 interrupt-names = "uplow", "critical"; 5529 #thermal-sensor-cells = <1>; 5530 }; 5531 5532 tsens0: thermal-sensor@c263000 { 5533 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5534 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5535 <0 0x0c222000 0 0x8>; /* SROT */ 5536 #qcom,sensors = <14>; 5537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 5538 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 5539 interrupt-names = "uplow", "critical"; 5540 #thermal-sensor-cells = <1>; 5541 }; 5542 5543 restart@c264000 { 5544 compatible = "qcom,pshold"; 5545 reg = <0 0x0c264000 0 0x4>; 5546 /* TZ seems to block access */ 5547 status = "reserved"; 5548 }; 5549 5550 tsens1: thermal-sensor@c265000 { 5551 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5552 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5553 <0 0x0c223000 0 0x8>; /* SROT */ 5554 #qcom,sensors = <16>; 5555 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 5556 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 5557 interrupt-names = "uplow", "critical"; 5558 #thermal-sensor-cells = <1>; 5559 }; 5560 5561 aoss_qmp: power-management@c300000 { 5562 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 5563 reg = <0 0x0c300000 0 0x400>; 5564 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 5565 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5566 5567 #clock-cells = <0>; 5568 }; 5569 5570 sram@c3f0000 { 5571 compatible = "qcom,rpmh-stats"; 5572 reg = <0 0x0c3f0000 0 0x400>; 5573 qcom,qmp = <&aoss_qmp>; 5574 }; 5575 5576 spmi_bus: spmi@c440000 { 5577 compatible = "qcom,spmi-pmic-arb"; 5578 reg = <0 0x0c440000 0 0x1100>, 5579 <0 0x0c600000 0 0x2000000>, 5580 <0 0x0e600000 0 0x100000>, 5581 <0 0x0e700000 0 0xa0000>, 5582 <0 0x0c40a000 0 0x26000>; 5583 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5584 interrupt-names = "periph_irq"; 5585 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5586 qcom,ee = <0>; 5587 qcom,channel = <0>; 5588 #address-cells = <2>; 5589 #size-cells = <0>; 5590 interrupt-controller; 5591 #interrupt-cells = <4>; 5592 }; 5593 5594 tlmm: pinctrl@f100000 { 5595 compatible = "qcom,sc8280xp-tlmm"; 5596 reg = <0 0x0f100000 0 0x300000>; 5597 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5598 gpio-controller; 5599 #gpio-cells = <2>; 5600 interrupt-controller; 5601 #interrupt-cells = <2>; 5602 gpio-ranges = <&tlmm 0 0 230>; 5603 wakeup-parent = <&pdc>; 5604 5605 cam_mclk0_default: cam-mclk0-default-state { 5606 pins = "gpio119"; 5607 function = "cam_mclk"; 5608 drive-strength = <6>; 5609 bias-disable; 5610 }; 5611 5612 cam_mclk1_default: cam-mclk1-default-state { 5613 pins = "gpio120"; 5614 function = "cam_mclk"; 5615 drive-strength = <6>; 5616 bias-disable; 5617 }; 5618 5619 cam_mclk2_default: cam-mclk2-default-state { 5620 pins = "gpio16"; 5621 function = "cam_mclk"; 5622 drive-strength = <6>; 5623 bias-disable; 5624 }; 5625 5626 cam_mclk3_default: cam-mclk3-default-state { 5627 pins = "gpio17"; 5628 function = "cam_mclk"; 5629 drive-strength = <6>; 5630 bias-disable; 5631 }; 5632 5633 cam_mclk4_default: cam-mclk4-default-state { 5634 pins = "gpio6"; 5635 function = "cam_mclk"; 5636 drive-strength = <6>; 5637 bias-disable; 5638 }; 5639 5640 cam_mclk5_default: cam-mclk5-default-state { 5641 pins = "gpio7"; 5642 function = "cam_mclk"; 5643 drive-strength = <6>; 5644 bias-disable; 5645 }; 5646 5647 cam_mclk6_default: cam-mclk6-default-state { 5648 pins = "gpio33"; 5649 function = "cam_mclk"; 5650 drive-strength = <6>; 5651 bias-disable; 5652 }; 5653 5654 cam_mclk7_default: cam-mclk7-default-state { 5655 pins = "gpio34"; 5656 function = "cam_mclk"; 5657 drive-strength = <6>; 5658 bias-disable; 5659 }; 5660 5661 cci0_default: cci0-default-state { 5662 cci0_i2c0_default: cci0-i2c0-default-pins { 5663 /* cci_i2c_sda0, cci_i2c_scl0 */ 5664 pins = "gpio113", "gpio114"; 5665 function = "cci_i2c"; 5666 drive-strength = <2>; 5667 bias-pull-up; 5668 }; 5669 5670 cci0_i2c1_default: cci0-i2c1-default-pins { 5671 /* cci_i2c_sda1, cci_i2c_scl1 */ 5672 pins = "gpio115", "gpio116"; 5673 function = "cci_i2c"; 5674 drive-strength = <2>; 5675 bias-pull-up; 5676 }; 5677 }; 5678 5679 cci0_sleep: cci0-sleep-state { 5680 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5681 /* cci_i2c_sda0, cci_i2c_scl0 */ 5682 pins = "gpio113", "gpio114"; 5683 function = "cci_i2c"; 5684 drive-strength = <2>; 5685 bias-pull-down; 5686 }; 5687 5688 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5689 /* cci_i2c_sda1, cci_i2c_scl1 */ 5690 pins = "gpio115", "gpio116"; 5691 function = "cci_i2c"; 5692 drive-strength = <2>; 5693 bias-pull-down; 5694 }; 5695 }; 5696 5697 cci1_default: cci1-default-state { 5698 cci1_i2c0_default: cci1-i2c0-default-pins { 5699 /* cci_i2c_sda2, cci_i2c_scl2 */ 5700 pins = "gpio10","gpio11"; 5701 function = "cci_i2c"; 5702 drive-strength = <2>; 5703 bias-pull-up; 5704 }; 5705 5706 cci1_i2c1_default: cci1-i2c1-default-pins { 5707 /* cci_i2c_sda3, cci_i2c_scl3 */ 5708 pins = "gpio123","gpio124"; 5709 function = "cci_i2c"; 5710 drive-strength = <2>; 5711 bias-pull-up; 5712 }; 5713 }; 5714 5715 cci1_sleep: cci1-sleep-state { 5716 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5717 /* cci_i2c_sda2, cci_i2c_scl2 */ 5718 pins = "gpio10","gpio11"; 5719 function = "cci_i2c"; 5720 drive-strength = <2>; 5721 bias-pull-down; 5722 }; 5723 5724 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5725 /* cci_i2c_sda3, cci_i2c_scl3 */ 5726 pins = "gpio123","gpio124"; 5727 function = "cci_i2c"; 5728 drive-strength = <2>; 5729 bias-pull-down; 5730 }; 5731 }; 5732 5733 cci2_default: cci2-default-state { 5734 cci2_i2c0_default: cci2-i2c0-default-pins { 5735 /* cci_i2c_sda4, cci_i2c_scl4 */ 5736 pins = "gpio117","gpio118"; 5737 function = "cci_i2c"; 5738 drive-strength = <2>; 5739 bias-pull-up; 5740 }; 5741 5742 cci2_i2c1_default: cci2-i2c1-default-pins { 5743 /* cci_i2c_sda5, cci_i2c_scl5 */ 5744 pins = "gpio12","gpio13"; 5745 function = "cci_i2c"; 5746 drive-strength = <2>; 5747 bias-pull-up; 5748 }; 5749 }; 5750 5751 cci2_sleep: cci2-sleep-state { 5752 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 5753 /* cci_i2c_sda4, cci_i2c_scl4 */ 5754 pins = "gpio117","gpio118"; 5755 function = "cci_i2c"; 5756 drive-strength = <2>; 5757 bias-pull-down; 5758 }; 5759 5760 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 5761 /* cci_i2c_sda5, cci_i2c_scl5 */ 5762 pins = "gpio12","gpio13"; 5763 function = "cci_i2c"; 5764 drive-strength = <2>; 5765 bias-pull-down; 5766 }; 5767 }; 5768 5769 cci3_default: cci3-default-state { 5770 cci3_i2c0_default: cci3-i2c0-default-pins { 5771 /* cci_i2c_sda6, cci_i2c_scl6 */ 5772 pins = "gpio145","gpio146"; 5773 function = "cci_i2c"; 5774 drive-strength = <2>; 5775 bias-pull-up; 5776 }; 5777 5778 cci3_i2c1_default: cci3-i2c1-default-pins { 5779 /* cci_i2c_sda7, cci_i2c_scl7 */ 5780 pins = "gpio164","gpio165"; 5781 function = "cci_i2c"; 5782 drive-strength = <2>; 5783 bias-pull-up; 5784 }; 5785 }; 5786 5787 cci3_sleep: cci3-sleep-state { 5788 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 5789 /* cci_i2c_sda6, cci_i2c_scl6 */ 5790 pins = "gpio145","gpio146"; 5791 function = "cci_i2c"; 5792 drive-strength = <2>; 5793 bias-pull-down; 5794 }; 5795 5796 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 5797 /* cci_i2c_sda7, cci_i2c_scl7 */ 5798 pins = "gpio164","gpio165"; 5799 function = "cci_i2c"; 5800 drive-strength = <2>; 5801 bias-pull-down; 5802 }; 5803 }; 5804 5805 qup_uart18_default: qup-uart18-default-state { 5806 cts-pins { 5807 pins = "gpio66"; 5808 function = "qup18"; 5809 drive-strength = <2>; 5810 bias-disable; 5811 }; 5812 5813 rts-pins { 5814 pins = "gpio67"; 5815 function = "qup18"; 5816 drive-strength = <2>; 5817 bias-disable; 5818 }; 5819 5820 tx-pins { 5821 pins = "gpio68"; 5822 function = "qup18"; 5823 drive-strength = <2>; 5824 bias-disable; 5825 }; 5826 5827 rx-pins { 5828 pins = "gpio69"; 5829 function = "qup18"; 5830 drive-strength = <2>; 5831 bias-disable; 5832 }; 5833 }; 5834 }; 5835 5836 pcie_smmu: iommu@14f80000 { 5837 compatible = "arm,smmu-v3"; 5838 reg = <0 0x14f80000 0 0x80000>; 5839 #iommu-cells = <1>; 5840 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5841 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5842 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5843 interrupt-names = "eventq", 5844 "gerror", 5845 "cmdq-sync"; 5846 dma-coherent; 5847 status = "reserved"; /* Controlled by QHEE. */ 5848 }; 5849 5850 apps_smmu: iommu@15000000 { 5851 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5852 reg = <0 0x15000000 0 0x100000>; 5853 #iommu-cells = <2>; 5854 #global-interrupts = <2>; 5855 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5856 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5960 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5961 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5962 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5963 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5964 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5965 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5966 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5967 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5968 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5969 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5970 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5971 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5972 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5973 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5974 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5975 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5976 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5977 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5978 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5979 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5980 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5981 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5982 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5983 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5984 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5985 dma-coherent; 5986 }; 5987 5988 intc: interrupt-controller@17a00000 { 5989 compatible = "arm,gic-v3"; 5990 interrupt-controller; 5991 #interrupt-cells = <3>; 5992 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5993 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5994 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5995 #redistributor-regions = <1>; 5996 redistributor-stride = <0 0x20000>; 5997 5998 #address-cells = <2>; 5999 #size-cells = <2>; 6000 ranges; 6001 6002 its: msi-controller@17a40000 { 6003 compatible = "arm,gic-v3-its"; 6004 reg = <0 0x17a40000 0 0x20000>; 6005 msi-controller; 6006 #msi-cells = <1>; 6007 }; 6008 }; 6009 6010 watchdog@17c10000 { 6011 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 6012 reg = <0 0x17c10000 0 0x1000>; 6013 clocks = <&sleep_clk>; 6014 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6015 }; 6016 6017 timer@17c20000 { 6018 compatible = "arm,armv7-timer-mem"; 6019 reg = <0x0 0x17c20000 0x0 0x1000>; 6020 #address-cells = <1>; 6021 #size-cells = <1>; 6022 ranges = <0x0 0x0 0x0 0x20000000>; 6023 6024 frame@17c21000 { 6025 frame-number = <0>; 6026 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6027 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6028 reg = <0x17c21000 0x1000>, 6029 <0x17c22000 0x1000>; 6030 }; 6031 6032 frame@17c23000 { 6033 frame-number = <1>; 6034 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6035 reg = <0x17c23000 0x1000>; 6036 status = "disabled"; 6037 }; 6038 6039 frame@17c25000 { 6040 frame-number = <2>; 6041 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6042 reg = <0x17c25000 0x1000>; 6043 status = "disabled"; 6044 }; 6045 6046 frame@17c27000 { 6047 frame-number = <3>; 6048 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6049 reg = <0x17c26000 0x1000>; 6050 status = "disabled"; 6051 }; 6052 6053 frame@17c29000 { 6054 frame-number = <4>; 6055 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6056 reg = <0x17c29000 0x1000>; 6057 status = "disabled"; 6058 }; 6059 6060 frame@17c2b000 { 6061 frame-number = <5>; 6062 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6063 reg = <0x17c2b000 0x1000>; 6064 status = "disabled"; 6065 }; 6066 6067 frame@17c2d000 { 6068 frame-number = <6>; 6069 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6070 reg = <0x17c2d000 0x1000>; 6071 status = "disabled"; 6072 }; 6073 }; 6074 6075 apps_rsc: rsc@18200000 { 6076 compatible = "qcom,rpmh-rsc"; 6077 reg = <0x0 0x18200000 0x0 0x10000>, 6078 <0x0 0x18210000 0x0 0x10000>, 6079 <0x0 0x18220000 0x0 0x10000>; 6080 reg-names = "drv-0", "drv-1", "drv-2"; 6081 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6082 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6083 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6084 qcom,tcs-offset = <0xd00>; 6085 qcom,drv-id = <2>; 6086 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6087 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6088 label = "apps_rsc"; 6089 power-domains = <&cluster_pd>; 6090 6091 apps_bcm_voter: bcm-voter { 6092 compatible = "qcom,bcm-voter"; 6093 }; 6094 6095 rpmhcc: clock-controller { 6096 compatible = "qcom,sc8280xp-rpmh-clk"; 6097 #clock-cells = <1>; 6098 clock-names = "xo"; 6099 clocks = <&xo_board_clk>; 6100 }; 6101 6102 rpmhpd: power-controller { 6103 compatible = "qcom,sc8280xp-rpmhpd"; 6104 #power-domain-cells = <1>; 6105 operating-points-v2 = <&rpmhpd_opp_table>; 6106 6107 rpmhpd_opp_table: opp-table { 6108 compatible = "operating-points-v2"; 6109 6110 rpmhpd_opp_ret: opp1 { 6111 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6112 }; 6113 6114 rpmhpd_opp_min_svs: opp2 { 6115 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6116 }; 6117 6118 rpmhpd_opp_low_svs: opp3 { 6119 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6120 }; 6121 6122 rpmhpd_opp_svs: opp4 { 6123 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6124 }; 6125 6126 rpmhpd_opp_svs_l1: opp5 { 6127 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6128 }; 6129 6130 rpmhpd_opp_nom: opp6 { 6131 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6132 }; 6133 6134 rpmhpd_opp_nom_l1: opp7 { 6135 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6136 }; 6137 6138 rpmhpd_opp_nom_l2: opp8 { 6139 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6140 }; 6141 6142 rpmhpd_opp_turbo: opp9 { 6143 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6144 }; 6145 6146 rpmhpd_opp_turbo_l1: opp10 { 6147 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6148 }; 6149 }; 6150 }; 6151 }; 6152 6153 epss_l3: interconnect@18590000 { 6154 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 6155 reg = <0 0x18590000 0 0x1000>; 6156 6157 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6158 clock-names = "xo", "alternate"; 6159 6160 #interconnect-cells = <1>; 6161 }; 6162 6163 cpufreq_hw: cpufreq@18591000 { 6164 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 6165 reg = <0 0x18591000 0 0x1000>, 6166 <0 0x18592000 0 0x1000>; 6167 reg-names = "freq-domain0", "freq-domain1"; 6168 6169 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6170 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6171 interrupt-names = "dcvsh-irq-0", 6172 "dcvsh-irq-1"; 6173 6174 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6175 clock-names = "xo", "alternate"; 6176 6177 #freq-domain-cells = <1>; 6178 #clock-cells = <1>; 6179 }; 6180 6181 nspa_noc: interconnect@1b0c0000 { 6182 compatible = "qcom,sc8280xp-nspa-noc"; 6183 reg = <0 0x1b0c0000 0 0x10000>; 6184 6185 #interconnect-cells = <2>; 6186 qcom,bcm-voters = <&apps_bcm_voter>; 6187 }; 6188 6189 remoteproc_nsp0: remoteproc@1b300000 { 6190 compatible = "qcom,sc8280xp-nsp0-pas"; 6191 reg = <0 0x1b300000 0 0x10000>; 6192 6193 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6194 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 6195 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 6196 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 6197 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 6198 interrupt-names = "wdog", "fatal", "ready", 6199 "handover", "stop-ack"; 6200 6201 clocks = <&rpmhcc RPMH_CXO_CLK>; 6202 clock-names = "xo"; 6203 6204 power-domains = <&rpmhpd SC8280XP_NSP>, 6205 <&rpmhpd SC8280XP_CX>, 6206 <&rpmhpd SC8280XP_MXC>; 6207 power-domain-names = "nsp", 6208 "cx", 6209 "mxc"; 6210 6211 memory-region = <&pil_nsp0_mem>; 6212 6213 qcom,smem-states = <&smp2p_nsp0_out 0>; 6214 qcom,smem-state-names = "stop"; 6215 6216 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 6217 6218 status = "disabled"; 6219 6220 glink-edge { 6221 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6222 IPCC_MPROC_SIGNAL_GLINK_QMP 6223 IRQ_TYPE_EDGE_RISING>; 6224 mboxes = <&ipcc IPCC_CLIENT_CDSP 6225 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6226 6227 label = "nsp0"; 6228 qcom,remote-pid = <5>; 6229 6230 fastrpc { 6231 compatible = "qcom,fastrpc"; 6232 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6233 label = "cdsp"; 6234 #address-cells = <1>; 6235 #size-cells = <0>; 6236 6237 compute-cb@1 { 6238 compatible = "qcom,fastrpc-compute-cb"; 6239 reg = <1>; 6240 iommus = <&apps_smmu 0x3181 0x0420>; 6241 dma-coherent; 6242 }; 6243 6244 compute-cb@2 { 6245 compatible = "qcom,fastrpc-compute-cb"; 6246 reg = <2>; 6247 iommus = <&apps_smmu 0x3182 0x0420>; 6248 dma-coherent; 6249 }; 6250 6251 compute-cb@3 { 6252 compatible = "qcom,fastrpc-compute-cb"; 6253 reg = <3>; 6254 iommus = <&apps_smmu 0x3183 0x0420>; 6255 dma-coherent; 6256 }; 6257 6258 compute-cb@4 { 6259 compatible = "qcom,fastrpc-compute-cb"; 6260 reg = <4>; 6261 iommus = <&apps_smmu 0x3184 0x0420>; 6262 dma-coherent; 6263 }; 6264 6265 compute-cb@5 { 6266 compatible = "qcom,fastrpc-compute-cb"; 6267 reg = <5>; 6268 iommus = <&apps_smmu 0x3185 0x0420>; 6269 dma-coherent; 6270 }; 6271 6272 compute-cb@6 { 6273 compatible = "qcom,fastrpc-compute-cb"; 6274 reg = <6>; 6275 iommus = <&apps_smmu 0x3186 0x0420>; 6276 dma-coherent; 6277 }; 6278 6279 compute-cb@7 { 6280 compatible = "qcom,fastrpc-compute-cb"; 6281 reg = <7>; 6282 iommus = <&apps_smmu 0x3187 0x0420>; 6283 dma-coherent; 6284 }; 6285 6286 compute-cb@8 { 6287 compatible = "qcom,fastrpc-compute-cb"; 6288 reg = <8>; 6289 iommus = <&apps_smmu 0x3188 0x0420>; 6290 dma-coherent; 6291 }; 6292 6293 compute-cb@9 { 6294 compatible = "qcom,fastrpc-compute-cb"; 6295 reg = <9>; 6296 iommus = <&apps_smmu 0x318b 0x0420>; 6297 dma-coherent; 6298 }; 6299 6300 compute-cb@10 { 6301 compatible = "qcom,fastrpc-compute-cb"; 6302 reg = <10>; 6303 iommus = <&apps_smmu 0x318b 0x0420>; 6304 dma-coherent; 6305 }; 6306 6307 compute-cb@11 { 6308 compatible = "qcom,fastrpc-compute-cb"; 6309 reg = <11>; 6310 iommus = <&apps_smmu 0x318c 0x0420>; 6311 dma-coherent; 6312 }; 6313 6314 compute-cb@12 { 6315 compatible = "qcom,fastrpc-compute-cb"; 6316 reg = <12>; 6317 iommus = <&apps_smmu 0x318d 0x0420>; 6318 dma-coherent; 6319 }; 6320 6321 compute-cb@13 { 6322 compatible = "qcom,fastrpc-compute-cb"; 6323 reg = <13>; 6324 iommus = <&apps_smmu 0x318e 0x0420>; 6325 dma-coherent; 6326 }; 6327 6328 compute-cb@14 { 6329 compatible = "qcom,fastrpc-compute-cb"; 6330 reg = <14>; 6331 iommus = <&apps_smmu 0x318f 0x0420>; 6332 dma-coherent; 6333 }; 6334 }; 6335 }; 6336 }; 6337 6338 nspb_noc: interconnect@210c0000 { 6339 compatible = "qcom,sc8280xp-nspb-noc"; 6340 reg = <0 0x210c0000 0 0x10000>; 6341 6342 #interconnect-cells = <2>; 6343 qcom,bcm-voters = <&apps_bcm_voter>; 6344 }; 6345 6346 remoteproc_nsp1: remoteproc@21300000 { 6347 compatible = "qcom,sc8280xp-nsp1-pas"; 6348 reg = <0 0x21300000 0 0x10000>; 6349 6350 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 6351 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 6352 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 6353 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 6354 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 6355 interrupt-names = "wdog", "fatal", "ready", 6356 "handover", "stop-ack"; 6357 6358 clocks = <&rpmhcc RPMH_CXO_CLK>; 6359 clock-names = "xo"; 6360 6361 power-domains = <&rpmhpd SC8280XP_NSP>, 6362 <&rpmhpd SC8280XP_CX>, 6363 <&rpmhpd SC8280XP_MXC>; 6364 power-domain-names = "nsp", 6365 "cx", 6366 "mxc"; 6367 6368 memory-region = <&pil_nsp1_mem>; 6369 6370 qcom,smem-states = <&smp2p_nsp1_out 0>; 6371 qcom,smem-state-names = "stop"; 6372 6373 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 6374 6375 status = "disabled"; 6376 6377 glink-edge { 6378 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 6379 IPCC_MPROC_SIGNAL_GLINK_QMP 6380 IRQ_TYPE_EDGE_RISING>; 6381 mboxes = <&ipcc IPCC_CLIENT_NSP1 6382 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6383 6384 label = "nsp1"; 6385 qcom,remote-pid = <12>; 6386 }; 6387 }; 6388 6389 mdss1: display-subsystem@22000000 { 6390 compatible = "qcom,sc8280xp-mdss"; 6391 reg = <0 0x22000000 0 0x1000>; 6392 reg-names = "mdss"; 6393 6394 clocks = <&gcc GCC_DISP_AHB_CLK>, 6395 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6396 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 6397 clock-names = "iface", 6398 "ahb", 6399 "core"; 6400 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 6401 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 6402 interconnect-names = "mdp0-mem", "mdp1-mem"; 6403 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 6404 6405 iommus = <&apps_smmu 0x1800 0x402>; 6406 power-domains = <&dispcc1 MDSS_GDSC>; 6407 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 6408 6409 interrupt-controller; 6410 #interrupt-cells = <1>; 6411 #address-cells = <2>; 6412 #size-cells = <2>; 6413 ranges; 6414 6415 status = "disabled"; 6416 6417 mdss1_mdp: display-controller@22001000 { 6418 compatible = "qcom,sc8280xp-dpu"; 6419 reg = <0 0x22001000 0 0x8f000>, 6420 <0 0x220b0000 0 0x3000>; 6421 reg-names = "mdp", "vbif"; 6422 6423 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 6424 <&gcc GCC_DISP_SF_AXI_CLK>, 6425 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6426 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 6427 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 6428 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6429 clock-names = "bus", 6430 "nrt_bus", 6431 "iface", 6432 "lut", 6433 "core", 6434 "vsync"; 6435 interrupt-parent = <&mdss1>; 6436 interrupts = <0>; 6437 power-domains = <&rpmhpd SC8280XP_MMCX>; 6438 6439 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6440 assigned-clock-rates = <19200000>; 6441 operating-points-v2 = <&mdss1_mdp_opp_table>; 6442 6443 ports { 6444 #address-cells = <1>; 6445 #size-cells = <0>; 6446 6447 port@0 { 6448 reg = <0>; 6449 6450 mdss1_intf0_out: endpoint { 6451 remote-endpoint = <&mdss1_dp0_in>; 6452 }; 6453 }; 6454 6455 port@1 { 6456 reg = <1>; 6457 6458 mdss1_intf1_out: endpoint { 6459 remote-endpoint = <&mdss1_dsi0_in>; 6460 }; 6461 }; 6462 6463 port@2 { 6464 reg = <2>; 6465 6466 mdss1_intf2_out: endpoint { 6467 remote-endpoint = <&mdss1_dsi1_in>; 6468 }; 6469 }; 6470 6471 port@4 { 6472 reg = <4>; 6473 6474 mdss1_intf4_out: endpoint { 6475 remote-endpoint = <&mdss1_dp1_in>; 6476 }; 6477 }; 6478 6479 port@5 { 6480 reg = <5>; 6481 6482 mdss1_intf5_out: endpoint { 6483 remote-endpoint = <&mdss1_dp3_in>; 6484 }; 6485 }; 6486 6487 port@6 { 6488 reg = <6>; 6489 6490 mdss1_intf6_out: endpoint { 6491 remote-endpoint = <&mdss1_dp2_in>; 6492 }; 6493 }; 6494 }; 6495 6496 mdss1_mdp_opp_table: opp-table { 6497 compatible = "operating-points-v2"; 6498 6499 opp-200000000 { 6500 opp-hz = /bits/ 64 <200000000>; 6501 required-opps = <&rpmhpd_opp_low_svs>; 6502 }; 6503 6504 opp-300000000 { 6505 opp-hz = /bits/ 64 <300000000>; 6506 required-opps = <&rpmhpd_opp_svs>; 6507 }; 6508 6509 opp-375000000 { 6510 opp-hz = /bits/ 64 <375000000>; 6511 required-opps = <&rpmhpd_opp_svs_l1>; 6512 }; 6513 6514 opp-500000000 { 6515 opp-hz = /bits/ 64 <500000000>; 6516 required-opps = <&rpmhpd_opp_nom>; 6517 }; 6518 opp-600000000 { 6519 opp-hz = /bits/ 64 <600000000>; 6520 required-opps = <&rpmhpd_opp_turbo_l1>; 6521 }; 6522 }; 6523 }; 6524 6525 mdss1_dp0: displayport-controller@22090000 { 6526 compatible = "qcom,sc8280xp-dp"; 6527 reg = <0 0x22090000 0 0x200>, 6528 <0 0x22090200 0 0x200>, 6529 <0 0x22090400 0 0x600>, 6530 <0 0x22091000 0 0x400>, 6531 <0 0x22091400 0 0x400>; 6532 6533 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6534 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 6535 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 6536 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 6537 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 6538 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 6539 clock-names = "core_iface", "core_aux", 6540 "ctrl_link", 6541 "ctrl_link_iface", "stream_pixel", 6542 "stream_1_pixel"; 6543 interrupt-parent = <&mdss1>; 6544 interrupts = <12>; 6545 phys = <&mdss1_dp0_phy>; 6546 phy-names = "dp"; 6547 power-domains = <&rpmhpd SC8280XP_MMCX>; 6548 6549 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6550 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6551 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 6552 assigned-clock-parents = <&mdss1_dp0_phy 0>, 6553 <&mdss1_dp0_phy 1>, 6554 <&mdss1_dp0_phy 1>; 6555 operating-points-v2 = <&mdss1_dp0_opp_table>; 6556 6557 #sound-dai-cells = <0>; 6558 6559 status = "disabled"; 6560 6561 ports { 6562 #address-cells = <1>; 6563 #size-cells = <0>; 6564 6565 port@0 { 6566 reg = <0>; 6567 mdss1_dp0_in: endpoint { 6568 remote-endpoint = <&mdss1_intf0_out>; 6569 }; 6570 }; 6571 6572 port@1 { 6573 reg = <1>; 6574 6575 mdss1_dp0_out: endpoint { 6576 }; 6577 }; 6578 }; 6579 6580 mdss1_dp0_opp_table: opp-table { 6581 compatible = "operating-points-v2"; 6582 6583 opp-162000000 { 6584 opp-hz = /bits/ 64 <162000000>; 6585 required-opps = <&rpmhpd_opp_low_svs>; 6586 }; 6587 6588 opp-270000000 { 6589 opp-hz = /bits/ 64 <270000000>; 6590 required-opps = <&rpmhpd_opp_svs>; 6591 }; 6592 6593 opp-540000000 { 6594 opp-hz = /bits/ 64 <540000000>; 6595 required-opps = <&rpmhpd_opp_svs_l1>; 6596 }; 6597 6598 opp-810000000 { 6599 opp-hz = /bits/ 64 <810000000>; 6600 required-opps = <&rpmhpd_opp_nom>; 6601 }; 6602 }; 6603 }; 6604 6605 mdss1_dsi0: dsi@22094000 { 6606 compatible = "qcom,sc8280xp-dsi-ctrl", 6607 "qcom,sa8775p-dsi-ctrl", 6608 "qcom,mdss-dsi-ctrl"; 6609 reg = <0 0x22094000 0 0x400>; 6610 reg-names = "dsi_ctrl"; 6611 6612 interrupt-parent = <&mdss1>; 6613 interrupts = <4>; 6614 6615 clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, 6616 <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, 6617 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, 6618 <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, 6619 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6620 <&gcc GCC_DISP_HF_AXI_CLK>; 6621 clock-names = "byte", 6622 "byte_intf", 6623 "pixel", 6624 "core", 6625 "iface", 6626 "bus"; 6627 6628 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, 6629 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; 6630 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6631 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; 6632 6633 operating-points-v2 = <&dsi_opp_table>; 6634 power-domains = <&rpmhpd SC8280XP_MMCX>; 6635 6636 refgen-supply = <&refgen>; 6637 6638 phys = <&mdss1_dsi0_phy>; 6639 phy-names = "dsi"; 6640 6641 #address-cells = <1>; 6642 #size-cells = <0>; 6643 6644 status = "disabled"; 6645 6646 ports { 6647 #address-cells = <1>; 6648 #size-cells = <0>; 6649 6650 port@0 { 6651 reg = <0>; 6652 6653 mdss1_dsi0_in: endpoint { 6654 remote-endpoint = <&mdss1_intf1_out>; 6655 }; 6656 }; 6657 6658 port@1 { 6659 reg = <1>; 6660 6661 mdss1_dsi0_out: endpoint { 6662 }; 6663 }; 6664 }; 6665 }; 6666 6667 mdss1_dsi0_phy: phy@22094400 { 6668 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6669 "qcom,sa8775p-dsi-phy-5nm"; 6670 reg = <0 0x22094400 0 0x200>, 6671 <0 0x22094600 0 0x280>, 6672 <0 0x22094900 0 0x280>; 6673 reg-names = "dsi_phy", 6674 "dsi_phy_lane", 6675 "dsi_pll"; 6676 6677 #clock-cells = <1>; 6678 #phy-cells = <0>; 6679 6680 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6681 <&rpmhcc RPMH_CXO_CLK>; 6682 clock-names = "iface", "ref"; 6683 6684 status = "disabled"; 6685 }; 6686 6687 mdss1_dsi1: dsi@22096000 { 6688 compatible = "qcom,sc8280xp-dsi-ctrl", 6689 "qcom,sa8775p-dsi-ctrl", 6690 "qcom,mdss-dsi-ctrl"; 6691 reg = <0 0x22096000 0 0x400>; 6692 reg-names = "dsi_ctrl"; 6693 6694 interrupt-parent = <&mdss1>; 6695 interrupts = <5>; 6696 6697 clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, 6698 <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, 6699 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, 6700 <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, 6701 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6702 <&gcc GCC_DISP_HF_AXI_CLK>; 6703 clock-names = "byte", 6704 "byte_intf", 6705 "pixel", 6706 "core", 6707 "iface", 6708 "bus"; 6709 6710 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, 6711 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; 6712 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6713 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 6714 6715 operating-points-v2 = <&dsi_opp_table>; 6716 power-domains = <&rpmhpd SC8280XP_MMCX>; 6717 6718 refgen-supply = <&refgen>; 6719 6720 phys = <&mdss1_dsi1_phy>; 6721 phy-names = "dsi"; 6722 6723 #address-cells = <1>; 6724 #size-cells = <0>; 6725 6726 status = "disabled"; 6727 6728 ports { 6729 #address-cells = <1>; 6730 #size-cells = <0>; 6731 6732 port@0 { 6733 reg = <0>; 6734 6735 mdss1_dsi1_in: endpoint { 6736 remote-endpoint = <&mdss1_intf2_out>; 6737 }; 6738 }; 6739 6740 port@1 { 6741 reg = <1>; 6742 6743 mdss1_dsi1_out: endpoint { 6744 }; 6745 }; 6746 }; 6747 }; 6748 6749 mdss1_dsi1_phy: phy@22096400 { 6750 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6751 "qcom,sa8775p-dsi-phy-5nm"; 6752 reg = <0 0x22096400 0 0x200>, 6753 <0 0x22096600 0 0x280>, 6754 <0 0x22096900 0 0x280>; 6755 reg-names = "dsi_phy", 6756 "dsi_phy_lane", 6757 "dsi_pll"; 6758 6759 #clock-cells = <1>; 6760 #phy-cells = <0>; 6761 6762 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6763 <&rpmhcc RPMH_CXO_CLK>; 6764 clock-names = "iface", "ref"; 6765 6766 status = "disabled"; 6767 }; 6768 6769 mdss1_dp1: displayport-controller@22098000 { 6770 compatible = "qcom,sc8280xp-dp"; 6771 reg = <0 0x22098000 0 0x200>, 6772 <0 0x22098200 0 0x200>, 6773 <0 0x22098400 0 0x600>, 6774 <0 0x22099000 0 0x400>, 6775 <0 0x22099400 0 0x400>; 6776 6777 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6778 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 6779 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 6780 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 6781 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 6782 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 6783 clock-names = "core_iface", "core_aux", 6784 "ctrl_link", 6785 "ctrl_link_iface", "stream_pixel", 6786 "stream_1_pixel"; 6787 interrupt-parent = <&mdss1>; 6788 interrupts = <13>; 6789 phys = <&mdss1_dp1_phy>; 6790 phy-names = "dp"; 6791 power-domains = <&rpmhpd SC8280XP_MMCX>; 6792 6793 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 6794 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 6795 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 6796 assigned-clock-parents = <&mdss1_dp1_phy 0>, 6797 <&mdss1_dp1_phy 1>, 6798 <&mdss1_dp1_phy 1>; 6799 operating-points-v2 = <&mdss1_dp1_opp_table>; 6800 6801 #sound-dai-cells = <0>; 6802 6803 status = "disabled"; 6804 6805 ports { 6806 #address-cells = <1>; 6807 #size-cells = <0>; 6808 6809 port@0 { 6810 reg = <0>; 6811 mdss1_dp1_in: endpoint { 6812 remote-endpoint = <&mdss1_intf4_out>; 6813 }; 6814 }; 6815 6816 port@1 { 6817 reg = <1>; 6818 6819 mdss1_dp1_out: endpoint { 6820 }; 6821 }; 6822 }; 6823 6824 mdss1_dp1_opp_table: opp-table { 6825 compatible = "operating-points-v2"; 6826 6827 opp-162000000 { 6828 opp-hz = /bits/ 64 <162000000>; 6829 required-opps = <&rpmhpd_opp_low_svs>; 6830 }; 6831 6832 opp-270000000 { 6833 opp-hz = /bits/ 64 <270000000>; 6834 required-opps = <&rpmhpd_opp_svs>; 6835 }; 6836 6837 opp-540000000 { 6838 opp-hz = /bits/ 64 <540000000>; 6839 required-opps = <&rpmhpd_opp_svs_l1>; 6840 }; 6841 6842 opp-810000000 { 6843 opp-hz = /bits/ 64 <810000000>; 6844 required-opps = <&rpmhpd_opp_nom>; 6845 }; 6846 }; 6847 }; 6848 6849 mdss1_dp2: displayport-controller@2209a000 { 6850 compatible = "qcom,sc8280xp-dp"; 6851 reg = <0 0x2209a000 0 0x200>, 6852 <0 0x2209a200 0 0x200>, 6853 <0 0x2209a400 0 0x600>, 6854 <0 0x2209b000 0 0x400>, 6855 <0 0x2209b400 0 0x400>; 6856 6857 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6858 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6859 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 6860 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 6861 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 6862 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 6863 clock-names = "core_iface", "core_aux", 6864 "ctrl_link", 6865 "ctrl_link_iface", "stream_pixel", 6866 "stream_1_pixel"; 6867 interrupt-parent = <&mdss1>; 6868 interrupts = <14>; 6869 phys = <&mdss1_dp2_phy>; 6870 phy-names = "dp"; 6871 power-domains = <&rpmhpd SC8280XP_MMCX>; 6872 6873 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 6874 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 6875 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 6876 assigned-clock-parents = <&mdss1_dp2_phy 0>, 6877 <&mdss1_dp2_phy 1>, 6878 <&mdss1_dp2_phy 1>; 6879 operating-points-v2 = <&mdss1_dp2_opp_table>; 6880 6881 #sound-dai-cells = <0>; 6882 6883 status = "disabled"; 6884 6885 ports { 6886 #address-cells = <1>; 6887 #size-cells = <0>; 6888 6889 port@0 { 6890 reg = <0>; 6891 mdss1_dp2_in: endpoint { 6892 remote-endpoint = <&mdss1_intf6_out>; 6893 }; 6894 }; 6895 6896 port@1 { 6897 reg = <1>; 6898 6899 mdss1_dp2_out: endpoint { 6900 }; 6901 }; 6902 }; 6903 6904 mdss1_dp2_opp_table: opp-table { 6905 compatible = "operating-points-v2"; 6906 6907 opp-162000000 { 6908 opp-hz = /bits/ 64 <162000000>; 6909 required-opps = <&rpmhpd_opp_low_svs>; 6910 }; 6911 6912 opp-270000000 { 6913 opp-hz = /bits/ 64 <270000000>; 6914 required-opps = <&rpmhpd_opp_svs>; 6915 }; 6916 6917 opp-540000000 { 6918 opp-hz = /bits/ 64 <540000000>; 6919 required-opps = <&rpmhpd_opp_svs_l1>; 6920 }; 6921 6922 opp-810000000 { 6923 opp-hz = /bits/ 64 <810000000>; 6924 required-opps = <&rpmhpd_opp_nom>; 6925 }; 6926 }; 6927 }; 6928 6929 mdss1_dp3: displayport-controller@220a0000 { 6930 compatible = "qcom,sc8280xp-dp"; 6931 reg = <0 0x220a0000 0 0x200>, 6932 <0 0x220a0200 0 0x200>, 6933 <0 0x220a0400 0 0x600>, 6934 <0 0x220a1000 0 0x400>, 6935 <0 0x220a1400 0 0x400>; 6936 6937 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6938 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6939 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 6940 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 6941 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 6942 clock-names = "core_iface", "core_aux", 6943 "ctrl_link", 6944 "ctrl_link_iface", "stream_pixel"; 6945 interrupt-parent = <&mdss1>; 6946 interrupts = <15>; 6947 phys = <&mdss1_dp3_phy>; 6948 phy-names = "dp"; 6949 power-domains = <&rpmhpd SC8280XP_MMCX>; 6950 6951 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 6952 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 6953 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 6954 operating-points-v2 = <&mdss1_dp3_opp_table>; 6955 6956 #sound-dai-cells = <0>; 6957 6958 status = "disabled"; 6959 6960 ports { 6961 #address-cells = <1>; 6962 #size-cells = <0>; 6963 6964 port@0 { 6965 reg = <0>; 6966 mdss1_dp3_in: endpoint { 6967 remote-endpoint = <&mdss1_intf5_out>; 6968 }; 6969 }; 6970 6971 port@1 { 6972 reg = <1>; 6973 6974 mdss1_dp3_out: endpoint { 6975 }; 6976 }; 6977 }; 6978 6979 mdss1_dp3_opp_table: opp-table { 6980 compatible = "operating-points-v2"; 6981 6982 opp-162000000 { 6983 opp-hz = /bits/ 64 <162000000>; 6984 required-opps = <&rpmhpd_opp_low_svs>; 6985 }; 6986 6987 opp-270000000 { 6988 opp-hz = /bits/ 64 <270000000>; 6989 required-opps = <&rpmhpd_opp_svs>; 6990 }; 6991 6992 opp-540000000 { 6993 opp-hz = /bits/ 64 <540000000>; 6994 required-opps = <&rpmhpd_opp_svs_l1>; 6995 }; 6996 6997 opp-810000000 { 6998 opp-hz = /bits/ 64 <810000000>; 6999 required-opps = <&rpmhpd_opp_nom>; 7000 }; 7001 }; 7002 }; 7003 }; 7004 7005 mdss1_dp2_phy: phy@220c2a00 { 7006 compatible = "qcom,sc8280xp-dp-phy"; 7007 reg = <0 0x220c2a00 0 0x19c>, 7008 <0 0x220c2200 0 0xec>, 7009 <0 0x220c2600 0 0xec>, 7010 <0 0x220c2000 0 0x1c8>; 7011 7012 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 7013 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 7014 clock-names = "aux", "cfg_ahb"; 7015 power-domains = <&rpmhpd SC8280XP_MX>; 7016 7017 #clock-cells = <1>; 7018 #phy-cells = <0>; 7019 7020 status = "disabled"; 7021 }; 7022 7023 mdss1_dp3_phy: phy@220c5a00 { 7024 compatible = "qcom,sc8280xp-dp-phy"; 7025 reg = <0 0x220c5a00 0 0x19c>, 7026 <0 0x220c5200 0 0xec>, 7027 <0 0x220c5600 0 0xec>, 7028 <0 0x220c5000 0 0x1c8>; 7029 7030 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 7031 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 7032 clock-names = "aux", "cfg_ahb"; 7033 power-domains = <&rpmhpd SC8280XP_MX>; 7034 7035 #clock-cells = <1>; 7036 #phy-cells = <0>; 7037 7038 status = "disabled"; 7039 }; 7040 7041 dispcc1: clock-controller@22100000 { 7042 compatible = "qcom,sc8280xp-dispcc1"; 7043 reg = <0 0x22100000 0 0x20000>; 7044 7045 clocks = <&gcc GCC_DISP_AHB_CLK>, 7046 <&rpmhcc RPMH_CXO_CLK>, 7047 <0>, 7048 <&mdss1_dp0_phy 0>, 7049 <&mdss1_dp0_phy 1>, 7050 <&mdss1_dp1_phy 0>, 7051 <&mdss1_dp1_phy 1>, 7052 <&mdss1_dp2_phy 0>, 7053 <&mdss1_dp2_phy 1>, 7054 <&mdss1_dp3_phy 0>, 7055 <&mdss1_dp3_phy 1>, 7056 <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, 7057 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, 7058 <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 7059 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 7060 power-domains = <&rpmhpd SC8280XP_MMCX>; 7061 7062 #clock-cells = <1>; 7063 #power-domain-cells = <1>; 7064 #reset-cells = <1>; 7065 7066 status = "disabled"; 7067 }; 7068 7069 ethernet1: ethernet@23000000 { 7070 compatible = "qcom,sc8280xp-ethqos"; 7071 reg = <0x0 0x23000000 0x0 0x10000>, 7072 <0x0 0x23016000 0x0 0x100>; 7073 reg-names = "stmmaceth", "rgmii"; 7074 7075 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7076 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7077 <&gcc GCC_EMAC1_PTP_CLK>, 7078 <&gcc GCC_EMAC1_RGMII_CLK>; 7079 clock-names = "stmmaceth", 7080 "pclk", 7081 "ptp_ref", 7082 "rgmii"; 7083 7084 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7085 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 7086 interrupt-names = "macirq", "eth_lpi"; 7087 7088 iommus = <&apps_smmu 0x40 0xf>; 7089 power-domains = <&gcc EMAC_1_GDSC>; 7090 7091 snps,tso; 7092 snps,pbl = <32>; 7093 rx-fifo-depth = <4096>; 7094 tx-fifo-depth = <4096>; 7095 7096 status = "disabled"; 7097 }; 7098 }; 7099 7100 sound: sound { 7101 }; 7102 7103 thermal-zones { 7104 aoss-0-thermal { 7105 thermal-sensors = <&tsens0 0>; 7106 7107 trips { 7108 aoss-critical { 7109 temperature = <110000>; 7110 hysteresis = <0>; 7111 type = "critical"; 7112 }; 7113 }; 7114 }; 7115 7116 cpu0-0-thermal { 7117 thermal-sensors = <&tsens0 1>; 7118 7119 trips { 7120 cpu-crit { 7121 temperature = <110000>; 7122 hysteresis = <1000>; 7123 type = "critical"; 7124 }; 7125 }; 7126 }; 7127 7128 cpu1-0-thermal { 7129 thermal-sensors = <&tsens0 2>; 7130 7131 trips { 7132 cpu-crit { 7133 temperature = <110000>; 7134 hysteresis = <1000>; 7135 type = "critical"; 7136 }; 7137 }; 7138 }; 7139 7140 cpu2-0-thermal { 7141 thermal-sensors = <&tsens0 3>; 7142 7143 trips { 7144 cpu-crit { 7145 temperature = <110000>; 7146 hysteresis = <1000>; 7147 type = "critical"; 7148 }; 7149 }; 7150 }; 7151 7152 cpu3-0-thermal { 7153 thermal-sensors = <&tsens0 4>; 7154 7155 trips { 7156 cpu-crit { 7157 temperature = <110000>; 7158 hysteresis = <1000>; 7159 type = "critical"; 7160 }; 7161 }; 7162 }; 7163 7164 cpu4-0-thermal { 7165 thermal-sensors = <&tsens0 5>; 7166 7167 trips { 7168 cpu-crit { 7169 temperature = <110000>; 7170 hysteresis = <1000>; 7171 type = "critical"; 7172 }; 7173 }; 7174 }; 7175 7176 cpu5-0-thermal { 7177 thermal-sensors = <&tsens0 6>; 7178 7179 trips { 7180 cpu-crit { 7181 temperature = <110000>; 7182 hysteresis = <1000>; 7183 type = "critical"; 7184 }; 7185 }; 7186 }; 7187 7188 cpu6-0-thermal { 7189 thermal-sensors = <&tsens0 7>; 7190 7191 trips { 7192 cpu-crit { 7193 temperature = <110000>; 7194 hysteresis = <1000>; 7195 type = "critical"; 7196 }; 7197 }; 7198 }; 7199 7200 cpu7-0-thermal { 7201 thermal-sensors = <&tsens0 8>; 7202 7203 trips { 7204 cpu-crit { 7205 temperature = <110000>; 7206 hysteresis = <1000>; 7207 type = "critical"; 7208 }; 7209 }; 7210 }; 7211 7212 cpuss0-thermal { 7213 thermal-sensors = <&tsens0 9>; 7214 7215 trips { 7216 cpu-crit { 7217 temperature = <110000>; 7218 hysteresis = <1000>; 7219 type = "critical"; 7220 }; 7221 }; 7222 }; 7223 7224 nsp0-0-thermal { 7225 thermal-sensors = <&tsens0 10>; 7226 7227 trips { 7228 nsp0-crit { 7229 temperature = <110000>; 7230 hysteresis = <1000>; 7231 type = "critical"; 7232 }; 7233 }; 7234 }; 7235 7236 nsp1-0-thermal { 7237 thermal-sensors = <&tsens0 11>; 7238 7239 trips { 7240 nsp1-crit { 7241 temperature = <110000>; 7242 hysteresis = <1000>; 7243 type = "critical"; 7244 }; 7245 }; 7246 }; 7247 7248 smss-0-thermal { 7249 thermal-sensors = <&tsens0 12>; 7250 7251 trips { 7252 smss-crit { 7253 temperature = <110000>; 7254 hysteresis = <1000>; 7255 type = "critical"; 7256 }; 7257 }; 7258 }; 7259 7260 camss-0-thermal { 7261 thermal-sensors = <&tsens0 13>; 7262 7263 trips { 7264 camss-crit { 7265 temperature = <110000>; 7266 hysteresis = <1000>; 7267 type = "critical"; 7268 }; 7269 }; 7270 }; 7271 7272 aoss-1-thermal { 7273 thermal-sensors = <&tsens1 0>; 7274 7275 trips { 7276 aoss-critical { 7277 temperature = <110000>; 7278 hysteresis = <0>; 7279 type = "critical"; 7280 }; 7281 }; 7282 }; 7283 7284 cpu0-1-thermal { 7285 thermal-sensors = <&tsens1 1>; 7286 7287 trips { 7288 cpu-crit { 7289 temperature = <110000>; 7290 hysteresis = <1000>; 7291 type = "critical"; 7292 }; 7293 }; 7294 }; 7295 7296 cpu1-1-thermal { 7297 thermal-sensors = <&tsens1 2>; 7298 7299 trips { 7300 cpu-crit { 7301 temperature = <110000>; 7302 hysteresis = <1000>; 7303 type = "critical"; 7304 }; 7305 }; 7306 }; 7307 7308 cpu2-1-thermal { 7309 thermal-sensors = <&tsens1 3>; 7310 7311 trips { 7312 cpu-crit { 7313 temperature = <110000>; 7314 hysteresis = <1000>; 7315 type = "critical"; 7316 }; 7317 }; 7318 }; 7319 7320 cpu3-1-thermal { 7321 thermal-sensors = <&tsens1 4>; 7322 7323 trips { 7324 cpu-crit { 7325 temperature = <110000>; 7326 hysteresis = <1000>; 7327 type = "critical"; 7328 }; 7329 }; 7330 }; 7331 7332 cpu4-1-thermal { 7333 thermal-sensors = <&tsens1 5>; 7334 7335 trips { 7336 cpu-crit { 7337 temperature = <110000>; 7338 hysteresis = <1000>; 7339 type = "critical"; 7340 }; 7341 }; 7342 }; 7343 7344 cpu5-1-thermal { 7345 thermal-sensors = <&tsens1 6>; 7346 7347 trips { 7348 cpu-crit { 7349 temperature = <110000>; 7350 hysteresis = <1000>; 7351 type = "critical"; 7352 }; 7353 }; 7354 }; 7355 7356 cpu6-1-thermal { 7357 thermal-sensors = <&tsens1 7>; 7358 7359 trips { 7360 cpu-crit { 7361 temperature = <110000>; 7362 hysteresis = <1000>; 7363 type = "critical"; 7364 }; 7365 }; 7366 }; 7367 7368 cpu7-1-thermal { 7369 thermal-sensors = <&tsens1 8>; 7370 7371 trips { 7372 cpu-crit { 7373 temperature = <110000>; 7374 hysteresis = <1000>; 7375 type = "critical"; 7376 }; 7377 }; 7378 }; 7379 7380 cpuss1-thermal { 7381 thermal-sensors = <&tsens1 9>; 7382 7383 trips { 7384 cpu-crit { 7385 temperature = <110000>; 7386 hysteresis = <1000>; 7387 type = "critical"; 7388 }; 7389 }; 7390 }; 7391 7392 nsp0-2-thermal { 7393 thermal-sensors = <&tsens1 10>; 7394 7395 trips { 7396 nsp0-crit { 7397 temperature = <110000>; 7398 hysteresis = <1000>; 7399 type = "critical"; 7400 }; 7401 }; 7402 }; 7403 7404 nsp1-2-thermal { 7405 thermal-sensors = <&tsens1 11>; 7406 7407 trips { 7408 nsp1-crit { 7409 temperature = <110000>; 7410 hysteresis = <1000>; 7411 type = "critical"; 7412 }; 7413 }; 7414 }; 7415 7416 smss-1-thermal { 7417 thermal-sensors = <&tsens1 12>; 7418 7419 trips { 7420 smss-crit { 7421 temperature = <110000>; 7422 hysteresis = <1000>; 7423 type = "critical"; 7424 }; 7425 }; 7426 }; 7427 7428 camss-1-thermal { 7429 thermal-sensors = <&tsens1 13>; 7430 7431 trips { 7432 camss-crit { 7433 temperature = <110000>; 7434 hysteresis = <1000>; 7435 type = "critical"; 7436 }; 7437 }; 7438 }; 7439 7440 pcie-0-thermal { 7441 thermal-sensors = <&tsens1 14>; 7442 7443 trips { 7444 pcie-crit { 7445 temperature = <110000>; 7446 hysteresis = <1000>; 7447 type = "critical"; 7448 }; 7449 }; 7450 }; 7451 7452 ddrss-0-thermal { 7453 thermal-sensors = <&tsens1 15>; 7454 7455 trips { 7456 trip-point0 { 7457 temperature = <90000>; 7458 hysteresis = <2000>; 7459 type = "hot"; 7460 }; 7461 }; 7462 }; 7463 7464 aoss-2-thermal { 7465 thermal-sensors = <&tsens2 0>; 7466 7467 trips { 7468 aoss-critical { 7469 temperature = <110000>; 7470 hysteresis = <0>; 7471 type = "critical"; 7472 }; 7473 }; 7474 }; 7475 7476 gpuss-0-thermal { 7477 polling-delay-passive = <250>; 7478 7479 thermal-sensors = <&tsens2 1>; 7480 7481 cooling-maps { 7482 map0 { 7483 trip = <&gpu_alert0>; 7484 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7485 }; 7486 }; 7487 7488 trips { 7489 gpu_alert0: trip-point0 { 7490 temperature = <85000>; 7491 hysteresis = <1000>; 7492 type = "passive"; 7493 }; 7494 7495 trip-point1 { 7496 temperature = <110000>; 7497 hysteresis = <1000>; 7498 type = "critical"; 7499 }; 7500 }; 7501 }; 7502 7503 gpuss-1-thermal { 7504 polling-delay-passive = <250>; 7505 7506 thermal-sensors = <&tsens2 2>; 7507 7508 cooling-maps { 7509 map0 { 7510 trip = <&gpu_alert1>; 7511 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7512 }; 7513 }; 7514 7515 trips { 7516 gpu_alert1: trip-point0 { 7517 temperature = <85000>; 7518 hysteresis = <1000>; 7519 type = "passive"; 7520 }; 7521 7522 trip-point1 { 7523 temperature = <110000>; 7524 hysteresis = <1000>; 7525 type = "critical"; 7526 }; 7527 }; 7528 }; 7529 7530 gpuss-2-thermal { 7531 polling-delay-passive = <250>; 7532 7533 thermal-sensors = <&tsens2 3>; 7534 7535 cooling-maps { 7536 map0 { 7537 trip = <&gpu_alert2>; 7538 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7539 }; 7540 }; 7541 7542 trips { 7543 gpu_alert2: trip-point0 { 7544 temperature = <85000>; 7545 hysteresis = <1000>; 7546 type = "passive"; 7547 }; 7548 7549 trip-point1 { 7550 temperature = <110000>; 7551 hysteresis = <1000>; 7552 type = "critical"; 7553 }; 7554 }; 7555 }; 7556 7557 gpuss-3-thermal { 7558 polling-delay-passive = <250>; 7559 7560 thermal-sensors = <&tsens2 4>; 7561 7562 cooling-maps { 7563 map0 { 7564 trip = <&gpu_alert3>; 7565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7566 }; 7567 }; 7568 7569 trips { 7570 gpu_alert3: trip-point0 { 7571 temperature = <85000>; 7572 hysteresis = <1000>; 7573 type = "passive"; 7574 }; 7575 7576 trip-point1 { 7577 temperature = <110000>; 7578 hysteresis = <1000>; 7579 type = "critical"; 7580 }; 7581 }; 7582 }; 7583 7584 pcie-1-thermal { 7585 thermal-sensors = <&tsens2 5>; 7586 7587 trips { 7588 pcie-crit { 7589 temperature = <110000>; 7590 hysteresis = <1000>; 7591 type = "critical"; 7592 }; 7593 }; 7594 }; 7595 7596 ddrss-1-thermal { 7597 thermal-sensors = <&tsens2 6>; 7598 7599 trips { 7600 trip-point0 { 7601 temperature = <90000>; 7602 hysteresis = <2000>; 7603 type = "hot"; 7604 }; 7605 }; 7606 }; 7607 7608 audio-thermal { 7609 thermal-sensors = <&tsens2 7>; 7610 7611 trips { 7612 audio-crit { 7613 temperature = <110000>; 7614 hysteresis = <1000>; 7615 type = "critical"; 7616 }; 7617 }; 7618 }; 7619 7620 video-thermal { 7621 thermal-sensors = <&tsens2 8>; 7622 7623 trips { 7624 video-crit { 7625 temperature = <110000>; 7626 hysteresis = <1000>; 7627 type = "critical"; 7628 }; 7629 }; 7630 }; 7631 7632 nsp0-1-thermal { 7633 thermal-sensors = <&tsens2 9>; 7634 7635 trips { 7636 nsp0-crit { 7637 temperature = <110000>; 7638 hysteresis = <1000>; 7639 type = "critical"; 7640 }; 7641 }; 7642 }; 7643 7644 nsp1-1-thermal { 7645 thermal-sensors = <&tsens2 10>; 7646 7647 trips { 7648 nsp1-crit { 7649 temperature = <110000>; 7650 hysteresis = <1000>; 7651 type = "critical"; 7652 }; 7653 }; 7654 }; 7655 7656 aoss-3-thermal { 7657 thermal-sensors = <&tsens3 0>; 7658 7659 trips { 7660 aoss-critical { 7661 temperature = <110000>; 7662 hysteresis = <0>; 7663 type = "critical"; 7664 }; 7665 }; 7666 }; 7667 7668 gpuss-4-thermal { 7669 polling-delay-passive = <250>; 7670 7671 thermal-sensors = <&tsens3 1>; 7672 7673 cooling-maps { 7674 map0 { 7675 trip = <&gpu_alert4>; 7676 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7677 }; 7678 }; 7679 7680 trips { 7681 gpu_alert4: trip-point0 { 7682 temperature = <85000>; 7683 hysteresis = <1000>; 7684 type = "passive"; 7685 }; 7686 7687 trip-point1 { 7688 temperature = <110000>; 7689 hysteresis = <1000>; 7690 type = "critical"; 7691 }; 7692 }; 7693 }; 7694 7695 gpuss-5-thermal { 7696 polling-delay-passive = <250>; 7697 7698 thermal-sensors = <&tsens3 2>; 7699 7700 cooling-maps { 7701 map0 { 7702 trip = <&gpu_alert5>; 7703 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7704 }; 7705 }; 7706 7707 trips { 7708 gpu_alert5: trip-point0 { 7709 temperature = <85000>; 7710 hysteresis = <1000>; 7711 type = "passive"; 7712 }; 7713 7714 trip-point1 { 7715 temperature = <110000>; 7716 hysteresis = <1000>; 7717 type = "critical"; 7718 }; 7719 }; 7720 }; 7721 7722 gpuss-6-thermal { 7723 polling-delay-passive = <250>; 7724 7725 thermal-sensors = <&tsens3 3>; 7726 7727 cooling-maps { 7728 map0 { 7729 trip = <&gpu_alert6>; 7730 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7731 }; 7732 }; 7733 7734 trips { 7735 gpu_alert6: trip-point0 { 7736 temperature = <85000>; 7737 hysteresis = <1000>; 7738 type = "passive"; 7739 }; 7740 7741 trip-point1 { 7742 temperature = <110000>; 7743 hysteresis = <1000>; 7744 type = "critical"; 7745 }; 7746 }; 7747 }; 7748 7749 gpuss-7-thermal { 7750 polling-delay-passive = <250>; 7751 7752 thermal-sensors = <&tsens3 4>; 7753 7754 cooling-maps { 7755 map0 { 7756 trip = <&gpu_alert7>; 7757 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7758 }; 7759 }; 7760 7761 trips { 7762 gpu_alert7: trip-point0 { 7763 temperature = <85000>; 7764 hysteresis = <1000>; 7765 type = "passive"; 7766 }; 7767 7768 trip-point1 { 7769 temperature = <110000>; 7770 hysteresis = <1000>; 7771 type = "critical"; 7772 }; 7773 }; 7774 }; 7775 }; 7776 7777 timer { 7778 compatible = "arm,armv8-timer"; 7779 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7780 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7781 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7782 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7783 }; 7784}; 7785