1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/fips.h> 8 #include <linux/ieee80211.h> 9 #include <linux/kernel.h> 10 #include <linux/skbuff.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hw.h" 14 #include "dp_rx.h" 15 #include "dp_tx.h" 16 #include "peer.h" 17 #include "dp_mon.h" 18 #include "debugfs_htt_stats.h" 19 20 #define ATH12K_2GHZ_MIN_CHAN_NUM 1 21 #define ATH12K_2GHZ_MAX_CHAN_NUM 14 22 #define ATH12K_5GHZ_MIN_CHAN_NUM 36 23 #define ATH12K_5GHZ_MAX_CHAN_NUM 177 24 25 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 26 struct ath12k_dp_rx_tid_rxq *rx_tid); 27 28 static size_t ath12k_dp_list_cut_nodes(struct list_head *list, 29 struct list_head *head, 30 size_t count) 31 { 32 struct list_head *cur; 33 struct ath12k_rx_desc_info *rx_desc; 34 size_t nodes = 0; 35 36 if (!count) { 37 INIT_LIST_HEAD(list); 38 goto out; 39 } 40 41 list_for_each(cur, head) { 42 if (!count) 43 break; 44 45 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); 46 rx_desc->in_use = true; 47 48 count--; 49 nodes++; 50 } 51 52 list_cut_before(list, head, cur); 53 out: 54 return nodes; 55 } 56 57 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, 58 struct list_head *used_list) 59 { 60 struct ath12k_rx_desc_info *rx_desc, *safe; 61 62 /* Reset the use flag */ 63 list_for_each_entry_safe(rx_desc, safe, used_list, list) 64 rx_desc->in_use = false; 65 66 spin_lock_bh(&dp->rx_desc_lock); 67 list_splice_tail(used_list, &dp->rx_desc_free_list); 68 spin_unlock_bh(&dp->rx_desc_lock); 69 } 70 71 /* Returns number of Rx buffers replenished */ 72 int ath12k_dp_rx_bufs_replenish(struct ath12k_dp *dp, 73 struct dp_rxdma_ring *rx_ring, 74 struct list_head *used_list, 75 int req_entries) 76 { 77 struct ath12k_base *ab = dp->ab; 78 struct ath12k_buffer_addr *desc; 79 struct hal_srng *srng; 80 struct sk_buff *skb; 81 int num_free; 82 int num_remain; 83 u32 cookie; 84 dma_addr_t paddr; 85 struct ath12k_rx_desc_info *rx_desc; 86 enum hal_rx_buf_return_buf_manager mgr = dp->hal->hal_params->rx_buf_rbm; 87 88 req_entries = min(req_entries, rx_ring->bufs_max); 89 90 srng = &dp->hal->srng_list[rx_ring->refill_buf_ring.ring_id]; 91 92 spin_lock_bh(&srng->lock); 93 94 ath12k_hal_srng_access_begin(ab, srng); 95 96 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 97 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 98 req_entries = num_free; 99 100 req_entries = min(num_free, req_entries); 101 num_remain = req_entries; 102 103 if (!num_remain) 104 goto out; 105 106 /* Get the descriptor from free list */ 107 if (list_empty(used_list)) { 108 spin_lock_bh(&dp->rx_desc_lock); 109 req_entries = ath12k_dp_list_cut_nodes(used_list, 110 &dp->rx_desc_free_list, 111 num_remain); 112 spin_unlock_bh(&dp->rx_desc_lock); 113 num_remain = req_entries; 114 } 115 116 while (num_remain > 0) { 117 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 118 DP_RX_BUFFER_ALIGN_SIZE); 119 if (!skb) 120 break; 121 122 if (!IS_ALIGNED((unsigned long)skb->data, 123 DP_RX_BUFFER_ALIGN_SIZE)) { 124 skb_pull(skb, 125 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 126 skb->data); 127 } 128 129 paddr = dma_map_single(dp->dev, skb->data, 130 skb->len + skb_tailroom(skb), 131 DMA_FROM_DEVICE); 132 if (dma_mapping_error(dp->dev, paddr)) 133 goto fail_free_skb; 134 135 rx_desc = list_first_entry_or_null(used_list, 136 struct ath12k_rx_desc_info, 137 list); 138 if (!rx_desc) 139 goto fail_dma_unmap; 140 141 rx_desc->skb = skb; 142 cookie = rx_desc->cookie; 143 144 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 145 if (!desc) 146 goto fail_dma_unmap; 147 148 list_del(&rx_desc->list); 149 ATH12K_SKB_RXCB(skb)->paddr = paddr; 150 151 num_remain--; 152 153 ath12k_hal_rx_buf_addr_info_set(dp->hal, desc, paddr, cookie, 154 mgr); 155 } 156 157 goto out; 158 159 fail_dma_unmap: 160 dma_unmap_single(dp->dev, paddr, skb->len + skb_tailroom(skb), 161 DMA_FROM_DEVICE); 162 fail_free_skb: 163 dev_kfree_skb_any(skb); 164 out: 165 ath12k_hal_srng_access_end(ab, srng); 166 167 if (!list_empty(used_list)) 168 ath12k_dp_rx_enqueue_free(dp, used_list); 169 170 spin_unlock_bh(&srng->lock); 171 172 return req_entries - num_remain; 173 } 174 EXPORT_SYMBOL(ath12k_dp_rx_bufs_replenish); 175 176 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab, 177 struct dp_rxdma_mon_ring *rx_ring) 178 { 179 struct sk_buff *skb; 180 int buf_id; 181 182 spin_lock_bh(&rx_ring->idr_lock); 183 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 184 idr_remove(&rx_ring->bufs_idr, buf_id); 185 /* TODO: Understand where internal driver does this dma_unmap 186 * of rxdma_buffer. 187 */ 188 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 189 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 190 dev_kfree_skb_any(skb); 191 } 192 193 idr_destroy(&rx_ring->bufs_idr); 194 spin_unlock_bh(&rx_ring->idr_lock); 195 196 return 0; 197 } 198 199 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 200 { 201 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 202 int i; 203 204 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring); 205 206 if (ab->hw_params->rxdma1_enable) 207 return 0; 208 209 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 210 ath12k_dp_rxdma_mon_buf_ring_free(ab, 211 &dp->rx_mon_status_refill_ring[i]); 212 213 return 0; 214 } 215 216 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab, 217 struct dp_rxdma_mon_ring *rx_ring, 218 u32 ringtype) 219 { 220 int num_entries; 221 222 num_entries = rx_ring->refill_buf_ring.size / 223 ath12k_hal_srng_get_entrysize(ab, ringtype); 224 225 rx_ring->bufs_max = num_entries; 226 227 if (ringtype == HAL_RXDMA_MONITOR_STATUS) 228 ath12k_dp_mon_status_bufs_replenish(ab, rx_ring, 229 num_entries); 230 else 231 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 232 233 return 0; 234 } 235 236 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 237 struct dp_rxdma_ring *rx_ring) 238 { 239 LIST_HEAD(list); 240 241 rx_ring->bufs_max = rx_ring->refill_buf_ring.size / 242 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF); 243 244 ath12k_dp_rx_bufs_replenish(ath12k_ab_to_dp(ab), rx_ring, &list, 0); 245 246 return 0; 247 } 248 249 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 250 { 251 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 252 struct dp_rxdma_mon_ring *mon_ring; 253 int ret, i; 254 255 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring); 256 if (ret) { 257 ath12k_warn(ab, 258 "failed to setup HAL_RXDMA_BUF\n"); 259 return ret; 260 } 261 262 if (ab->hw_params->rxdma1_enable) { 263 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, 264 &dp->rxdma_mon_buf_ring, 265 HAL_RXDMA_MONITOR_BUF); 266 if (ret) 267 ath12k_warn(ab, 268 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 269 return ret; 270 } 271 272 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 273 mon_ring = &dp->rx_mon_status_refill_ring[i]; 274 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab, mon_ring, 275 HAL_RXDMA_MONITOR_STATUS); 276 if (ret) { 277 ath12k_warn(ab, 278 "failed to setup HAL_RXDMA_MONITOR_STATUS\n"); 279 return ret; 280 } 281 } 282 283 return 0; 284 } 285 286 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 287 { 288 struct ath12k_pdev_dp *dp = &ar->dp; 289 struct ath12k_base *ab = ar->ab; 290 int i; 291 292 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) 293 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 294 } 295 296 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 297 { 298 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 299 int i; 300 301 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 302 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 303 } 304 305 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 306 { 307 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 308 int ret; 309 int i; 310 311 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 312 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 313 HAL_REO_DST, i, 0, 314 DP_REO_DST_RING_SIZE); 315 if (ret) { 316 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 317 goto err_reo_cleanup; 318 } 319 } 320 321 return 0; 322 323 err_reo_cleanup: 324 ath12k_dp_rx_pdev_reo_cleanup(ab); 325 326 return ret; 327 } 328 329 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 330 { 331 struct ath12k_pdev_dp *dp = &ar->dp; 332 struct ath12k_base *ab = ar->ab; 333 u32 monitor_dst_ring_size; 334 u32 mac_id = dp->mac_id; 335 int i; 336 int ret; 337 338 monitor_dst_ring_size = 339 ath12k_dp_rxdma_monitor_dst_ring_size(&ab->profile_param->dp_params); 340 341 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 342 ret = ath12k_dp_srng_setup(ar->ab, 343 &dp->rxdma_mon_dst_ring[i], 344 HAL_RXDMA_MONITOR_DST, 345 0, mac_id + i, 346 monitor_dst_ring_size); 347 if (ret) { 348 ath12k_warn(ar->ab, 349 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 350 return ret; 351 } 352 } 353 354 return 0; 355 } 356 357 void ath12k_dp_init_rx_tid_rxq(struct ath12k_dp_rx_tid_rxq *rx_tid_rxq, 358 struct ath12k_dp_rx_tid *rx_tid, 359 bool active) 360 { 361 rx_tid_rxq->tid = rx_tid->tid; 362 rx_tid_rxq->active = active; 363 rx_tid_rxq->qbuf = rx_tid->qbuf; 364 } 365 EXPORT_SYMBOL(ath12k_dp_init_rx_tid_rxq); 366 367 static void ath12k_dp_rx_tid_cleanup(struct ath12k_base *ab, 368 struct ath12k_reoq_buf *tid_qbuf) 369 { 370 if (tid_qbuf->vaddr) { 371 dma_unmap_single(ab->dev, tid_qbuf->paddr_aligned, 372 tid_qbuf->size, DMA_BIDIRECTIONAL); 373 kfree(tid_qbuf->vaddr); 374 tid_qbuf->vaddr = NULL; 375 } 376 } 377 378 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 379 { 380 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 381 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 382 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 383 struct dp_reo_update_rx_queue_elem *cmd_queue, *tmp_queue; 384 385 spin_lock_bh(&dp->reo_rxq_flush_lock); 386 list_for_each_entry_safe(cmd_queue, tmp_queue, &dp->reo_cmd_update_rx_queue_list, 387 list) { 388 list_del(&cmd_queue->list); 389 ath12k_dp_rx_tid_cleanup(ab, &cmd_queue->rx_tid.qbuf); 390 kfree(cmd_queue); 391 } 392 list_for_each_entry_safe(cmd_cache, tmp_cache, 393 &dp->reo_cmd_cache_flush_list, list) { 394 list_del(&cmd_cache->list); 395 dp->reo_cmd_cache_flush_count--; 396 ath12k_dp_rx_tid_cleanup(ab, &cmd_cache->data.qbuf); 397 kfree(cmd_cache); 398 } 399 spin_unlock_bh(&dp->reo_rxq_flush_lock); 400 401 spin_lock_bh(&dp->reo_cmd_lock); 402 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 403 list_del(&cmd->list); 404 ath12k_dp_rx_tid_cleanup(ab, &cmd->data.qbuf); 405 kfree(cmd); 406 } 407 spin_unlock_bh(&dp->reo_cmd_lock); 408 } 409 410 void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 411 enum hal_reo_cmd_status status) 412 { 413 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 414 415 if (status != HAL_REO_CMD_SUCCESS) 416 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 417 rx_tid->tid, status); 418 419 ath12k_dp_rx_tid_cleanup(dp->ab, &rx_tid->qbuf); 420 } 421 EXPORT_SYMBOL(ath12k_dp_reo_cmd_free); 422 423 void ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(struct ath12k_dp *dp) 424 { 425 struct ath12k_base *ab = dp->ab; 426 struct dp_reo_update_rx_queue_elem *elem, *tmp; 427 428 spin_lock_bh(&dp->reo_rxq_flush_lock); 429 430 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_update_rx_queue_list, list) { 431 if (elem->rx_tid.active) 432 continue; 433 434 if (ath12k_dp_rx_tid_delete_handler(ab, &elem->rx_tid)) 435 break; 436 437 ath12k_dp_arch_peer_rx_tid_qref_reset(dp, 438 elem->is_ml_peer ? 439 elem->ml_peer_id : elem->peer_id, 440 elem->rx_tid.tid); 441 442 if (ab->hw_params->reoq_lut_support) 443 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 444 445 list_del(&elem->list); 446 kfree(elem); 447 } 448 449 spin_unlock_bh(&dp->reo_rxq_flush_lock); 450 } 451 EXPORT_SYMBOL(ath12k_dp_rx_process_reo_cmd_update_rx_queue_list); 452 453 void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 454 enum hal_reo_cmd_status status) 455 { 456 struct ath12k_base *ab = dp->ab; 457 struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 458 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 459 460 if (status == HAL_REO_CMD_DRAIN) { 461 goto free_desc; 462 } else if (status != HAL_REO_CMD_SUCCESS) { 463 /* Shouldn't happen! Cleanup in case of other failure? */ 464 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 465 rx_tid->tid, status); 466 return; 467 } 468 469 /* Retry the HAL_REO_CMD_UPDATE_RX_QUEUE command for entries 470 * in the pending queue list marked TID as inactive 471 */ 472 spin_lock_bh(&dp->dp_lock); 473 ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 474 spin_unlock_bh(&dp->dp_lock); 475 476 elem = kzalloc_obj(*elem, GFP_ATOMIC); 477 if (!elem) 478 goto free_desc; 479 480 elem->ts = jiffies; 481 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 482 483 spin_lock_bh(&dp->reo_rxq_flush_lock); 484 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 485 dp->reo_cmd_cache_flush_count++; 486 487 /* Flush and invalidate aged REO desc from HW cache */ 488 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 489 list) { 490 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 491 time_after(jiffies, elem->ts + 492 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 493 /* The reo_cmd_cache_flush_list is used in only two contexts, 494 * one is in this function called from napi and the 495 * other in ath12k_dp_free during core destroy. 496 * If cache command sent is success, delete the element in 497 * the cache list. ath12k_dp_rx_reo_cmd_list_cleanup 498 * will be called during core destroy. 499 */ 500 501 if (ath12k_dp_arch_reo_cache_flush(dp, &elem->data)) 502 break; 503 504 list_del(&elem->list); 505 dp->reo_cmd_cache_flush_count--; 506 507 kfree(elem); 508 } 509 } 510 spin_unlock_bh(&dp->reo_rxq_flush_lock); 511 512 return; 513 free_desc: 514 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 515 } 516 EXPORT_SYMBOL(ath12k_dp_rx_tid_del_func); 517 518 static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 519 struct ath12k_dp_rx_tid_rxq *rx_tid) 520 { 521 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 522 523 return ath12k_dp_arch_rx_tid_delete_handler(dp, rx_tid); 524 } 525 526 void ath12k_dp_mark_tid_as_inactive(struct ath12k_dp *dp, int peer_id, u8 tid) 527 { 528 struct dp_reo_update_rx_queue_elem *elem; 529 struct ath12k_dp_rx_tid_rxq *rx_tid; 530 531 spin_lock_bh(&dp->reo_rxq_flush_lock); 532 list_for_each_entry(elem, &dp->reo_cmd_update_rx_queue_list, list) { 533 if (elem->peer_id == peer_id) { 534 rx_tid = &elem->rx_tid; 535 if (rx_tid->tid == tid) { 536 rx_tid->active = false; 537 break; 538 } 539 } 540 } 541 spin_unlock_bh(&dp->reo_rxq_flush_lock); 542 } 543 EXPORT_SYMBOL(ath12k_dp_mark_tid_as_inactive); 544 545 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_dp_link_peer *peer) 546 { 547 struct ath12k_dp_rx_tid *rx_tid; 548 int i; 549 struct ath12k_base *ab = ar->ab; 550 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 551 552 lockdep_assert_held(&dp->dp_lock); 553 554 if (!peer->primary_link) 555 return; 556 557 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 558 rx_tid = &peer->dp_peer->rx_tid[i]; 559 560 ath12k_dp_arch_rx_peer_tid_delete(dp, peer, i); 561 ath12k_dp_arch_rx_frags_cleanup(dp, rx_tid, true); 562 563 spin_unlock_bh(&dp->dp_lock); 564 timer_delete_sync(&rx_tid->frag_timer); 565 spin_lock_bh(&dp->dp_lock); 566 } 567 } 568 569 static int ath12k_dp_prepare_reo_update_elem(struct ath12k_dp *dp, 570 struct ath12k_dp_link_peer *peer, 571 struct ath12k_dp_rx_tid *rx_tid) 572 { 573 struct dp_reo_update_rx_queue_elem *elem; 574 575 lockdep_assert_held(&dp->dp_lock); 576 577 if (!peer->primary_link) 578 return 0; 579 580 elem = kzalloc_obj(*elem, GFP_ATOMIC); 581 if (!elem) 582 return -ENOMEM; 583 584 elem->peer_id = peer->peer_id; 585 elem->is_ml_peer = peer->mlo; 586 elem->ml_peer_id = peer->ml_id; 587 588 ath12k_dp_init_rx_tid_rxq(&elem->rx_tid, rx_tid, 589 (peer->rx_tid_active_bitmask & (1 << rx_tid->tid))); 590 591 spin_lock_bh(&dp->reo_rxq_flush_lock); 592 list_add_tail(&elem->list, &dp->reo_cmd_update_rx_queue_list); 593 spin_unlock_bh(&dp->reo_rxq_flush_lock); 594 595 return 0; 596 } 597 598 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 599 u8 tid, u32 ba_win_sz, u16 ssn, 600 enum hal_pn_type pn_type) 601 { 602 struct ath12k_base *ab = ar->ab; 603 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 604 struct ath12k_dp_link_peer *peer; 605 struct ath12k_dp_rx_tid *rx_tid; 606 dma_addr_t paddr_aligned; 607 int ret; 608 609 spin_lock_bh(&dp->dp_lock); 610 611 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, peer_mac); 612 if (!peer || !peer->dp_peer) { 613 spin_unlock_bh(&dp->dp_lock); 614 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 615 return -ENOENT; 616 } 617 618 if (ab->hw_params->dp_primary_link_only && 619 !peer->primary_link) { 620 spin_unlock_bh(&dp->dp_lock); 621 return 0; 622 } 623 624 if (ab->hw_params->reoq_lut_support && 625 (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { 626 spin_unlock_bh(&dp->dp_lock); 627 ath12k_warn(ab, "reo qref table is not setup\n"); 628 return -EINVAL; 629 } 630 631 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 632 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 633 peer->peer_id, tid); 634 spin_unlock_bh(&dp->dp_lock); 635 return -EINVAL; 636 } 637 638 rx_tid = &peer->dp_peer->rx_tid[tid]; 639 /* Update the tid queue if it is already setup */ 640 if (peer->rx_tid_active_bitmask & (1 << tid)) { 641 ret = ath12k_dp_arch_peer_rx_tid_reo_update(dp, peer, rx_tid, 642 ba_win_sz, ssn, true); 643 spin_unlock_bh(&dp->dp_lock); 644 if (ret) { 645 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 646 return ret; 647 } 648 649 if (!ab->hw_params->reoq_lut_support) { 650 paddr_aligned = rx_tid->qbuf.paddr_aligned; 651 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 652 peer_mac, 653 paddr_aligned, tid, 654 1, ba_win_sz); 655 if (ret) { 656 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 657 tid, ret); 658 return ret; 659 } 660 } 661 662 return 0; 663 } 664 665 rx_tid->tid = tid; 666 667 rx_tid->ba_win_sz = ba_win_sz; 668 669 ret = ath12k_dp_arch_rx_assign_reoq(dp, peer->dp_peer, rx_tid, ssn, pn_type); 670 if (ret) { 671 spin_unlock_bh(&dp->dp_lock); 672 ath12k_warn(ab, "failed to assign reoq buf for rx tid %u\n", tid); 673 return ret; 674 } 675 676 peer->rx_tid_active_bitmask |= (1 << tid); 677 678 /* Pre-allocate the update_rxq_list for the corresponding tid 679 * This will be used during the tid delete. The reason we are not 680 * allocating during tid delete is that, if any alloc fail in update_rxq_list 681 * we may not be able to delete the tid vaddr/paddr and may lead to leak 682 */ 683 ret = ath12k_dp_prepare_reo_update_elem(dp, peer, rx_tid); 684 if (ret) { 685 ath12k_warn(ab, "failed to alloc update_rxq_list for rx tid %u\n", tid); 686 ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 687 spin_unlock_bh(&dp->dp_lock); 688 return ret; 689 } 690 691 paddr_aligned = rx_tid->qbuf.paddr_aligned; 692 if (ab->hw_params->reoq_lut_support) { 693 /* Update the REO queue LUT at the corresponding peer id 694 * and tid with qaddr. 695 */ 696 if (peer->mlo) 697 ath12k_dp_arch_peer_rx_tid_qref_setup(dp, peer->ml_id, tid, 698 paddr_aligned); 699 else 700 ath12k_dp_arch_peer_rx_tid_qref_setup(dp, peer->peer_id, tid, 701 paddr_aligned); 702 703 spin_unlock_bh(&dp->dp_lock); 704 } else { 705 spin_unlock_bh(&dp->dp_lock); 706 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 707 paddr_aligned, tid, 1, 708 ba_win_sz); 709 } 710 711 return ret; 712 } 713 714 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 715 struct ieee80211_ampdu_params *params, 716 u8 link_id) 717 { 718 struct ath12k_base *ab = ar->ab; 719 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 720 struct ath12k_link_sta *arsta; 721 int vdev_id; 722 int ret; 723 724 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 725 726 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 727 ahsta->link[link_id]); 728 if (!arsta) 729 return -ENOLINK; 730 731 vdev_id = arsta->arvif->vdev_id; 732 733 ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id, 734 params->tid, params->buf_size, 735 params->ssn, arsta->ahsta->pn_type); 736 if (ret) 737 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 738 739 return ret; 740 } 741 742 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 743 struct ieee80211_ampdu_params *params, 744 u8 link_id) 745 { 746 struct ath12k_base *ab = ar->ab; 747 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 748 struct ath12k_dp_link_peer *peer; 749 struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); 750 struct ath12k_dp_rx_tid *rx_tid; 751 struct ath12k_link_sta *arsta; 752 int vdev_id; 753 bool active; 754 int ret; 755 756 lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy); 757 758 arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy, 759 ahsta->link[link_id]); 760 if (!arsta) 761 return -ENOLINK; 762 763 vdev_id = arsta->arvif->vdev_id; 764 765 spin_lock_bh(&dp->dp_lock); 766 767 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, arsta->addr); 768 if (!peer || !peer->dp_peer) { 769 spin_unlock_bh(&dp->dp_lock); 770 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 771 return -ENOENT; 772 } 773 774 if (ab->hw_params->dp_primary_link_only && 775 !peer->primary_link) { 776 spin_unlock_bh(&dp->dp_lock); 777 return 0; 778 } 779 780 active = peer->rx_tid_active_bitmask & (1 << params->tid); 781 if (!active) { 782 spin_unlock_bh(&dp->dp_lock); 783 return 0; 784 } 785 786 rx_tid = &peer->dp_peer->rx_tid[params->tid]; 787 ret = ath12k_dp_arch_peer_rx_tid_reo_update(dp, peer, rx_tid, 788 1, 0, false); 789 spin_unlock_bh(&dp->dp_lock); 790 if (ret) { 791 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 792 params->tid, ret); 793 return ret; 794 } 795 796 return ret; 797 } 798 799 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, 800 const u8 *peer_addr, 801 enum set_key_cmd key_cmd, 802 struct ieee80211_key_conf *key) 803 { 804 struct ath12k *ar = arvif->ar; 805 struct ath12k_base *ab = ar->ab; 806 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 807 struct ath12k_hal_reo_cmd cmd = {}; 808 struct ath12k_dp_link_peer *peer; 809 struct ath12k_dp_rx_tid *rx_tid; 810 struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 811 u8 tid; 812 int ret = 0; 813 814 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 815 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 816 * for now. 817 */ 818 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 819 return 0; 820 821 spin_lock_bh(&dp->dp_lock); 822 823 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, arvif->vdev_id, 824 peer_addr); 825 if (!peer || !peer->dp_peer) { 826 spin_unlock_bh(&dp->dp_lock); 827 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 828 peer_addr); 829 return -ENOENT; 830 } 831 832 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 833 if (!(peer->rx_tid_active_bitmask & (1 << tid))) 834 continue; 835 836 rx_tid = &peer->dp_peer->rx_tid[tid]; 837 ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid, 838 (peer->rx_tid_active_bitmask & (1 << tid))); 839 ath12k_dp_arch_setup_pn_check_reo_cmd(dp, &cmd, rx_tid, key->cipher, 840 key_cmd); 841 ret = ath12k_dp_arch_reo_cmd_send(dp, &rx_tid_rxq, 842 HAL_REO_CMD_UPDATE_RX_QUEUE, 843 &cmd, NULL); 844 if (ret) { 845 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 846 tid, peer_addr, ret); 847 break; 848 } 849 } 850 851 spin_unlock_bh(&dp->dp_lock); 852 853 return ret; 854 } 855 EXPORT_SYMBOL(ath12k_dp_rx_get_msdu_last_buf); 856 857 struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 858 struct sk_buff *first) 859 { 860 struct sk_buff *skb; 861 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 862 863 if (!rxcb->is_continuation) 864 return first; 865 866 skb_queue_walk(msdu_list, skb) { 867 rxcb = ATH12K_SKB_RXCB(skb); 868 if (!rxcb->is_continuation) 869 return skb; 870 } 871 872 return NULL; 873 } 874 875 int ath12k_dp_rx_crypto_mic_len(struct ath12k_dp *dp, enum hal_encrypt_type enctype) 876 { 877 switch (enctype) { 878 case HAL_ENCRYPT_TYPE_OPEN: 879 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 880 case HAL_ENCRYPT_TYPE_TKIP_MIC: 881 return 0; 882 case HAL_ENCRYPT_TYPE_CCMP_128: 883 return IEEE80211_CCMP_MIC_LEN; 884 case HAL_ENCRYPT_TYPE_CCMP_256: 885 return IEEE80211_CCMP_256_MIC_LEN; 886 case HAL_ENCRYPT_TYPE_GCMP_128: 887 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 888 return IEEE80211_GCMP_MIC_LEN; 889 case HAL_ENCRYPT_TYPE_WEP_40: 890 case HAL_ENCRYPT_TYPE_WEP_104: 891 case HAL_ENCRYPT_TYPE_WEP_128: 892 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 893 case HAL_ENCRYPT_TYPE_WAPI: 894 break; 895 } 896 897 ath12k_warn(dp->ab, "unsupported encryption type %d for mic len\n", enctype); 898 return 0; 899 } 900 901 static int ath12k_dp_rx_crypto_param_len(struct ath12k_pdev_dp *dp_pdev, 902 enum hal_encrypt_type enctype) 903 { 904 switch (enctype) { 905 case HAL_ENCRYPT_TYPE_OPEN: 906 return 0; 907 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 908 case HAL_ENCRYPT_TYPE_TKIP_MIC: 909 return IEEE80211_TKIP_IV_LEN; 910 case HAL_ENCRYPT_TYPE_CCMP_128: 911 return IEEE80211_CCMP_HDR_LEN; 912 case HAL_ENCRYPT_TYPE_CCMP_256: 913 return IEEE80211_CCMP_256_HDR_LEN; 914 case HAL_ENCRYPT_TYPE_GCMP_128: 915 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 916 return IEEE80211_GCMP_HDR_LEN; 917 case HAL_ENCRYPT_TYPE_WEP_40: 918 case HAL_ENCRYPT_TYPE_WEP_104: 919 case HAL_ENCRYPT_TYPE_WEP_128: 920 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 921 case HAL_ENCRYPT_TYPE_WAPI: 922 break; 923 } 924 925 ath12k_warn(dp_pdev->dp->ab, "unsupported encryption type %d\n", enctype); 926 return 0; 927 } 928 929 static int ath12k_dp_rx_crypto_icv_len(struct ath12k_pdev_dp *dp_pdev, 930 enum hal_encrypt_type enctype) 931 { 932 switch (enctype) { 933 case HAL_ENCRYPT_TYPE_OPEN: 934 case HAL_ENCRYPT_TYPE_CCMP_128: 935 case HAL_ENCRYPT_TYPE_CCMP_256: 936 case HAL_ENCRYPT_TYPE_GCMP_128: 937 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 938 return 0; 939 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 940 case HAL_ENCRYPT_TYPE_TKIP_MIC: 941 return IEEE80211_TKIP_ICV_LEN; 942 case HAL_ENCRYPT_TYPE_WEP_40: 943 case HAL_ENCRYPT_TYPE_WEP_104: 944 case HAL_ENCRYPT_TYPE_WEP_128: 945 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 946 case HAL_ENCRYPT_TYPE_WAPI: 947 break; 948 } 949 950 ath12k_warn(dp_pdev->dp->ab, "unsupported encryption type %d\n", enctype); 951 return 0; 952 } 953 954 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k_pdev_dp *dp_pdev, 955 struct sk_buff *msdu, 956 enum hal_encrypt_type enctype, 957 struct hal_rx_desc_data *rx_info) 958 { 959 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 960 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 961 struct ieee80211_hdr *hdr; 962 size_t hdr_len; 963 u8 *crypto_hdr; 964 u16 qos_ctl; 965 966 /* pull decapped header */ 967 hdr = (struct ieee80211_hdr *)msdu->data; 968 hdr_len = ieee80211_hdrlen(hdr->frame_control); 969 skb_pull(msdu, hdr_len); 970 971 /* Rebuild qos header */ 972 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 973 974 /* Reset the order bit as the HT_Control header is stripped */ 975 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 976 977 qos_ctl = rxcb->tid; 978 979 if (rx_info->mesh_ctrl_present) 980 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 981 982 /* TODO: Add other QoS ctl fields when required */ 983 984 /* copy decap header before overwriting for reuse below */ 985 memcpy(decap_hdr, hdr, hdr_len); 986 987 /* Rebuild crypto header for mac80211 use */ 988 if (!(rx_info->rx_status->flag & RX_FLAG_IV_STRIPPED)) { 989 crypto_hdr = skb_push(msdu, 990 ath12k_dp_rx_crypto_param_len(dp_pdev, enctype)); 991 ath12k_dp_rx_desc_get_crypto_header(dp_pdev->dp->hal, 992 rxcb->rx_desc, crypto_hdr, 993 enctype); 994 } 995 996 memcpy(skb_push(msdu, 997 IEEE80211_QOS_CTL_LEN), &qos_ctl, 998 IEEE80211_QOS_CTL_LEN); 999 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 1000 } 1001 1002 static void ath12k_dp_rx_h_undecap_raw(struct ath12k_pdev_dp *dp_pdev, 1003 struct sk_buff *msdu, 1004 enum hal_encrypt_type enctype, 1005 struct ieee80211_rx_status *status, 1006 bool decrypted) 1007 { 1008 struct ath12k_dp *dp = dp_pdev->dp; 1009 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1010 struct ieee80211_hdr *hdr; 1011 size_t hdr_len; 1012 size_t crypto_len; 1013 1014 if (!rxcb->is_first_msdu || 1015 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 1016 WARN_ON_ONCE(1); 1017 return; 1018 } 1019 1020 skb_trim(msdu, msdu->len - FCS_LEN); 1021 1022 if (!decrypted) 1023 return; 1024 1025 hdr = (void *)msdu->data; 1026 1027 /* Tail */ 1028 if (status->flag & RX_FLAG_IV_STRIPPED) { 1029 skb_trim(msdu, msdu->len - 1030 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1031 1032 skb_trim(msdu, msdu->len - 1033 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1034 } else { 1035 /* MIC */ 1036 if (status->flag & RX_FLAG_MIC_STRIPPED) 1037 skb_trim(msdu, msdu->len - 1038 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1039 1040 /* ICV */ 1041 if (status->flag & RX_FLAG_ICV_STRIPPED) 1042 skb_trim(msdu, msdu->len - 1043 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1044 } 1045 1046 /* MMIC */ 1047 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 1048 !ieee80211_has_morefrags(hdr->frame_control) && 1049 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 1050 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 1051 1052 /* Head */ 1053 if (status->flag & RX_FLAG_IV_STRIPPED) { 1054 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1055 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1056 1057 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 1058 skb_pull(msdu, crypto_len); 1059 } 1060 } 1061 1062 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k_pdev_dp *dp_pdev, 1063 struct sk_buff *msdu, 1064 struct ath12k_skb_rxcb *rxcb, 1065 enum hal_encrypt_type enctype, 1066 struct hal_rx_desc_data *rx_info) 1067 { 1068 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 1069 struct ath12k_dp *dp = dp_pdev->dp; 1070 struct ath12k_hal *hal = dp->hal; 1071 size_t hdr_len, crypto_len; 1072 struct ieee80211_hdr hdr; 1073 __le16 qos_ctl; 1074 u8 *crypto_hdr; 1075 1076 ath12k_dp_rx_desc_get_dot11_hdr(hal, rx_desc, &hdr); 1077 hdr_len = ieee80211_hdrlen(hdr.frame_control); 1078 1079 if (!(rx_info->rx_status->flag & RX_FLAG_IV_STRIPPED)) { 1080 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1081 crypto_hdr = skb_push(msdu, crypto_len); 1082 ath12k_dp_rx_desc_get_crypto_header(dp->hal, rx_desc, crypto_hdr, 1083 enctype); 1084 } 1085 1086 skb_push(msdu, hdr_len); 1087 memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr))); 1088 1089 if (rxcb->is_mcbc) 1090 rx_info->rx_status->flag &= ~RX_FLAG_PN_VALIDATED; 1091 1092 /* Add QOS header */ 1093 if (ieee80211_is_data_qos(hdr.frame_control)) { 1094 struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data; 1095 1096 qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK); 1097 if (rx_info->mesh_ctrl_present) 1098 qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT); 1099 1100 memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN); 1101 } 1102 } 1103 1104 static void ath12k_dp_rx_h_undecap_eth(struct ath12k_pdev_dp *dp_pdev, 1105 struct sk_buff *msdu, 1106 enum hal_encrypt_type enctype, 1107 struct hal_rx_desc_data *rx_info, 1108 enum ath12k_dp_rx_decap_type decap_type) 1109 { 1110 struct ieee80211_hdr *hdr; 1111 struct ethhdr *eth; 1112 u8 da[ETH_ALEN]; 1113 u8 sa[ETH_ALEN]; 1114 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1115 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 1116 struct ath12k_dp_rx_rfc1042_hdr *llc; 1117 1118 eth = (struct ethhdr *)msdu->data; 1119 ether_addr_copy(da, eth->h_dest); 1120 ether_addr_copy(sa, eth->h_source); 1121 if (decap_type == DP_RX_DECAP_TYPE_8023) { 1122 /* 1123 * For 802.3 frames, eth->h_proto carries a length field, not 1124 * an EtherType. The actual EtherType is in the LLC/SNAP header 1125 * that follows the Ethernet header. 1126 */ 1127 llc = (struct ath12k_dp_rx_rfc1042_hdr *)(msdu->data + sizeof(*eth)); 1128 rfc.snap_type = llc->snap_type; 1129 skb_pull(msdu, sizeof(*eth) + sizeof(*llc)); 1130 } else { 1131 rfc.snap_type = eth->h_proto; 1132 skb_pull(msdu, sizeof(*eth)); 1133 } 1134 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 1135 sizeof(rfc)); 1136 ath12k_get_dot11_hdr_from_rx_desc(dp_pdev, msdu, rxcb, enctype, rx_info); 1137 1138 /* original 802.11 header has a different DA and in 1139 * case of 4addr it may also have different SA 1140 */ 1141 hdr = (struct ieee80211_hdr *)msdu->data; 1142 ether_addr_copy(ieee80211_get_DA(hdr), da); 1143 ether_addr_copy(ieee80211_get_SA(hdr), sa); 1144 } 1145 1146 void ath12k_dp_rx_h_undecap(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *msdu, 1147 enum hal_encrypt_type enctype, 1148 bool decrypted, 1149 struct hal_rx_desc_data *rx_info, 1150 struct ath12k_dp_peer *peer) 1151 { 1152 enum ath12k_dp_rx_decap_type decap_type = rx_info->decap_type; 1153 struct ethhdr *ehdr; 1154 1155 switch (decap_type) { 1156 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 1157 ath12k_dp_rx_h_undecap_nwifi(dp_pdev, msdu, enctype, rx_info); 1158 break; 1159 case DP_RX_DECAP_TYPE_RAW: 1160 ath12k_dp_rx_h_undecap_raw(dp_pdev, msdu, enctype, rx_info->rx_status, 1161 decrypted); 1162 break; 1163 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 1164 ehdr = (struct ethhdr *)msdu->data; 1165 1166 /* mac80211 allows fast path only for authorized STA */ 1167 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 1168 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 1169 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1170 decap_type); 1171 break; 1172 } 1173 1174 if (peer && !peer->use_4addr && 1175 rx_info->is_from_ds && rx_info->is_to_ds) { 1176 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1177 decap_type); 1178 break; 1179 } 1180 1181 /* PN for mcast packets will be validated in mac80211; 1182 * remove eth header and add 802.11 header. 1183 */ 1184 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) { 1185 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1186 decap_type); 1187 break; 1188 } 1189 1190 rx_info->rx_status->flag |= RX_FLAG_8023; 1191 break; 1192 case DP_RX_DECAP_TYPE_8023: 1193 /* 1194 * Note that ethernet decap format indicates that the decapped 1195 * packet is either Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC). 1196 */ 1197 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) { 1198 ath12k_dp_rx_h_undecap_eth(dp_pdev, msdu, enctype, rx_info, 1199 decap_type); 1200 break; 1201 } 1202 rx_info->rx_status->flag |= RX_FLAG_8023; 1203 } 1204 } 1205 EXPORT_SYMBOL(ath12k_dp_rx_h_undecap); 1206 1207 static void ath12k_dp_rx_h_rate(struct ath12k_pdev_dp *dp_pdev, 1208 struct hal_rx_desc_data *rx_info) 1209 { 1210 struct ath12k_dp *dp = dp_pdev->dp; 1211 struct ieee80211_supported_band *sband; 1212 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 1213 enum rx_msdu_start_pkt_type pkt_type = rx_info->pkt_type; 1214 u8 bw = rx_info->bw, sgi = rx_info->sgi; 1215 u8 rate_mcs = rx_info->rate_mcs, nss = rx_info->nss; 1216 bool is_cck; 1217 struct ath12k *ar; 1218 1219 switch (pkt_type) { 1220 case RX_MSDU_START_PKT_TYPE_11A: 1221 case RX_MSDU_START_PKT_TYPE_11B: 1222 ar = ath12k_pdev_dp_to_ar(dp_pdev); 1223 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 1224 sband = &ar->mac.sbands[rx_status->band]; 1225 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 1226 is_cck); 1227 break; 1228 case RX_MSDU_START_PKT_TYPE_11N: 1229 rx_status->encoding = RX_ENC_HT; 1230 if (rate_mcs > ATH12K_HT_MCS_MAX) { 1231 ath12k_warn(dp->ab, 1232 "Received with invalid mcs in HT mode %d\n", 1233 rate_mcs); 1234 break; 1235 } 1236 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 1237 if (sgi) 1238 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1239 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1240 break; 1241 case RX_MSDU_START_PKT_TYPE_11AC: 1242 rx_status->encoding = RX_ENC_VHT; 1243 rx_status->rate_idx = rate_mcs; 1244 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 1245 ath12k_warn(dp->ab, 1246 "Received with invalid mcs in VHT mode %d\n", 1247 rate_mcs); 1248 break; 1249 } 1250 rx_status->nss = nss; 1251 if (sgi) 1252 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1253 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1254 break; 1255 case RX_MSDU_START_PKT_TYPE_11AX: 1256 rx_status->rate_idx = rate_mcs; 1257 if (rate_mcs > ATH12K_HE_MCS_MAX) { 1258 ath12k_warn(dp->ab, 1259 "Received with invalid mcs in HE mode %d\n", 1260 rate_mcs); 1261 break; 1262 } 1263 rx_status->encoding = RX_ENC_HE; 1264 rx_status->nss = nss; 1265 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1266 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1267 break; 1268 case RX_MSDU_START_PKT_TYPE_11BE: 1269 rx_status->rate_idx = rate_mcs; 1270 1271 if (rate_mcs > ATH12K_EHT_MCS_MAX) { 1272 ath12k_warn(dp->ab, 1273 "Received with invalid mcs in EHT mode %d\n", 1274 rate_mcs); 1275 break; 1276 } 1277 1278 rx_status->encoding = RX_ENC_EHT; 1279 rx_status->nss = nss; 1280 rx_status->eht.gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi); 1281 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 1282 break; 1283 default: 1284 break; 1285 } 1286 } 1287 1288 void ath12k_dp_rx_h_ppdu(struct ath12k_pdev_dp *dp_pdev, 1289 struct hal_rx_desc_data *rx_info) 1290 { 1291 struct ieee80211_rx_status *rx_status = rx_info->rx_status; 1292 u8 channel_num; 1293 u32 center_freq, meta_data; 1294 struct ieee80211_channel *channel; 1295 1296 rx_status->freq = 0; 1297 rx_status->rate_idx = 0; 1298 rx_status->nss = 0; 1299 rx_status->encoding = RX_ENC_LEGACY; 1300 rx_status->bw = RATE_INFO_BW_20; 1301 rx_status->enc_flags = 0; 1302 1303 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 1304 1305 meta_data = rx_info->phy_meta_data; 1306 channel_num = meta_data; 1307 center_freq = meta_data >> 16; 1308 1309 rx_status->band = NUM_NL80211_BANDS; 1310 1311 if (center_freq >= ATH12K_MIN_6GHZ_FREQ && 1312 center_freq <= ATH12K_MAX_6GHZ_FREQ) { 1313 rx_status->band = NL80211_BAND_6GHZ; 1314 rx_status->freq = center_freq; 1315 } else if (channel_num >= ATH12K_2GHZ_MIN_CHAN_NUM && 1316 channel_num <= ATH12K_2GHZ_MAX_CHAN_NUM) { 1317 rx_status->band = NL80211_BAND_2GHZ; 1318 } else if (channel_num >= ATH12K_5GHZ_MIN_CHAN_NUM && 1319 channel_num <= ATH12K_5GHZ_MAX_CHAN_NUM) { 1320 rx_status->band = NL80211_BAND_5GHZ; 1321 } 1322 1323 if (unlikely(rx_status->band == NUM_NL80211_BANDS || 1324 !ath12k_pdev_dp_to_hw(dp_pdev)->wiphy->bands[rx_status->band])) { 1325 struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev); 1326 1327 ath12k_warn(ar->ab, "sband is NULL for status band %d channel_num %d center_freq %d pdev_id %d\n", 1328 rx_status->band, channel_num, center_freq, ar->pdev_idx); 1329 1330 spin_lock_bh(&ar->data_lock); 1331 channel = ar->rx_channel; 1332 if (channel) { 1333 rx_status->band = channel->band; 1334 channel_num = 1335 ieee80211_frequency_to_channel(channel->center_freq); 1336 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 1337 rx_status->band); 1338 } else { 1339 ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); 1340 } 1341 spin_unlock_bh(&ar->data_lock); 1342 goto h_rate; 1343 } 1344 1345 if (rx_status->band != NL80211_BAND_6GHZ) 1346 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 1347 rx_status->band); 1348 1349 h_rate: 1350 ath12k_dp_rx_h_rate(dp_pdev, rx_info); 1351 } 1352 EXPORT_SYMBOL(ath12k_dp_rx_h_ppdu); 1353 1354 void ath12k_dp_rx_deliver_msdu(struct ath12k_pdev_dp *dp_pdev, struct napi_struct *napi, 1355 struct sk_buff *msdu, 1356 struct hal_rx_desc_data *rx_info) 1357 { 1358 struct ath12k_dp *dp = dp_pdev->dp; 1359 struct ieee80211_rx_status *rx_status; 1360 struct ieee80211_sta *pubsta; 1361 struct ieee80211_link_sta *link_pubsta = NULL; 1362 struct ath12k_dp_peer *peer; 1363 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1364 struct ieee80211_rx_status *status = rx_info->rx_status; 1365 bool is_mcbc = rxcb->is_mcbc; 1366 1367 peer = ath12k_dp_peer_find_by_peerid(dp_pdev, rxcb->peer_id); 1368 1369 pubsta = peer ? peer->sta : NULL; 1370 1371 if (pubsta) { 1372 if (pubsta->valid_links) { 1373 int link_id = 1374 ath12k_hw_get_rx_link_id(dp->hw_params, peer, 1375 rxcb, status); 1376 1377 if (link_id >= 0) 1378 link_pubsta = 1379 rcu_dereference(pubsta->link[link_id]); 1380 } else { 1381 link_pubsta = &pubsta->deflink; 1382 } 1383 } 1384 1385 ath12k_dbg(dp->ab, ATH12K_DBG_DATA, 1386 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 1387 msdu, 1388 msdu->len, 1389 peer ? peer->addr : NULL, 1390 rxcb->tid, 1391 is_mcbc ? "mcast" : "ucast", 1392 rx_info->seq_no, 1393 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 1394 (status->encoding == RX_ENC_HT) ? "ht" : "", 1395 (status->encoding == RX_ENC_VHT) ? "vht" : "", 1396 (status->encoding == RX_ENC_HE) ? "he" : "", 1397 (status->encoding == RX_ENC_EHT) ? "eht" : "", 1398 (status->bw == RATE_INFO_BW_40) ? "40" : "", 1399 (status->bw == RATE_INFO_BW_80) ? "80" : "", 1400 (status->bw == RATE_INFO_BW_160) ? "160" : "", 1401 (status->bw == RATE_INFO_BW_320) ? "320" : "", 1402 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 1403 status->rate_idx, 1404 status->nss, 1405 status->freq, 1406 status->band, status->flag, 1407 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 1408 !!(status->flag & RX_FLAG_MMIC_ERROR), 1409 !!(status->flag & RX_FLAG_AMSDU_MORE)); 1410 1411 ath12k_dbg_dump(dp->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 1412 msdu->data, msdu->len); 1413 1414 rx_status = IEEE80211_SKB_RXCB(msdu); 1415 *rx_status = *status; 1416 1417 /* TODO: trace rx packet */ 1418 1419 ieee80211_rx_napi(ath12k_pdev_dp_to_hw(dp_pdev), link_pubsta, msdu, 1420 napi); 1421 } 1422 EXPORT_SYMBOL(ath12k_dp_rx_deliver_msdu); 1423 1424 bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_dp *dp, 1425 struct sk_buff *msdu, 1426 struct hal_rx_desc_data *rx_info) 1427 { 1428 struct ieee80211_hdr *hdr; 1429 u32 hdr_len; 1430 1431 if (rx_info->decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI) 1432 return true; 1433 1434 hdr = (struct ieee80211_hdr *)msdu->data; 1435 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1436 1437 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))) 1438 return true; 1439 1440 dp->device_stats.invalid_rbm++; 1441 WARN_ON_ONCE(1); 1442 return false; 1443 } 1444 EXPORT_SYMBOL(ath12k_dp_rx_check_nwifi_hdr_len_valid); 1445 1446 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 1447 { 1448 struct ath12k_dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer, 1449 frag_timer); 1450 1451 spin_lock_bh(&rx_tid->dp->dp_lock); 1452 if (rx_tid->last_frag_no && 1453 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 1454 spin_unlock_bh(&rx_tid->dp->dp_lock); 1455 return; 1456 } 1457 ath12k_dp_arch_rx_frags_cleanup(rx_tid->dp, rx_tid, true); 1458 spin_unlock_bh(&rx_tid->dp->dp_lock); 1459 } 1460 1461 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 1462 { 1463 struct ath12k_base *ab = ar->ab; 1464 struct ath12k_dp_link_peer *peer; 1465 struct ath12k_dp_rx_tid *rx_tid; 1466 int i; 1467 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1468 1469 if (fips_enabled) { 1470 ath12k_warn(ab, "This driver is disabled due to FIPS\n"); 1471 return -ENOENT; 1472 } 1473 1474 spin_lock_bh(&dp->dp_lock); 1475 1476 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, peer_mac); 1477 if (!peer || !peer->dp_peer) { 1478 spin_unlock_bh(&dp->dp_lock); 1479 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 1480 return -ENOENT; 1481 } 1482 1483 if (!peer->primary_link) { 1484 spin_unlock_bh(&dp->dp_lock); 1485 return 0; 1486 } 1487 1488 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 1489 rx_tid = &peer->dp_peer->rx_tid[i]; 1490 rx_tid->dp = dp; 1491 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 1492 skb_queue_head_init(&rx_tid->rx_frags); 1493 } 1494 1495 peer->dp_peer->dp_setup_done = true; 1496 spin_unlock_bh(&dp->dp_lock); 1497 1498 return 0; 1499 } 1500 1501 void ath12k_dp_rx_h_undecap_frag(struct ath12k_pdev_dp *dp_pdev, struct sk_buff *msdu, 1502 enum hal_encrypt_type enctype, u32 flags) 1503 { 1504 struct ath12k_dp *dp = dp_pdev->dp; 1505 struct ieee80211_hdr *hdr; 1506 size_t hdr_len; 1507 size_t crypto_len; 1508 u32 hal_rx_desc_sz = dp->ab->hal.hal_desc_sz; 1509 1510 if (!flags) 1511 return; 1512 1513 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 1514 1515 if (flags & RX_FLAG_MIC_STRIPPED) 1516 skb_trim(msdu, msdu->len - 1517 ath12k_dp_rx_crypto_mic_len(dp, enctype)); 1518 1519 if (flags & RX_FLAG_ICV_STRIPPED) 1520 skb_trim(msdu, msdu->len - 1521 ath12k_dp_rx_crypto_icv_len(dp_pdev, enctype)); 1522 1523 if (flags & RX_FLAG_IV_STRIPPED) { 1524 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1525 crypto_len = ath12k_dp_rx_crypto_param_len(dp_pdev, enctype); 1526 1527 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 1528 msdu->data + hal_rx_desc_sz, hdr_len); 1529 skb_pull(msdu, crypto_len); 1530 } 1531 } 1532 EXPORT_SYMBOL(ath12k_dp_rx_h_undecap_frag); 1533 1534 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_hal *hal, 1535 struct sk_buff *a, struct sk_buff *b) 1536 { 1537 int frag1, frag2; 1538 1539 frag1 = ath12k_dp_rx_h_frag_no(hal, a); 1540 frag2 = ath12k_dp_rx_h_frag_no(hal, b); 1541 1542 return frag1 - frag2; 1543 } 1544 1545 void ath12k_dp_rx_h_sort_frags(struct ath12k_hal *hal, 1546 struct sk_buff_head *frag_list, 1547 struct sk_buff *cur_frag) 1548 { 1549 struct sk_buff *skb; 1550 int cmp; 1551 1552 skb_queue_walk(frag_list, skb) { 1553 cmp = ath12k_dp_rx_h_cmp_frags(hal, skb, cur_frag); 1554 if (cmp < 0) 1555 continue; 1556 __skb_queue_before(frag_list, skb, cur_frag); 1557 return; 1558 } 1559 __skb_queue_tail(frag_list, cur_frag); 1560 } 1561 EXPORT_SYMBOL(ath12k_dp_rx_h_sort_frags); 1562 1563 u64 ath12k_dp_rx_h_get_pn(struct ath12k_dp *dp, struct sk_buff *skb) 1564 { 1565 struct ieee80211_hdr *hdr; 1566 u64 pn = 0; 1567 u8 *ehdr; 1568 u32 hal_rx_desc_sz = dp->ab->hal.hal_desc_sz; 1569 1570 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 1571 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 1572 1573 pn = ehdr[0]; 1574 pn |= (u64)ehdr[1] << 8; 1575 pn |= (u64)ehdr[4] << 16; 1576 pn |= (u64)ehdr[5] << 24; 1577 pn |= (u64)ehdr[6] << 32; 1578 pn |= (u64)ehdr[7] << 40; 1579 1580 return pn; 1581 } 1582 EXPORT_SYMBOL(ath12k_dp_rx_h_get_pn); 1583 1584 void ath12k_dp_rx_free(struct ath12k_base *ab) 1585 { 1586 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1587 struct dp_srng *srng; 1588 int i; 1589 1590 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 1591 1592 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1593 if (ab->hw_params->rx_mac_buf_ring) 1594 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 1595 if (!ab->hw_params->rxdma1_enable) { 1596 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 1597 ath12k_dp_srng_cleanup(ab, srng); 1598 } 1599 } 1600 1601 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 1602 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 1603 1604 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 1605 1606 ath12k_dp_rxdma_buf_free(ab); 1607 } 1608 1609 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 1610 { 1611 struct ath12k *ar = ab->pdevs[mac_id].ar; 1612 1613 ath12k_dp_rx_pdev_srng_free(ar); 1614 } 1615 1616 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 1617 { 1618 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1619 u32 ring_id; 1620 int i, ret; 1621 1622 /* TODO: Need to verify the HTT setup for QCN9224 */ 1623 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 1624 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 1625 if (ret) { 1626 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 1627 ret); 1628 return ret; 1629 } 1630 1631 if (ab->hw_params->rx_mac_buf_ring) { 1632 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1633 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1634 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1635 i, HAL_RXDMA_BUF); 1636 if (ret) { 1637 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 1638 i, ret); 1639 return ret; 1640 } 1641 } 1642 } 1643 1644 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 1645 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 1646 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1647 i, HAL_RXDMA_DST); 1648 if (ret) { 1649 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 1650 i, ret); 1651 return ret; 1652 } 1653 } 1654 1655 if (ab->hw_params->rxdma1_enable) { 1656 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1657 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1658 0, HAL_RXDMA_MONITOR_BUF); 1659 if (ret) { 1660 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 1661 ret); 1662 return ret; 1663 } 1664 } else { 1665 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1666 ring_id = 1667 dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1668 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, i, 1669 HAL_RXDMA_MONITOR_STATUS); 1670 if (ret) { 1671 ath12k_warn(ab, 1672 "failed to configure mon_status_refill_ring%d %d\n", 1673 i, ret); 1674 return ret; 1675 } 1676 } 1677 } 1678 1679 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 1680 if (ret) { 1681 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 1682 return ret; 1683 } 1684 1685 return 0; 1686 } 1687 1688 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 1689 { 1690 const struct ath12k_dp_profile_params *dp_params = &ab->profile_param->dp_params; 1691 u32 monitor_buf_ring_size = ath12k_dp_rxdma_monitor_buf_ring_size(dp_params); 1692 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1693 struct dp_srng *srng; 1694 int i, ret; 1695 1696 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 1697 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 1698 1699 ret = ath12k_dp_srng_setup(ab, 1700 &dp->rx_refill_buf_ring.refill_buf_ring, 1701 HAL_RXDMA_BUF, 0, 0, 1702 ath12k_dp_rxdma_buf_ring_size(dp_params)); 1703 if (ret) { 1704 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 1705 return ret; 1706 } 1707 1708 if (ab->hw_params->rx_mac_buf_ring) { 1709 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1710 ret = ath12k_dp_srng_setup(ab, 1711 &dp->rx_mac_buf_ring[i], 1712 HAL_RXDMA_BUF, 1, 1713 i, DP_RX_MAC_BUF_RING_SIZE); 1714 if (ret) { 1715 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 1716 i); 1717 return ret; 1718 } 1719 } 1720 } 1721 1722 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 1723 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 1724 HAL_RXDMA_DST, 0, i, 1725 DP_RXDMA_ERR_DST_RING_SIZE); 1726 if (ret) { 1727 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 1728 return ret; 1729 } 1730 } 1731 1732 if (ab->hw_params->rxdma1_enable) { 1733 ret = ath12k_dp_srng_setup(ab, 1734 &dp->rxdma_mon_buf_ring.refill_buf_ring, 1735 HAL_RXDMA_MONITOR_BUF, 0, 0, 1736 monitor_buf_ring_size); 1737 if (ret) { 1738 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 1739 return ret; 1740 } 1741 } else { 1742 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1743 idr_init(&dp->rx_mon_status_refill_ring[i].bufs_idr); 1744 spin_lock_init(&dp->rx_mon_status_refill_ring[i].idr_lock); 1745 } 1746 1747 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1748 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 1749 ret = ath12k_dp_srng_setup(ab, srng, 1750 HAL_RXDMA_MONITOR_STATUS, 0, i, 1751 DP_RXDMA_MON_STATUS_RING_SIZE); 1752 if (ret) { 1753 ath12k_warn(ab, "failed to setup mon status ring %d\n", 1754 i); 1755 return ret; 1756 } 1757 } 1758 } 1759 1760 ret = ath12k_dp_rxdma_buf_setup(ab); 1761 if (ret) { 1762 ath12k_warn(ab, "failed to setup rxdma ring\n"); 1763 return ret; 1764 } 1765 1766 return 0; 1767 } 1768 1769 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 1770 { 1771 struct ath12k *ar = ab->pdevs[mac_id].ar; 1772 struct ath12k_pdev_dp *dp = &ar->dp; 1773 u32 ring_id; 1774 int i; 1775 int ret; 1776 1777 if (!ab->hw_params->rxdma1_enable) 1778 goto out; 1779 1780 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 1781 if (ret) { 1782 ath12k_warn(ab, "failed to setup rx srngs\n"); 1783 return ret; 1784 } 1785 1786 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 1787 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 1788 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 1789 mac_id + i, 1790 HAL_RXDMA_MONITOR_DST); 1791 if (ret) { 1792 ath12k_warn(ab, 1793 "failed to configure rxdma_mon_dst_ring %d %d\n", 1794 i, ret); 1795 return ret; 1796 } 1797 } 1798 out: 1799 return 0; 1800 } 1801 1802 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 1803 { 1804 struct ath12k_pdev_dp *dp = &ar->dp; 1805 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 1806 1807 skb_queue_head_init(&pmon->rx_status_q); 1808 1809 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 1810 1811 memset(&pmon->rx_mon_stats, 0, 1812 sizeof(pmon->rx_mon_stats)); 1813 return 0; 1814 } 1815 1816 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 1817 { 1818 struct ath12k_pdev_dp *dp = &ar->dp; 1819 struct ath12k_mon_data *pmon = &dp->mon_data; 1820 int ret = 0; 1821 1822 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 1823 if (ret) { 1824 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 1825 return ret; 1826 } 1827 1828 pmon->mon_last_linkdesc_paddr = 0; 1829 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 1830 spin_lock_init(&pmon->mon_lock); 1831 1832 if (!ar->ab->hw_params->rxdma1_enable) 1833 return 0; 1834 1835 INIT_LIST_HEAD(&pmon->dp_rx_mon_mpdu_list); 1836 pmon->mon_mpdu = NULL; 1837 1838 return 0; 1839 } 1840