1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> 4 */ 5 6#include <dt-bindings/clock/spacemit,k1-syscon.h> 7#include <dt-bindings/phy/phy.h> 8 9/dts-v1/; 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 model = "SpacemiT K1"; 14 compatible = "spacemit,k1"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 timebase-frequency = <24000000>; 20 21 cpu-map { 22 cluster0 { 23 core0 { 24 cpu = <&cpu_0>; 25 }; 26 core1 { 27 cpu = <&cpu_1>; 28 }; 29 core2 { 30 cpu = <&cpu_2>; 31 }; 32 core3 { 33 cpu = <&cpu_3>; 34 }; 35 }; 36 37 cluster1 { 38 core0 { 39 cpu = <&cpu_4>; 40 }; 41 core1 { 42 cpu = <&cpu_5>; 43 }; 44 core2 { 45 cpu = <&cpu_6>; 46 }; 47 core3 { 48 cpu = <&cpu_7>; 49 }; 50 }; 51 }; 52 53 cpu_0: cpu@0 { 54 compatible = "spacemit,x60", "riscv"; 55 device_type = "cpu"; 56 reg = <0>; 57 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 58 riscv,isa-base = "rv64i"; 59 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 60 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 61 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 62 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 63 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 64 riscv,cbom-block-size = <64>; 65 riscv,cbop-block-size = <64>; 66 riscv,cboz-block-size = <64>; 67 i-cache-block-size = <64>; 68 i-cache-size = <32768>; 69 i-cache-sets = <128>; 70 d-cache-block-size = <64>; 71 d-cache-size = <32768>; 72 d-cache-sets = <128>; 73 next-level-cache = <&cluster0_l2_cache>; 74 mmu-type = "riscv,sv39"; 75 76 cpu0_intc: interrupt-controller { 77 compatible = "riscv,cpu-intc"; 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 }; 81 }; 82 83 cpu_1: cpu@1 { 84 compatible = "spacemit,x60", "riscv"; 85 device_type = "cpu"; 86 reg = <1>; 87 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 88 riscv,isa-base = "rv64i"; 89 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 90 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 91 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 92 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 93 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 94 riscv,cbom-block-size = <64>; 95 riscv,cbop-block-size = <64>; 96 riscv,cboz-block-size = <64>; 97 i-cache-block-size = <64>; 98 i-cache-size = <32768>; 99 i-cache-sets = <128>; 100 d-cache-block-size = <64>; 101 d-cache-size = <32768>; 102 d-cache-sets = <128>; 103 next-level-cache = <&cluster0_l2_cache>; 104 mmu-type = "riscv,sv39"; 105 106 cpu1_intc: interrupt-controller { 107 compatible = "riscv,cpu-intc"; 108 interrupt-controller; 109 #interrupt-cells = <1>; 110 }; 111 }; 112 113 cpu_2: cpu@2 { 114 compatible = "spacemit,x60", "riscv"; 115 device_type = "cpu"; 116 reg = <2>; 117 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 118 riscv,isa-base = "rv64i"; 119 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 120 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 121 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 122 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 123 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 124 riscv,cbom-block-size = <64>; 125 riscv,cbop-block-size = <64>; 126 riscv,cboz-block-size = <64>; 127 i-cache-block-size = <64>; 128 i-cache-size = <32768>; 129 i-cache-sets = <128>; 130 d-cache-block-size = <64>; 131 d-cache-size = <32768>; 132 d-cache-sets = <128>; 133 next-level-cache = <&cluster0_l2_cache>; 134 mmu-type = "riscv,sv39"; 135 136 cpu2_intc: interrupt-controller { 137 compatible = "riscv,cpu-intc"; 138 interrupt-controller; 139 #interrupt-cells = <1>; 140 }; 141 }; 142 143 cpu_3: cpu@3 { 144 compatible = "spacemit,x60", "riscv"; 145 device_type = "cpu"; 146 reg = <3>; 147 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 148 riscv,isa-base = "rv64i"; 149 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 150 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 151 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 152 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 153 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 154 riscv,cbom-block-size = <64>; 155 riscv,cbop-block-size = <64>; 156 riscv,cboz-block-size = <64>; 157 i-cache-block-size = <64>; 158 i-cache-size = <32768>; 159 i-cache-sets = <128>; 160 d-cache-block-size = <64>; 161 d-cache-size = <32768>; 162 d-cache-sets = <128>; 163 next-level-cache = <&cluster0_l2_cache>; 164 mmu-type = "riscv,sv39"; 165 166 cpu3_intc: interrupt-controller { 167 compatible = "riscv,cpu-intc"; 168 interrupt-controller; 169 #interrupt-cells = <1>; 170 }; 171 }; 172 173 cpu_4: cpu@4 { 174 compatible = "spacemit,x60", "riscv"; 175 device_type = "cpu"; 176 reg = <4>; 177 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 178 riscv,isa-base = "rv64i"; 179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 180 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 181 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 182 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 183 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 184 riscv,cbom-block-size = <64>; 185 riscv,cbop-block-size = <64>; 186 riscv,cboz-block-size = <64>; 187 i-cache-block-size = <64>; 188 i-cache-size = <32768>; 189 i-cache-sets = <128>; 190 d-cache-block-size = <64>; 191 d-cache-size = <32768>; 192 d-cache-sets = <128>; 193 next-level-cache = <&cluster1_l2_cache>; 194 mmu-type = "riscv,sv39"; 195 196 cpu4_intc: interrupt-controller { 197 compatible = "riscv,cpu-intc"; 198 interrupt-controller; 199 #interrupt-cells = <1>; 200 }; 201 }; 202 203 cpu_5: cpu@5 { 204 compatible = "spacemit,x60", "riscv"; 205 device_type = "cpu"; 206 reg = <5>; 207 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 208 riscv,isa-base = "rv64i"; 209 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 210 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 211 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 212 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 213 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 214 riscv,cbom-block-size = <64>; 215 riscv,cbop-block-size = <64>; 216 riscv,cboz-block-size = <64>; 217 i-cache-block-size = <64>; 218 i-cache-size = <32768>; 219 i-cache-sets = <128>; 220 d-cache-block-size = <64>; 221 d-cache-size = <32768>; 222 d-cache-sets = <128>; 223 next-level-cache = <&cluster1_l2_cache>; 224 mmu-type = "riscv,sv39"; 225 226 cpu5_intc: interrupt-controller { 227 compatible = "riscv,cpu-intc"; 228 interrupt-controller; 229 #interrupt-cells = <1>; 230 }; 231 }; 232 233 cpu_6: cpu@6 { 234 compatible = "spacemit,x60", "riscv"; 235 device_type = "cpu"; 236 reg = <6>; 237 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 238 riscv,isa-base = "rv64i"; 239 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 240 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 241 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 242 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 243 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 244 riscv,cbom-block-size = <64>; 245 riscv,cbop-block-size = <64>; 246 riscv,cboz-block-size = <64>; 247 i-cache-block-size = <64>; 248 i-cache-size = <32768>; 249 i-cache-sets = <128>; 250 d-cache-block-size = <64>; 251 d-cache-size = <32768>; 252 d-cache-sets = <128>; 253 next-level-cache = <&cluster1_l2_cache>; 254 mmu-type = "riscv,sv39"; 255 256 cpu6_intc: interrupt-controller { 257 compatible = "riscv,cpu-intc"; 258 interrupt-controller; 259 #interrupt-cells = <1>; 260 }; 261 }; 262 263 cpu_7: cpu@7 { 264 compatible = "spacemit,x60", "riscv"; 265 device_type = "cpu"; 266 reg = <7>; 267 riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 268 riscv,isa-base = "rv64i"; 269 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", 270 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 271 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 272 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 273 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 274 riscv,cbom-block-size = <64>; 275 riscv,cbop-block-size = <64>; 276 riscv,cboz-block-size = <64>; 277 i-cache-block-size = <64>; 278 i-cache-size = <32768>; 279 i-cache-sets = <128>; 280 d-cache-block-size = <64>; 281 d-cache-size = <32768>; 282 d-cache-sets = <128>; 283 next-level-cache = <&cluster1_l2_cache>; 284 mmu-type = "riscv,sv39"; 285 286 cpu7_intc: interrupt-controller { 287 compatible = "riscv,cpu-intc"; 288 interrupt-controller; 289 #interrupt-cells = <1>; 290 }; 291 }; 292 293 cluster0_l2_cache: l2-cache0 { 294 compatible = "cache"; 295 cache-block-size = <64>; 296 cache-level = <2>; 297 cache-size = <524288>; 298 cache-sets = <512>; 299 cache-unified; 300 }; 301 302 cluster1_l2_cache: l2-cache1 { 303 compatible = "cache"; 304 cache-block-size = <64>; 305 cache-level = <2>; 306 cache-size = <524288>; 307 cache-sets = <512>; 308 cache-unified; 309 }; 310 }; 311 312 clocks { 313 vctcxo_1m: clock-1m { 314 compatible = "fixed-clock"; 315 clock-frequency = <1000000>; 316 clock-output-names = "vctcxo_1m"; 317 #clock-cells = <0>; 318 }; 319 320 vctcxo_24m: clock-24m { 321 compatible = "fixed-clock"; 322 clock-frequency = <24000000>; 323 clock-output-names = "vctcxo_24m"; 324 #clock-cells = <0>; 325 }; 326 327 vctcxo_3m: clock-3m { 328 compatible = "fixed-clock"; 329 clock-frequency = <3000000>; 330 clock-output-names = "vctcxo_3m"; 331 #clock-cells = <0>; 332 }; 333 334 osc_32k: clock-32k { 335 compatible = "fixed-clock"; 336 clock-frequency = <32000>; 337 clock-output-names = "osc_32k"; 338 #clock-cells = <0>; 339 }; 340 }; 341 342 soc { 343 compatible = "simple-bus"; 344 interrupt-parent = <&plic>; 345 #address-cells = <2>; 346 #size-cells = <2>; 347 dma-noncoherent; 348 ranges; 349 350 syscon_rcpu: system-controller@c0880000 { 351 compatible = "spacemit,k1-syscon-rcpu"; 352 reg = <0x0 0xc0880000 0x0 0x2048>; 353 #reset-cells = <1>; 354 }; 355 356 syscon_rcpu2: system-controller@c0888000 { 357 compatible = "spacemit,k1-syscon-rcpu2"; 358 reg = <0x0 0xc0888000 0x0 0x28>; 359 #reset-cells = <1>; 360 }; 361 362 i2c0: i2c@d4010800 { 363 compatible = "spacemit,k1-i2c"; 364 reg = <0x0 0xd4010800 0x0 0x38>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clocks = <&syscon_apbc CLK_TWSI0>, 368 <&syscon_apbc CLK_TWSI0_BUS>; 369 clock-names = "func", "bus"; 370 clock-frequency = <400000>; 371 resets = <&syscon_apbc RESET_TWSI0>; 372 interrupts = <36>; 373 status = "disabled"; 374 }; 375 376 i2c1: i2c@d4011000 { 377 compatible = "spacemit,k1-i2c"; 378 reg = <0x0 0xd4011000 0x0 0x38>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&syscon_apbc CLK_TWSI1>, 382 <&syscon_apbc CLK_TWSI1_BUS>; 383 clock-names = "func", "bus"; 384 clock-frequency = <400000>; 385 resets = <&syscon_apbc RESET_TWSI1>; 386 interrupts = <37>; 387 status = "disabled"; 388 }; 389 390 i2c2: i2c@d4012000 { 391 compatible = "spacemit,k1-i2c"; 392 reg = <0x0 0xd4012000 0x0 0x38>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clocks = <&syscon_apbc CLK_TWSI2>, 396 <&syscon_apbc CLK_TWSI2_BUS>; 397 clock-names = "func", "bus"; 398 clock-frequency = <400000>; 399 resets = <&syscon_apbc RESET_TWSI2>; 400 interrupts = <38>; 401 status = "disabled"; 402 }; 403 404 i2c4: i2c@d4012800 { 405 compatible = "spacemit,k1-i2c"; 406 reg = <0x0 0xd4012800 0x0 0x38>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 clocks = <&syscon_apbc CLK_TWSI4>, 410 <&syscon_apbc CLK_TWSI4_BUS>; 411 clock-names = "func", "bus"; 412 clock-frequency = <400000>; 413 resets = <&syscon_apbc RESET_TWSI4>; 414 interrupts = <40>; 415 status = "disabled"; 416 }; 417 418 i2c5: i2c@d4013800 { 419 compatible = "spacemit,k1-i2c"; 420 reg = <0x0 0xd4013800 0x0 0x38>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 clocks = <&syscon_apbc CLK_TWSI5>, 424 <&syscon_apbc CLK_TWSI5_BUS>; 425 clock-names = "func", "bus"; 426 clock-frequency = <400000>; 427 resets = <&syscon_apbc RESET_TWSI5>; 428 interrupts = <41>; 429 status = "disabled"; 430 }; 431 432 usbphy2: phy@c0a30000 { 433 compatible = "spacemit,k1-usb2-phy"; 434 reg = <0x0 0xc0a30000 0x0 0x200>; 435 clocks = <&syscon_apmu CLK_USB30>; 436 #phy-cells = <0>; 437 status = "disabled"; 438 }; 439 440 combo_phy: phy@c0b10000 { 441 compatible = "spacemit,k1-combo-phy"; 442 reg = <0x0 0xc0b10000 0x0 0x1000>; 443 clocks = <&vctcxo_24m>, 444 <&syscon_apmu CLK_PCIE0_DBI>, 445 <&syscon_apmu CLK_PCIE0_MASTER>, 446 <&syscon_apmu CLK_PCIE0_SLAVE>; 447 clock-names = "refclk", 448 "dbi", 449 "mstr", 450 "slv"; 451 resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, 452 <&syscon_apmu RESET_PCIE0_DBI>, 453 <&syscon_apmu RESET_PCIE0_MASTER>, 454 <&syscon_apmu RESET_PCIE0_SLAVE>; 455 reset-names = "phy", 456 "dbi", 457 "mstr", 458 "slv"; 459 #phy-cells = <1>; 460 spacemit,apmu = <&syscon_apmu>; 461 status = "disabled"; 462 }; 463 464 pcie1_phy: phy@c0c10000 { 465 compatible = "spacemit,k1-pcie-phy"; 466 reg = <0x0 0xc0c10000 0x0 0x1000>; 467 clocks = <&vctcxo_24m>; 468 clock-names = "refclk"; 469 resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; 470 reset-names = "phy"; 471 #phy-cells = <0>; 472 status = "disabled"; 473 }; 474 475 pcie2_phy: phy@c0d10000 { 476 compatible = "spacemit,k1-pcie-phy"; 477 reg = <0x0 0xc0d10000 0x0 0x1000>; 478 clocks = <&vctcxo_24m>; 479 clock-names = "refclk"; 480 resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; 481 reset-names = "phy"; 482 #phy-cells = <0>; 483 status = "disabled"; 484 }; 485 486 syscon_apbc: system-controller@d4015000 { 487 compatible = "spacemit,k1-syscon-apbc"; 488 reg = <0x0 0xd4015000 0x0 0x1000>; 489 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 490 <&vctcxo_24m>; 491 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 492 "vctcxo_24m"; 493 #clock-cells = <1>; 494 #reset-cells = <1>; 495 }; 496 497 i2c6: i2c@d4018800 { 498 compatible = "spacemit,k1-i2c"; 499 reg = <0x0 0xd4018800 0x0 0x38>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&syscon_apbc CLK_TWSI6>, 503 <&syscon_apbc CLK_TWSI6_BUS>; 504 clock-names = "func", "bus"; 505 clock-frequency = <400000>; 506 resets = <&syscon_apbc RESET_TWSI6>; 507 interrupts = <70>; 508 status = "disabled"; 509 }; 510 511 gpio: gpio@d4019000 { 512 compatible = "spacemit,k1-gpio"; 513 reg = <0x0 0xd4019000 0x0 0x100>; 514 clocks = <&syscon_apbc CLK_GPIO>, 515 <&syscon_apbc CLK_GPIO_BUS>; 516 clock-names = "core", "bus"; 517 gpio-controller; 518 #gpio-cells = <3>; 519 interrupts = <58>; 520 interrupt-parent = <&plic>; 521 interrupt-controller; 522 #interrupt-cells = <3>; 523 gpio-ranges = <&pinctrl 0 0 0 32>, 524 <&pinctrl 1 0 32 32>, 525 <&pinctrl 2 0 64 32>, 526 <&pinctrl 3 0 96 32>; 527 }; 528 529 pwm0: pwm@d401a000 { 530 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 531 reg = <0x0 0xd401a000 0x0 0x10>; 532 #pwm-cells = <3>; 533 clocks = <&syscon_apbc CLK_PWM0>; 534 resets = <&syscon_apbc RESET_PWM0>; 535 status = "disabled"; 536 }; 537 538 pwm1: pwm@d401a400 { 539 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 540 reg = <0x0 0xd401a400 0x0 0x10>; 541 #pwm-cells = <3>; 542 clocks = <&syscon_apbc CLK_PWM1>; 543 resets = <&syscon_apbc RESET_PWM1>; 544 status = "disabled"; 545 }; 546 547 pwm2: pwm@d401a800 { 548 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 549 reg = <0x0 0xd401a800 0x0 0x10>; 550 #pwm-cells = <3>; 551 clocks = <&syscon_apbc CLK_PWM2>; 552 resets = <&syscon_apbc RESET_PWM2>; 553 status = "disabled"; 554 }; 555 556 pwm3: pwm@d401ac00 { 557 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 558 reg = <0x0 0xd401ac00 0x0 0x10>; 559 #pwm-cells = <3>; 560 clocks = <&syscon_apbc CLK_PWM3>; 561 resets = <&syscon_apbc RESET_PWM3>; 562 status = "disabled"; 563 }; 564 565 pwm4: pwm@d401b000 { 566 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 567 reg = <0x0 0xd401b000 0x0 0x10>; 568 #pwm-cells = <3>; 569 clocks = <&syscon_apbc CLK_PWM4>; 570 resets = <&syscon_apbc RESET_PWM4>; 571 status = "disabled"; 572 }; 573 574 pwm5: pwm@d401b400 { 575 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 576 reg = <0x0 0xd401b400 0x0 0x10>; 577 #pwm-cells = <3>; 578 clocks = <&syscon_apbc CLK_PWM5>; 579 resets = <&syscon_apbc RESET_PWM5>; 580 status = "disabled"; 581 }; 582 583 pwm6: pwm@d401b800 { 584 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 585 reg = <0x0 0xd401b800 0x0 0x10>; 586 #pwm-cells = <3>; 587 clocks = <&syscon_apbc CLK_PWM6>; 588 resets = <&syscon_apbc RESET_PWM6>; 589 status = "disabled"; 590 }; 591 592 pwm7: pwm@d401bc00 { 593 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 594 reg = <0x0 0xd401bc00 0x0 0x10>; 595 #pwm-cells = <3>; 596 clocks = <&syscon_apbc CLK_PWM7>; 597 resets = <&syscon_apbc RESET_PWM7>; 598 status = "disabled"; 599 }; 600 601 i2c7: i2c@d401d000 { 602 compatible = "spacemit,k1-i2c"; 603 reg = <0x0 0xd401d000 0x0 0x38>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 clocks = <&syscon_apbc CLK_TWSI7>, 607 <&syscon_apbc CLK_TWSI7_BUS>; 608 clock-names = "func", "bus"; 609 clock-frequency = <400000>; 610 resets = <&syscon_apbc RESET_TWSI7>; 611 interrupts = <18>; 612 status = "disabled"; 613 }; 614 615 i2c8: i2c@d401d800 { 616 compatible = "spacemit,k1-i2c"; 617 reg = <0x0 0xd401d800 0x0 0x38>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&syscon_apbc CLK_TWSI8>, 621 <&syscon_apbc CLK_TWSI8_BUS>; 622 clock-names = "func", "bus"; 623 clock-frequency = <400000>; 624 resets = <&syscon_apbc RESET_TWSI8>; 625 interrupts = <19>; 626 status = "disabled"; 627 }; 628 629 pinctrl: pinctrl@d401e000 { 630 compatible = "spacemit,k1-pinctrl"; 631 reg = <0x0 0xd401e000 0x0 0x1000>; 632 clocks = <&syscon_apbc CLK_AIB>, 633 <&syscon_apbc CLK_AIB_BUS>; 634 clock-names = "func", "bus"; 635 spacemit,apbc = <&syscon_apbc>; 636 }; 637 638 pwm8: pwm@d4020000 { 639 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 640 reg = <0x0 0xd4020000 0x0 0x10>; 641 #pwm-cells = <3>; 642 clocks = <&syscon_apbc CLK_PWM8>; 643 resets = <&syscon_apbc RESET_PWM8>; 644 status = "disabled"; 645 }; 646 647 pwm9: pwm@d4020400 { 648 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 649 reg = <0x0 0xd4020400 0x0 0x10>; 650 #pwm-cells = <3>; 651 clocks = <&syscon_apbc CLK_PWM9>; 652 resets = <&syscon_apbc RESET_PWM9>; 653 status = "disabled"; 654 }; 655 656 pwm10: pwm@d4020800 { 657 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 658 reg = <0x0 0xd4020800 0x0 0x10>; 659 #pwm-cells = <3>; 660 clocks = <&syscon_apbc CLK_PWM10>; 661 resets = <&syscon_apbc RESET_PWM10>; 662 status = "disabled"; 663 }; 664 665 pwm11: pwm@d4020c00 { 666 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 667 reg = <0x0 0xd4020c00 0x0 0x10>; 668 #pwm-cells = <3>; 669 clocks = <&syscon_apbc CLK_PWM11>; 670 resets = <&syscon_apbc RESET_PWM11>; 671 status = "disabled"; 672 }; 673 674 pwm12: pwm@d4021000 { 675 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 676 reg = <0x0 0xd4021000 0x0 0x10>; 677 #pwm-cells = <3>; 678 clocks = <&syscon_apbc CLK_PWM12>; 679 resets = <&syscon_apbc RESET_PWM12>; 680 status = "disabled"; 681 }; 682 683 pwm13: pwm@d4021400 { 684 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 685 reg = <0x0 0xd4021400 0x0 0x10>; 686 #pwm-cells = <3>; 687 clocks = <&syscon_apbc CLK_PWM13>; 688 resets = <&syscon_apbc RESET_PWM13>; 689 status = "disabled"; 690 }; 691 692 pwm14: pwm@d4021800 { 693 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 694 reg = <0x0 0xd4021800 0x0 0x10>; 695 #pwm-cells = <3>; 696 clocks = <&syscon_apbc CLK_PWM14>; 697 resets = <&syscon_apbc RESET_PWM14>; 698 status = "disabled"; 699 }; 700 701 pwm15: pwm@d4021c00 { 702 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 703 reg = <0x0 0xd4021c00 0x0 0x10>; 704 #pwm-cells = <3>; 705 clocks = <&syscon_apbc CLK_PWM15>; 706 resets = <&syscon_apbc RESET_PWM15>; 707 status = "disabled"; 708 }; 709 710 pwm16: pwm@d4022000 { 711 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 712 reg = <0x0 0xd4022000 0x0 0x10>; 713 #pwm-cells = <3>; 714 clocks = <&syscon_apbc CLK_PWM16>; 715 resets = <&syscon_apbc RESET_PWM16>; 716 status = "disabled"; 717 }; 718 719 pwm17: pwm@d4022400 { 720 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 721 reg = <0x0 0xd4022400 0x0 0x10>; 722 #pwm-cells = <3>; 723 clocks = <&syscon_apbc CLK_PWM17>; 724 resets = <&syscon_apbc RESET_PWM17>; 725 status = "disabled"; 726 }; 727 728 pwm18: pwm@d4022800 { 729 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 730 reg = <0x0 0xd4022800 0x0 0x10>; 731 #pwm-cells = <3>; 732 clocks = <&syscon_apbc CLK_PWM18>; 733 resets = <&syscon_apbc RESET_PWM18>; 734 status = "disabled"; 735 }; 736 737 pwm19: pwm@d4022c00 { 738 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 739 reg = <0x0 0xd4022c00 0x0 0x10>; 740 #pwm-cells = <3>; 741 clocks = <&syscon_apbc CLK_PWM19>; 742 resets = <&syscon_apbc RESET_PWM19>; 743 status = "disabled"; 744 }; 745 746 syscon_mpmu: system-controller@d4050000 { 747 compatible = "spacemit,k1-syscon-mpmu"; 748 reg = <0x0 0xd4050000 0x0 0x209c>; 749 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 750 <&vctcxo_24m>; 751 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 752 "vctcxo_24m"; 753 #clock-cells = <1>; 754 #power-domain-cells = <1>; 755 #reset-cells = <1>; 756 }; 757 758 pll: clock-controller@d4090000 { 759 compatible = "spacemit,k1-pll"; 760 reg = <0x0 0xd4090000 0x0 0x1000>; 761 clocks = <&vctcxo_24m>; 762 spacemit,mpmu = <&syscon_mpmu>; 763 #clock-cells = <1>; 764 }; 765 766 syscon_apmu: system-controller@d4282800 { 767 compatible = "spacemit,k1-syscon-apmu"; 768 reg = <0x0 0xd4282800 0x0 0x400>; 769 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 770 <&vctcxo_24m>; 771 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 772 "vctcxo_24m"; 773 #clock-cells = <1>; 774 #power-domain-cells = <1>; 775 #reset-cells = <1>; 776 }; 777 778 plic: interrupt-controller@e0000000 { 779 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; 780 reg = <0x0 0xe0000000 0x0 0x4000000>; 781 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 782 <&cpu1_intc 11>, <&cpu1_intc 9>, 783 <&cpu2_intc 11>, <&cpu2_intc 9>, 784 <&cpu3_intc 11>, <&cpu3_intc 9>, 785 <&cpu4_intc 11>, <&cpu4_intc 9>, 786 <&cpu5_intc 11>, <&cpu5_intc 9>, 787 <&cpu6_intc 11>, <&cpu6_intc 9>, 788 <&cpu7_intc 11>, <&cpu7_intc 9>; 789 interrupt-controller; 790 #address-cells = <0>; 791 #interrupt-cells = <1>; 792 riscv,ndev = <159>; 793 }; 794 795 clint: timer@e4000000 { 796 compatible = "spacemit,k1-clint", "sifive,clint0"; 797 reg = <0x0 0xe4000000 0x0 0x10000>; 798 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 799 <&cpu1_intc 3>, <&cpu1_intc 7>, 800 <&cpu2_intc 3>, <&cpu2_intc 7>, 801 <&cpu3_intc 3>, <&cpu3_intc 7>, 802 <&cpu4_intc 3>, <&cpu4_intc 7>, 803 <&cpu5_intc 3>, <&cpu5_intc 7>, 804 <&cpu6_intc 3>, <&cpu6_intc 7>, 805 <&cpu7_intc 3>, <&cpu7_intc 7>; 806 }; 807 808 syscon_apbc2: system-controller@f0610000 { 809 compatible = "spacemit,k1-syscon-apbc2"; 810 reg = <0x0 0xf0610000 0x0 0x20>; 811 #reset-cells = <1>; 812 }; 813 814 /* sec_i2c3: 0xf0614000, not available from Linux */ 815 816 camera-bus { 817 compatible = "simple-bus"; 818 ranges; 819 #address-cells = <2>; 820 #size-cells = <2>; 821 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 822 <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>; 823 }; 824 825 dma-bus { 826 compatible = "simple-bus"; 827 ranges; 828 #address-cells = <2>; 829 #size-cells = <2>; 830 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 831 <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; 832 833 pdma: dma-controller@d4000000 { 834 compatible = "spacemit,k1-pdma"; 835 reg = <0x0 0xd4000000 0x0 0x4000>; 836 clocks = <&syscon_apmu CLK_DMA>; 837 resets = <&syscon_apmu RESET_DMA>; 838 interrupts = <72>; 839 dma-channels = <16>; 840 #dma-cells= <1>; 841 status = "disabled"; 842 }; 843 844 uart0: serial@d4017000 { 845 compatible = "spacemit,k1-uart", 846 "intel,xscale-uart"; 847 reg = <0x0 0xd4017000 0x0 0x100>; 848 clocks = <&syscon_apbc CLK_UART0>, 849 <&syscon_apbc CLK_UART0_BUS>; 850 clock-names = "core", "bus"; 851 resets = <&syscon_apbc RESET_UART0>; 852 interrupts = <42>; 853 reg-shift = <2>; 854 reg-io-width = <4>; 855 status = "disabled"; 856 }; 857 858 uart2: serial@d4017100 { 859 compatible = "spacemit,k1-uart", 860 "intel,xscale-uart"; 861 reg = <0x0 0xd4017100 0x0 0x100>; 862 clocks = <&syscon_apbc CLK_UART2>, 863 <&syscon_apbc CLK_UART2_BUS>; 864 clock-names = "core", "bus"; 865 resets = <&syscon_apbc RESET_UART2>; 866 interrupts = <44>; 867 reg-shift = <2>; 868 reg-io-width = <4>; 869 status = "disabled"; 870 }; 871 872 uart3: serial@d4017200 { 873 compatible = "spacemit,k1-uart", 874 "intel,xscale-uart"; 875 reg = <0x0 0xd4017200 0x0 0x100>; 876 clocks = <&syscon_apbc CLK_UART3>, 877 <&syscon_apbc CLK_UART3_BUS>; 878 clock-names = "core", "bus"; 879 resets = <&syscon_apbc RESET_UART3>; 880 interrupts = <45>; 881 reg-shift = <2>; 882 reg-io-width = <4>; 883 status = "disabled"; 884 }; 885 886 uart4: serial@d4017300 { 887 compatible = "spacemit,k1-uart", 888 "intel,xscale-uart"; 889 reg = <0x0 0xd4017300 0x0 0x100>; 890 clocks = <&syscon_apbc CLK_UART4>, 891 <&syscon_apbc CLK_UART4_BUS>; 892 clock-names = "core", "bus"; 893 resets = <&syscon_apbc RESET_UART4>; 894 interrupts = <46>; 895 reg-shift = <2>; 896 reg-io-width = <4>; 897 status = "disabled"; 898 }; 899 900 uart5: serial@d4017400 { 901 compatible = "spacemit,k1-uart", 902 "intel,xscale-uart"; 903 reg = <0x0 0xd4017400 0x0 0x100>; 904 clocks = <&syscon_apbc CLK_UART5>, 905 <&syscon_apbc CLK_UART5_BUS>; 906 clock-names = "core", "bus"; 907 resets = <&syscon_apbc RESET_UART5>; 908 interrupts = <47>; 909 reg-shift = <2>; 910 reg-io-width = <4>; 911 status = "disabled"; 912 }; 913 914 uart6: serial@d4017500 { 915 compatible = "spacemit,k1-uart", 916 "intel,xscale-uart"; 917 reg = <0x0 0xd4017500 0x0 0x100>; 918 clocks = <&syscon_apbc CLK_UART6>, 919 <&syscon_apbc CLK_UART6_BUS>; 920 clock-names = "core", "bus"; 921 resets = <&syscon_apbc RESET_UART6>; 922 interrupts = <48>; 923 reg-shift = <2>; 924 reg-io-width = <4>; 925 status = "disabled"; 926 }; 927 928 uart7: serial@d4017600 { 929 compatible = "spacemit,k1-uart", 930 "intel,xscale-uart"; 931 reg = <0x0 0xd4017600 0x0 0x100>; 932 clocks = <&syscon_apbc CLK_UART7>, 933 <&syscon_apbc CLK_UART7_BUS>; 934 clock-names = "core", "bus"; 935 resets = <&syscon_apbc RESET_UART7>; 936 interrupts = <49>; 937 reg-shift = <2>; 938 reg-io-width = <4>; 939 status = "disabled"; 940 }; 941 942 uart8: serial@d4017700 { 943 compatible = "spacemit,k1-uart", 944 "intel,xscale-uart"; 945 reg = <0x0 0xd4017700 0x0 0x100>; 946 clocks = <&syscon_apbc CLK_UART8>, 947 <&syscon_apbc CLK_UART8_BUS>; 948 clock-names = "core", "bus"; 949 resets = <&syscon_apbc RESET_UART8>; 950 interrupts = <50>; 951 reg-shift = <2>; 952 reg-io-width = <4>; 953 status = "disabled"; 954 }; 955 956 uart9: serial@d4017800 { 957 compatible = "spacemit,k1-uart", 958 "intel,xscale-uart"; 959 reg = <0x0 0xd4017800 0x0 0x100>; 960 clocks = <&syscon_apbc CLK_UART9>, 961 <&syscon_apbc CLK_UART9_BUS>; 962 clock-names = "core", "bus"; 963 resets = <&syscon_apbc RESET_UART9>; 964 interrupts = <51>; 965 reg-shift = <2>; 966 reg-io-width = <4>; 967 status = "disabled"; 968 }; 969 970 qspi: spi@d420c000 { 971 compatible = "spacemit,k1-qspi"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 reg = <0x0 0xd420c000 0x0 0x1000>, 975 <0x0 0xb8000000 0x0 0xc00000>; 976 reg-names = "QuadSPI", "QuadSPI-memory"; 977 clocks = <&syscon_apmu CLK_QSPI_BUS>, 978 <&syscon_apmu CLK_QSPI>; 979 clock-names = "qspi_en", "qspi"; 980 resets = <&syscon_apmu RESET_QSPI>, 981 <&syscon_apmu RESET_QSPI_BUS>; 982 interrupts = <117>; 983 status = "disabled"; 984 }; 985 986 /* sec_uart1: 0xf0612000, not available from Linux */ 987 }; 988 989 multimedia-bus { 990 compatible = "simple-bus"; 991 ranges; 992 #address-cells = <2>; 993 #size-cells = <2>; 994 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 995 <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>; 996 }; 997 998 network-bus { 999 compatible = "simple-bus"; 1000 ranges; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 1004 <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>; 1005 1006 eth0: ethernet@cac80000 { 1007 compatible = "spacemit,k1-emac"; 1008 reg = <0x0 0xcac80000 0x0 0x420>; 1009 clocks = <&syscon_apmu CLK_EMAC0_BUS>; 1010 interrupts = <131>; 1011 mac-address = [ 00 00 00 00 00 00 ]; 1012 resets = <&syscon_apmu RESET_EMAC0>; 1013 spacemit,apmu = <&syscon_apmu 0x3e4>; 1014 status = "disabled"; 1015 }; 1016 1017 eth1: ethernet@cac81000 { 1018 compatible = "spacemit,k1-emac"; 1019 reg = <0x0 0xcac81000 0x0 0x420>; 1020 clocks = <&syscon_apmu CLK_EMAC1_BUS>; 1021 interrupts = <133>; 1022 mac-address = [ 00 00 00 00 00 00 ]; 1023 resets = <&syscon_apmu RESET_EMAC1>; 1024 spacemit,apmu = <&syscon_apmu 0x3ec>; 1025 status = "disabled"; 1026 }; 1027 }; 1028 1029 pcie-bus { 1030 compatible = "simple-bus"; 1031 ranges; 1032 #address-cells = <2>; 1033 #size-cells = <2>; 1034 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 1035 <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; 1036 pcie0: pcie@ca000000 { 1037 device_type = "pci"; 1038 compatible = "spacemit,k1-pcie"; 1039 reg = <0x0 0xca000000 0x0 0x00001000>, 1040 <0x0 0xca300000 0x0 0x0001ff24>, 1041 <0x0 0x8f000000 0x0 0x00002000>, 1042 <0x0 0xc0b20000 0x0 0x00001000>; 1043 reg-names = "dbi", 1044 "atu", 1045 "config", 1046 "link"; 1047 #address-cells = <3>; 1048 #size-cells = <2>; 1049 ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, 1050 <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; 1051 interrupts = <141>; 1052 interrupt-names = "msi"; 1053 clocks = <&syscon_apmu CLK_PCIE0_DBI>, 1054 <&syscon_apmu CLK_PCIE0_MASTER>, 1055 <&syscon_apmu CLK_PCIE0_SLAVE>; 1056 clock-names = "dbi", 1057 "mstr", 1058 "slv"; 1059 resets = <&syscon_apmu RESET_PCIE0_DBI>, 1060 <&syscon_apmu RESET_PCIE0_MASTER>, 1061 <&syscon_apmu RESET_PCIE0_SLAVE>; 1062 reset-names = "dbi", 1063 "mstr", 1064 "slv"; 1065 spacemit,apmu = <&syscon_apmu 0x03cc>; 1066 status = "disabled"; 1067 1068 pcie0_port: pcie@0 { 1069 device_type = "pci"; 1070 compatible = "pciclass,0604"; 1071 reg = <0x0 0x0 0x0 0x0 0x0>; 1072 bus-range = <0x01 0xff>; 1073 #address-cells = <3>; 1074 #size-cells = <2>; 1075 ranges; 1076 }; 1077 }; 1078 1079 pcie1: pcie@ca400000 { 1080 device_type = "pci"; 1081 compatible = "spacemit,k1-pcie"; 1082 reg = <0x0 0xca400000 0x0 0x00001000>, 1083 <0x0 0xca700000 0x0 0x0001ff24>, 1084 <0x0 0x9f000000 0x0 0x00002000>, 1085 <0x0 0xc0c20000 0x0 0x00001000>; 1086 reg-names = "dbi", 1087 "atu", 1088 "config", 1089 "link"; 1090 #address-cells = <3>; 1091 #size-cells = <2>; 1092 ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, 1093 <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; 1094 interrupts = <142>; 1095 interrupt-names = "msi"; 1096 clocks = <&syscon_apmu CLK_PCIE1_DBI>, 1097 <&syscon_apmu CLK_PCIE1_MASTER>, 1098 <&syscon_apmu CLK_PCIE1_SLAVE>; 1099 clock-names = "dbi", 1100 "mstr", 1101 "slv"; 1102 resets = <&syscon_apmu RESET_PCIE1_DBI>, 1103 <&syscon_apmu RESET_PCIE1_MASTER>, 1104 <&syscon_apmu RESET_PCIE1_SLAVE>; 1105 reset-names = "dbi", 1106 "mstr", 1107 "slv"; 1108 spacemit,apmu = <&syscon_apmu 0x3d4>; 1109 status = "disabled"; 1110 1111 pcie1_port: pcie@0 { 1112 device_type = "pci"; 1113 compatible = "pciclass,0604"; 1114 reg = <0x0 0x0 0x0 0x0 0x0>; 1115 bus-range = <0x01 0xff>; 1116 #address-cells = <3>; 1117 #size-cells = <2>; 1118 ranges; 1119 }; 1120 }; 1121 1122 pcie2: pcie@ca800000 { 1123 device_type = "pci"; 1124 compatible = "spacemit,k1-pcie"; 1125 reg = <0x0 0xca800000 0x0 0x00001000>, 1126 <0x0 0xcab00000 0x0 0x0001ff24>, 1127 <0x0 0xb7000000 0x0 0x00002000>, 1128 <0x0 0xc0d20000 0x0 0x00001000>; 1129 reg-names = "dbi", 1130 "atu", 1131 "config", 1132 "link"; 1133 #address-cells = <3>; 1134 #size-cells = <2>; 1135 ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, 1136 <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, 1137 <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; 1138 interrupts = <143>; 1139 interrupt-names = "msi"; 1140 clocks = <&syscon_apmu CLK_PCIE2_DBI>, 1141 <&syscon_apmu CLK_PCIE2_MASTER>, 1142 <&syscon_apmu CLK_PCIE2_SLAVE>; 1143 clock-names = "dbi", 1144 "mstr", 1145 "slv"; 1146 resets = <&syscon_apmu RESET_PCIE2_DBI>, 1147 <&syscon_apmu RESET_PCIE2_MASTER>, 1148 <&syscon_apmu RESET_PCIE2_SLAVE>; 1149 reset-names = "dbi", 1150 "mstr", 1151 "slv"; 1152 spacemit,apmu = <&syscon_apmu 0x3dc>; 1153 status = "disabled"; 1154 1155 pcie2_port: pcie@0 { 1156 device_type = "pci"; 1157 compatible = "pciclass,0604"; 1158 reg = <0x0 0x0 0x0 0x0 0x0>; 1159 bus-range = <0x01 0xff>; 1160 #address-cells = <3>; 1161 #size-cells = <2>; 1162 ranges; 1163 }; 1164 }; 1165 }; 1166 1167 storage-bus { 1168 compatible = "simple-bus"; 1169 ranges; 1170 #address-cells = <2>; 1171 #size-cells = <2>; 1172 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; 1173 1174 usb_dwc3: usb@c0a00000 { 1175 compatible = "spacemit,k1-dwc3"; 1176 reg = <0x0 0xc0a00000 0x0 0x10000>; 1177 clocks = <&syscon_apmu CLK_USB30>; 1178 clock-names = "usbdrd30"; 1179 interrupts = <125>; 1180 phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; 1181 phy-names = "usb2-phy", "usb3-phy"; 1182 phy_type = "utmi"; 1183 resets = <&syscon_apmu RESET_USB30_AHB>, 1184 <&syscon_apmu RESET_USB30_VCC>, 1185 <&syscon_apmu RESET_USB30_PHY>; 1186 reset-names = "ahb", "vcc", "phy"; 1187 reset-delay = <2>; 1188 snps,hsphy_interface = "utmi"; 1189 snps,dis_enblslpm_quirk; 1190 snps,dis-u2-freeclk-exists-quirk; 1191 snps,dis-del-phy-power-chg-quirk; 1192 snps,dis_u2_susphy_quirk; 1193 snps,dis_u3_susphy_quirk; 1194 snps,dis_rxdet_inp3_quirk; 1195 status = "disabled"; 1196 }; 1197 1198 emmc: mmc@d4281000 { 1199 compatible = "spacemit,k1-sdhci"; 1200 reg = <0x0 0xd4281000 0x0 0x200>; 1201 clocks = <&syscon_apmu CLK_SDH_AXI>, 1202 <&syscon_apmu CLK_SDH2>; 1203 clock-names = "core", "io"; 1204 resets = <&syscon_apmu RESET_SDH_AXI>, 1205 <&syscon_apmu RESET_SDH2>; 1206 reset-names = "axi", "sdh"; 1207 interrupts = <101>; 1208 status = "disabled"; 1209 }; 1210 }; 1211 }; 1212}; 1213