1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek HDMI v2 Display Data Channel Driver
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Copyright (c) 2021 BayLibre, SAS
7 * Copyright (c) 2024 Collabora Ltd.
8 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/types.h>
26
27 #include <drm/drm_edid.h>
28
29 #include "mtk_hdmi_common.h"
30 #include "mtk_hdmi_regs_v2.h"
31
32 #define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
33 #define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
34 #define SI2C_ADDR_READ 0xf4
35 #define SCDC_I2C_SLAVE_ADDRESS 0x54
36
37 struct mtk_hdmi_ddc {
38 struct device *dev;
39 struct regmap *regs;
40 struct clk *clk;
41 struct i2c_adapter adap;
42 };
43
mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc * ddc)44 static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
45 {
46 u32 val;
47
48 regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
49 if (val & DDC_I2C_BUS_LOW) {
50 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
51 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
52 usleep_range(250, 300);
53 }
54
55 if (val & DDC_I2C_NO_ACK) {
56 u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
57
58 regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
59 regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
60 regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
61 }
62
63 if (val & DDC_I2C_NO_ACK)
64 return -EIO;
65
66 return 0;
67 }
68
mtk_ddc_wr_one(struct mtk_hdmi_ddc * ddc,u16 addr_id,u16 offset_id,u8 * wr_data)69 static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
70 u16 offset_id, u8 *wr_data)
71 {
72 u32 val;
73 int ret;
74
75 /* If down, rise bus for write operation */
76 mtk_ddc_check_and_rise_low_bus(ddc);
77
78 regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
79 FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
80
81 if (wr_data) {
82 regmap_write(ddc->regs, SI2C_CTRL,
83 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
84 FIELD_PREP(SI2C_WDATA, *wr_data) |
85 SI2C_WR);
86 }
87
88 regmap_write(ddc->regs, DDC_CTRL,
89 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
90 FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : 1) |
91 FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
92 FIELD_PREP(DDC_CTRL_ADDR, addr_id));
93 usleep_range(1000, 1250);
94
95 ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
96 !(val & DDC_I2C_IN_PROG), 500, 1000);
97 if (ret) {
98 dev_err(ddc->dev, "DDC I2C write timeout\n");
99 return ret;
100 }
101
102 /* The I2C bus might be down after WR operation: rise it again */
103 ret = mtk_ddc_check_and_rise_low_bus(ddc);
104 if (ret) {
105 dev_err(ddc->dev, "Error during write operation: No ACK\n");
106 return ret;
107 }
108
109 return 0;
110 }
111
mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc * ddc,u16 uc_dev,u8 addr,u8 * puc_value,u16 data_cnt)112 static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
113 u8 addr, u8 *puc_value, u16 data_cnt)
114 {
115 u16 dly_cnt, i, uc_idx;
116 u32 rem, temp_length, uc_read_count, val;
117 u64 loop_counter;
118 int ret;
119
120 mtk_ddc_check_and_rise_low_bus(ddc);
121
122 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
123 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
124
125 if (data_cnt >= 16) {
126 temp_length = 16;
127 loop_counter = data_cnt;
128
129 rem = do_div(loop_counter, temp_length);
130 if (rem)
131 loop_counter++;
132 } else {
133 temp_length = data_cnt;
134 loop_counter = 1;
135 }
136
137 if (uc_dev >= DDC_ADDR)
138 dly_cnt = DDC2_DLY_CNT_EDID;
139 else
140 dly_cnt = DDC2_DLY_CNT;
141
142 regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
143 FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
144
145 for (i = 0; i < loop_counter; i++) {
146 rem = data_cnt % 16;
147
148 if (i > 0 && i == (loop_counter - 1) && rem)
149 temp_length = rem;
150
151 /* 0x51 - 0x53: Flow control */
152 if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
153 regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
154 FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
155
156 regmap_write(ddc->regs, DDC_CTRL,
157 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
158 FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
159 FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
160 FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
161 } else {
162 u16 offset;
163
164 if (addr != 0x43)
165 offset = i * 16;
166 else
167 offset = 0;
168
169 regmap_write(ddc->regs, DDC_CTRL,
170 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
171 FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
172 FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
173 FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
174 }
175 usleep_range(5000, 5500);
176
177 ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
178 !(val & DDC_I2C_IN_PROG), 1000,
179 500 * (temp_length + 5));
180 if (ret) {
181 dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
182 return ret;
183 }
184
185 ret = mtk_ddc_check_and_rise_low_bus(ddc);
186 if (ret) {
187 dev_err(ddc->dev, "Error during read operation: No ACK\n");
188 return ret;
189 }
190
191 for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
192 unsigned int read_idx = i * 16 + uc_idx;
193
194 regmap_write(ddc->regs, SI2C_CTRL,
195 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
196 SI2C_RD);
197
198 regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
199 puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
200
201 regmap_write(ddc->regs, SI2C_CTRL,
202 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
203 SI2C_CONFIRM_READ);
204
205 /*
206 * If HDMI IP gets reset during EDID read, DDC read
207 * operation will fail and its delay counter will be
208 * reset to 400.
209 */
210 regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
211 if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
212 return 0;
213
214 uc_read_count = read_idx + 1;
215 }
216 }
217 if (uc_read_count > U8_MAX)
218 dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
219
220 return uc_read_count;
221 }
222
mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc * ddc,u16 b_dev,u8 data_addr,u16 data_cnt,u8 * pr_data)223 static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
224 u8 data_addr, u16 data_cnt, u8 *pr_data)
225 {
226 int read_data_cnt;
227 u16 req_data_cnt;
228
229 if (!data_cnt) {
230 dev_err(ddc->dev, "Invalid DDCM read request\n");
231 return -EINVAL;
232 }
233
234 req_data_cnt = U8_MAX - data_addr + 1;
235 if (req_data_cnt > data_cnt)
236 req_data_cnt = data_cnt;
237
238 regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
239
240 read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
241
242 if (read_data_cnt < 0)
243 return read_data_cnt;
244 else if (read_data_cnt != req_data_cnt)
245 return -EINVAL;
246
247 return 0;
248 }
249
mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc * ddc,u16 b_dev,u8 data_addr,u16 data_cnt,u8 * pr_data)250 static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
251 u8 data_addr, u16 data_cnt, u8 *pr_data)
252 {
253 int i, ret;
254
255 regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
256 /*
257 * In case there is no payload data, just do a single write for the
258 * address only
259 */
260 if (data_cnt == 0)
261 return mtk_ddc_wr_one(ddc, b_dev, data_addr, NULL);
262
263 i = 0;
264 do {
265 ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data + i);
266 if (ret)
267 return ret;
268 } while (++i < data_cnt);
269
270 return 0;
271 }
272
mtk_hdmi_ddc_v2_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)273 static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
274 {
275 struct mtk_hdmi_ddc *ddc;
276 u8 offset = 0;
277 int i, ret;
278
279 ddc = adapter->algo_data;
280
281 for (i = 0; i < num; i++) {
282 struct i2c_msg *msg = &msgs[i];
283
284 if (!msg->buf) {
285 dev_err(ddc->dev, "No message buffer\n");
286 return -EINVAL;
287 }
288
289 if (msg->flags & I2C_M_RD) {
290 /*
291 * The underlying DDC hardware always issues a write request
292 * that assigns the read offset as part of the read operation,
293 * therefore, use the `offset` value assigned in the previous
294 * write request from drm_edid
295 */
296 ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
297 msg->len, &msg->buf[0]);
298 if (ret)
299 return ret;
300 } else {
301 /*
302 * The HW needs the data offset, found in buf[0], in the
303 * DDC_CTRL register, and each byte of data, starting at
304 * buf[1], goes in the SI2C_WDATA register.
305 */
306 ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
307 msg->len - 1, &msg->buf[1]);
308 if (ret)
309 return ret;
310
311 /*
312 * Store the offset value requested by drm_edid or by
313 * scdc to use in subsequent read requests.
314 */
315 if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
316 msg->len == 1) {
317 offset = msg->buf[0];
318 }
319 }
320 }
321
322 return i;
323 }
324
mtk_hdmi_ddc_v2_func(struct i2c_adapter * adapter)325 static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
326 {
327 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
328 }
329
330 static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
331 .master_xfer = mtk_hdmi_ddc_v2_xfer,
332 .functionality = mtk_hdmi_ddc_v2_func,
333 };
334
mtk_hdmi_ddc_v2_probe(struct platform_device * pdev)335 static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
336 {
337 struct device *dev = &pdev->dev;
338 struct mtk_hdmi_ddc *ddc;
339 int ret;
340
341 ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
342 if (!ddc)
343 return -ENOMEM;
344
345 ddc->dev = dev;
346 ddc->regs = device_node_to_regmap(dev->parent->of_node);
347 if (IS_ERR_OR_NULL(ddc->regs))
348 return dev_err_probe(dev,
349 IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
350 "Cannot get regmap\n");
351
352 ddc->clk = devm_clk_get_enabled(dev, NULL);
353 if (IS_ERR(ddc->clk))
354 return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
355
356 strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
357 ddc->adap.owner = THIS_MODULE;
358 ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
359 ddc->adap.retries = 3;
360 ddc->adap.dev.of_node = dev->of_node;
361 ddc->adap.algo_data = ddc;
362 ddc->adap.dev.parent = &pdev->dev;
363
364 ret = devm_pm_runtime_enable(&pdev->dev);
365 if (ret)
366 return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
367
368 pm_runtime_get_sync(dev);
369
370 ret = devm_i2c_add_adapter(dev, &ddc->adap);
371 if (ret < 0)
372 return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
373
374 platform_set_drvdata(pdev, ddc);
375 return 0;
376 }
377
378 static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
379 { .compatible = "mediatek,mt8195-hdmi-ddc" },
380 { /* sentinel */ }
381 };
382 MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
383
384 struct platform_driver mtk_hdmi_ddc_v2_driver = {
385 .probe = mtk_hdmi_ddc_v2_probe,
386 .driver = {
387 .name = "mediatek-hdmi-ddc-v2",
388 .of_match_table = mtk_hdmi_ddc_v2_match,
389 },
390 };
391 module_platform_driver(mtk_hdmi_ddc_v2_driver);
392
393 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
394 MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
395 MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
396 MODULE_LICENSE("GPL");
397