1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
41 #include "psp_v14_0.h"
42
43 #include "amdgpu_ras.h"
44 #include "amdgpu_securedisplay.h"
45 #include "amdgpu_atomfirmware.h"
46
47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
48
49 static int psp_load_smu_fw(struct psp_context *psp);
50 static int psp_rap_terminate(struct psp_context *psp);
51 static int psp_securedisplay_terminate(struct psp_context *psp);
52
psp_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)53 static int psp_ring_init(struct psp_context *psp,
54 enum psp_ring_type ring_type)
55 {
56 int ret = 0;
57 struct psp_ring *ring;
58 struct amdgpu_device *adev = psp->adev;
59
60 ring = &psp->km_ring;
61
62 ring->ring_type = ring_type;
63
64 /* allocate 4k Page of Local Frame Buffer memory for ring */
65 ring->ring_size = 0x1000;
66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
67 AMDGPU_GEM_DOMAIN_VRAM |
68 AMDGPU_GEM_DOMAIN_GTT,
69 &adev->firmware.rbuf,
70 &ring->ring_mem_mc_addr,
71 (void **)&ring->ring_mem);
72 if (ret) {
73 ring->ring_size = 0;
74 return ret;
75 }
76
77 return 0;
78 }
79
80 /*
81 * Due to DF Cstate management centralized to PMFW, the firmware
82 * loading sequence will be updated as below:
83 * - Load KDB
84 * - Load SYS_DRV
85 * - Load tOS
86 * - Load PMFW
87 * - Setup TMR
88 * - Load other non-psp fw
89 * - Load ASD
90 * - Load XGMI/RAS/HDCP/DTM TA if any
91 *
92 * This new sequence is required for
93 * - Arcturus and onwards
94 */
psp_check_pmfw_centralized_cstate_management(struct psp_context * psp)95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
96 {
97 struct amdgpu_device *adev = psp->adev;
98
99 if (amdgpu_sriov_vf(adev)) {
100 psp->pmfw_centralized_cstate_management = false;
101 return;
102 }
103
104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
105 case IP_VERSION(11, 0, 0):
106 case IP_VERSION(11, 0, 4):
107 case IP_VERSION(11, 0, 5):
108 case IP_VERSION(11, 0, 7):
109 case IP_VERSION(11, 0, 9):
110 case IP_VERSION(11, 0, 11):
111 case IP_VERSION(11, 0, 12):
112 case IP_VERSION(11, 0, 13):
113 case IP_VERSION(13, 0, 0):
114 case IP_VERSION(13, 0, 2):
115 case IP_VERSION(13, 0, 7):
116 psp->pmfw_centralized_cstate_management = true;
117 break;
118 default:
119 psp->pmfw_centralized_cstate_management = false;
120 break;
121 }
122 }
123
psp_init_sriov_microcode(struct psp_context * psp)124 static int psp_init_sriov_microcode(struct psp_context *psp)
125 {
126 struct amdgpu_device *adev = psp->adev;
127 char ucode_prefix[30];
128 int ret = 0;
129
130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
131
132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
133 case IP_VERSION(9, 0, 0):
134 case IP_VERSION(11, 0, 7):
135 case IP_VERSION(11, 0, 9):
136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
137 ret = psp_init_cap_microcode(psp, ucode_prefix);
138 break;
139 case IP_VERSION(13, 0, 2):
140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
141 ret = psp_init_cap_microcode(psp, ucode_prefix);
142 ret &= psp_init_ta_microcode(psp, ucode_prefix);
143 break;
144 case IP_VERSION(13, 0, 0):
145 adev->virt.autoload_ucode_id = 0;
146 break;
147 case IP_VERSION(13, 0, 6):
148 case IP_VERSION(13, 0, 14):
149 ret = psp_init_cap_microcode(psp, ucode_prefix);
150 ret &= psp_init_ta_microcode(psp, ucode_prefix);
151 break;
152 case IP_VERSION(13, 0, 10):
153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
154 ret = psp_init_cap_microcode(psp, ucode_prefix);
155 break;
156 default:
157 return -EINVAL;
158 }
159 return ret;
160 }
161
psp_early_init(struct amdgpu_ip_block * ip_block)162 static int psp_early_init(struct amdgpu_ip_block *ip_block)
163 {
164 struct amdgpu_device *adev = ip_block->adev;
165 struct psp_context *psp = &adev->psp;
166
167 psp->autoload_supported = true;
168 psp->boot_time_tmr = true;
169
170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
171 case IP_VERSION(9, 0, 0):
172 psp_v3_1_set_psp_funcs(psp);
173 psp->autoload_supported = false;
174 psp->boot_time_tmr = false;
175 break;
176 case IP_VERSION(10, 0, 0):
177 case IP_VERSION(10, 0, 1):
178 psp_v10_0_set_psp_funcs(psp);
179 psp->autoload_supported = false;
180 psp->boot_time_tmr = false;
181 break;
182 case IP_VERSION(11, 0, 2):
183 case IP_VERSION(11, 0, 4):
184 psp_v11_0_set_psp_funcs(psp);
185 psp->autoload_supported = false;
186 psp->boot_time_tmr = false;
187 break;
188 case IP_VERSION(11, 0, 0):
189 case IP_VERSION(11, 0, 7):
190 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
191 fallthrough;
192 case IP_VERSION(11, 0, 5):
193 case IP_VERSION(11, 0, 9):
194 case IP_VERSION(11, 0, 11):
195 case IP_VERSION(11, 5, 0):
196 case IP_VERSION(11, 0, 12):
197 case IP_VERSION(11, 0, 13):
198 psp_v11_0_set_psp_funcs(psp);
199 psp->boot_time_tmr = false;
200 break;
201 case IP_VERSION(11, 0, 3):
202 case IP_VERSION(12, 0, 1):
203 psp_v12_0_set_psp_funcs(psp);
204 psp->autoload_supported = false;
205 psp->boot_time_tmr = false;
206 break;
207 case IP_VERSION(13, 0, 2):
208 psp->boot_time_tmr = false;
209 fallthrough;
210 case IP_VERSION(13, 0, 6):
211 case IP_VERSION(13, 0, 12):
212 case IP_VERSION(13, 0, 14):
213 psp_v13_0_set_psp_funcs(psp);
214 psp->autoload_supported = false;
215 break;
216 case IP_VERSION(13, 0, 1):
217 case IP_VERSION(13, 0, 3):
218 case IP_VERSION(13, 0, 5):
219 case IP_VERSION(13, 0, 8):
220 case IP_VERSION(13, 0, 11):
221 case IP_VERSION(14, 0, 0):
222 case IP_VERSION(14, 0, 1):
223 case IP_VERSION(14, 0, 4):
224 psp_v13_0_set_psp_funcs(psp);
225 psp->boot_time_tmr = false;
226 break;
227 case IP_VERSION(11, 0, 8):
228 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
229 psp_v11_0_8_set_psp_funcs(psp);
230 }
231 psp->autoload_supported = false;
232 psp->boot_time_tmr = false;
233 break;
234 case IP_VERSION(13, 0, 0):
235 case IP_VERSION(13, 0, 7):
236 case IP_VERSION(13, 0, 10):
237 psp_v13_0_set_psp_funcs(psp);
238 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
239 psp->boot_time_tmr = false;
240 break;
241 case IP_VERSION(13, 0, 4):
242 psp_v13_0_4_set_psp_funcs(psp);
243 psp->boot_time_tmr = false;
244 break;
245 case IP_VERSION(14, 0, 2):
246 case IP_VERSION(14, 0, 3):
247 psp_v14_0_set_psp_funcs(psp);
248 break;
249 default:
250 return -EINVAL;
251 }
252
253 psp->adev = adev;
254
255 adev->psp_timeout = 20000;
256
257 psp_check_pmfw_centralized_cstate_management(psp);
258
259 if (amdgpu_sriov_vf(adev))
260 return psp_init_sriov_microcode(psp);
261 else
262 return psp_init_microcode(psp);
263 }
264
psp_ta_free_shared_buf(struct ta_mem_context * mem_ctx)265 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
266 {
267 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
268 &mem_ctx->shared_buf);
269 mem_ctx->shared_bo = NULL;
270 }
271
psp_free_shared_bufs(struct psp_context * psp)272 static void psp_free_shared_bufs(struct psp_context *psp)
273 {
274 void *tmr_buf;
275 void **pptr;
276
277 /* free TMR memory buffer */
278 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
279 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
280 psp->tmr_bo = NULL;
281
282 /* free xgmi shared memory */
283 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
284
285 /* free ras shared memory */
286 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
287
288 /* free hdcp shared memory */
289 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
290
291 /* free dtm shared memory */
292 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
293
294 /* free rap shared memory */
295 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
296
297 /* free securedisplay shared memory */
298 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
299
300
301 }
302
psp_memory_training_fini(struct psp_context * psp)303 static void psp_memory_training_fini(struct psp_context *psp)
304 {
305 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
306
307 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
308 kfree(ctx->sys_cache);
309 ctx->sys_cache = NULL;
310 }
311
psp_memory_training_init(struct psp_context * psp)312 static int psp_memory_training_init(struct psp_context *psp)
313 {
314 int ret;
315 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
316
317 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
318 dev_dbg(psp->adev->dev, "memory training is not supported!\n");
319 return 0;
320 }
321
322 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
323 if (ctx->sys_cache == NULL) {
324 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n");
325 ret = -ENOMEM;
326 goto Err_out;
327 }
328
329 dev_dbg(psp->adev->dev,
330 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
331 ctx->train_data_size,
332 ctx->p2c_train_data_offset,
333 ctx->c2p_train_data_offset);
334 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
335 return 0;
336
337 Err_out:
338 psp_memory_training_fini(psp);
339 return ret;
340 }
341
342 /*
343 * Helper funciton to query psp runtime database entry
344 *
345 * @adev: amdgpu_device pointer
346 * @entry_type: the type of psp runtime database entry
347 * @db_entry: runtime database entry pointer
348 *
349 * Return false if runtime database doesn't exit or entry is invalid
350 * or true if the specific database entry is found, and copy to @db_entry
351 */
psp_get_runtime_db_entry(struct amdgpu_device * adev,enum psp_runtime_entry_type entry_type,void * db_entry)352 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
353 enum psp_runtime_entry_type entry_type,
354 void *db_entry)
355 {
356 uint64_t db_header_pos, db_dir_pos;
357 struct psp_runtime_data_header db_header = {0};
358 struct psp_runtime_data_directory db_dir = {0};
359 bool ret = false;
360 int i;
361
362 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
363 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
364 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))
365 return false;
366
367 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
368 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
369
370 /* read runtime db header from vram */
371 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
372 sizeof(struct psp_runtime_data_header), false);
373
374 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
375 /* runtime db doesn't exist, exit */
376 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
377 return false;
378 }
379
380 /* read runtime database entry from vram */
381 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
382 sizeof(struct psp_runtime_data_directory), false);
383
384 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
385 /* invalid db entry count, exit */
386 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
387 return false;
388 }
389
390 /* look up for requested entry type */
391 for (i = 0; i < db_dir.entry_count && !ret; i++) {
392 if (db_dir.entry_list[i].entry_type == entry_type) {
393 switch (entry_type) {
394 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
395 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
396 /* invalid db entry size */
397 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
398 return false;
399 }
400 /* read runtime database entry */
401 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
402 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
403 ret = true;
404 break;
405 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
406 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
407 /* invalid db entry size */
408 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
409 return false;
410 }
411 /* read runtime database entry */
412 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
413 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
414 ret = true;
415 break;
416 default:
417 ret = false;
418 break;
419 }
420 }
421 }
422
423 return ret;
424 }
425
psp_sw_init(struct amdgpu_ip_block * ip_block)426 static int psp_sw_init(struct amdgpu_ip_block *ip_block)
427 {
428 struct amdgpu_device *adev = ip_block->adev;
429 struct psp_context *psp = &adev->psp;
430 int ret;
431 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
432 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
433 struct psp_runtime_scpm_entry scpm_entry;
434
435 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
436 if (!psp->cmd) {
437 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n");
438 ret = -ENOMEM;
439 }
440
441 adev->psp.xgmi_context.supports_extended_data =
442 !adev->gmc.xgmi.connected_to_cpu &&
443 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2);
444
445 memset(&scpm_entry, 0, sizeof(scpm_entry));
446 if ((psp_get_runtime_db_entry(adev,
447 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
448 &scpm_entry)) &&
449 (scpm_entry.scpm_status != SCPM_DISABLE)) {
450 adev->scpm_enabled = true;
451 adev->scpm_status = scpm_entry.scpm_status;
452 } else {
453 adev->scpm_enabled = false;
454 adev->scpm_status = SCPM_DISABLE;
455 }
456
457 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
458
459 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
460 if (psp_get_runtime_db_entry(adev,
461 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
462 &boot_cfg_entry)) {
463 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
464 if ((psp->boot_cfg_bitmask) &
465 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
466 /* If psp runtime database exists, then
467 * only enable two stage memory training
468 * when TWO_STAGE_DRAM_TRAINING bit is set
469 * in runtime database
470 */
471 mem_training_ctx->enable_mem_training = true;
472 }
473
474 } else {
475 /* If psp runtime database doesn't exist or is
476 * invalid, force enable two stage memory training
477 */
478 mem_training_ctx->enable_mem_training = true;
479 }
480
481 if (mem_training_ctx->enable_mem_training) {
482 ret = psp_memory_training_init(psp);
483 if (ret) {
484 dev_err(adev->dev, "Failed to initialize memory training!\n");
485 return ret;
486 }
487
488 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
489 if (ret) {
490 dev_err(adev->dev, "Failed to process memory training!\n");
491 return ret;
492 }
493 }
494
495 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
496 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ?
497 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
498 &psp->fw_pri_bo,
499 &psp->fw_pri_mc_addr,
500 &psp->fw_pri_buf);
501 if (ret)
502 return ret;
503
504 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
505 AMDGPU_GEM_DOMAIN_VRAM |
506 AMDGPU_GEM_DOMAIN_GTT,
507 &psp->fence_buf_bo,
508 &psp->fence_buf_mc_addr,
509 &psp->fence_buf);
510 if (ret)
511 goto failed1;
512
513 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
514 AMDGPU_GEM_DOMAIN_VRAM |
515 AMDGPU_GEM_DOMAIN_GTT,
516 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
517 (void **)&psp->cmd_buf_mem);
518 if (ret)
519 goto failed2;
520
521 return 0;
522
523 failed2:
524 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
525 &psp->fence_buf_mc_addr, &psp->fence_buf);
526 failed1:
527 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
528 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
529 return ret;
530 }
531
psp_sw_fini(struct amdgpu_ip_block * ip_block)532 static int psp_sw_fini(struct amdgpu_ip_block *ip_block)
533 {
534 struct amdgpu_device *adev = ip_block->adev;
535 struct psp_context *psp = &adev->psp;
536 struct psp_gfx_cmd_resp *cmd = psp->cmd;
537
538 psp_memory_training_fini(psp);
539
540 amdgpu_ucode_release(&psp->sos_fw);
541 amdgpu_ucode_release(&psp->asd_fw);
542 amdgpu_ucode_release(&psp->ta_fw);
543 amdgpu_ucode_release(&psp->cap_fw);
544 amdgpu_ucode_release(&psp->toc_fw);
545
546 kfree(cmd);
547 cmd = NULL;
548
549 psp_free_shared_bufs(psp);
550
551 if (psp->km_ring.ring_mem)
552 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
553 &psp->km_ring.ring_mem_mc_addr,
554 (void **)&psp->km_ring.ring_mem);
555
556 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
557 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
558 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
559 &psp->fence_buf_mc_addr, &psp->fence_buf);
560 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
561 (void **)&psp->cmd_buf_mem);
562
563 return 0;
564 }
565
psp_wait_for(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,bool check_changed)566 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
567 uint32_t reg_val, uint32_t mask, bool check_changed)
568 {
569 uint32_t val;
570 int i;
571 struct amdgpu_device *adev = psp->adev;
572
573 if (psp->adev->no_hw_access)
574 return 0;
575
576 for (i = 0; i < adev->usec_timeout; i++) {
577 val = RREG32(reg_index);
578 if (check_changed) {
579 if (val != reg_val)
580 return 0;
581 } else {
582 if ((val & mask) == reg_val)
583 return 0;
584 }
585 udelay(1);
586 }
587
588 return -ETIME;
589 }
590
psp_wait_for_spirom_update(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,uint32_t msec_timeout)591 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
592 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
593 {
594 uint32_t val;
595 int i;
596 struct amdgpu_device *adev = psp->adev;
597
598 if (psp->adev->no_hw_access)
599 return 0;
600
601 for (i = 0; i < msec_timeout; i++) {
602 val = RREG32(reg_index);
603 if ((val & mask) == reg_val)
604 return 0;
605 msleep(1);
606 }
607
608 return -ETIME;
609 }
610
psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)611 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
612 {
613 switch (cmd_id) {
614 case GFX_CMD_ID_LOAD_TA:
615 return "LOAD_TA";
616 case GFX_CMD_ID_UNLOAD_TA:
617 return "UNLOAD_TA";
618 case GFX_CMD_ID_INVOKE_CMD:
619 return "INVOKE_CMD";
620 case GFX_CMD_ID_LOAD_ASD:
621 return "LOAD_ASD";
622 case GFX_CMD_ID_SETUP_TMR:
623 return "SETUP_TMR";
624 case GFX_CMD_ID_LOAD_IP_FW:
625 return "LOAD_IP_FW";
626 case GFX_CMD_ID_DESTROY_TMR:
627 return "DESTROY_TMR";
628 case GFX_CMD_ID_SAVE_RESTORE:
629 return "SAVE_RESTORE_IP_FW";
630 case GFX_CMD_ID_SETUP_VMR:
631 return "SETUP_VMR";
632 case GFX_CMD_ID_DESTROY_VMR:
633 return "DESTROY_VMR";
634 case GFX_CMD_ID_PROG_REG:
635 return "PROG_REG";
636 case GFX_CMD_ID_GET_FW_ATTESTATION:
637 return "GET_FW_ATTESTATION";
638 case GFX_CMD_ID_LOAD_TOC:
639 return "ID_LOAD_TOC";
640 case GFX_CMD_ID_AUTOLOAD_RLC:
641 return "AUTOLOAD_RLC";
642 case GFX_CMD_ID_BOOT_CFG:
643 return "BOOT_CFG";
644 case GFX_CMD_ID_CONFIG_SQ_PERFMON:
645 return "CONFIG_SQ_PERFMON";
646 default:
647 return "UNKNOWN CMD";
648 }
649 }
650
psp_err_warn(struct psp_context * psp)651 static bool psp_err_warn(struct psp_context *psp)
652 {
653 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem;
654
655 /* This response indicates reg list is already loaded */
656 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
657 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW &&
658 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST &&
659 cmd->resp.status == TEE_ERROR_CANCEL)
660 return false;
661
662 return true;
663 }
664
665 static int
psp_cmd_submit_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd,uint64_t fence_mc_addr)666 psp_cmd_submit_buf(struct psp_context *psp,
667 struct amdgpu_firmware_info *ucode,
668 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
669 {
670 int ret;
671 int index;
672 int timeout = psp->adev->psp_timeout;
673 bool ras_intr = false;
674 bool skip_unsupport = false;
675
676 if (psp->adev->no_hw_access)
677 return 0;
678
679 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
680
681 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
682
683 index = atomic_inc_return(&psp->fence_value);
684 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
685 if (ret) {
686 atomic_dec(&psp->fence_value);
687 goto exit;
688 }
689
690 amdgpu_device_invalidate_hdp(psp->adev, NULL);
691 while (*((unsigned int *)psp->fence_buf) != index) {
692 if (--timeout == 0)
693 break;
694 /*
695 * Shouldn't wait for timeout when err_event_athub occurs,
696 * because gpu reset thread triggered and lock resource should
697 * be released for psp resume sequence.
698 */
699 ras_intr = amdgpu_ras_intr_triggered();
700 if (ras_intr)
701 break;
702 usleep_range(10, 100);
703 amdgpu_device_invalidate_hdp(psp->adev, NULL);
704 }
705
706 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
707 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
708 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
709
710 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
711
712 /* In some cases, psp response status is not 0 even there is no
713 * problem while the command is submitted. Some version of PSP FW
714 * doesn't write 0 to that field.
715 * So here we would like to only print a warning instead of an error
716 * during psp initialization to avoid breaking hw_init and it doesn't
717 * return -EINVAL.
718 */
719 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
720 if (ucode)
721 dev_warn(psp->adev->dev,
722 "failed to load ucode %s(0x%X) ",
723 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
724 if (psp_err_warn(psp))
725 dev_warn(
726 psp->adev->dev,
727 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
728 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
729 psp->cmd_buf_mem->cmd_id,
730 psp->cmd_buf_mem->resp.status);
731 /* If any firmware (including CAP) load fails under SRIOV, it should
732 * return failure to stop the VF from initializing.
733 * Also return failure in case of timeout
734 */
735 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
736 ret = -EINVAL;
737 goto exit;
738 }
739 }
740
741 if (ucode) {
742 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
743 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
744 }
745
746 exit:
747 return ret;
748 }
749
acquire_psp_cmd_buf(struct psp_context * psp)750 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
751 {
752 struct psp_gfx_cmd_resp *cmd = psp->cmd;
753
754 mutex_lock(&psp->mutex);
755
756 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
757
758 return cmd;
759 }
760
release_psp_cmd_buf(struct psp_context * psp)761 static void release_psp_cmd_buf(struct psp_context *psp)
762 {
763 mutex_unlock(&psp->mutex);
764 }
765
psp_prep_tmr_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd,uint64_t tmr_mc,struct amdgpu_bo * tmr_bo)766 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
767 struct psp_gfx_cmd_resp *cmd,
768 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
769 {
770 struct amdgpu_device *adev = psp->adev;
771 uint32_t size = 0;
772 uint64_t tmr_pa = 0;
773
774 if (tmr_bo) {
775 size = amdgpu_bo_size(tmr_bo);
776 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
777 }
778
779 if (amdgpu_sriov_vf(psp->adev))
780 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
781 else
782 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
783 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
784 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
785 cmd->cmd.cmd_setup_tmr.buf_size = size;
786 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
787 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
788 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
789 }
790
psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t pri_buf_mc,uint32_t size)791 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
792 uint64_t pri_buf_mc, uint32_t size)
793 {
794 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
795 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
796 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
797 cmd->cmd.cmd_load_toc.toc_size = size;
798 }
799
800 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
psp_load_toc(struct psp_context * psp,uint32_t * tmr_size)801 static int psp_load_toc(struct psp_context *psp,
802 uint32_t *tmr_size)
803 {
804 int ret;
805 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
806
807 /* Copy toc to psp firmware private buffer */
808 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
809
810 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
811
812 ret = psp_cmd_submit_buf(psp, NULL, cmd,
813 psp->fence_buf_mc_addr);
814 if (!ret)
815 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
816
817 release_psp_cmd_buf(psp);
818
819 return ret;
820 }
821
822 /* Set up Trusted Memory Region */
psp_tmr_init(struct psp_context * psp)823 static int psp_tmr_init(struct psp_context *psp)
824 {
825 int ret = 0;
826 int tmr_size;
827 void *tmr_buf;
828 void **pptr;
829
830 /*
831 * According to HW engineer, they prefer the TMR address be "naturally
832 * aligned" , e.g. the start address be an integer divide of TMR size.
833 *
834 * Note: this memory need be reserved till the driver
835 * uninitializes.
836 */
837 tmr_size = PSP_TMR_SIZE(psp->adev);
838
839 /* For ASICs support RLC autoload, psp will parse the toc
840 * and calculate the total size of TMR needed
841 */
842 if (!amdgpu_sriov_vf(psp->adev) &&
843 psp->toc.start_addr &&
844 psp->toc.size_bytes &&
845 psp->fw_pri_buf) {
846 ret = psp_load_toc(psp, &tmr_size);
847 if (ret) {
848 dev_err(psp->adev->dev, "Failed to load toc\n");
849 return ret;
850 }
851 }
852
853 if (!psp->tmr_bo && !psp->boot_time_tmr) {
854 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
855 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
856 PSP_TMR_ALIGNMENT,
857 AMDGPU_HAS_VRAM(psp->adev) ?
858 AMDGPU_GEM_DOMAIN_VRAM :
859 AMDGPU_GEM_DOMAIN_GTT,
860 &psp->tmr_bo, &psp->tmr_mc_addr,
861 pptr);
862 }
863
864 return ret;
865 }
866
psp_skip_tmr(struct psp_context * psp)867 static bool psp_skip_tmr(struct psp_context *psp)
868 {
869 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
870 case IP_VERSION(11, 0, 9):
871 case IP_VERSION(11, 0, 7):
872 case IP_VERSION(13, 0, 2):
873 case IP_VERSION(13, 0, 6):
874 case IP_VERSION(13, 0, 10):
875 case IP_VERSION(13, 0, 12):
876 case IP_VERSION(13, 0, 14):
877 return true;
878 default:
879 return false;
880 }
881 }
882
psp_tmr_load(struct psp_context * psp)883 static int psp_tmr_load(struct psp_context *psp)
884 {
885 int ret;
886 struct psp_gfx_cmd_resp *cmd;
887
888 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
889 * Already set up by host driver.
890 */
891 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
892 return 0;
893
894 cmd = acquire_psp_cmd_buf(psp);
895
896 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
897 if (psp->tmr_bo)
898 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n",
899 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
900
901 ret = psp_cmd_submit_buf(psp, NULL, cmd,
902 psp->fence_buf_mc_addr);
903
904 release_psp_cmd_buf(psp);
905
906 return ret;
907 }
908
psp_prep_tmr_unload_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd)909 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
910 struct psp_gfx_cmd_resp *cmd)
911 {
912 if (amdgpu_sriov_vf(psp->adev))
913 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
914 else
915 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
916 }
917
psp_tmr_unload(struct psp_context * psp)918 static int psp_tmr_unload(struct psp_context *psp)
919 {
920 int ret;
921 struct psp_gfx_cmd_resp *cmd;
922
923 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
924 * as TMR is not loaded at all
925 */
926 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
927 return 0;
928
929 cmd = acquire_psp_cmd_buf(psp);
930
931 psp_prep_tmr_unload_cmd_buf(psp, cmd);
932 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
933
934 ret = psp_cmd_submit_buf(psp, NULL, cmd,
935 psp->fence_buf_mc_addr);
936
937 release_psp_cmd_buf(psp);
938
939 return ret;
940 }
941
psp_tmr_terminate(struct psp_context * psp)942 static int psp_tmr_terminate(struct psp_context *psp)
943 {
944 return psp_tmr_unload(psp);
945 }
946
psp_get_fw_attestation_records_addr(struct psp_context * psp,uint64_t * output_ptr)947 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
948 uint64_t *output_ptr)
949 {
950 int ret;
951 struct psp_gfx_cmd_resp *cmd;
952
953 if (!output_ptr)
954 return -EINVAL;
955
956 if (amdgpu_sriov_vf(psp->adev))
957 return 0;
958
959 cmd = acquire_psp_cmd_buf(psp);
960
961 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
962
963 ret = psp_cmd_submit_buf(psp, NULL, cmd,
964 psp->fence_buf_mc_addr);
965
966 if (!ret) {
967 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
968 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
969 }
970
971 release_psp_cmd_buf(psp);
972
973 return ret;
974 }
975
psp_boot_config_get(struct amdgpu_device * adev,uint32_t * boot_cfg)976 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
977 {
978 struct psp_context *psp = &adev->psp;
979 struct psp_gfx_cmd_resp *cmd;
980 int ret;
981
982 if (amdgpu_sriov_vf(adev))
983 return 0;
984
985 cmd = acquire_psp_cmd_buf(psp);
986
987 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
988 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
989
990 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
991 if (!ret) {
992 *boot_cfg =
993 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
994 }
995
996 release_psp_cmd_buf(psp);
997
998 return ret;
999 }
1000
psp_boot_config_set(struct amdgpu_device * adev,uint32_t boot_cfg)1001 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
1002 {
1003 int ret;
1004 struct psp_context *psp = &adev->psp;
1005 struct psp_gfx_cmd_resp *cmd;
1006
1007 if (amdgpu_sriov_vf(adev))
1008 return 0;
1009
1010 cmd = acquire_psp_cmd_buf(psp);
1011
1012 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
1013 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
1014 cmd->cmd.boot_cfg.boot_config = boot_cfg;
1015 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
1016
1017 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1018
1019 release_psp_cmd_buf(psp);
1020
1021 return ret;
1022 }
1023
psp_rl_load(struct amdgpu_device * adev)1024 static int psp_rl_load(struct amdgpu_device *adev)
1025 {
1026 int ret;
1027 struct psp_context *psp = &adev->psp;
1028 struct psp_gfx_cmd_resp *cmd;
1029
1030 if (!is_psp_fw_valid(psp->rl))
1031 return 0;
1032
1033 cmd = acquire_psp_cmd_buf(psp);
1034
1035 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1036 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
1037
1038 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1039 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1040 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1041 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1042 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1043
1044 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1045
1046 release_psp_cmd_buf(psp);
1047
1048 return ret;
1049 }
1050
psp_memory_partition(struct psp_context * psp,int mode)1051 int psp_memory_partition(struct psp_context *psp, int mode)
1052 {
1053 struct psp_gfx_cmd_resp *cmd;
1054 int ret;
1055
1056 if (amdgpu_sriov_vf(psp->adev))
1057 return 0;
1058
1059 cmd = acquire_psp_cmd_buf(psp);
1060
1061 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE;
1062 cmd->cmd.cmd_memory_part.mode = mode;
1063
1064 dev_info(psp->adev->dev,
1065 "Requesting %d memory partition change through PSP", mode);
1066 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1067 if (ret)
1068 dev_err(psp->adev->dev,
1069 "PSP request failed to change to NPS%d mode\n", mode);
1070
1071 release_psp_cmd_buf(psp);
1072
1073 return ret;
1074 }
1075
psp_spatial_partition(struct psp_context * psp,int mode)1076 int psp_spatial_partition(struct psp_context *psp, int mode)
1077 {
1078 struct psp_gfx_cmd_resp *cmd;
1079 int ret;
1080
1081 if (amdgpu_sriov_vf(psp->adev))
1082 return 0;
1083
1084 cmd = acquire_psp_cmd_buf(psp);
1085
1086 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1087 cmd->cmd.cmd_spatial_part.mode = mode;
1088
1089 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1090 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1091
1092 release_psp_cmd_buf(psp);
1093
1094 return ret;
1095 }
1096
psp_asd_initialize(struct psp_context * psp)1097 static int psp_asd_initialize(struct psp_context *psp)
1098 {
1099 int ret;
1100
1101 /* If PSP version doesn't match ASD version, asd loading will be failed.
1102 * add workaround to bypass it for sriov now.
1103 * TODO: add version check to make it common
1104 */
1105 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1106 return 0;
1107
1108 /* bypass asd if display hardware is not available */
1109 if (!amdgpu_device_has_display_hardware(psp->adev) &&
1110 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10))
1111 return 0;
1112
1113 psp->asd_context.mem_context.shared_mc_addr = 0;
1114 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1115 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
1116
1117 ret = psp_ta_load(psp, &psp->asd_context);
1118 if (!ret)
1119 psp->asd_context.initialized = true;
1120
1121 return ret;
1122 }
1123
psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t session_id)1124 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1125 uint32_t session_id)
1126 {
1127 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1128 cmd->cmd.cmd_unload_ta.session_id = session_id;
1129 }
1130
psp_ta_unload(struct psp_context * psp,struct ta_context * context)1131 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1132 {
1133 int ret;
1134 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1135
1136 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1137
1138 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1139
1140 context->resp_status = cmd->resp.status;
1141
1142 release_psp_cmd_buf(psp);
1143
1144 return ret;
1145 }
1146
psp_asd_terminate(struct psp_context * psp)1147 static int psp_asd_terminate(struct psp_context *psp)
1148 {
1149 int ret;
1150
1151 if (amdgpu_sriov_vf(psp->adev))
1152 return 0;
1153
1154 if (!psp->asd_context.initialized)
1155 return 0;
1156
1157 ret = psp_ta_unload(psp, &psp->asd_context);
1158 if (!ret)
1159 psp->asd_context.initialized = false;
1160
1161 return ret;
1162 }
1163
psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t id,uint32_t value)1164 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1165 uint32_t id, uint32_t value)
1166 {
1167 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1168 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1169 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1170 }
1171
psp_reg_program(struct psp_context * psp,enum psp_reg_prog_id reg,uint32_t value)1172 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1173 uint32_t value)
1174 {
1175 struct psp_gfx_cmd_resp *cmd;
1176 int ret = 0;
1177
1178 if (reg >= PSP_REG_LAST)
1179 return -EINVAL;
1180
1181 cmd = acquire_psp_cmd_buf(psp);
1182
1183 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1184 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1185 if (ret)
1186 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg);
1187
1188 release_psp_cmd_buf(psp);
1189
1190 return ret;
1191 }
1192
psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t ta_bin_mc,struct ta_context * context)1193 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1194 uint64_t ta_bin_mc,
1195 struct ta_context *context)
1196 {
1197 cmd->cmd_id = context->ta_load_type;
1198 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1199 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1200 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1201
1202 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1203 lower_32_bits(context->mem_context.shared_mc_addr);
1204 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1205 upper_32_bits(context->mem_context.shared_mc_addr);
1206 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1207 }
1208
psp_ta_init_shared_buf(struct psp_context * psp,struct ta_mem_context * mem_ctx)1209 int psp_ta_init_shared_buf(struct psp_context *psp,
1210 struct ta_mem_context *mem_ctx)
1211 {
1212 /*
1213 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1214 * physical) for ta to host memory
1215 */
1216 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1217 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1218 AMDGPU_GEM_DOMAIN_GTT,
1219 &mem_ctx->shared_bo,
1220 &mem_ctx->shared_mc_addr,
1221 &mem_ctx->shared_buf);
1222 }
1223
psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,uint32_t session_id)1224 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1225 uint32_t ta_cmd_id,
1226 uint32_t session_id)
1227 {
1228 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1229 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1230 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1231 }
1232
psp_ta_invoke(struct psp_context * psp,uint32_t ta_cmd_id,struct ta_context * context)1233 int psp_ta_invoke(struct psp_context *psp,
1234 uint32_t ta_cmd_id,
1235 struct ta_context *context)
1236 {
1237 int ret;
1238 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1239
1240 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1241
1242 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1243 psp->fence_buf_mc_addr);
1244
1245 context->resp_status = cmd->resp.status;
1246
1247 release_psp_cmd_buf(psp);
1248
1249 return ret;
1250 }
1251
psp_ta_load(struct psp_context * psp,struct ta_context * context)1252 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1253 {
1254 int ret;
1255 struct psp_gfx_cmd_resp *cmd;
1256
1257 cmd = acquire_psp_cmd_buf(psp);
1258
1259 psp_copy_fw(psp, context->bin_desc.start_addr,
1260 context->bin_desc.size_bytes);
1261
1262 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1263
1264 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1265 psp->fence_buf_mc_addr);
1266
1267 context->resp_status = cmd->resp.status;
1268
1269 if (!ret)
1270 context->session_id = cmd->resp.session_id;
1271
1272 release_psp_cmd_buf(psp);
1273
1274 return ret;
1275 }
1276
psp_xgmi_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1277 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1278 {
1279 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1280 }
1281
psp_xgmi_terminate(struct psp_context * psp)1282 int psp_xgmi_terminate(struct psp_context *psp)
1283 {
1284 int ret;
1285 struct amdgpu_device *adev = psp->adev;
1286
1287 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1288 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
1289 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
1290 adev->gmc.xgmi.connected_to_cpu))
1291 return 0;
1292
1293 if (!psp->xgmi_context.context.initialized)
1294 return 0;
1295
1296 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1297
1298 psp->xgmi_context.context.initialized = false;
1299
1300 return ret;
1301 }
1302
psp_xgmi_initialize(struct psp_context * psp,bool set_extended_data,bool load_ta)1303 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1304 {
1305 struct ta_xgmi_shared_memory *xgmi_cmd;
1306 int ret;
1307
1308 if (!psp->ta_fw ||
1309 !psp->xgmi_context.context.bin_desc.size_bytes ||
1310 !psp->xgmi_context.context.bin_desc.start_addr)
1311 return -ENOENT;
1312
1313 if (!load_ta)
1314 goto invoke;
1315
1316 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1317 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1318
1319 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1320 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1321 if (ret)
1322 return ret;
1323 }
1324
1325 /* Load XGMI TA */
1326 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1327 if (!ret)
1328 psp->xgmi_context.context.initialized = true;
1329 else
1330 return ret;
1331
1332 invoke:
1333 /* Initialize XGMI session */
1334 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1335 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1336 xgmi_cmd->flag_extend_link_record = set_extended_data;
1337 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1338
1339 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1340 /* note down the capbility flag for XGMI TA */
1341 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag;
1342
1343 return ret;
1344 }
1345
psp_xgmi_get_hive_id(struct psp_context * psp,uint64_t * hive_id)1346 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1347 {
1348 struct ta_xgmi_shared_memory *xgmi_cmd;
1349 int ret;
1350
1351 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1352 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1353
1354 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1355
1356 /* Invoke xgmi ta to get hive id */
1357 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1358 if (ret)
1359 return ret;
1360
1361 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1362
1363 return 0;
1364 }
1365
psp_xgmi_get_node_id(struct psp_context * psp,uint64_t * node_id)1366 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1367 {
1368 struct ta_xgmi_shared_memory *xgmi_cmd;
1369 int ret;
1370
1371 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1372 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1373
1374 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1375
1376 /* Invoke xgmi ta to get the node id */
1377 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1378 if (ret)
1379 return ret;
1380
1381 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1382
1383 return 0;
1384 }
1385
psp_xgmi_peer_link_info_supported(struct psp_context * psp)1386 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1387 {
1388 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1389 IP_VERSION(13, 0, 2) &&
1390 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1391 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >=
1392 IP_VERSION(13, 0, 6);
1393 }
1394
1395 /*
1396 * Chips that support extended topology information require the driver to
1397 * reflect topology information in the opposite direction. This is
1398 * because the TA has already exceeded its link record limit and if the
1399 * TA holds bi-directional information, the driver would have to do
1400 * multiple fetches instead of just two.
1401 */
psp_xgmi_reflect_topology_info(struct psp_context * psp,struct psp_xgmi_node_info node_info)1402 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1403 struct psp_xgmi_node_info node_info)
1404 {
1405 struct amdgpu_device *mirror_adev;
1406 struct amdgpu_hive_info *hive;
1407 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1408 uint64_t dst_node_id = node_info.node_id;
1409 uint8_t dst_num_hops = node_info.num_hops;
1410 uint8_t dst_num_links = node_info.num_links;
1411
1412 hive = amdgpu_get_xgmi_hive(psp->adev);
1413 if (WARN_ON(!hive))
1414 return;
1415
1416 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1417 struct psp_xgmi_topology_info *mirror_top_info;
1418 int j;
1419
1420 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1421 continue;
1422
1423 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1424 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1425 if (mirror_top_info->nodes[j].node_id != src_node_id)
1426 continue;
1427
1428 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1429 /*
1430 * prevent 0 num_links value re-reflection since reflection
1431 * criteria is based on num_hops (direct or indirect).
1432 *
1433 */
1434 if (dst_num_links)
1435 mirror_top_info->nodes[j].num_links = dst_num_links;
1436
1437 break;
1438 }
1439
1440 break;
1441 }
1442
1443 amdgpu_put_xgmi_hive(hive);
1444 }
1445
psp_xgmi_get_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology,bool get_extended_data)1446 int psp_xgmi_get_topology_info(struct psp_context *psp,
1447 int number_devices,
1448 struct psp_xgmi_topology_info *topology,
1449 bool get_extended_data)
1450 {
1451 struct ta_xgmi_shared_memory *xgmi_cmd;
1452 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1453 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1454 int i;
1455 int ret;
1456
1457 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1458 return -EINVAL;
1459
1460 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1461 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1462 xgmi_cmd->flag_extend_link_record = get_extended_data;
1463
1464 /* Fill in the shared memory with topology information as input */
1465 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1466 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO;
1467 topology_info_input->num_nodes = number_devices;
1468
1469 for (i = 0; i < topology_info_input->num_nodes; i++) {
1470 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1471 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1472 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1473 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1474 }
1475
1476 /* Invoke xgmi ta to get the topology information */
1477 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO);
1478 if (ret)
1479 return ret;
1480
1481 /* Read the output topology information from the shared memory */
1482 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1483 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1484 for (i = 0; i < topology->num_nodes; i++) {
1485 /* extended data will either be 0 or equal to non-extended data */
1486 if (topology_info_output->nodes[i].num_hops)
1487 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1488
1489 /* non-extended data gets everything here so no need to update */
1490 if (!get_extended_data) {
1491 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1492 topology->nodes[i].is_sharing_enabled =
1493 topology_info_output->nodes[i].is_sharing_enabled;
1494 topology->nodes[i].sdma_engine =
1495 topology_info_output->nodes[i].sdma_engine;
1496 }
1497
1498 }
1499
1500 /* Invoke xgmi ta again to get the link information */
1501 if (psp_xgmi_peer_link_info_supported(psp)) {
1502 struct ta_xgmi_cmd_get_peer_link_info *link_info_output;
1503 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output;
1504 bool requires_reflection =
1505 (psp->xgmi_context.supports_extended_data &&
1506 get_extended_data) ||
1507 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1508 IP_VERSION(13, 0, 6) ||
1509 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1510 IP_VERSION(13, 0, 14);
1511 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 :
1512 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG;
1513
1514 /* popluate the shared output buffer rather than the cmd input buffer
1515 * with node_ids as the input for GET_PEER_LINKS command execution.
1516 * This is required for GET_PEER_LINKS per xgmi ta implementation.
1517 * The same requirement for GET_EXTEND_PEER_LINKS command.
1518 */
1519 if (ta_port_num_support) {
1520 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info;
1521
1522 for (i = 0; i < topology->num_nodes; i++)
1523 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id;
1524
1525 link_extend_info_output->num_nodes = topology->num_nodes;
1526 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS;
1527 } else {
1528 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1529
1530 for (i = 0; i < topology->num_nodes; i++)
1531 link_info_output->nodes[i].node_id = topology->nodes[i].node_id;
1532
1533 link_info_output->num_nodes = topology->num_nodes;
1534 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1535 }
1536
1537 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1538 if (ret)
1539 return ret;
1540
1541 for (i = 0; i < topology->num_nodes; i++) {
1542 uint8_t node_num_links = ta_port_num_support ?
1543 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links;
1544 /* accumulate num_links on extended data */
1545 if (get_extended_data) {
1546 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links;
1547 } else {
1548 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ?
1549 topology->nodes[i].num_links : node_num_links;
1550 }
1551 /* popluate the connected port num info if supported and available */
1552 if (ta_port_num_support && topology->nodes[i].num_links) {
1553 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num,
1554 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM);
1555 }
1556
1557 /* reflect the topology information for bi-directionality */
1558 if (requires_reflection && topology->nodes[i].num_hops)
1559 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1560 }
1561 }
1562
1563 return 0;
1564 }
1565
psp_xgmi_set_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)1566 int psp_xgmi_set_topology_info(struct psp_context *psp,
1567 int number_devices,
1568 struct psp_xgmi_topology_info *topology)
1569 {
1570 struct ta_xgmi_shared_memory *xgmi_cmd;
1571 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1572 int i;
1573
1574 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1575 return -EINVAL;
1576
1577 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1578 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1579
1580 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1581 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1582 topology_info_input->num_nodes = number_devices;
1583
1584 for (i = 0; i < topology_info_input->num_nodes; i++) {
1585 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1586 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1587 topology_info_input->nodes[i].is_sharing_enabled = 1;
1588 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1589 }
1590
1591 /* Invoke xgmi ta to set topology information */
1592 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1593 }
1594
1595 // ras begin
psp_ras_ta_check_status(struct psp_context * psp)1596 static void psp_ras_ta_check_status(struct psp_context *psp)
1597 {
1598 struct ta_ras_shared_memory *ras_cmd =
1599 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1600
1601 switch (ras_cmd->ras_status) {
1602 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1603 dev_warn(psp->adev->dev,
1604 "RAS WARNING: cmd failed due to unsupported ip\n");
1605 break;
1606 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1607 dev_warn(psp->adev->dev,
1608 "RAS WARNING: cmd failed due to unsupported error injection\n");
1609 break;
1610 case TA_RAS_STATUS__SUCCESS:
1611 break;
1612 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1613 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1614 dev_warn(psp->adev->dev,
1615 "RAS WARNING: Inject error to critical region is not allowed\n");
1616 break;
1617 default:
1618 dev_warn(psp->adev->dev,
1619 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1620 break;
1621 }
1622 }
1623
psp_ras_send_cmd(struct psp_context * psp,enum ras_command cmd_id,void * in,void * out)1624 static int psp_ras_send_cmd(struct psp_context *psp,
1625 enum ras_command cmd_id, void *in, void *out)
1626 {
1627 struct ta_ras_shared_memory *ras_cmd;
1628 uint32_t cmd = cmd_id;
1629 int ret = 0;
1630
1631 if (!in)
1632 return -EINVAL;
1633
1634 mutex_lock(&psp->ras_context.mutex);
1635 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1636 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1637
1638 switch (cmd) {
1639 case TA_RAS_COMMAND__ENABLE_FEATURES:
1640 case TA_RAS_COMMAND__DISABLE_FEATURES:
1641 memcpy(&ras_cmd->ras_in_message,
1642 in, sizeof(ras_cmd->ras_in_message));
1643 break;
1644 case TA_RAS_COMMAND__TRIGGER_ERROR:
1645 memcpy(&ras_cmd->ras_in_message.trigger_error,
1646 in, sizeof(ras_cmd->ras_in_message.trigger_error));
1647 break;
1648 case TA_RAS_COMMAND__QUERY_ADDRESS:
1649 memcpy(&ras_cmd->ras_in_message.address,
1650 in, sizeof(ras_cmd->ras_in_message.address));
1651 break;
1652 default:
1653 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd);
1654 ret = -EINVAL;
1655 goto err_out;
1656 }
1657
1658 ras_cmd->cmd_id = cmd;
1659 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1660
1661 switch (cmd) {
1662 case TA_RAS_COMMAND__TRIGGER_ERROR:
1663 if (!ret && out)
1664 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status));
1665 break;
1666 case TA_RAS_COMMAND__QUERY_ADDRESS:
1667 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status)
1668 ret = -EINVAL;
1669 else if (out)
1670 memcpy(out,
1671 &ras_cmd->ras_out_message.address,
1672 sizeof(ras_cmd->ras_out_message.address));
1673 break;
1674 default:
1675 break;
1676 }
1677
1678 err_out:
1679 mutex_unlock(&psp->ras_context.mutex);
1680
1681 return ret;
1682 }
1683
psp_ras_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1684 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1685 {
1686 struct ta_ras_shared_memory *ras_cmd;
1687 int ret;
1688
1689 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1690
1691 /*
1692 * TODO: bypass the loading in sriov for now
1693 */
1694 if (amdgpu_sriov_vf(psp->adev))
1695 return 0;
1696
1697 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1698
1699 if (amdgpu_ras_intr_triggered())
1700 return ret;
1701
1702 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1703 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n");
1704 return -EINVAL;
1705 }
1706
1707 if (!ret) {
1708 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1709 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1710
1711 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1712 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1713 dev_warn(psp->adev->dev,
1714 "RAS internal register access blocked\n");
1715
1716 psp_ras_ta_check_status(psp);
1717 }
1718
1719 return ret;
1720 }
1721
psp_ras_enable_features(struct psp_context * psp,union ta_ras_cmd_input * info,bool enable)1722 int psp_ras_enable_features(struct psp_context *psp,
1723 union ta_ras_cmd_input *info, bool enable)
1724 {
1725 enum ras_command cmd_id;
1726 int ret;
1727
1728 if (!psp->ras_context.context.initialized || !info)
1729 return -EINVAL;
1730
1731 cmd_id = enable ?
1732 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES;
1733 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL);
1734 if (ret)
1735 return -EINVAL;
1736
1737 return 0;
1738 }
1739
psp_ras_terminate(struct psp_context * psp)1740 int psp_ras_terminate(struct psp_context *psp)
1741 {
1742 int ret;
1743
1744 /*
1745 * TODO: bypass the terminate in sriov for now
1746 */
1747 if (amdgpu_sriov_vf(psp->adev))
1748 return 0;
1749
1750 if (!psp->ras_context.context.initialized)
1751 return 0;
1752
1753 ret = psp_ta_unload(psp, &psp->ras_context.context);
1754
1755 psp->ras_context.context.initialized = false;
1756
1757 mutex_destroy(&psp->ras_context.mutex);
1758
1759 return ret;
1760 }
1761
psp_ras_initialize(struct psp_context * psp)1762 int psp_ras_initialize(struct psp_context *psp)
1763 {
1764 int ret;
1765 uint32_t boot_cfg = 0xFF;
1766 struct amdgpu_device *adev = psp->adev;
1767 struct ta_ras_shared_memory *ras_cmd;
1768
1769 /*
1770 * TODO: bypass the initialize in sriov for now
1771 */
1772 if (amdgpu_sriov_vf(adev))
1773 return 0;
1774
1775 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1776 !adev->psp.ras_context.context.bin_desc.start_addr) {
1777 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1778 return 0;
1779 }
1780
1781 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1782 /* query GECC enablement status from boot config
1783 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1784 */
1785 ret = psp_boot_config_get(adev, &boot_cfg);
1786 if (ret)
1787 dev_warn(adev->dev, "PSP get boot config failed\n");
1788
1789 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1790 if (!boot_cfg) {
1791 dev_info(adev->dev, "GECC is disabled\n");
1792 } else {
1793 /* disable GECC in next boot cycle if ras is
1794 * disabled by module parameter amdgpu_ras_enable
1795 * and/or amdgpu_ras_mask, or boot_config_get call
1796 * is failed
1797 */
1798 ret = psp_boot_config_set(adev, 0);
1799 if (ret)
1800 dev_warn(adev->dev, "PSP set boot config failed\n");
1801 else
1802 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1803 }
1804 } else {
1805 if (boot_cfg == 1) {
1806 dev_info(adev->dev, "GECC is enabled\n");
1807 } else {
1808 /* enable GECC in next boot cycle if it is disabled
1809 * in boot config, or force enable GECC if failed to
1810 * get boot configuration
1811 */
1812 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1813 if (ret)
1814 dev_warn(adev->dev, "PSP set boot config failed\n");
1815 else
1816 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1817 }
1818 }
1819 }
1820
1821 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1822 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1823
1824 if (!psp->ras_context.context.mem_context.shared_buf) {
1825 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1826 if (ret)
1827 return ret;
1828 }
1829
1830 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1831 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1832
1833 if (amdgpu_ras_is_poison_mode_supported(adev))
1834 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1835 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1836 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1837 ras_cmd->ras_in_message.init_flags.xcc_mask =
1838 adev->gfx.xcc_mask;
1839 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1840 if (adev->gmc.gmc_funcs->query_mem_partition_mode)
1841 ras_cmd->ras_in_message.init_flags.nps_mode =
1842 adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
1843
1844 ret = psp_ta_load(psp, &psp->ras_context.context);
1845
1846 if (!ret && !ras_cmd->ras_status) {
1847 psp->ras_context.context.initialized = true;
1848 mutex_init(&psp->ras_context.mutex);
1849 } else {
1850 if (ras_cmd->ras_status)
1851 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1852
1853 /* fail to load RAS TA */
1854 psp->ras_context.context.initialized = false;
1855 }
1856
1857 return ret;
1858 }
1859
psp_ras_trigger_error(struct psp_context * psp,struct ta_ras_trigger_error_input * info,uint32_t instance_mask)1860 int psp_ras_trigger_error(struct psp_context *psp,
1861 struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1862 {
1863 struct amdgpu_device *adev = psp->adev;
1864 int ret;
1865 uint32_t dev_mask;
1866 uint32_t ras_status = 0;
1867
1868 if (!psp->ras_context.context.initialized || !info)
1869 return -EINVAL;
1870
1871 switch (info->block_id) {
1872 case TA_RAS_BLOCK__GFX:
1873 dev_mask = GET_MASK(GC, instance_mask);
1874 break;
1875 case TA_RAS_BLOCK__SDMA:
1876 dev_mask = GET_MASK(SDMA0, instance_mask);
1877 break;
1878 case TA_RAS_BLOCK__VCN:
1879 case TA_RAS_BLOCK__JPEG:
1880 dev_mask = GET_MASK(VCN, instance_mask);
1881 break;
1882 default:
1883 dev_mask = instance_mask;
1884 break;
1885 }
1886
1887 /* reuse sub_block_index for backward compatibility */
1888 dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1889 dev_mask &= AMDGPU_RAS_INST_MASK;
1890 info->sub_block_index |= dev_mask;
1891
1892 ret = psp_ras_send_cmd(psp,
1893 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status);
1894 if (ret)
1895 return -EINVAL;
1896
1897 /* If err_event_athub occurs error inject was successful, however
1898 * return status from TA is no long reliable
1899 */
1900 if (amdgpu_ras_intr_triggered())
1901 return 0;
1902
1903 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1904 return -EACCES;
1905 else if (ras_status)
1906 return -EINVAL;
1907
1908 return 0;
1909 }
1910
psp_ras_query_address(struct psp_context * psp,struct ta_ras_query_address_input * addr_in,struct ta_ras_query_address_output * addr_out)1911 int psp_ras_query_address(struct psp_context *psp,
1912 struct ta_ras_query_address_input *addr_in,
1913 struct ta_ras_query_address_output *addr_out)
1914 {
1915 int ret;
1916
1917 if (!psp->ras_context.context.initialized ||
1918 !addr_in || !addr_out)
1919 return -EINVAL;
1920
1921 ret = psp_ras_send_cmd(psp,
1922 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out);
1923
1924 return ret;
1925 }
1926 // ras end
1927
1928 // HDCP start
psp_hdcp_initialize(struct psp_context * psp)1929 static int psp_hdcp_initialize(struct psp_context *psp)
1930 {
1931 int ret;
1932
1933 /*
1934 * TODO: bypass the initialize in sriov for now
1935 */
1936 if (amdgpu_sriov_vf(psp->adev))
1937 return 0;
1938
1939 /* bypass hdcp initialization if dmu is harvested */
1940 if (!amdgpu_device_has_display_hardware(psp->adev))
1941 return 0;
1942
1943 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1944 !psp->hdcp_context.context.bin_desc.start_addr) {
1945 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1946 return 0;
1947 }
1948
1949 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1950 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1951
1952 if (!psp->hdcp_context.context.mem_context.shared_buf) {
1953 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1954 if (ret)
1955 return ret;
1956 }
1957
1958 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1959 if (!ret) {
1960 psp->hdcp_context.context.initialized = true;
1961 mutex_init(&psp->hdcp_context.mutex);
1962 }
1963
1964 return ret;
1965 }
1966
psp_hdcp_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1967 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1968 {
1969 /*
1970 * TODO: bypass the loading in sriov for now
1971 */
1972 if (amdgpu_sriov_vf(psp->adev))
1973 return 0;
1974
1975 if (!psp->hdcp_context.context.initialized)
1976 return 0;
1977
1978 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1979 }
1980
psp_hdcp_terminate(struct psp_context * psp)1981 static int psp_hdcp_terminate(struct psp_context *psp)
1982 {
1983 int ret;
1984
1985 /*
1986 * TODO: bypass the terminate in sriov for now
1987 */
1988 if (amdgpu_sriov_vf(psp->adev))
1989 return 0;
1990
1991 if (!psp->hdcp_context.context.initialized)
1992 return 0;
1993
1994 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1995
1996 psp->hdcp_context.context.initialized = false;
1997
1998 return ret;
1999 }
2000 // HDCP end
2001
2002 // DTM start
psp_dtm_initialize(struct psp_context * psp)2003 static int psp_dtm_initialize(struct psp_context *psp)
2004 {
2005 int ret;
2006
2007 /*
2008 * TODO: bypass the initialize in sriov for now
2009 */
2010 if (amdgpu_sriov_vf(psp->adev))
2011 return 0;
2012
2013 /* bypass dtm initialization if dmu is harvested */
2014 if (!amdgpu_device_has_display_hardware(psp->adev))
2015 return 0;
2016
2017 if (!psp->dtm_context.context.bin_desc.size_bytes ||
2018 !psp->dtm_context.context.bin_desc.start_addr) {
2019 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
2020 return 0;
2021 }
2022
2023 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
2024 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2025
2026 if (!psp->dtm_context.context.mem_context.shared_buf) {
2027 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
2028 if (ret)
2029 return ret;
2030 }
2031
2032 ret = psp_ta_load(psp, &psp->dtm_context.context);
2033 if (!ret) {
2034 psp->dtm_context.context.initialized = true;
2035 mutex_init(&psp->dtm_context.mutex);
2036 }
2037
2038 return ret;
2039 }
2040
psp_dtm_invoke(struct psp_context * psp,uint32_t ta_cmd_id)2041 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2042 {
2043 /*
2044 * TODO: bypass the loading in sriov for now
2045 */
2046 if (amdgpu_sriov_vf(psp->adev))
2047 return 0;
2048
2049 if (!psp->dtm_context.context.initialized)
2050 return 0;
2051
2052 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
2053 }
2054
psp_dtm_terminate(struct psp_context * psp)2055 static int psp_dtm_terminate(struct psp_context *psp)
2056 {
2057 int ret;
2058
2059 /*
2060 * TODO: bypass the terminate in sriov for now
2061 */
2062 if (amdgpu_sriov_vf(psp->adev))
2063 return 0;
2064
2065 if (!psp->dtm_context.context.initialized)
2066 return 0;
2067
2068 ret = psp_ta_unload(psp, &psp->dtm_context.context);
2069
2070 psp->dtm_context.context.initialized = false;
2071
2072 return ret;
2073 }
2074 // DTM end
2075
2076 // RAP start
psp_rap_initialize(struct psp_context * psp)2077 static int psp_rap_initialize(struct psp_context *psp)
2078 {
2079 int ret;
2080 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
2081
2082 /*
2083 * TODO: bypass the initialize in sriov for now
2084 */
2085 if (amdgpu_sriov_vf(psp->adev))
2086 return 0;
2087
2088 if (!psp->rap_context.context.bin_desc.size_bytes ||
2089 !psp->rap_context.context.bin_desc.start_addr) {
2090 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
2091 return 0;
2092 }
2093
2094 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
2095 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2096
2097 if (!psp->rap_context.context.mem_context.shared_buf) {
2098 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
2099 if (ret)
2100 return ret;
2101 }
2102
2103 ret = psp_ta_load(psp, &psp->rap_context.context);
2104 if (!ret) {
2105 psp->rap_context.context.initialized = true;
2106 mutex_init(&psp->rap_context.mutex);
2107 } else
2108 return ret;
2109
2110 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
2111 if (ret || status != TA_RAP_STATUS__SUCCESS) {
2112 psp_rap_terminate(psp);
2113 /* free rap shared memory */
2114 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
2115
2116 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
2117 ret, status);
2118
2119 return ret;
2120 }
2121
2122 return 0;
2123 }
2124
psp_rap_terminate(struct psp_context * psp)2125 static int psp_rap_terminate(struct psp_context *psp)
2126 {
2127 int ret;
2128
2129 if (!psp->rap_context.context.initialized)
2130 return 0;
2131
2132 ret = psp_ta_unload(psp, &psp->rap_context.context);
2133
2134 psp->rap_context.context.initialized = false;
2135
2136 return ret;
2137 }
2138
psp_rap_invoke(struct psp_context * psp,uint32_t ta_cmd_id,enum ta_rap_status * status)2139 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
2140 {
2141 struct ta_rap_shared_memory *rap_cmd;
2142 int ret = 0;
2143
2144 if (!psp->rap_context.context.initialized)
2145 return 0;
2146
2147 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
2148 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
2149 return -EINVAL;
2150
2151 mutex_lock(&psp->rap_context.mutex);
2152
2153 rap_cmd = (struct ta_rap_shared_memory *)
2154 psp->rap_context.context.mem_context.shared_buf;
2155 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
2156
2157 rap_cmd->cmd_id = ta_cmd_id;
2158 rap_cmd->validation_method_id = METHOD_A;
2159
2160 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
2161 if (ret)
2162 goto out_unlock;
2163
2164 if (status)
2165 *status = rap_cmd->rap_status;
2166
2167 out_unlock:
2168 mutex_unlock(&psp->rap_context.mutex);
2169
2170 return ret;
2171 }
2172 // RAP end
2173
2174 /* securedisplay start */
psp_securedisplay_initialize(struct psp_context * psp)2175 static int psp_securedisplay_initialize(struct psp_context *psp)
2176 {
2177 int ret;
2178 struct ta_securedisplay_cmd *securedisplay_cmd;
2179
2180 /*
2181 * TODO: bypass the initialize in sriov for now
2182 */
2183 if (amdgpu_sriov_vf(psp->adev))
2184 return 0;
2185
2186 /* bypass securedisplay initialization if dmu is harvested */
2187 if (!amdgpu_device_has_display_hardware(psp->adev))
2188 return 0;
2189
2190 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
2191 !psp->securedisplay_context.context.bin_desc.start_addr) {
2192 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2193 return 0;
2194 }
2195
2196 psp->securedisplay_context.context.mem_context.shared_mem_size =
2197 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2198 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2199
2200 if (!psp->securedisplay_context.context.initialized) {
2201 ret = psp_ta_init_shared_buf(psp,
2202 &psp->securedisplay_context.context.mem_context);
2203 if (ret)
2204 return ret;
2205 }
2206
2207 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2208 if (!ret) {
2209 psp->securedisplay_context.context.initialized = true;
2210 mutex_init(&psp->securedisplay_context.mutex);
2211 } else
2212 return ret;
2213
2214 mutex_lock(&psp->securedisplay_context.mutex);
2215
2216 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2217 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2218
2219 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2220
2221 mutex_unlock(&psp->securedisplay_context.mutex);
2222
2223 if (ret) {
2224 psp_securedisplay_terminate(psp);
2225 /* free securedisplay shared memory */
2226 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2227 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2228 return -EINVAL;
2229 }
2230
2231 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2232 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2233 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2234 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2235 /* don't try again */
2236 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2237 }
2238
2239 return 0;
2240 }
2241
psp_securedisplay_terminate(struct psp_context * psp)2242 static int psp_securedisplay_terminate(struct psp_context *psp)
2243 {
2244 int ret;
2245
2246 /*
2247 * TODO:bypass the terminate in sriov for now
2248 */
2249 if (amdgpu_sriov_vf(psp->adev))
2250 return 0;
2251
2252 if (!psp->securedisplay_context.context.initialized)
2253 return 0;
2254
2255 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2256
2257 psp->securedisplay_context.context.initialized = false;
2258
2259 return ret;
2260 }
2261
psp_securedisplay_invoke(struct psp_context * psp,uint32_t ta_cmd_id)2262 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2263 {
2264 int ret;
2265
2266 if (!psp->securedisplay_context.context.initialized)
2267 return -EINVAL;
2268
2269 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2270 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC &&
2271 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2)
2272 return -EINVAL;
2273
2274 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2275
2276 return ret;
2277 }
2278 /* SECUREDISPLAY end */
2279
amdgpu_psp_wait_for_bootloader(struct amdgpu_device * adev)2280 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
2281 {
2282 struct psp_context *psp = &adev->psp;
2283 int ret = 0;
2284
2285 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)
2286 ret = psp->funcs->wait_for_bootloader(psp);
2287
2288 return ret;
2289 }
2290
amdgpu_psp_get_ras_capability(struct psp_context * psp)2291 bool amdgpu_psp_get_ras_capability(struct psp_context *psp)
2292 {
2293 if (psp->funcs &&
2294 psp->funcs->get_ras_capability) {
2295 return psp->funcs->get_ras_capability(psp);
2296 } else {
2297 return false;
2298 }
2299 }
2300
amdgpu_psp_tos_reload_needed(struct amdgpu_device * adev)2301 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev)
2302 {
2303 struct psp_context *psp = &adev->psp;
2304
2305 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
2306 return false;
2307
2308 if (psp->funcs && psp->funcs->is_reload_needed)
2309 return psp->funcs->is_reload_needed(psp);
2310
2311 return false;
2312 }
2313
psp_hw_start(struct psp_context * psp)2314 static int psp_hw_start(struct psp_context *psp)
2315 {
2316 struct amdgpu_device *adev = psp->adev;
2317 int ret;
2318
2319 if (!amdgpu_sriov_vf(adev)) {
2320 if ((is_psp_fw_valid(psp->kdb)) &&
2321 (psp->funcs->bootloader_load_kdb != NULL)) {
2322 ret = psp_bootloader_load_kdb(psp);
2323 if (ret) {
2324 dev_err(adev->dev, "PSP load kdb failed!\n");
2325 return ret;
2326 }
2327 }
2328
2329 if ((is_psp_fw_valid(psp->spl)) &&
2330 (psp->funcs->bootloader_load_spl != NULL)) {
2331 ret = psp_bootloader_load_spl(psp);
2332 if (ret) {
2333 dev_err(adev->dev, "PSP load spl failed!\n");
2334 return ret;
2335 }
2336 }
2337
2338 if ((is_psp_fw_valid(psp->sys)) &&
2339 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2340 ret = psp_bootloader_load_sysdrv(psp);
2341 if (ret) {
2342 dev_err(adev->dev, "PSP load sys drv failed!\n");
2343 return ret;
2344 }
2345 }
2346
2347 if ((is_psp_fw_valid(psp->soc_drv)) &&
2348 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2349 ret = psp_bootloader_load_soc_drv(psp);
2350 if (ret) {
2351 dev_err(adev->dev, "PSP load soc drv failed!\n");
2352 return ret;
2353 }
2354 }
2355
2356 if ((is_psp_fw_valid(psp->intf_drv)) &&
2357 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2358 ret = psp_bootloader_load_intf_drv(psp);
2359 if (ret) {
2360 dev_err(adev->dev, "PSP load intf drv failed!\n");
2361 return ret;
2362 }
2363 }
2364
2365 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2366 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2367 ret = psp_bootloader_load_dbg_drv(psp);
2368 if (ret) {
2369 dev_err(adev->dev, "PSP load dbg drv failed!\n");
2370 return ret;
2371 }
2372 }
2373
2374 if ((is_psp_fw_valid(psp->ras_drv)) &&
2375 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2376 ret = psp_bootloader_load_ras_drv(psp);
2377 if (ret) {
2378 dev_err(adev->dev, "PSP load ras_drv failed!\n");
2379 return ret;
2380 }
2381 }
2382
2383 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) &&
2384 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) {
2385 ret = psp_bootloader_load_ipkeymgr_drv(psp);
2386 if (ret) {
2387 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n");
2388 return ret;
2389 }
2390 }
2391
2392 if ((is_psp_fw_valid(psp->spdm_drv)) &&
2393 (psp->funcs->bootloader_load_spdm_drv != NULL)) {
2394 ret = psp_bootloader_load_spdm_drv(psp);
2395 if (ret) {
2396 dev_err(adev->dev, "PSP load spdm_drv failed!\n");
2397 return ret;
2398 }
2399 }
2400
2401 if ((is_psp_fw_valid(psp->sos)) &&
2402 (psp->funcs->bootloader_load_sos != NULL)) {
2403 ret = psp_bootloader_load_sos(psp);
2404 if (ret) {
2405 dev_err(adev->dev, "PSP load sos failed!\n");
2406 return ret;
2407 }
2408 }
2409 }
2410
2411 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2412 if (ret) {
2413 dev_err(adev->dev, "PSP create ring failed!\n");
2414 return ret;
2415 }
2416
2417 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2418 goto skip_pin_bo;
2419
2420 if (!psp->boot_time_tmr || psp->autoload_supported) {
2421 ret = psp_tmr_init(psp);
2422 if (ret) {
2423 dev_err(adev->dev, "PSP tmr init failed!\n");
2424 return ret;
2425 }
2426 }
2427
2428 skip_pin_bo:
2429 /*
2430 * For ASICs with DF Cstate management centralized
2431 * to PMFW, TMR setup should be performed after PMFW
2432 * loaded and before other non-psp firmware loaded.
2433 */
2434 if (psp->pmfw_centralized_cstate_management) {
2435 ret = psp_load_smu_fw(psp);
2436 if (ret)
2437 return ret;
2438 }
2439
2440 if (!psp->boot_time_tmr || !psp->autoload_supported) {
2441 ret = psp_tmr_load(psp);
2442 if (ret) {
2443 dev_err(adev->dev, "PSP load tmr failed!\n");
2444 return ret;
2445 }
2446 }
2447
2448 return 0;
2449 }
2450
psp_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)2451 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2452 enum psp_gfx_fw_type *type)
2453 {
2454 switch (ucode->ucode_id) {
2455 case AMDGPU_UCODE_ID_CAP:
2456 *type = GFX_FW_TYPE_CAP;
2457 break;
2458 case AMDGPU_UCODE_ID_SDMA0:
2459 *type = GFX_FW_TYPE_SDMA0;
2460 break;
2461 case AMDGPU_UCODE_ID_SDMA1:
2462 *type = GFX_FW_TYPE_SDMA1;
2463 break;
2464 case AMDGPU_UCODE_ID_SDMA2:
2465 *type = GFX_FW_TYPE_SDMA2;
2466 break;
2467 case AMDGPU_UCODE_ID_SDMA3:
2468 *type = GFX_FW_TYPE_SDMA3;
2469 break;
2470 case AMDGPU_UCODE_ID_SDMA4:
2471 *type = GFX_FW_TYPE_SDMA4;
2472 break;
2473 case AMDGPU_UCODE_ID_SDMA5:
2474 *type = GFX_FW_TYPE_SDMA5;
2475 break;
2476 case AMDGPU_UCODE_ID_SDMA6:
2477 *type = GFX_FW_TYPE_SDMA6;
2478 break;
2479 case AMDGPU_UCODE_ID_SDMA7:
2480 *type = GFX_FW_TYPE_SDMA7;
2481 break;
2482 case AMDGPU_UCODE_ID_CP_MES:
2483 *type = GFX_FW_TYPE_CP_MES;
2484 break;
2485 case AMDGPU_UCODE_ID_CP_MES_DATA:
2486 *type = GFX_FW_TYPE_MES_STACK;
2487 break;
2488 case AMDGPU_UCODE_ID_CP_MES1:
2489 *type = GFX_FW_TYPE_CP_MES_KIQ;
2490 break;
2491 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2492 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2493 break;
2494 case AMDGPU_UCODE_ID_CP_CE:
2495 *type = GFX_FW_TYPE_CP_CE;
2496 break;
2497 case AMDGPU_UCODE_ID_CP_PFP:
2498 *type = GFX_FW_TYPE_CP_PFP;
2499 break;
2500 case AMDGPU_UCODE_ID_CP_ME:
2501 *type = GFX_FW_TYPE_CP_ME;
2502 break;
2503 case AMDGPU_UCODE_ID_CP_MEC1:
2504 *type = GFX_FW_TYPE_CP_MEC;
2505 break;
2506 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2507 *type = GFX_FW_TYPE_CP_MEC_ME1;
2508 break;
2509 case AMDGPU_UCODE_ID_CP_MEC2:
2510 *type = GFX_FW_TYPE_CP_MEC;
2511 break;
2512 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2513 *type = GFX_FW_TYPE_CP_MEC_ME2;
2514 break;
2515 case AMDGPU_UCODE_ID_RLC_P:
2516 *type = GFX_FW_TYPE_RLC_P;
2517 break;
2518 case AMDGPU_UCODE_ID_RLC_V:
2519 *type = GFX_FW_TYPE_RLC_V;
2520 break;
2521 case AMDGPU_UCODE_ID_RLC_G:
2522 *type = GFX_FW_TYPE_RLC_G;
2523 break;
2524 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2525 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2526 break;
2527 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2528 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2529 break;
2530 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2531 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2532 break;
2533 case AMDGPU_UCODE_ID_RLC_IRAM:
2534 *type = GFX_FW_TYPE_RLC_IRAM;
2535 break;
2536 case AMDGPU_UCODE_ID_RLC_DRAM:
2537 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2538 break;
2539 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2540 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2541 break;
2542 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2543 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2544 break;
2545 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2546 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2547 break;
2548 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2549 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2550 break;
2551 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2552 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2553 break;
2554 case AMDGPU_UCODE_ID_SMC:
2555 *type = GFX_FW_TYPE_SMU;
2556 break;
2557 case AMDGPU_UCODE_ID_PPTABLE:
2558 *type = GFX_FW_TYPE_PPTABLE;
2559 break;
2560 case AMDGPU_UCODE_ID_UVD:
2561 *type = GFX_FW_TYPE_UVD;
2562 break;
2563 case AMDGPU_UCODE_ID_UVD1:
2564 *type = GFX_FW_TYPE_UVD1;
2565 break;
2566 case AMDGPU_UCODE_ID_VCE:
2567 *type = GFX_FW_TYPE_VCE;
2568 break;
2569 case AMDGPU_UCODE_ID_VCN:
2570 *type = GFX_FW_TYPE_VCN;
2571 break;
2572 case AMDGPU_UCODE_ID_VCN1:
2573 *type = GFX_FW_TYPE_VCN1;
2574 break;
2575 case AMDGPU_UCODE_ID_DMCU_ERAM:
2576 *type = GFX_FW_TYPE_DMCU_ERAM;
2577 break;
2578 case AMDGPU_UCODE_ID_DMCU_INTV:
2579 *type = GFX_FW_TYPE_DMCU_ISR;
2580 break;
2581 case AMDGPU_UCODE_ID_VCN0_RAM:
2582 *type = GFX_FW_TYPE_VCN0_RAM;
2583 break;
2584 case AMDGPU_UCODE_ID_VCN1_RAM:
2585 *type = GFX_FW_TYPE_VCN1_RAM;
2586 break;
2587 case AMDGPU_UCODE_ID_DMCUB:
2588 *type = GFX_FW_TYPE_DMUB;
2589 break;
2590 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2591 case AMDGPU_UCODE_ID_SDMA_RS64:
2592 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2593 break;
2594 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2595 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2596 break;
2597 case AMDGPU_UCODE_ID_IMU_I:
2598 *type = GFX_FW_TYPE_IMU_I;
2599 break;
2600 case AMDGPU_UCODE_ID_IMU_D:
2601 *type = GFX_FW_TYPE_IMU_D;
2602 break;
2603 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2604 *type = GFX_FW_TYPE_RS64_PFP;
2605 break;
2606 case AMDGPU_UCODE_ID_CP_RS64_ME:
2607 *type = GFX_FW_TYPE_RS64_ME;
2608 break;
2609 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2610 *type = GFX_FW_TYPE_RS64_MEC;
2611 break;
2612 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2613 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2614 break;
2615 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2616 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2617 break;
2618 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2619 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2620 break;
2621 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2622 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2623 break;
2624 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2625 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2626 break;
2627 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2628 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2629 break;
2630 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2631 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2632 break;
2633 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2634 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2635 break;
2636 case AMDGPU_UCODE_ID_VPE_CTX:
2637 *type = GFX_FW_TYPE_VPEC_FW1;
2638 break;
2639 case AMDGPU_UCODE_ID_VPE_CTL:
2640 *type = GFX_FW_TYPE_VPEC_FW2;
2641 break;
2642 case AMDGPU_UCODE_ID_VPE:
2643 *type = GFX_FW_TYPE_VPE;
2644 break;
2645 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
2646 *type = GFX_FW_TYPE_UMSCH_UCODE;
2647 break;
2648 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
2649 *type = GFX_FW_TYPE_UMSCH_DATA;
2650 break;
2651 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
2652 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
2653 break;
2654 case AMDGPU_UCODE_ID_P2S_TABLE:
2655 *type = GFX_FW_TYPE_P2S_TABLE;
2656 break;
2657 case AMDGPU_UCODE_ID_JPEG_RAM:
2658 *type = GFX_FW_TYPE_JPEG_RAM;
2659 break;
2660 case AMDGPU_UCODE_ID_ISP:
2661 *type = GFX_FW_TYPE_ISP;
2662 break;
2663 case AMDGPU_UCODE_ID_MAXIMUM:
2664 default:
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669 }
2670
psp_print_fw_hdr(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2671 static void psp_print_fw_hdr(struct psp_context *psp,
2672 struct amdgpu_firmware_info *ucode)
2673 {
2674 struct amdgpu_device *adev = psp->adev;
2675 struct common_firmware_header *hdr;
2676
2677 switch (ucode->ucode_id) {
2678 case AMDGPU_UCODE_ID_SDMA0:
2679 case AMDGPU_UCODE_ID_SDMA1:
2680 case AMDGPU_UCODE_ID_SDMA2:
2681 case AMDGPU_UCODE_ID_SDMA3:
2682 case AMDGPU_UCODE_ID_SDMA4:
2683 case AMDGPU_UCODE_ID_SDMA5:
2684 case AMDGPU_UCODE_ID_SDMA6:
2685 case AMDGPU_UCODE_ID_SDMA7:
2686 hdr = (struct common_firmware_header *)
2687 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2688 amdgpu_ucode_print_sdma_hdr(hdr);
2689 break;
2690 case AMDGPU_UCODE_ID_CP_CE:
2691 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2692 amdgpu_ucode_print_gfx_hdr(hdr);
2693 break;
2694 case AMDGPU_UCODE_ID_CP_PFP:
2695 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2696 amdgpu_ucode_print_gfx_hdr(hdr);
2697 break;
2698 case AMDGPU_UCODE_ID_CP_ME:
2699 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2700 amdgpu_ucode_print_gfx_hdr(hdr);
2701 break;
2702 case AMDGPU_UCODE_ID_CP_MEC1:
2703 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2704 amdgpu_ucode_print_gfx_hdr(hdr);
2705 break;
2706 case AMDGPU_UCODE_ID_RLC_G:
2707 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2708 amdgpu_ucode_print_rlc_hdr(hdr);
2709 break;
2710 case AMDGPU_UCODE_ID_SMC:
2711 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2712 amdgpu_ucode_print_smc_hdr(hdr);
2713 break;
2714 default:
2715 break;
2716 }
2717 }
2718
psp_prep_load_ip_fw_cmd_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)2719 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp,
2720 struct amdgpu_firmware_info *ucode,
2721 struct psp_gfx_cmd_resp *cmd)
2722 {
2723 int ret;
2724 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2725
2726 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2727 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2728 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2729 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2730
2731 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2732 if (ret)
2733 dev_err(psp->adev->dev, "Unknown firmware type\n");
2734
2735 return ret;
2736 }
2737
psp_execute_ip_fw_load(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2738 int psp_execute_ip_fw_load(struct psp_context *psp,
2739 struct amdgpu_firmware_info *ucode)
2740 {
2741 int ret = 0;
2742 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2743
2744 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd);
2745 if (!ret) {
2746 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2747 psp->fence_buf_mc_addr);
2748 }
2749
2750 release_psp_cmd_buf(psp);
2751
2752 return ret;
2753 }
2754
psp_load_p2s_table(struct psp_context * psp)2755 static int psp_load_p2s_table(struct psp_context *psp)
2756 {
2757 int ret;
2758 struct amdgpu_device *adev = psp->adev;
2759 struct amdgpu_firmware_info *ucode =
2760 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
2761
2762 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2763 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))
2764 return 0;
2765
2766 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
2767 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
2768 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :
2769 0x0036003C;
2770 if (psp->sos.fw_version < supp_vers)
2771 return 0;
2772 }
2773
2774 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2775 return 0;
2776
2777 ret = psp_execute_ip_fw_load(psp, ucode);
2778
2779 return ret;
2780 }
2781
psp_load_smu_fw(struct psp_context * psp)2782 static int psp_load_smu_fw(struct psp_context *psp)
2783 {
2784 int ret;
2785 struct amdgpu_device *adev = psp->adev;
2786 struct amdgpu_firmware_info *ucode =
2787 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2788 struct amdgpu_ras *ras = psp->ras_context.ras;
2789
2790 /*
2791 * Skip SMU FW reloading in case of using BACO for runpm only,
2792 * as SMU is always alive.
2793 */
2794 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2795 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))
2796 return 0;
2797
2798 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2799 return 0;
2800
2801 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled &&
2802 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
2803 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) {
2804 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2805 if (ret)
2806 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n");
2807 }
2808
2809 ret = psp_execute_ip_fw_load(psp, ucode);
2810
2811 if (ret)
2812 dev_err(adev->dev, "PSP load smu failed!\n");
2813
2814 return ret;
2815 }
2816
fw_load_skip_check(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2817 static bool fw_load_skip_check(struct psp_context *psp,
2818 struct amdgpu_firmware_info *ucode)
2819 {
2820 if (!ucode->fw || !ucode->ucode_size)
2821 return true;
2822
2823 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE)
2824 return true;
2825
2826 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2827 (psp_smu_reload_quirk(psp) ||
2828 psp->autoload_supported ||
2829 psp->pmfw_centralized_cstate_management))
2830 return true;
2831
2832 if (amdgpu_sriov_vf(psp->adev) &&
2833 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2834 return true;
2835
2836 if (psp->autoload_supported &&
2837 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2838 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2839 /* skip mec JT when autoload is enabled */
2840 return true;
2841
2842 return false;
2843 }
2844
psp_load_fw_list(struct psp_context * psp,struct amdgpu_firmware_info ** ucode_list,int ucode_count)2845 int psp_load_fw_list(struct psp_context *psp,
2846 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2847 {
2848 int ret = 0, i;
2849 struct amdgpu_firmware_info *ucode;
2850
2851 for (i = 0; i < ucode_count; ++i) {
2852 ucode = ucode_list[i];
2853 psp_print_fw_hdr(psp, ucode);
2854 ret = psp_execute_ip_fw_load(psp, ucode);
2855 if (ret)
2856 return ret;
2857 }
2858 return ret;
2859 }
2860
psp_load_non_psp_fw(struct psp_context * psp)2861 static int psp_load_non_psp_fw(struct psp_context *psp)
2862 {
2863 int i, ret;
2864 struct amdgpu_firmware_info *ucode;
2865 struct amdgpu_device *adev = psp->adev;
2866
2867 if (psp->autoload_supported &&
2868 !psp->pmfw_centralized_cstate_management) {
2869 ret = psp_load_smu_fw(psp);
2870 if (ret)
2871 return ret;
2872 }
2873
2874 /* Load P2S table first if it's available */
2875 psp_load_p2s_table(psp);
2876
2877 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2878 ucode = &adev->firmware.ucode[i];
2879
2880 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2881 !fw_load_skip_check(psp, ucode)) {
2882 ret = psp_load_smu_fw(psp);
2883 if (ret)
2884 return ret;
2885 continue;
2886 }
2887
2888 if (fw_load_skip_check(psp, ucode))
2889 continue;
2890
2891 if (psp->autoload_supported &&
2892 (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2893 IP_VERSION(11, 0, 7) ||
2894 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2895 IP_VERSION(11, 0, 11) ||
2896 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2897 IP_VERSION(11, 0, 12)) &&
2898 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2899 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2900 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2901 /* PSP only receive one SDMA fw for sienna_cichlid,
2902 * as all four sdma fw are same
2903 */
2904 continue;
2905
2906 psp_print_fw_hdr(psp, ucode);
2907
2908 ret = psp_execute_ip_fw_load(psp, ucode);
2909 if (ret)
2910 return ret;
2911
2912 /* Start rlc autoload after psp received all the gfx firmware */
2913 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2914 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2915 ret = psp_rlc_autoload_start(psp);
2916 if (ret) {
2917 dev_err(adev->dev, "Failed to start rlc autoload\n");
2918 return ret;
2919 }
2920 }
2921 }
2922
2923 return 0;
2924 }
2925
psp_load_fw(struct amdgpu_device * adev)2926 static int psp_load_fw(struct amdgpu_device *adev)
2927 {
2928 int ret;
2929 struct psp_context *psp = &adev->psp;
2930
2931 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2932 /* should not destroy ring, only stop */
2933 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2934 } else {
2935 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2936
2937 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2938 if (ret) {
2939 dev_err(adev->dev, "PSP ring init failed!\n");
2940 goto failed;
2941 }
2942 }
2943
2944 ret = psp_hw_start(psp);
2945 if (ret)
2946 goto failed;
2947
2948 ret = psp_load_non_psp_fw(psp);
2949 if (ret)
2950 goto failed1;
2951
2952 ret = psp_asd_initialize(psp);
2953 if (ret) {
2954 dev_err(adev->dev, "PSP load asd failed!\n");
2955 goto failed1;
2956 }
2957
2958 ret = psp_rl_load(adev);
2959 if (ret) {
2960 dev_err(adev->dev, "PSP load RL failed!\n");
2961 goto failed1;
2962 }
2963
2964 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2965 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2966 ret = psp_xgmi_initialize(psp, false, true);
2967 /* Warning the XGMI seesion initialize failure
2968 * Instead of stop driver initialization
2969 */
2970 if (ret)
2971 dev_err(psp->adev->dev,
2972 "XGMI: Failed to initialize XGMI session\n");
2973 }
2974 }
2975
2976 if (psp->ta_fw) {
2977 ret = psp_ras_initialize(psp);
2978 if (ret)
2979 dev_err(psp->adev->dev,
2980 "RAS: Failed to initialize RAS\n");
2981
2982 ret = psp_hdcp_initialize(psp);
2983 if (ret)
2984 dev_err(psp->adev->dev,
2985 "HDCP: Failed to initialize HDCP\n");
2986
2987 ret = psp_dtm_initialize(psp);
2988 if (ret)
2989 dev_err(psp->adev->dev,
2990 "DTM: Failed to initialize DTM\n");
2991
2992 ret = psp_rap_initialize(psp);
2993 if (ret)
2994 dev_err(psp->adev->dev,
2995 "RAP: Failed to initialize RAP\n");
2996
2997 ret = psp_securedisplay_initialize(psp);
2998 if (ret)
2999 dev_err(psp->adev->dev,
3000 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
3001 }
3002
3003 return 0;
3004
3005 failed1:
3006 psp_free_shared_bufs(psp);
3007 failed:
3008 /*
3009 * all cleanup jobs (xgmi terminate, ras terminate,
3010 * ring destroy, cmd/fence/fw buffers destory,
3011 * psp->cmd destory) are delayed to psp_hw_fini
3012 */
3013 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
3014 return ret;
3015 }
3016
psp_hw_init(struct amdgpu_ip_block * ip_block)3017 static int psp_hw_init(struct amdgpu_ip_block *ip_block)
3018 {
3019 int ret;
3020 struct amdgpu_device *adev = ip_block->adev;
3021
3022 mutex_lock(&adev->firmware.mutex);
3023
3024 ret = amdgpu_ucode_init_bo(adev);
3025 if (ret)
3026 goto failed;
3027
3028 ret = psp_load_fw(adev);
3029 if (ret) {
3030 dev_err(adev->dev, "PSP firmware loading failed\n");
3031 goto failed;
3032 }
3033
3034 mutex_unlock(&adev->firmware.mutex);
3035 return 0;
3036
3037 failed:
3038 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
3039 mutex_unlock(&adev->firmware.mutex);
3040 return -EINVAL;
3041 }
3042
psp_hw_fini(struct amdgpu_ip_block * ip_block)3043 static int psp_hw_fini(struct amdgpu_ip_block *ip_block)
3044 {
3045 struct amdgpu_device *adev = ip_block->adev;
3046 struct psp_context *psp = &adev->psp;
3047
3048 if (psp->ta_fw) {
3049 psp_ras_terminate(psp);
3050 psp_securedisplay_terminate(psp);
3051 psp_rap_terminate(psp);
3052 psp_dtm_terminate(psp);
3053 psp_hdcp_terminate(psp);
3054
3055 if (adev->gmc.xgmi.num_physical_nodes > 1)
3056 psp_xgmi_terminate(psp);
3057 }
3058
3059 psp_asd_terminate(psp);
3060 psp_tmr_terminate(psp);
3061
3062 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
3063
3064 return 0;
3065 }
3066
psp_suspend(struct amdgpu_ip_block * ip_block)3067 static int psp_suspend(struct amdgpu_ip_block *ip_block)
3068 {
3069 int ret = 0;
3070 struct amdgpu_device *adev = ip_block->adev;
3071 struct psp_context *psp = &adev->psp;
3072
3073 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
3074 psp->xgmi_context.context.initialized) {
3075 ret = psp_xgmi_terminate(psp);
3076 if (ret) {
3077 dev_err(adev->dev, "Failed to terminate xgmi ta\n");
3078 goto out;
3079 }
3080 }
3081
3082 if (psp->ta_fw) {
3083 ret = psp_ras_terminate(psp);
3084 if (ret) {
3085 dev_err(adev->dev, "Failed to terminate ras ta\n");
3086 goto out;
3087 }
3088 ret = psp_hdcp_terminate(psp);
3089 if (ret) {
3090 dev_err(adev->dev, "Failed to terminate hdcp ta\n");
3091 goto out;
3092 }
3093 ret = psp_dtm_terminate(psp);
3094 if (ret) {
3095 dev_err(adev->dev, "Failed to terminate dtm ta\n");
3096 goto out;
3097 }
3098 ret = psp_rap_terminate(psp);
3099 if (ret) {
3100 dev_err(adev->dev, "Failed to terminate rap ta\n");
3101 goto out;
3102 }
3103 ret = psp_securedisplay_terminate(psp);
3104 if (ret) {
3105 dev_err(adev->dev, "Failed to terminate securedisplay ta\n");
3106 goto out;
3107 }
3108 }
3109
3110 ret = psp_asd_terminate(psp);
3111 if (ret) {
3112 dev_err(adev->dev, "Failed to terminate asd\n");
3113 goto out;
3114 }
3115
3116 ret = psp_tmr_terminate(psp);
3117 if (ret) {
3118 dev_err(adev->dev, "Failed to terminate tmr\n");
3119 goto out;
3120 }
3121
3122 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
3123 if (ret)
3124 dev_err(adev->dev, "PSP ring stop failed\n");
3125
3126 out:
3127 return ret;
3128 }
3129
psp_resume(struct amdgpu_ip_block * ip_block)3130 static int psp_resume(struct amdgpu_ip_block *ip_block)
3131 {
3132 int ret;
3133 struct amdgpu_device *adev = ip_block->adev;
3134 struct psp_context *psp = &adev->psp;
3135
3136 dev_info(adev->dev, "PSP is resuming...\n");
3137
3138 if (psp->mem_train_ctx.enable_mem_training) {
3139 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
3140 if (ret) {
3141 dev_err(adev->dev, "Failed to process memory training!\n");
3142 return ret;
3143 }
3144 }
3145
3146 mutex_lock(&adev->firmware.mutex);
3147
3148 ret = amdgpu_ucode_init_bo(adev);
3149 if (ret)
3150 goto failed;
3151
3152 ret = psp_hw_start(psp);
3153 if (ret)
3154 goto failed;
3155
3156 ret = psp_load_non_psp_fw(psp);
3157 if (ret)
3158 goto failed;
3159
3160 ret = psp_asd_initialize(psp);
3161 if (ret) {
3162 dev_err(adev->dev, "PSP load asd failed!\n");
3163 goto failed;
3164 }
3165
3166 ret = psp_rl_load(adev);
3167 if (ret) {
3168 dev_err(adev->dev, "PSP load RL failed!\n");
3169 goto failed;
3170 }
3171
3172 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3173 ret = psp_xgmi_initialize(psp, false, true);
3174 /* Warning the XGMI seesion initialize failure
3175 * Instead of stop driver initialization
3176 */
3177 if (ret)
3178 dev_err(psp->adev->dev,
3179 "XGMI: Failed to initialize XGMI session\n");
3180 }
3181
3182 if (psp->ta_fw) {
3183 ret = psp_ras_initialize(psp);
3184 if (ret)
3185 dev_err(psp->adev->dev,
3186 "RAS: Failed to initialize RAS\n");
3187
3188 ret = psp_hdcp_initialize(psp);
3189 if (ret)
3190 dev_err(psp->adev->dev,
3191 "HDCP: Failed to initialize HDCP\n");
3192
3193 ret = psp_dtm_initialize(psp);
3194 if (ret)
3195 dev_err(psp->adev->dev,
3196 "DTM: Failed to initialize DTM\n");
3197
3198 ret = psp_rap_initialize(psp);
3199 if (ret)
3200 dev_err(psp->adev->dev,
3201 "RAP: Failed to initialize RAP\n");
3202
3203 ret = psp_securedisplay_initialize(psp);
3204 if (ret)
3205 dev_err(psp->adev->dev,
3206 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
3207 }
3208
3209 mutex_unlock(&adev->firmware.mutex);
3210
3211 return 0;
3212
3213 failed:
3214 dev_err(adev->dev, "PSP resume failed\n");
3215 mutex_unlock(&adev->firmware.mutex);
3216 return ret;
3217 }
3218
psp_gpu_reset(struct amdgpu_device * adev)3219 int psp_gpu_reset(struct amdgpu_device *adev)
3220 {
3221 int ret;
3222
3223 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
3224 return 0;
3225
3226 mutex_lock(&adev->psp.mutex);
3227 ret = psp_mode1_reset(&adev->psp);
3228 mutex_unlock(&adev->psp.mutex);
3229
3230 return ret;
3231 }
3232
psp_rlc_autoload_start(struct psp_context * psp)3233 int psp_rlc_autoload_start(struct psp_context *psp)
3234 {
3235 int ret;
3236 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
3237
3238 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
3239
3240 ret = psp_cmd_submit_buf(psp, NULL, cmd,
3241 psp->fence_buf_mc_addr);
3242
3243 release_psp_cmd_buf(psp);
3244
3245 return ret;
3246 }
3247
psp_ring_cmd_submit(struct psp_context * psp,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)3248 int psp_ring_cmd_submit(struct psp_context *psp,
3249 uint64_t cmd_buf_mc_addr,
3250 uint64_t fence_mc_addr,
3251 int index)
3252 {
3253 unsigned int psp_write_ptr_reg = 0;
3254 struct psp_gfx_rb_frame *write_frame;
3255 struct psp_ring *ring = &psp->km_ring;
3256 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
3257 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
3258 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
3259 struct amdgpu_device *adev = psp->adev;
3260 uint32_t ring_size_dw = ring->ring_size / 4;
3261 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
3262
3263 /* KM (GPCOM) prepare write pointer */
3264 psp_write_ptr_reg = psp_ring_get_wptr(psp);
3265
3266 /* Update KM RB frame pointer to new frame */
3267 /* write_frame ptr increments by size of rb_frame in bytes */
3268 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
3269 if ((psp_write_ptr_reg % ring_size_dw) == 0)
3270 write_frame = ring_buffer_start;
3271 else
3272 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
3273 /* Check invalid write_frame ptr address */
3274 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
3275 dev_err(adev->dev,
3276 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
3277 ring_buffer_start, ring_buffer_end, write_frame);
3278 dev_err(adev->dev,
3279 "write_frame is pointing to address out of bounds\n");
3280 return -EINVAL;
3281 }
3282
3283 /* Initialize KM RB frame */
3284 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
3285
3286 /* Update KM RB frame */
3287 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3288 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3289 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3290 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3291 write_frame->fence_value = index;
3292 amdgpu_device_flush_hdp(adev, NULL);
3293
3294 /* Update the write Pointer in DWORDs */
3295 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3296 psp_ring_set_wptr(psp, psp_write_ptr_reg);
3297 return 0;
3298 }
3299
psp_init_asd_microcode(struct psp_context * psp,const char * chip_name)3300 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
3301 {
3302 struct amdgpu_device *adev = psp->adev;
3303 const struct psp_firmware_header_v1_0 *asd_hdr;
3304 int err = 0;
3305
3306 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED,
3307 "amdgpu/%s_asd.bin", chip_name);
3308 if (err)
3309 goto out;
3310
3311 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3312 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3313 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3314 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3315 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3316 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3317 return 0;
3318 out:
3319 amdgpu_ucode_release(&adev->psp.asd_fw);
3320 return err;
3321 }
3322
psp_init_toc_microcode(struct psp_context * psp,const char * chip_name)3323 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3324 {
3325 struct amdgpu_device *adev = psp->adev;
3326 const struct psp_firmware_header_v1_0 *toc_hdr;
3327 int err = 0;
3328
3329 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
3330 "amdgpu/%s_toc.bin", chip_name);
3331 if (err)
3332 goto out;
3333
3334 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3335 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3336 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3337 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3338 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3339 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3340 return 0;
3341 out:
3342 amdgpu_ucode_release(&adev->psp.toc_fw);
3343 return err;
3344 }
3345
parse_sos_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct psp_firmware_header_v2_0 * sos_hdr)3346 static int parse_sos_bin_descriptor(struct psp_context *psp,
3347 const struct psp_fw_bin_desc *desc,
3348 const struct psp_firmware_header_v2_0 *sos_hdr)
3349 {
3350 uint8_t *ucode_start_addr = NULL;
3351
3352 if (!psp || !desc || !sos_hdr)
3353 return -EINVAL;
3354
3355 ucode_start_addr = (uint8_t *)sos_hdr +
3356 le32_to_cpu(desc->offset_bytes) +
3357 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3358
3359 switch (desc->fw_type) {
3360 case PSP_FW_TYPE_PSP_SOS:
3361 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3362 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3363 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3364 psp->sos.start_addr = ucode_start_addr;
3365 break;
3366 case PSP_FW_TYPE_PSP_SYS_DRV:
3367 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3368 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3369 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3370 psp->sys.start_addr = ucode_start_addr;
3371 break;
3372 case PSP_FW_TYPE_PSP_KDB:
3373 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3374 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3375 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3376 psp->kdb.start_addr = ucode_start_addr;
3377 break;
3378 case PSP_FW_TYPE_PSP_TOC:
3379 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3380 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3381 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3382 psp->toc.start_addr = ucode_start_addr;
3383 break;
3384 case PSP_FW_TYPE_PSP_SPL:
3385 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3386 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3387 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3388 psp->spl.start_addr = ucode_start_addr;
3389 break;
3390 case PSP_FW_TYPE_PSP_RL:
3391 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3392 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3393 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3394 psp->rl.start_addr = ucode_start_addr;
3395 break;
3396 case PSP_FW_TYPE_PSP_SOC_DRV:
3397 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3398 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3399 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3400 psp->soc_drv.start_addr = ucode_start_addr;
3401 break;
3402 case PSP_FW_TYPE_PSP_INTF_DRV:
3403 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3404 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3405 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3406 psp->intf_drv.start_addr = ucode_start_addr;
3407 break;
3408 case PSP_FW_TYPE_PSP_DBG_DRV:
3409 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3410 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3411 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3412 psp->dbg_drv.start_addr = ucode_start_addr;
3413 break;
3414 case PSP_FW_TYPE_PSP_RAS_DRV:
3415 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3416 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3417 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3418 psp->ras_drv.start_addr = ucode_start_addr;
3419 break;
3420 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV:
3421 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version);
3422 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version);
3423 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3424 psp->ipkeymgr_drv.start_addr = ucode_start_addr;
3425 break;
3426 case PSP_FW_TYPE_PSP_SPDM_DRV:
3427 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version);
3428 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version);
3429 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3430 psp->spdm_drv.start_addr = ucode_start_addr;
3431 break;
3432 default:
3433 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3434 break;
3435 }
3436
3437 return 0;
3438 }
3439
psp_init_sos_base_fw(struct amdgpu_device * adev)3440 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3441 {
3442 const struct psp_firmware_header_v1_0 *sos_hdr;
3443 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3444 uint8_t *ucode_array_start_addr;
3445
3446 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3447 ucode_array_start_addr = (uint8_t *)sos_hdr +
3448 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3449
3450 if (adev->gmc.xgmi.connected_to_cpu ||
3451 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) {
3452 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3453 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3454
3455 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3456 adev->psp.sys.start_addr = ucode_array_start_addr;
3457
3458 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3459 adev->psp.sos.start_addr = ucode_array_start_addr +
3460 le32_to_cpu(sos_hdr->sos.offset_bytes);
3461 } else {
3462 /* Load alternate PSP SOS FW */
3463 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3464
3465 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3466 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3467
3468 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3469 adev->psp.sys.start_addr = ucode_array_start_addr +
3470 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3471
3472 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3473 adev->psp.sos.start_addr = ucode_array_start_addr +
3474 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3475 }
3476
3477 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3478 dev_warn(adev->dev, "PSP SOS FW not available");
3479 return -EINVAL;
3480 }
3481
3482 return 0;
3483 }
3484
psp_init_sos_microcode(struct psp_context * psp,const char * chip_name)3485 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3486 {
3487 struct amdgpu_device *adev = psp->adev;
3488 const struct psp_firmware_header_v1_0 *sos_hdr;
3489 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3490 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3491 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3492 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3493 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1;
3494 int fw_index, fw_bin_count, start_index = 0;
3495 const struct psp_fw_bin_desc *fw_bin;
3496 uint8_t *ucode_array_start_addr;
3497 int err = 0;
3498
3499 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
3500 "amdgpu/%s_sos.bin", chip_name);
3501 if (err)
3502 goto out;
3503
3504 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3505 ucode_array_start_addr = (uint8_t *)sos_hdr +
3506 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3507 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3508
3509 switch (sos_hdr->header.header_version_major) {
3510 case 1:
3511 err = psp_init_sos_base_fw(adev);
3512 if (err)
3513 goto out;
3514
3515 if (sos_hdr->header.header_version_minor == 1) {
3516 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3517 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3518 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3519 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3520 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3521 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3522 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3523 }
3524 if (sos_hdr->header.header_version_minor == 2) {
3525 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3526 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3527 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3528 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3529 }
3530 if (sos_hdr->header.header_version_minor == 3) {
3531 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3532 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3533 adev->psp.toc.start_addr = ucode_array_start_addr +
3534 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3535 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3536 adev->psp.kdb.start_addr = ucode_array_start_addr +
3537 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3538 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3539 adev->psp.spl.start_addr = ucode_array_start_addr +
3540 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3541 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3542 adev->psp.rl.start_addr = ucode_array_start_addr +
3543 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3544 }
3545 break;
3546 case 2:
3547 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3548
3549 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count);
3550
3551 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) {
3552 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3553 err = -EINVAL;
3554 goto out;
3555 }
3556
3557 if (sos_hdr_v2_0->header.header_version_minor == 1) {
3558 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data;
3559
3560 fw_bin = sos_hdr_v2_1->psp_fw_bin;
3561
3562 if (psp_is_aux_sos_load_required(psp))
3563 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index);
3564 else
3565 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index);
3566
3567 } else {
3568 fw_bin = sos_hdr_v2_0->psp_fw_bin;
3569 }
3570
3571 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) {
3572 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index,
3573 sos_hdr_v2_0);
3574 if (err)
3575 goto out;
3576 }
3577 break;
3578 default:
3579 dev_err(adev->dev,
3580 "unsupported psp sos firmware\n");
3581 err = -EINVAL;
3582 goto out;
3583 }
3584
3585 return 0;
3586 out:
3587 amdgpu_ucode_release(&adev->psp.sos_fw);
3588
3589 return err;
3590 }
3591
is_ta_fw_applicable(struct psp_context * psp,const struct psp_fw_bin_desc * desc)3592 static bool is_ta_fw_applicable(struct psp_context *psp,
3593 const struct psp_fw_bin_desc *desc)
3594 {
3595 struct amdgpu_device *adev = psp->adev;
3596 uint32_t fw_version;
3597
3598 switch (desc->fw_type) {
3599 case TA_FW_TYPE_PSP_XGMI:
3600 case TA_FW_TYPE_PSP_XGMI_AUX:
3601 /* for now, AUX TA only exists on 13.0.6 ta bin,
3602 * from v20.00.0x.14
3603 */
3604 if (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3605 IP_VERSION(13, 0, 6)) {
3606 fw_version = le32_to_cpu(desc->fw_version);
3607
3608 if (adev->flags & AMD_IS_APU &&
3609 (fw_version & 0xff) >= 0x14)
3610 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX;
3611 else
3612 return desc->fw_type == TA_FW_TYPE_PSP_XGMI;
3613 }
3614 break;
3615 default:
3616 break;
3617 }
3618
3619 return true;
3620 }
3621
parse_ta_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct ta_firmware_header_v2_0 * ta_hdr)3622 static int parse_ta_bin_descriptor(struct psp_context *psp,
3623 const struct psp_fw_bin_desc *desc,
3624 const struct ta_firmware_header_v2_0 *ta_hdr)
3625 {
3626 uint8_t *ucode_start_addr = NULL;
3627
3628 if (!psp || !desc || !ta_hdr)
3629 return -EINVAL;
3630
3631 if (!is_ta_fw_applicable(psp, desc))
3632 return 0;
3633
3634 ucode_start_addr = (uint8_t *)ta_hdr +
3635 le32_to_cpu(desc->offset_bytes) +
3636 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3637
3638 switch (desc->fw_type) {
3639 case TA_FW_TYPE_PSP_ASD:
3640 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3641 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3642 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3643 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3644 break;
3645 case TA_FW_TYPE_PSP_XGMI:
3646 case TA_FW_TYPE_PSP_XGMI_AUX:
3647 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3648 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3649 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3650 break;
3651 case TA_FW_TYPE_PSP_RAS:
3652 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3653 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3654 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3655 break;
3656 case TA_FW_TYPE_PSP_HDCP:
3657 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3658 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3659 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3660 break;
3661 case TA_FW_TYPE_PSP_DTM:
3662 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3663 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3664 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3665 break;
3666 case TA_FW_TYPE_PSP_RAP:
3667 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3668 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3669 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3670 break;
3671 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3672 psp->securedisplay_context.context.bin_desc.fw_version =
3673 le32_to_cpu(desc->fw_version);
3674 psp->securedisplay_context.context.bin_desc.size_bytes =
3675 le32_to_cpu(desc->size_bytes);
3676 psp->securedisplay_context.context.bin_desc.start_addr =
3677 ucode_start_addr;
3678 break;
3679 default:
3680 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3681 break;
3682 }
3683
3684 return 0;
3685 }
3686
parse_ta_v1_microcode(struct psp_context * psp)3687 static int parse_ta_v1_microcode(struct psp_context *psp)
3688 {
3689 const struct ta_firmware_header_v1_0 *ta_hdr;
3690 struct amdgpu_device *adev = psp->adev;
3691
3692 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3693
3694 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3695 return -EINVAL;
3696
3697 adev->psp.xgmi_context.context.bin_desc.fw_version =
3698 le32_to_cpu(ta_hdr->xgmi.fw_version);
3699 adev->psp.xgmi_context.context.bin_desc.size_bytes =
3700 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3701 adev->psp.xgmi_context.context.bin_desc.start_addr =
3702 (uint8_t *)ta_hdr +
3703 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3704
3705 adev->psp.ras_context.context.bin_desc.fw_version =
3706 le32_to_cpu(ta_hdr->ras.fw_version);
3707 adev->psp.ras_context.context.bin_desc.size_bytes =
3708 le32_to_cpu(ta_hdr->ras.size_bytes);
3709 adev->psp.ras_context.context.bin_desc.start_addr =
3710 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3711 le32_to_cpu(ta_hdr->ras.offset_bytes);
3712
3713 adev->psp.hdcp_context.context.bin_desc.fw_version =
3714 le32_to_cpu(ta_hdr->hdcp.fw_version);
3715 adev->psp.hdcp_context.context.bin_desc.size_bytes =
3716 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3717 adev->psp.hdcp_context.context.bin_desc.start_addr =
3718 (uint8_t *)ta_hdr +
3719 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3720
3721 adev->psp.dtm_context.context.bin_desc.fw_version =
3722 le32_to_cpu(ta_hdr->dtm.fw_version);
3723 adev->psp.dtm_context.context.bin_desc.size_bytes =
3724 le32_to_cpu(ta_hdr->dtm.size_bytes);
3725 adev->psp.dtm_context.context.bin_desc.start_addr =
3726 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3727 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3728
3729 adev->psp.securedisplay_context.context.bin_desc.fw_version =
3730 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3731 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3732 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3733 adev->psp.securedisplay_context.context.bin_desc.start_addr =
3734 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3735 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3736
3737 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3738
3739 return 0;
3740 }
3741
parse_ta_v2_microcode(struct psp_context * psp)3742 static int parse_ta_v2_microcode(struct psp_context *psp)
3743 {
3744 const struct ta_firmware_header_v2_0 *ta_hdr;
3745 struct amdgpu_device *adev = psp->adev;
3746 int err = 0;
3747 int ta_index = 0;
3748
3749 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3750
3751 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3752 return -EINVAL;
3753
3754 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3755 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3756 return -EINVAL;
3757 }
3758
3759 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3760 err = parse_ta_bin_descriptor(psp,
3761 &ta_hdr->ta_fw_bin[ta_index],
3762 ta_hdr);
3763 if (err)
3764 return err;
3765 }
3766
3767 return 0;
3768 }
3769
psp_init_ta_microcode(struct psp_context * psp,const char * chip_name)3770 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3771 {
3772 const struct common_firmware_header *hdr;
3773 struct amdgpu_device *adev = psp->adev;
3774 int err;
3775
3776 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
3777 "amdgpu/%s_ta.bin", chip_name);
3778 if (err)
3779 return err;
3780
3781 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3782 switch (le16_to_cpu(hdr->header_version_major)) {
3783 case 1:
3784 err = parse_ta_v1_microcode(psp);
3785 break;
3786 case 2:
3787 err = parse_ta_v2_microcode(psp);
3788 break;
3789 default:
3790 dev_err(adev->dev, "unsupported TA header version\n");
3791 err = -EINVAL;
3792 }
3793
3794 if (err)
3795 amdgpu_ucode_release(&adev->psp.ta_fw);
3796
3797 return err;
3798 }
3799
psp_init_cap_microcode(struct psp_context * psp,const char * chip_name)3800 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3801 {
3802 struct amdgpu_device *adev = psp->adev;
3803 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3804 struct amdgpu_firmware_info *info = NULL;
3805 int err = 0;
3806
3807 if (!amdgpu_sriov_vf(adev)) {
3808 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3809 return -EINVAL;
3810 }
3811
3812 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL,
3813 "amdgpu/%s_cap.bin", chip_name);
3814 if (err) {
3815 if (err == -ENODEV) {
3816 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3817 err = 0;
3818 } else {
3819 dev_err(adev->dev, "fail to initialize cap microcode\n");
3820 }
3821 goto out;
3822 }
3823
3824 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3825 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3826 info->fw = adev->psp.cap_fw;
3827 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3828 adev->psp.cap_fw->data;
3829 adev->firmware.fw_size += ALIGN(
3830 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3831 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3832 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3833 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3834
3835 return 0;
3836
3837 out:
3838 amdgpu_ucode_release(&adev->psp.cap_fw);
3839 return err;
3840 }
3841
psp_config_sq_perfmon(struct psp_context * psp,uint32_t xcp_id,bool core_override_enable,bool reg_override_enable,bool perfmon_override_enable)3842 int psp_config_sq_perfmon(struct psp_context *psp,
3843 uint32_t xcp_id, bool core_override_enable,
3844 bool reg_override_enable, bool perfmon_override_enable)
3845 {
3846 int ret;
3847
3848 if (amdgpu_sriov_vf(psp->adev))
3849 return 0;
3850
3851 if (xcp_id > MAX_XCP) {
3852 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id);
3853 return -EINVAL;
3854 }
3855
3856 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) {
3857 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n",
3858 amdgpu_ip_version(psp->adev, MP0_HWIP, 0));
3859 return -EINVAL;
3860 }
3861 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
3862
3863 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON;
3864 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id);
3865 cmd->cmd.config_sq_perfmon.core_override = core_override_enable;
3866 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable;
3867 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable;
3868
3869 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
3870 if (ret)
3871 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n",
3872 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable);
3873
3874 release_psp_cmd_buf(psp);
3875 return ret;
3876 }
3877
psp_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)3878 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
3879 enum amd_clockgating_state state)
3880 {
3881 return 0;
3882 }
3883
psp_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)3884 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
3885 enum amd_powergating_state state)
3886 {
3887 return 0;
3888 }
3889
psp_usbc_pd_fw_sysfs_read(struct device * dev,struct device_attribute * attr,char * buf)3890 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3891 struct device_attribute *attr,
3892 char *buf)
3893 {
3894 struct drm_device *ddev = dev_get_drvdata(dev);
3895 struct amdgpu_device *adev = drm_to_adev(ddev);
3896 struct amdgpu_ip_block *ip_block;
3897 uint32_t fw_ver;
3898 int ret;
3899
3900 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);
3901 if (!ip_block || !ip_block->status.late_initialized) {
3902 dev_info(adev->dev, "PSP block is not ready yet\n.");
3903 return -EBUSY;
3904 }
3905
3906 mutex_lock(&adev->psp.mutex);
3907 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3908 mutex_unlock(&adev->psp.mutex);
3909
3910 if (ret) {
3911 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret);
3912 return ret;
3913 }
3914
3915 return sysfs_emit(buf, "%x\n", fw_ver);
3916 }
3917
psp_usbc_pd_fw_sysfs_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3918 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3919 struct device_attribute *attr,
3920 const char *buf,
3921 size_t count)
3922 {
3923 struct drm_device *ddev = dev_get_drvdata(dev);
3924 struct amdgpu_device *adev = drm_to_adev(ddev);
3925 int ret, idx;
3926 const struct firmware *usbc_pd_fw;
3927 struct amdgpu_bo *fw_buf_bo = NULL;
3928 uint64_t fw_pri_mc_addr;
3929 void *fw_pri_cpu_addr;
3930 struct amdgpu_ip_block *ip_block;
3931
3932 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);
3933 if (!ip_block || !ip_block->status.late_initialized) {
3934 dev_err(adev->dev, "PSP block is not ready yet.");
3935 return -EBUSY;
3936 }
3937
3938 if (!drm_dev_enter(ddev, &idx))
3939 return -ENODEV;
3940
3941 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED,
3942 "amdgpu/%s", buf);
3943 if (ret)
3944 goto fail;
3945
3946 /* LFB address which is aligned to 1MB boundary per PSP request */
3947 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3948 AMDGPU_GEM_DOMAIN_VRAM |
3949 AMDGPU_GEM_DOMAIN_GTT,
3950 &fw_buf_bo, &fw_pri_mc_addr,
3951 &fw_pri_cpu_addr);
3952 if (ret)
3953 goto rel_buf;
3954
3955 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3956
3957 mutex_lock(&adev->psp.mutex);
3958 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3959 mutex_unlock(&adev->psp.mutex);
3960
3961 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3962
3963 rel_buf:
3964 amdgpu_ucode_release(&usbc_pd_fw);
3965 fail:
3966 if (ret) {
3967 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret);
3968 count = ret;
3969 }
3970
3971 drm_dev_exit(idx);
3972 return count;
3973 }
3974
psp_copy_fw(struct psp_context * psp,uint8_t * start_addr,uint32_t bin_size)3975 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3976 {
3977 int idx;
3978
3979 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3980 return;
3981
3982 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3983 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3984
3985 drm_dev_exit(idx);
3986 }
3987
3988 /**
3989 * DOC: usbc_pd_fw
3990 * Reading from this file will retrieve the USB-C PD firmware version. Writing to
3991 * this file will trigger the update process.
3992 */
3993 static DEVICE_ATTR(usbc_pd_fw, 0644,
3994 psp_usbc_pd_fw_sysfs_read,
3995 psp_usbc_pd_fw_sysfs_write);
3996
is_psp_fw_valid(struct psp_bin_desc bin)3997 int is_psp_fw_valid(struct psp_bin_desc bin)
3998 {
3999 return bin.size_bytes;
4000 }
4001
amdgpu_psp_vbflash_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)4002 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
4003 struct bin_attribute *bin_attr,
4004 char *buffer, loff_t pos, size_t count)
4005 {
4006 struct device *dev = kobj_to_dev(kobj);
4007 struct drm_device *ddev = dev_get_drvdata(dev);
4008 struct amdgpu_device *adev = drm_to_adev(ddev);
4009
4010 adev->psp.vbflash_done = false;
4011
4012 /* Safeguard against memory drain */
4013 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
4014 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B);
4015 kvfree(adev->psp.vbflash_tmp_buf);
4016 adev->psp.vbflash_tmp_buf = NULL;
4017 adev->psp.vbflash_image_size = 0;
4018 return -ENOMEM;
4019 }
4020
4021 /* TODO Just allocate max for now and optimize to realloc later if needed */
4022 if (!adev->psp.vbflash_tmp_buf) {
4023 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
4024 if (!adev->psp.vbflash_tmp_buf)
4025 return -ENOMEM;
4026 }
4027
4028 mutex_lock(&adev->psp.mutex);
4029 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
4030 adev->psp.vbflash_image_size += count;
4031 mutex_unlock(&adev->psp.mutex);
4032
4033 dev_dbg(adev->dev, "IFWI staged for update\n");
4034
4035 return count;
4036 }
4037
amdgpu_psp_vbflash_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)4038 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
4039 struct bin_attribute *bin_attr, char *buffer,
4040 loff_t pos, size_t count)
4041 {
4042 struct device *dev = kobj_to_dev(kobj);
4043 struct drm_device *ddev = dev_get_drvdata(dev);
4044 struct amdgpu_device *adev = drm_to_adev(ddev);
4045 struct amdgpu_bo *fw_buf_bo = NULL;
4046 uint64_t fw_pri_mc_addr;
4047 void *fw_pri_cpu_addr;
4048 int ret;
4049
4050 if (adev->psp.vbflash_image_size == 0)
4051 return -EINVAL;
4052
4053 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n");
4054
4055 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
4056 AMDGPU_GPU_PAGE_SIZE,
4057 AMDGPU_GEM_DOMAIN_VRAM,
4058 &fw_buf_bo,
4059 &fw_pri_mc_addr,
4060 &fw_pri_cpu_addr);
4061 if (ret)
4062 goto rel_buf;
4063
4064 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
4065
4066 mutex_lock(&adev->psp.mutex);
4067 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
4068 mutex_unlock(&adev->psp.mutex);
4069
4070 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
4071
4072 rel_buf:
4073 kvfree(adev->psp.vbflash_tmp_buf);
4074 adev->psp.vbflash_tmp_buf = NULL;
4075 adev->psp.vbflash_image_size = 0;
4076
4077 if (ret) {
4078 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret);
4079 return ret;
4080 }
4081
4082 dev_dbg(adev->dev, "PSP IFWI flash process done\n");
4083 return 0;
4084 }
4085
4086 /**
4087 * DOC: psp_vbflash
4088 * Writing to this file will stage an IFWI for update. Reading from this file
4089 * will trigger the update process.
4090 */
4091 static struct bin_attribute psp_vbflash_bin_attr = {
4092 .attr = {.name = "psp_vbflash", .mode = 0660},
4093 .size = 0,
4094 .write = amdgpu_psp_vbflash_write,
4095 .read = amdgpu_psp_vbflash_read,
4096 };
4097
4098 /**
4099 * DOC: psp_vbflash_status
4100 * The status of the flash process.
4101 * 0: IFWI flash not complete.
4102 * 1: IFWI flash complete.
4103 */
amdgpu_psp_vbflash_status(struct device * dev,struct device_attribute * attr,char * buf)4104 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
4105 struct device_attribute *attr,
4106 char *buf)
4107 {
4108 struct drm_device *ddev = dev_get_drvdata(dev);
4109 struct amdgpu_device *adev = drm_to_adev(ddev);
4110 uint32_t vbflash_status;
4111
4112 vbflash_status = psp_vbflash_status(&adev->psp);
4113 if (!adev->psp.vbflash_done)
4114 vbflash_status = 0;
4115 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
4116 vbflash_status = 1;
4117
4118 return sysfs_emit(buf, "0x%x\n", vbflash_status);
4119 }
4120 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
4121
4122 static struct bin_attribute *bin_flash_attrs[] = {
4123 &psp_vbflash_bin_attr,
4124 NULL
4125 };
4126
4127 static struct attribute *flash_attrs[] = {
4128 &dev_attr_psp_vbflash_status.attr,
4129 &dev_attr_usbc_pd_fw.attr,
4130 NULL
4131 };
4132
amdgpu_flash_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)4133 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
4134 {
4135 struct device *dev = kobj_to_dev(kobj);
4136 struct drm_device *ddev = dev_get_drvdata(dev);
4137 struct amdgpu_device *adev = drm_to_adev(ddev);
4138
4139 if (attr == &dev_attr_usbc_pd_fw.attr)
4140 return adev->psp.sup_pd_fw_up ? 0660 : 0;
4141
4142 return adev->psp.sup_ifwi_up ? 0440 : 0;
4143 }
4144
amdgpu_bin_flash_attr_is_visible(struct kobject * kobj,const struct bin_attribute * attr,int idx)4145 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
4146 const struct bin_attribute *attr,
4147 int idx)
4148 {
4149 struct device *dev = kobj_to_dev(kobj);
4150 struct drm_device *ddev = dev_get_drvdata(dev);
4151 struct amdgpu_device *adev = drm_to_adev(ddev);
4152
4153 return adev->psp.sup_ifwi_up ? 0660 : 0;
4154 }
4155
4156 const struct attribute_group amdgpu_flash_attr_group = {
4157 .attrs = flash_attrs,
4158 .bin_attrs = bin_flash_attrs,
4159 .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
4160 .is_visible = amdgpu_flash_attr_is_visible,
4161 };
4162
4163 const struct amd_ip_funcs psp_ip_funcs = {
4164 .name = "psp",
4165 .early_init = psp_early_init,
4166 .sw_init = psp_sw_init,
4167 .sw_fini = psp_sw_fini,
4168 .hw_init = psp_hw_init,
4169 .hw_fini = psp_hw_fini,
4170 .suspend = psp_suspend,
4171 .resume = psp_resume,
4172 .set_clockgating_state = psp_set_clockgating_state,
4173 .set_powergating_state = psp_set_powergating_state,
4174 };
4175
4176 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
4177 .type = AMD_IP_BLOCK_TYPE_PSP,
4178 .major = 3,
4179 .minor = 1,
4180 .rev = 0,
4181 .funcs = &psp_ip_funcs,
4182 };
4183
4184 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
4185 .type = AMD_IP_BLOCK_TYPE_PSP,
4186 .major = 10,
4187 .minor = 0,
4188 .rev = 0,
4189 .funcs = &psp_ip_funcs,
4190 };
4191
4192 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
4193 .type = AMD_IP_BLOCK_TYPE_PSP,
4194 .major = 11,
4195 .minor = 0,
4196 .rev = 0,
4197 .funcs = &psp_ip_funcs,
4198 };
4199
4200 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
4201 .type = AMD_IP_BLOCK_TYPE_PSP,
4202 .major = 11,
4203 .minor = 0,
4204 .rev = 8,
4205 .funcs = &psp_ip_funcs,
4206 };
4207
4208 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
4209 .type = AMD_IP_BLOCK_TYPE_PSP,
4210 .major = 12,
4211 .minor = 0,
4212 .rev = 0,
4213 .funcs = &psp_ip_funcs,
4214 };
4215
4216 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
4217 .type = AMD_IP_BLOCK_TYPE_PSP,
4218 .major = 13,
4219 .minor = 0,
4220 .rev = 0,
4221 .funcs = &psp_ip_funcs,
4222 };
4223
4224 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
4225 .type = AMD_IP_BLOCK_TYPE_PSP,
4226 .major = 13,
4227 .minor = 0,
4228 .rev = 4,
4229 .funcs = &psp_ip_funcs,
4230 };
4231
4232 const struct amdgpu_ip_block_version psp_v14_0_ip_block = {
4233 .type = AMD_IP_BLOCK_TYPE_PSP,
4234 .major = 14,
4235 .minor = 0,
4236 .rev = 0,
4237 .funcs = &psp_ip_funcs,
4238 };
4239