1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/soc/bcm-pmb.h> 7 8/dts-v1/; 9 10/ { 11 interrupt-parent = <&gic>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "brcm,brahma-b53"; 31 reg = <0x0>; 32 enable-method = "spin-table"; 33 cpu-release-addr = <0x0 0xff8>; 34 next-level-cache = <&l2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "brcm,brahma-b53"; 40 reg = <0x1>; 41 enable-method = "spin-table"; 42 cpu-release-addr = <0x0 0xff8>; 43 next-level-cache = <&l2>; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "brcm,brahma-b53"; 49 reg = <0x2>; 50 enable-method = "spin-table"; 51 cpu-release-addr = <0x0 0xff8>; 52 next-level-cache = <&l2>; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "brcm,brahma-b53"; 58 reg = <0x3>; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0xff8>; 61 next-level-cache = <&l2>; 62 }; 63 64 l2: l2-cache0 { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 }; 69 }; 70 71 reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 cfe-stub@0 { 77 reg = <0x0 0x0 0x0 0x1000>; 78 }; 79 }; 80 81 axi@81000000 { 82 compatible = "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x00 0x00 0x81000000 0x4000>; 86 87 gic: interrupt-controller@1000 { 88 compatible = "arm,gic-400"; 89 #interrupt-cells = <3>; 90 #address-cells = <0>; 91 interrupt-controller; 92 reg = <0x1000 0x1000>, 93 <0x2000 0x2000>; 94 }; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 103 }; 104 105 pmu { 106 compatible = "arm,cortex-a53-pmu"; 107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 111 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 112 }; 113 114 clocks { 115 periph_clk: periph_clk { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <50000000>; 119 clock-output-names = "periph"; 120 }; 121 122 hsspi_pll: hsspi-pll { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <400000000>; 126 }; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges = <0x00 0x00 0x80000000 0x281000>; 134 135 enet: ethernet@2000 { 136 compatible = "brcm,bcm4908-enet"; 137 reg = <0x2000 0x1000>; 138 139 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 141 interrupt-names = "rx", "tx"; 142 }; 143 144 usb_phy: usb-phy@c200 { 145 compatible = "brcm,bcm4908-usb-phy"; 146 reg = <0xc200 0x100>; 147 reg-names = "ctrl"; 148 power-domains = <&pmb BCM_PMB_HOST_USB>; 149 dr_mode = "host"; 150 brcm,has-xhci; 151 brcm,has-eohci; 152 #phy-cells = <1>; 153 status = "disabled"; 154 }; 155 156 ehci: usb@c300 { 157 compatible = "generic-ehci"; 158 reg = <0xc300 0x100>; 159 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 160 phys = <&usb_phy PHY_TYPE_USB2>; 161 status = "disabled"; 162 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 ehci_port1: port@1 { 167 reg = <1>; 168 #trigger-source-cells = <0>; 169 }; 170 171 ehci_port2: port@2 { 172 reg = <2>; 173 #trigger-source-cells = <0>; 174 }; 175 }; 176 177 ohci: usb@c400 { 178 compatible = "generic-ohci"; 179 reg = <0xc400 0x100>; 180 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 181 phys = <&usb_phy PHY_TYPE_USB2>; 182 status = "disabled"; 183 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 ohci_port1: port@1 { 188 reg = <1>; 189 #trigger-source-cells = <0>; 190 }; 191 192 ohci_port2: port@2 { 193 reg = <2>; 194 #trigger-source-cells = <0>; 195 }; 196 }; 197 198 xhci: usb@d000 { 199 compatible = "generic-xhci"; 200 reg = <0xd000 0x8c8>; 201 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 202 phys = <&usb_phy PHY_TYPE_USB3>; 203 status = "disabled"; 204 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 xhci_port1: port@1 { 209 reg = <1>; 210 #trigger-source-cells = <0>; 211 }; 212 213 xhci_port2: port@2 { 214 reg = <2>; 215 #trigger-source-cells = <0>; 216 }; 217 }; 218 219 bus@80000 { 220 compatible = "simple-bus"; 221 #size-cells = <1>; 222 #address-cells = <1>; 223 ranges = <0 0x80000 0x50000>; 224 225 ethernet-switch@0 { 226 compatible = "brcm,bcm4908-switch"; 227 reg = <0x0 0x40000>, 228 <0x40000 0x110>, 229 <0x40340 0x30>, 230 <0x40380 0x30>, 231 <0x40600 0x34>, 232 <0x40800 0x208>; 233 reg-names = "core", "reg", "intrl2_0", 234 "intrl2_1", "fcb", "acb"; 235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 237 brcm,num-gphy = <5>; 238 brcm,num-rgmii-ports = <2>; 239 240 ports: ports { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 port@0 { 245 reg = <0>; 246 phy-mode = "internal"; 247 phy-handle = <&phy8>; 248 }; 249 250 port@1 { 251 reg = <1>; 252 phy-mode = "internal"; 253 phy-handle = <&phy9>; 254 }; 255 256 port@2 { 257 reg = <2>; 258 phy-mode = "internal"; 259 phy-handle = <&phy10>; 260 }; 261 262 port@3 { 263 reg = <3>; 264 phy-mode = "internal"; 265 phy-handle = <&phy11>; 266 }; 267 268 port@8 { 269 reg = <8>; 270 phy-mode = "internal"; 271 ethernet = <&enet>; 272 273 fixed-link { 274 speed = <1000>; 275 full-duplex; 276 }; 277 }; 278 }; 279 }; 280 281 mdio: mdio@405c0 { 282 compatible = "brcm,unimac-mdio"; 283 reg = <0x405c0 0x8>; 284 reg-names = "mdio"; 285 #size-cells = <0>; 286 #address-cells = <1>; 287 288 phy8: ethernet-phy@8 { 289 reg = <8>; 290 }; 291 292 phy9: ethernet-phy@9 { 293 reg = <9>; 294 }; 295 296 phy10: ethernet-phy@a { 297 reg = <10>; 298 }; 299 300 phy11: ethernet-phy@b { 301 reg = <11>; 302 }; 303 304 phy12: ethernet-phy@c { 305 reg = <12>; 306 }; 307 }; 308 }; 309 310 procmon: bus@280000 { 311 compatible = "simple-bus"; 312 reg = <0x280000 0x1000>; 313 ranges; 314 315 #address-cells = <1>; 316 #size-cells = <1>; 317 318 pmb: power-controller@2800c0 { 319 compatible = "brcm,bcm4908-pmb"; 320 reg = <0x2800c0 0x40>; 321 #power-domain-cells = <1>; 322 }; 323 }; 324 }; 325 326 /* PERF Peripherals */ 327 bus@ff800000 { 328 compatible = "simple-bus"; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 ranges = <0x00 0x00 0xff800000 0x400000>; 332 333 twd: timer-mfd@400 { 334 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; 335 reg = <0x400 0x4c>; 336 ranges = <0x0 0x400 0x4c>; 337 338 #address-cells = <1>; 339 #size-cells = <1>; 340 341 timer@0 { 342 compatible = "brcm,bcm63138-timer"; 343 reg = <0x0 0x28>; 344 }; 345 346 watchdog@28 { 347 compatible = "brcm,bcm6345-wdt"; 348 reg = <0x28 0x8>; 349 }; 350 }; 351 352 /* GPIOs 0 .. 31 */ 353 gpio0: gpio@500 { 354 compatible = "brcm,bcm6345-gpio"; 355 reg = <0x500 0x04>, <0x528 0x04>; 356 reg-names = "dirout", "dat"; 357 gpio-controller; 358 #gpio-cells = <2>; 359 }; 360 361 /* GPIOs 32 .. 63 */ 362 gpio1: gpio@504 { 363 compatible = "brcm,bcm6345-gpio"; 364 reg = <0x504 0x04>, <0x52c 0x04>; 365 reg-names = "dirout", "dat"; 366 gpio-controller; 367 #gpio-cells = <2>; 368 status = "disabled"; 369 }; 370 371 /* GPIOs 64 .. 95 */ 372 gpio2: gpio@508 { 373 compatible = "brcm,bcm6345-gpio"; 374 reg = <0x508 0x04>, <0x530 0x04>; 375 reg-names = "dirout", "dat"; 376 gpio-controller; 377 #gpio-cells = <2>; 378 status = "disabled"; 379 }; 380 381 /* GPIOs 96 .. 127 */ 382 gpio3: gpio@50c { 383 compatible = "brcm,bcm6345-gpio"; 384 reg = <0x50c 0x04>, <0x534 0x04>; 385 reg-names = "dirout", "dat"; 386 gpio-controller; 387 #gpio-cells = <2>; 388 status = "disabled"; 389 }; 390 391 /* GPIOs 128 .. 159 */ 392 gpio4: gpio@510 { 393 compatible = "brcm,bcm6345-gpio"; 394 reg = <0x510 0x04>, <0x538 0x04>; 395 reg-names = "dirout", "dat"; 396 gpio-controller; 397 #gpio-cells = <2>; 398 status = "disabled"; 399 }; 400 401 /* GPIOs 160 .. 191 */ 402 gpio5: gpio@514 { 403 compatible = "brcm,bcm6345-gpio"; 404 reg = <0x514 0x04>, <0x53c 0x04>; 405 reg-names = "dirout", "dat"; 406 gpio-controller; 407 #gpio-cells = <2>; 408 status = "disabled"; 409 }; 410 411 /* GPIOs 192 .. 223 */ 412 gpio6: gpio@518 { 413 compatible = "brcm,bcm6345-gpio"; 414 reg = <0x518 0x04>, <0x540 0x04>; 415 reg-names = "dirout", "dat"; 416 gpio-controller; 417 #gpio-cells = <2>; 418 status = "disabled"; 419 }; 420 421 /* GPIOs 224 .. 255 */ 422 gpio7: gpio@51c { 423 compatible = "brcm,bcm6345-gpio"; 424 reg = <0x51c 0x04>, <0x544 0x04>; 425 reg-names = "dirout", "dat"; 426 gpio-controller; 427 #gpio-cells = <2>; 428 status = "disabled"; 429 }; 430 431 /* GPIOs 256 .. 287 */ 432 gpio8: gpio@520 { 433 compatible = "brcm,bcm6345-gpio"; 434 reg = <0x520 0x04>, <0x548 0x04>; 435 reg-names = "dirout", "dat"; 436 gpio-controller; 437 #gpio-cells = <2>; 438 status = "disabled"; 439 }; 440 441 /* GPIOs 288 .. 319 */ 442 gpio9: gpio@524 { 443 compatible = "brcm,bcm6345-gpio"; 444 reg = <0x524 0x04>, <0x54c 0x04>; 445 reg-names = "dirout", "dat"; 446 gpio-controller; 447 #gpio-cells = <2>; 448 status = "disabled"; 449 }; 450 451 pinctrl@560 { 452 compatible = "brcm,bcm4908-pinctrl"; 453 reg = <0x560 0x10>; 454 455 pins_led_0_a: led_0-a-pins { 456 function = "led_0"; 457 groups = "led_0_grp_a"; 458 }; 459 460 pins_led_1_a: led_1-a-pins { 461 function = "led_1"; 462 groups = "led_1_grp_a"; 463 }; 464 465 pins_led_2_a: led_2-a-pins { 466 function = "led_2"; 467 groups = "led_2_grp_a"; 468 }; 469 470 pins_led_3_a: led_3-a-pins { 471 function = "led_3"; 472 groups = "led_3_grp_a"; 473 }; 474 475 pins_led_4_a: led_4-a-pins { 476 function = "led_4"; 477 groups = "led_4_grp_a"; 478 }; 479 480 pins_led_5_a: led_5-a-pins { 481 function = "led_5"; 482 groups = "led_5_grp_a"; 483 }; 484 485 pins_led_6_a: led_6-a-pins { 486 function = "led_6"; 487 groups = "led_6_grp_a"; 488 }; 489 490 pins_led_7_a: led_7-a-pins { 491 function = "led_7"; 492 groups = "led_7_grp_a"; 493 }; 494 495 pins_led_8_a: led_8-a-pins { 496 function = "led_8"; 497 groups = "led_8_grp_a"; 498 }; 499 500 pins_led_9_a: led_9-a-pins { 501 function = "led_9"; 502 groups = "led_9_grp_a"; 503 }; 504 505 pins_led_10_a: led_10-a-pins { 506 function = "led_10"; 507 groups = "led_10_grp_a"; 508 }; 509 510 pins_led_11_a: led_11-a-pins { 511 function = "led_11"; 512 groups = "led_11_grp_a"; 513 }; 514 515 pins_led_12_a: led_12-a-pins { 516 function = "led_12"; 517 groups = "led_12_grp_a"; 518 }; 519 520 pins_led_13_a: led_13-a-pins { 521 function = "led_13"; 522 groups = "led_13_grp_a"; 523 }; 524 525 pins_led_14_a: led_14-a-pins { 526 function = "led_14"; 527 groups = "led_14_grp_a"; 528 }; 529 530 pins_led_15_a: led_15-a-pins { 531 function = "led_15"; 532 groups = "led_15_grp_a"; 533 }; 534 535 pins_led_16_a: led_16-a-pins { 536 function = "led_16"; 537 groups = "led_16_grp_a"; 538 }; 539 540 pins_led_17_a: led_17-a-pins { 541 function = "led_17"; 542 groups = "led_17_grp_a"; 543 }; 544 545 pins_led_18_a: led_18-a-pins { 546 function = "led_18"; 547 groups = "led_18_grp_a"; 548 }; 549 550 pins_led_19_a: led_19-a-pins { 551 function = "led_19"; 552 groups = "led_19_grp_a"; 553 }; 554 555 pins_led_20_a: led_20-a-pins { 556 function = "led_20"; 557 groups = "led_20_grp_a"; 558 }; 559 560 pins_led_21_a: led_21-a-pins { 561 function = "led_21"; 562 groups = "led_21_grp_a"; 563 }; 564 565 pins_led_22_a: led_22-a-pins { 566 function = "led_22"; 567 groups = "led_22_grp_a"; 568 }; 569 570 pins_led_23_a: led_23-a-pins { 571 function = "led_23"; 572 groups = "led_23_grp_a"; 573 }; 574 575 pins_led_24_a: led_24-a-pins { 576 function = "led_24"; 577 groups = "led_24_grp_a"; 578 }; 579 580 pins_led_25_a: led_25-a-pins { 581 function = "led_25"; 582 groups = "led_25_grp_a"; 583 }; 584 585 pins_led_26_a: led_26-a-pins { 586 function = "led_26"; 587 groups = "led_26_grp_a"; 588 }; 589 590 pins_led_27_a: led_27-a-pins { 591 function = "led_27"; 592 groups = "led_27_grp_a"; 593 }; 594 595 pins_led_28_a: led_28-a-pins { 596 function = "led_28"; 597 groups = "led_28_grp_a"; 598 }; 599 600 pins_led_29_a: led_29-a-pins { 601 function = "led_29"; 602 groups = "led_29_grp_a"; 603 }; 604 605 pins_led_30_a: led_30-a-pins { 606 function = "led_30"; 607 groups = "led_30_grp_a"; 608 }; 609 610 pins_led_31_a: led_31-a-pins { 611 function = "led_31"; 612 groups = "led_31_grp_a"; 613 }; 614 615 pins_hs_uart: hs_uart-pins { 616 function = "hs_uart"; 617 groups = "hs_uart_grp"; 618 }; 619 620 pins_i2c_a: i2c-a-pins { 621 function = "i2c"; 622 groups = "i2c_grp_a"; 623 }; 624 625 pins_i2c_b: i2c-b-pins { 626 function = "i2c"; 627 groups = "i2c_grp_b"; 628 }; 629 630 pins_i2s: i2s-pins { 631 function = "i2s"; 632 groups = "i2s_grp"; 633 }; 634 635 pins_nand_ctrl: nand_ctrl-pins { 636 function = "nand_ctrl"; 637 groups = "nand_ctrl_grp"; 638 }; 639 640 pins_nand_data: nand_data-pins { 641 function = "nand_data"; 642 groups = "nand_data_grp"; 643 }; 644 645 pins_emmc_ctrl: emmc_ctrl-pins { 646 function = "emmc_ctrl"; 647 groups = "emmc_ctrl_grp"; 648 }; 649 650 pins_usb0_pwr: usb0_pwr-pins { 651 function = "usb0_pwr"; 652 groups = "usb0_pwr_grp"; 653 }; 654 655 pins_usb1_pwr: usb1_pwr-pins { 656 function = "usb1_pwr"; 657 groups = "usb1_pwr_grp"; 658 }; 659 }; 660 661 uart0: serial@640 { 662 compatible = "brcm,bcm6345-uart"; 663 reg = <0x640 0x18>; 664 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&periph_clk>; 666 clock-names = "refclk"; 667 status = "okay"; 668 }; 669 670 leds: leds@800 { 671 compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; 672 reg = <0x800 0xdc>; 673 674 #address-cells = <1>; 675 #size-cells = <0>; 676 }; 677 678 rng@b80 { 679 compatible = "brcm,iproc-rng200"; 680 reg = <0xb80 0x28>; 681 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 682 }; 683 684 hsspi: spi@1000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; 688 reg = <0x1000 0x600>; 689 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&hsspi_pll &hsspi_pll>; 691 clock-names = "hsspi", "pll"; 692 num-cs = <8>; 693 status = "disabled"; 694 }; 695 696 nand_controller: nand-controller@1800 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 700 reg = <0x1800 0x600>, <0x2000 0x10>; 701 reg-names = "nand", "nand-int-base"; 702 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "nand_ctlrdy"; 704 brcm,wp-not-connected; 705 status = "disabled"; 706 707 nandcs: nand@0 { 708 compatible = "brcm,nandcs"; 709 reg = <0>; 710 }; 711 }; 712 713 i2c@2100 { 714 compatible = "brcm,brcmper-i2c"; 715 reg = <0x2100 0x58>; 716 clock-frequency = <97500>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pins_i2c_a>; 719 status = "disabled"; 720 }; 721 722 misc@2600 { 723 compatible = "brcm,misc", "simple-mfd"; 724 reg = <0x2600 0xe4>; 725 726 #address-cells = <1>; 727 #size-cells = <1>; 728 ranges = <0x00 0x2600 0xe4>; 729 730 reset-controller@2644 { 731 compatible = "brcm,bcm4908-misc-pcie-reset"; 732 reg = <0x44 0x04>; 733 #reset-cells = <1>; 734 }; 735 }; 736 737 pl081_dma: dma-controller@59000 { 738 compatible = "arm,pl081", "arm,primecell"; 739 // The magic B105F00D info is missing 740 arm,primecell-periphid = <0x00041081>; 741 reg = <0x59000 0x1000>; 742 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 743 memcpy-burst-size = <256>; 744 memcpy-bus-width = <32>; 745 clocks = <&periph_clk>; 746 clock-names = "apb_pclk"; 747 #dma-cells = <2>; 748 }; 749 }; 750 751 reboot { 752 compatible = "syscon-reboot"; 753 regmap = <&twd>; 754 offset = <0x34>; 755 mask = <1>; 756 }; 757}; 758