1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/ptrace.h
4 *
5 * Copyright (C) 1996-2003 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_PTRACE_H
9 #define __ASM_PTRACE_H
10
11 #include <asm/cpufeature.h>
12
13 #include <uapi/asm/ptrace.h>
14
15 /* Current Exception Level values, as contained in CurrentEL */
16 #define CurrentEL_EL1 (1 << 2)
17 #define CurrentEL_EL2 (2 << 2)
18
19 #define INIT_PSTATE_EL1 \
20 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
21
22 #include <linux/irqchip/arm-gic-v3-prio.h>
23
24 #define GIC_PRIO_IRQON GICV3_PRIO_UNMASKED
25 #define GIC_PRIO_IRQOFF GICV3_PRIO_IRQ
26
27 #define GIC_PRIO_PSR_I_SET GICV3_PRIO_PSR_I_SET
28
29 /* Additional SPSR bits not exposed in the UABI */
30 #define PSR_MODE_THREAD_BIT (1 << 0)
31 #define PSR_IL_BIT (1 << 20)
32
33 /* AArch32-specific ptrace requests */
34 #define COMPAT_PTRACE_GETREGS 12
35 #define COMPAT_PTRACE_SETREGS 13
36 #define COMPAT_PTRACE_GET_THREAD_AREA 22
37 #define COMPAT_PTRACE_SET_SYSCALL 23
38 #define COMPAT_PTRACE_GETVFPREGS 27
39 #define COMPAT_PTRACE_SETVFPREGS 28
40 #define COMPAT_PTRACE_GETHBPREGS 29
41 #define COMPAT_PTRACE_SETHBPREGS 30
42
43 /* SPSR_ELx bits for exceptions taken from AArch32 */
44 #define PSR_AA32_MODE_MASK 0x0000001f
45 #define PSR_AA32_MODE_USR 0x00000010
46 #define PSR_AA32_MODE_FIQ 0x00000011
47 #define PSR_AA32_MODE_IRQ 0x00000012
48 #define PSR_AA32_MODE_SVC 0x00000013
49 #define PSR_AA32_MODE_ABT 0x00000017
50 #define PSR_AA32_MODE_HYP 0x0000001a
51 #define PSR_AA32_MODE_UND 0x0000001b
52 #define PSR_AA32_MODE_SYS 0x0000001f
53 #define PSR_AA32_T_BIT 0x00000020
54 #define PSR_AA32_F_BIT 0x00000040
55 #define PSR_AA32_I_BIT 0x00000080
56 #define PSR_AA32_A_BIT 0x00000100
57 #define PSR_AA32_E_BIT 0x00000200
58 #define PSR_AA32_PAN_BIT 0x00400000
59 #define PSR_AA32_SSBS_BIT 0x00800000
60 #define PSR_AA32_DIT_BIT 0x01000000
61 #define PSR_AA32_Q_BIT 0x08000000
62 #define PSR_AA32_V_BIT 0x10000000
63 #define PSR_AA32_C_BIT 0x20000000
64 #define PSR_AA32_Z_BIT 0x40000000
65 #define PSR_AA32_N_BIT 0x80000000
66 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
67 #define PSR_AA32_GE_MASK 0x000f0000
68
69 /* AArch32 CPSR bits, as seen in AArch32 */
70 #define COMPAT_PSR_DIT_BIT 0x00200000
71
72 /*
73 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
74 * process is located in memory.
75 */
76 #define COMPAT_PT_TEXT_ADDR 0x10000
77 #define COMPAT_PT_DATA_ADDR 0x10004
78 #define COMPAT_PT_TEXT_END_ADDR 0x10008
79
80 /*
81 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
82 * a syscall -- i.e., its most recent entry into the kernel from
83 * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
84 *
85 * This must have the value -1, for ABI compatibility with ptrace etc.
86 */
87 #define NO_SYSCALL (-1)
88
89 #ifndef __ASSEMBLER__
90 #include <linux/bug.h>
91 #include <linux/types.h>
92
93 #include <asm/stacktrace/frame.h>
94
95 /* sizeof(struct user) for AArch32 */
96 #define COMPAT_USER_SZ 296
97
98 /* Architecturally defined mapping between AArch32 and AArch64 registers */
99 #define compat_usr(x) regs[(x)]
100 #define compat_fp regs[11]
101 #define compat_sp regs[13]
102 #define compat_lr regs[14]
103 #define compat_sp_hyp regs[15]
104 #define compat_lr_irq regs[16]
105 #define compat_sp_irq regs[17]
106 #define compat_lr_svc regs[18]
107 #define compat_sp_svc regs[19]
108 #define compat_lr_abt regs[20]
109 #define compat_sp_abt regs[21]
110 #define compat_lr_und regs[22]
111 #define compat_sp_und regs[23]
112 #define compat_r8_fiq regs[24]
113 #define compat_r9_fiq regs[25]
114 #define compat_r10_fiq regs[26]
115 #define compat_r11_fiq regs[27]
116 #define compat_r12_fiq regs[28]
117 #define compat_sp_fiq regs[29]
118 #define compat_lr_fiq regs[30]
119
compat_psr_to_pstate(const unsigned long psr)120 static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
121 {
122 unsigned long pstate;
123
124 pstate = psr & ~COMPAT_PSR_DIT_BIT;
125
126 if (psr & COMPAT_PSR_DIT_BIT)
127 pstate |= PSR_AA32_DIT_BIT;
128
129 return pstate;
130 }
131
pstate_to_compat_psr(const unsigned long pstate)132 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
133 {
134 unsigned long psr;
135
136 psr = pstate & ~PSR_AA32_DIT_BIT;
137
138 if (pstate & PSR_AA32_DIT_BIT)
139 psr |= COMPAT_PSR_DIT_BIT;
140
141 return psr;
142 }
143
144 /*
145 * This struct defines the way the registers are stored on the stack during an
146 * exception. struct user_pt_regs must form a prefix of struct pt_regs.
147 */
148 struct pt_regs {
149 union {
150 struct user_pt_regs user_regs;
151 struct {
152 u64 regs[31];
153 u64 sp;
154 u64 pc;
155 u64 pstate;
156 };
157 };
158 u64 orig_x0;
159 s32 syscallno;
160 u32 pmr;
161
162 u64 sdei_ttbr1;
163 struct frame_record_meta stackframe;
164
165 u16 pcpu_gprs;
166 u16 __unused1;
167 u32 __unused2;
168 u64 __unused3;
169 };
170
171 /* For correct stack alignment, pt_regs has to be a multiple of 16 bytes. */
172 static_assert(IS_ALIGNED(sizeof(struct pt_regs), 16));
173
in_syscall(struct pt_regs const * regs)174 static inline bool in_syscall(struct pt_regs const *regs)
175 {
176 return regs->syscallno != NO_SYSCALL;
177 }
178
forget_syscall(struct pt_regs * regs)179 static inline void forget_syscall(struct pt_regs *regs)
180 {
181 regs->syscallno = NO_SYSCALL;
182 }
183
184 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
185
186 #define arch_has_single_step() (1)
187
188 #ifdef CONFIG_COMPAT
189 #define compat_thumb_mode(regs) \
190 (((regs)->pstate & PSR_AA32_T_BIT))
191 #else
192 #define compat_thumb_mode(regs) (0)
193 #endif
194
195 #define user_mode(regs) \
196 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
197
198 #define compat_user_mode(regs) \
199 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
200 (PSR_MODE32_BIT | PSR_MODE_EL0t))
201
202 #define processor_mode(regs) \
203 ((regs)->pstate & PSR_MODE_MASK)
204
205 #define irqs_priority_unmasked(regs) \
206 (system_uses_irq_prio_masking() ? \
207 (regs)->pmr == GIC_PRIO_IRQON : \
208 true)
209
regs_irqs_disabled(const struct pt_regs * regs)210 static __always_inline bool regs_irqs_disabled(const struct pt_regs *regs)
211 {
212 return (regs->pstate & PSR_I_BIT) || !irqs_priority_unmasked(regs);
213 }
214
215 #define interrupts_enabled(regs) (!regs_irqs_disabled(regs))
216
user_stack_pointer(struct pt_regs * regs)217 static inline unsigned long user_stack_pointer(struct pt_regs *regs)
218 {
219 if (compat_user_mode(regs))
220 return regs->compat_sp;
221 return regs->sp;
222 }
223
224 extern int regs_query_register_offset(const char *name);
225 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
226 unsigned int n);
227
228 /**
229 * regs_get_register() - get register value from its offset
230 * @regs: pt_regs from which register value is gotten
231 * @offset: offset of the register.
232 *
233 * regs_get_register returns the value of a register whose offset from @regs.
234 * The @offset is the offset of the register in struct pt_regs.
235 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
236 */
regs_get_register(struct pt_regs * regs,unsigned int offset)237 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
238 {
239 u64 val = 0;
240
241 WARN_ON(offset & 7);
242
243 offset >>= 3;
244 switch (offset) {
245 case 0 ... 30:
246 val = regs->regs[offset];
247 break;
248 case offsetof(struct pt_regs, sp) >> 3:
249 val = regs->sp;
250 break;
251 case offsetof(struct pt_regs, pc) >> 3:
252 val = regs->pc;
253 break;
254 case offsetof(struct pt_regs, pstate) >> 3:
255 val = regs->pstate;
256 break;
257 default:
258 val = 0;
259 }
260
261 return val;
262 }
263
264 /*
265 * Read a register given an architectural register index r.
266 * This handles the common case where 31 means XZR, not SP.
267 */
268 static __always_inline unsigned long
pt_regs_read_reg(const struct pt_regs * regs,int r)269 pt_regs_read_reg(const struct pt_regs *regs, int r)
270 {
271 return (r == 31) ? 0 : regs->regs[r];
272 }
273
274 /*
275 * Write a register given an architectural register index r.
276 * This handles the common case where 31 means XZR, not SP.
277 */
278 static __always_inline void
pt_regs_write_reg(struct pt_regs * regs,int r,unsigned long val)279 pt_regs_write_reg(struct pt_regs *regs, int r, unsigned long val)
280 {
281 if (r != 31)
282 regs->regs[r] = val;
283 }
284
285 /* Valid only for Kernel mode traps. */
kernel_stack_pointer(struct pt_regs * regs)286 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
287 {
288 return regs->sp;
289 }
290
regs_return_value(struct pt_regs * regs)291 static inline unsigned long regs_return_value(struct pt_regs *regs)
292 {
293 unsigned long val = regs->regs[0];
294
295 /*
296 * Audit currently uses regs_return_value() instead of
297 * syscall_get_return_value(). Apply the same sign-extension here until
298 * audit is updated to use syscall_get_return_value().
299 */
300 if (compat_user_mode(regs))
301 val = sign_extend64(val, 31);
302
303 return val;
304 }
305
regs_set_return_value(struct pt_regs * regs,unsigned long rc)306 static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
307 {
308 regs->regs[0] = rc;
309 }
310
311 /**
312 * regs_get_kernel_argument() - get Nth function argument in kernel
313 * @regs: pt_regs of that context
314 * @n: function argument number (start from 0)
315 *
316 * regs_get_argument() returns @n th argument of the function call.
317 *
318 * Note that this chooses the most likely register mapping. In very rare
319 * cases this may not return correct data, for example, if one of the
320 * function parameters is 16 bytes or bigger. In such cases, we cannot
321 * get access the parameter correctly and the register assignment of
322 * subsequent parameters will be shifted.
323 */
regs_get_kernel_argument(struct pt_regs * regs,unsigned int n)324 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
325 unsigned int n)
326 {
327 #define NR_REG_ARGUMENTS 8
328 if (n < NR_REG_ARGUMENTS)
329 return pt_regs_read_reg(regs, n);
330 return 0;
331 }
332
333 /* We must avoid circular header include via sched.h */
334 struct task_struct;
335 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
336
instruction_pointer(struct pt_regs * regs)337 static inline unsigned long instruction_pointer(struct pt_regs *regs)
338 {
339 return regs->pc;
340 }
instruction_pointer_set(struct pt_regs * regs,unsigned long val)341 static inline void instruction_pointer_set(struct pt_regs *regs,
342 unsigned long val)
343 {
344 regs->pc = val;
345 }
346
frame_pointer(struct pt_regs * regs)347 static inline unsigned long frame_pointer(struct pt_regs *regs)
348 {
349 return regs->regs[29];
350 }
351
352 #define procedure_link_pointer(regs) ((regs)->regs[30])
353
procedure_link_pointer_set(struct pt_regs * regs,unsigned long val)354 static inline void procedure_link_pointer_set(struct pt_regs *regs,
355 unsigned long val)
356 {
357 procedure_link_pointer(regs) = val;
358 }
359
360 extern unsigned long profile_pc(struct pt_regs *regs);
361
362 #endif /* __ASSEMBLER__ */
363 #endif
364