1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Virtual Function ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/etherdevice.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/net_tstamp.h>
12
13 #include "otx2_common.h"
14 #include "otx2_reg.h"
15 #include "otx2_ptp.h"
16 #include "cn10k.h"
17 #include "cn10k_ipsec.h"
18
19 #define DRV_NAME "rvu_nicvf"
20 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
21
22 static const struct pci_device_id otx2_vf_id_table[] = {
23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
24 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) },
25 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_SDP_REP) },
26 { }
27 };
28
29 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
30 MODULE_DESCRIPTION(DRV_STRING);
31 MODULE_LICENSE("GPL v2");
32 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table);
33
34 /* RVU VF Interrupt Vector Enumeration */
35 enum {
36 RVU_VF_INT_VEC_MBOX = 0x0,
37 };
38
otx2vf_process_vfaf_mbox_msg(struct otx2_nic * vf,struct mbox_msghdr * msg)39 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf,
40 struct mbox_msghdr *msg)
41 {
42 if (msg->id >= MBOX_MSG_MAX) {
43 dev_err(vf->dev,
44 "Mbox msg with unknown ID %d\n", msg->id);
45 return;
46 }
47
48 if (msg->sig != OTX2_MBOX_RSP_SIG) {
49 dev_err(vf->dev,
50 "Mbox msg with wrong signature %x, ID %d\n",
51 msg->sig, msg->id);
52 return;
53 }
54
55 if (msg->rc == MBOX_MSG_INVALID) {
56 dev_err(vf->dev,
57 "PF/AF says the sent msg(s) %d were invalid\n",
58 msg->id);
59 return;
60 }
61
62 switch (msg->id) {
63 case MBOX_MSG_READY:
64 vf->pcifunc = msg->pcifunc;
65 break;
66 case MBOX_MSG_MSIX_OFFSET:
67 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);
68 break;
69 case MBOX_MSG_NPA_LF_ALLOC:
70 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg);
71 break;
72 case MBOX_MSG_NIX_LF_ALLOC:
73 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg);
74 break;
75 case MBOX_MSG_NIX_BP_ENABLE:
76 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg);
77 break;
78 default:
79 if (msg->rc)
80 dev_err(vf->dev,
81 "Mbox msg response has err %d, ID %d\n",
82 msg->rc, msg->id);
83 }
84 }
85
otx2vf_vfaf_mbox_handler(struct work_struct * work)86 static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
87 {
88 struct otx2_mbox_dev *mdev;
89 struct mbox_hdr *rsp_hdr;
90 struct mbox_msghdr *msg;
91 struct otx2_mbox *mbox;
92 struct mbox *af_mbox;
93 int offset, id;
94 u16 num_msgs;
95
96 af_mbox = container_of(work, struct mbox, mbox_wrk);
97 mbox = &af_mbox->mbox;
98 mdev = &mbox->dev[0];
99 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
100 num_msgs = rsp_hdr->num_msgs;
101
102 if (num_msgs == 0)
103 return;
104
105 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
106
107 for (id = 0; id < num_msgs; id++) {
108 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
109 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg);
110 offset = mbox->rx_start + msg->next_msgoff;
111 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
112 __otx2_mbox_reset(mbox, 0);
113 mdev->msgs_acked++;
114 }
115 }
116
otx2vf_process_mbox_msg_up(struct otx2_nic * vf,struct mbox_msghdr * req)117 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
118 struct mbox_msghdr *req)
119 {
120 struct msg_rsp *rsp;
121 int err;
122
123 /* Check if valid, if not reply with a invalid msg */
124 if (req->sig != OTX2_MBOX_REQ_SIG) {
125 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
126 return -ENODEV;
127 }
128
129 switch (req->id) {
130 case MBOX_MSG_CGX_LINK_EVENT:
131 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(
132 &vf->mbox.mbox_up, 0,
133 sizeof(struct msg_rsp));
134 if (!rsp)
135 return -ENOMEM;
136
137 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
138 rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
139 rsp->hdr.pcifunc = req->pcifunc;
140 rsp->hdr.rc = 0;
141 err = otx2_mbox_up_handler_cgx_link_event(
142 vf, (struct cgx_link_info_msg *)req, rsp);
143 return err;
144 default:
145 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
146 return -ENODEV;
147 }
148 return 0;
149 }
150
otx2vf_vfaf_mbox_up_handler(struct work_struct * work)151 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work)
152 {
153 struct otx2_mbox_dev *mdev;
154 struct mbox_hdr *rsp_hdr;
155 struct mbox_msghdr *msg;
156 struct otx2_mbox *mbox;
157 struct mbox *vf_mbox;
158 struct otx2_nic *vf;
159 int offset, id;
160 u16 num_msgs;
161
162 vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
163 vf = vf_mbox->pfvf;
164 mbox = &vf_mbox->mbox_up;
165 mdev = &mbox->dev[0];
166
167 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
168 num_msgs = rsp_hdr->num_msgs;
169
170 if (num_msgs == 0)
171 return;
172
173 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
174
175 for (id = 0; id < num_msgs; id++) {
176 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
177 otx2vf_process_mbox_msg_up(vf, msg);
178 offset = mbox->rx_start + msg->next_msgoff;
179 }
180
181 otx2_mbox_msg_send(mbox, 0);
182 }
183
otx2vf_vfaf_mbox_intr_handler(int irq,void * vf_irq)184 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq)
185 {
186 struct otx2_nic *vf = (struct otx2_nic *)vf_irq;
187 struct otx2_mbox_dev *mdev;
188 struct otx2_mbox *mbox;
189 struct mbox_hdr *hdr;
190 u64 mbox_data;
191
192 /* Clear the IRQ */
193 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
194
195 mbox_data = otx2_read64(vf, RVU_VF_VFPF_MBOX0);
196
197 /* Read latest mbox data */
198 smp_rmb();
199
200 if (mbox_data & MBOX_DOWN_MSG) {
201 mbox_data &= ~MBOX_DOWN_MSG;
202 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data);
203
204 /* Check for PF => VF response messages */
205 mbox = &vf->mbox.mbox;
206 mdev = &mbox->dev[0];
207 otx2_sync_mbox_bbuf(mbox, 0);
208
209 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
210 if (hdr->num_msgs)
211 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
212
213 trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF to VF",
214 BIT_ULL(0));
215 }
216
217 if (mbox_data & MBOX_UP_MSG) {
218 mbox_data &= ~MBOX_UP_MSG;
219 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data);
220
221 /* Check for PF => VF notification messages */
222 mbox = &vf->mbox.mbox_up;
223 mdev = &mbox->dev[0];
224 otx2_sync_mbox_bbuf(mbox, 0);
225
226 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
227 if (hdr->num_msgs)
228 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
229
230 trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF to VF",
231 BIT_ULL(0));
232 }
233
234 return IRQ_HANDLED;
235 }
236
otx2vf_disable_mbox_intr(struct otx2_nic * vf)237 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf)
238 {
239 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX);
240
241 /* Disable VF => PF mailbox IRQ */
242 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
243
244 if (is_cn20k(vf->pdev))
245 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0) | BIT_ULL(1));
246
247 free_irq(vector, vf);
248 }
249
otx2vf_register_mbox_intr(struct otx2_nic * vf,bool probe_pf)250 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
251 {
252 struct otx2_hw *hw = &vf->hw;
253 struct msg_req *req;
254 u64 mbox_int_mask;
255 char *irq_name;
256 int err;
257
258 mbox_int_mask = !is_cn20k(vf->pdev) ? BIT_ULL(0) :
259 BIT_ULL(0) | BIT_ULL(1) |
260 BIT_ULL(2) | BIT_ULL(3);
261
262 /* Clear stale mailbox interrupt state before installing the handler. */
263 otx2_write64(vf, RVU_VF_INT, mbox_int_mask);
264
265 /* Register mailbox interrupt handler */
266 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
267 snprintf(irq_name, NAME_SIZE, "RVUVF%d AFVF Mbox", ((vf->pcifunc &
268 RVU_PFVF_FUNC_MASK) - 1));
269
270 if (!is_cn20k(vf->pdev)) {
271 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
272 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf);
273 } else {
274 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
275 vf->hw_ops->vfaf_mbox_intr_handler, 0, irq_name,
276 vf);
277 }
278
279 if (err) {
280 dev_err(vf->dev,
281 "RVUPF: IRQ registration failed for VFAF mbox irq\n");
282 return err;
283 }
284
285 /* Enable mailbox interrupt for msgs coming from PF. */
286 otx2_write64(vf, RVU_VF_INT_ENA_W1S, mbox_int_mask);
287
288 if (!probe_pf)
289 return 0;
290
291 /* Check mailbox communication with PF */
292 req = otx2_mbox_alloc_msg_ready(&vf->mbox);
293 if (!req) {
294 otx2vf_disable_mbox_intr(vf);
295 return -ENOMEM;
296 }
297
298 err = otx2_sync_mbox_msg(&vf->mbox);
299 if (err) {
300 dev_warn(vf->dev,
301 "AF not responding to mailbox, deferring probe\n");
302 otx2vf_disable_mbox_intr(vf);
303 return -EPROBE_DEFER;
304 }
305 return 0;
306 }
307
otx2vf_vfaf_mbox_destroy(struct otx2_nic * vf)308 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
309 {
310 struct mbox *mbox = &vf->mbox;
311
312 if (vf->mbox_wq) {
313 destroy_workqueue(vf->mbox_wq);
314 vf->mbox_wq = NULL;
315 }
316
317 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
318 iounmap((void __iomem *)mbox->mbox.hwbase);
319
320 otx2_mbox_destroy(&mbox->mbox);
321 otx2_mbox_destroy(&mbox->mbox_up);
322 }
323
otx2vf_vfaf_mbox_init(struct otx2_nic * vf)324 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
325 {
326 struct mbox *mbox = &vf->mbox;
327 void __iomem *hwbase;
328 int err;
329
330 mbox->pfvf = vf;
331 vf->mbox_wq = alloc_ordered_workqueue("otx2_vfaf_mailbox",
332 WQ_HIGHPRI | WQ_MEM_RECLAIM);
333 if (!vf->mbox_wq)
334 return -ENOMEM;
335
336 /* For cn20k platform, VF mailbox region is in dram aliased from AF
337 * VF MBOX ADDR, MBOX is a separate RVU block.
338 */
339 if (is_cn20k(vf->pdev)) {
340 hwbase = vf->reg_base + RVU_VF_MBOX_REGION + ((u64)BLKADDR_MBOX <<
341 RVU_FUNC_BLKADDR_SHIFT);
342 } else if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
343 /* For cn10k platform, VF mailbox region is in its BAR2
344 * register space
345 */
346 hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
347 } else {
348 /* Mailbox is a reserved memory (in RAM) region shared between
349 * admin function (i.e PF0) and this VF, shouldn't be mapped as
350 * device memory to allow unaligned accesses.
351 */
352 hwbase = ioremap_wc(pci_resource_start(vf->pdev,
353 PCI_MBOX_BAR_NUM),
354 pci_resource_len(vf->pdev,
355 PCI_MBOX_BAR_NUM));
356 if (!hwbase) {
357 dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
358 err = -ENOMEM;
359 goto exit;
360 }
361 }
362
363 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
364 MBOX_DIR_VFPF, 1);
365 if (err)
366 goto exit;
367
368 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base,
369 MBOX_DIR_VFPF_UP, 1);
370 if (err)
371 goto exit;
372
373 err = otx2_mbox_bbuf_init(mbox, vf->pdev);
374 if (err)
375 goto exit;
376
377 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler);
378 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler);
379 mutex_init(&mbox->lock);
380
381 return 0;
382 exit:
383 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
384 iounmap(hwbase);
385 destroy_workqueue(vf->mbox_wq);
386 return err;
387 }
388
otx2vf_open(struct net_device * netdev)389 static int otx2vf_open(struct net_device *netdev)
390 {
391 struct otx2_nic *vf;
392 int err;
393
394 err = otx2_open(netdev);
395 if (err)
396 return err;
397
398 /* LBKs do not receive link events so tell everyone we are up here */
399 vf = netdev_priv(netdev);
400 if (is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev)) {
401 pr_info("%s NIC Link is UP\n", netdev->name);
402 netif_carrier_on(netdev);
403 netif_tx_start_all_queues(netdev);
404 }
405
406 return 0;
407 }
408
otx2vf_stop(struct net_device * netdev)409 static int otx2vf_stop(struct net_device *netdev)
410 {
411 return otx2_stop(netdev);
412 }
413
otx2vf_xmit(struct sk_buff * skb,struct net_device * netdev)414 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev)
415 {
416 struct otx2_nic *vf = netdev_priv(netdev);
417 int qidx = skb_get_queue_mapping(skb);
418 struct otx2_dev_stats *dev_stats;
419 struct otx2_snd_queue *sq;
420 struct netdev_queue *txq;
421
422 /* Check for minimum and maximum packet length */
423 if (skb->len <= ETH_HLEN ||
424 (!skb_shinfo(skb)->gso_size && skb->len > vf->tx_max_pktlen)) {
425 dev_stats = &vf->hw.dev_stats;
426 atomic_long_inc(&dev_stats->tx_discards);
427 dev_kfree_skb(skb);
428 return NETDEV_TX_OK;
429 }
430
431 sq = &vf->qset.sq[qidx];
432 txq = netdev_get_tx_queue(netdev, qidx);
433
434 if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) {
435 netif_tx_stop_queue(txq);
436
437 /* Check again, incase SQBs got freed up */
438 smp_mb();
439 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
440 > sq->sqe_thresh)
441 netif_tx_wake_queue(txq);
442
443 return NETDEV_TX_BUSY;
444 }
445
446 return NETDEV_TX_OK;
447 }
448
otx2vf_set_rx_mode(struct net_device * netdev)449 static void otx2vf_set_rx_mode(struct net_device *netdev)
450 {
451 struct otx2_nic *vf = netdev_priv(netdev);
452
453 queue_work(vf->otx2_wq, &vf->rx_mode_work);
454 }
455
otx2vf_do_set_rx_mode(struct work_struct * work)456 static void otx2vf_do_set_rx_mode(struct work_struct *work)
457 {
458 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work);
459 struct net_device *netdev = vf->netdev;
460 unsigned int flags = netdev->flags;
461 struct nix_rx_mode *req;
462
463 mutex_lock(&vf->mbox.lock);
464
465 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox);
466 if (!req) {
467 mutex_unlock(&vf->mbox.lock);
468 return;
469 }
470
471 req->mode = NIX_RX_MODE_UCAST;
472
473 if (flags & IFF_PROMISC)
474 req->mode |= NIX_RX_MODE_PROMISC;
475 if (flags & (IFF_ALLMULTI | IFF_MULTICAST))
476 req->mode |= NIX_RX_MODE_ALLMULTI;
477
478 req->mode |= NIX_RX_MODE_USE_MCE;
479
480 otx2_sync_mbox_msg(&vf->mbox);
481
482 mutex_unlock(&vf->mbox.lock);
483 }
484
otx2vf_change_mtu(struct net_device * netdev,int new_mtu)485 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu)
486 {
487 bool if_up = netif_running(netdev);
488 int err = 0;
489
490 if (if_up)
491 otx2vf_stop(netdev);
492
493 netdev_info(netdev, "Changing MTU from %d to %d\n",
494 netdev->mtu, new_mtu);
495 WRITE_ONCE(netdev->mtu, new_mtu);
496
497 if (if_up)
498 err = otx2vf_open(netdev);
499
500 return err;
501 }
502
otx2vf_reset_task(struct work_struct * work)503 static void otx2vf_reset_task(struct work_struct *work)
504 {
505 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task);
506
507 rtnl_lock();
508
509 if (netif_running(vf->netdev)) {
510 otx2vf_stop(vf->netdev);
511 vf->reset_count++;
512 otx2vf_open(vf->netdev);
513 }
514
515 rtnl_unlock();
516 }
517
otx2vf_set_features(struct net_device * netdev,netdev_features_t features)518 static int otx2vf_set_features(struct net_device *netdev,
519 netdev_features_t features)
520 {
521 return otx2_handle_ntuple_tc_features(netdev, features);
522 }
523
524 static const struct net_device_ops otx2vf_netdev_ops = {
525 .ndo_open = otx2vf_open,
526 .ndo_stop = otx2vf_stop,
527 .ndo_start_xmit = otx2vf_xmit,
528 .ndo_select_queue = otx2_select_queue,
529 .ndo_set_rx_mode = otx2vf_set_rx_mode,
530 .ndo_set_mac_address = otx2_set_mac_address,
531 .ndo_change_mtu = otx2vf_change_mtu,
532 .ndo_set_features = otx2vf_set_features,
533 .ndo_get_stats64 = otx2_get_stats64,
534 .ndo_tx_timeout = otx2_tx_timeout,
535 .ndo_setup_tc = otx2_setup_tc,
536 .ndo_hwtstamp_get = otx2_config_hwtstamp_get,
537 .ndo_hwtstamp_set = otx2_config_hwtstamp_set,
538 };
539
otx2_vf_wq_init(struct otx2_nic * vf)540 static int otx2_vf_wq_init(struct otx2_nic *vf)
541 {
542 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq");
543 if (!vf->otx2_wq)
544 return -ENOMEM;
545
546 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode);
547 INIT_WORK(&vf->reset_task, otx2vf_reset_task);
548 return 0;
549 }
550
otx2vf_realloc_msix_vectors(struct otx2_nic * vf)551 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf)
552 {
553 struct otx2_hw *hw = &vf->hw;
554 int num_vec, err;
555
556 num_vec = hw->nix_msixoff;
557 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
558
559 otx2vf_disable_mbox_intr(vf);
560 pci_free_irq_vectors(hw->pdev);
561 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
562 if (err < 0) {
563 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n",
564 __func__, num_vec);
565 return err;
566 }
567
568 return otx2vf_register_mbox_intr(vf, false);
569 }
570
otx2vf_probe(struct pci_dev * pdev,const struct pci_device_id * id)571 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
572 {
573 int num_vec = pci_msix_vec_count(pdev);
574 struct device *dev = &pdev->dev;
575 int err, qcount, qos_txqs;
576 struct net_device *netdev;
577 struct otx2_nic *vf;
578 struct otx2_hw *hw;
579
580 err = pcim_enable_device(pdev);
581 if (err) {
582 dev_err(dev, "Failed to enable PCI device\n");
583 return err;
584 }
585
586 err = pcim_request_all_regions(pdev, DRV_NAME);
587 if (err) {
588 dev_err(dev, "PCI request regions failed 0x%x\n", err);
589 return err;
590 }
591
592 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
593 if (err) {
594 dev_err(dev, "DMA mask config failed, abort\n");
595 return err;
596 }
597
598 pci_set_master(pdev);
599
600 qcount = num_online_cpus();
601 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES);
602 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount);
603 if (!netdev)
604 return -ENOMEM;
605
606 pci_set_drvdata(pdev, netdev);
607 SET_NETDEV_DEV(netdev, &pdev->dev);
608 vf = netdev_priv(netdev);
609 vf->netdev = netdev;
610 vf->pdev = pdev;
611 vf->dev = dev;
612 vf->iommu_domain = iommu_get_domain_for_dev(dev);
613
614 vf->flags |= OTX2_FLAG_INTF_DOWN;
615 hw = &vf->hw;
616 hw->pdev = vf->pdev;
617 hw->rx_queues = qcount;
618 hw->tx_queues = qcount;
619 hw->max_queues = qcount;
620 hw->non_qos_queues = qcount;
621 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN;
622 /* Use CQE of 128 byte descriptor size by default */
623 hw->xqe_size = 128;
624
625 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
626 GFP_KERNEL);
627 if (!hw->irq_name) {
628 err = -ENOMEM;
629 goto err_free_netdev;
630 }
631
632 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
633 sizeof(cpumask_var_t), GFP_KERNEL);
634 if (!hw->affinity_mask) {
635 err = -ENOMEM;
636 goto err_free_netdev;
637 }
638
639 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
640 if (err < 0) {
641 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
642 __func__, num_vec);
643 goto err_free_netdev;
644 }
645
646 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
647 if (!vf->reg_base) {
648 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
649 err = -ENOMEM;
650 goto err_free_irq_vectors;
651 }
652
653 otx2_setup_dev_hw_settings(vf);
654
655 if (is_cn20k(vf->pdev))
656 cn20k_init(vf);
657 else
658 otx2_init_hw_ops(vf);
659
660 /* Init VF <=> PF mailbox stuff */
661 err = otx2vf_vfaf_mbox_init(vf);
662 if (err)
663 goto err_free_irq_vectors;
664
665 /* Register mailbox interrupt */
666 err = otx2vf_register_mbox_intr(vf, true);
667 if (err)
668 goto err_mbox_destroy;
669
670 /* Request AF to attach NPA and LIX LFs to this AF */
671 err = otx2_attach_npa_nix(vf);
672 if (err)
673 goto err_disable_mbox_intr;
674
675 err = otx2vf_realloc_msix_vectors(vf);
676 if (err)
677 goto err_detach_rsrc;
678
679 err = otx2_set_real_num_queues(netdev, qcount, qcount);
680 if (err)
681 goto err_detach_rsrc;
682
683 err = cn10k_lmtst_init(vf);
684 if (err)
685 goto err_detach_rsrc;
686
687 /* Don't check for error. Proceed without ptp */
688 otx2_ptp_init(vf);
689
690 /* Assign default mac address */
691 otx2_get_mac_from_af(netdev);
692
693 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
694 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
695 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
696 NETIF_F_GSO_UDP_L4;
697 netdev->features = netdev->hw_features;
698 /* Support TSO on tag interface */
699 netdev->vlan_features |= netdev->features;
700 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
701 NETIF_F_HW_VLAN_STAG_TX;
702 netdev->features |= netdev->hw_features;
703
704 netdev->hw_features |= NETIF_F_NTUPLE;
705 netdev->hw_features |= NETIF_F_RXALL;
706 netdev->hw_features |= NETIF_F_HW_TC;
707
708 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
709 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
710
711 netdev->netdev_ops = &otx2vf_netdev_ops;
712
713 netdev->min_mtu = OTX2_MIN_MTU;
714 netdev->max_mtu = otx2_get_max_mtu(vf);
715 hw->max_mtu = netdev->max_mtu;
716
717 /* To distinguish, for LBK VFs set netdev name explicitly */
718 if (is_otx2_lbkvf(vf->pdev)) {
719 int n;
720
721 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;
722 /* Need to subtract 1 to get proper VF number */
723 n -= 1;
724 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
725 }
726
727 if (is_otx2_sdp_rep(vf->pdev)) {
728 int n;
729
730 n = vf->pcifunc & RVU_PFVF_FUNC_MASK;
731 n -= 1;
732 snprintf(netdev->name, sizeof(netdev->name), "sdp%d-%d",
733 pdev->bus->number, n);
734 }
735
736 err = cn10k_ipsec_init(netdev);
737 if (err)
738 goto err_ptp_destroy;
739
740 err = otx2_vf_wq_init(vf);
741 if (err)
742 goto err_ipsec_clean;
743
744 err = register_netdev(netdev);
745 if (err) {
746 dev_err(dev, "Failed to register netdevice\n");
747 goto err_wq_destroy;
748 }
749
750 otx2vf_set_ethtool_ops(netdev);
751
752 err = otx2vf_mcam_flow_init(vf);
753 if (err)
754 goto err_unreg_netdev;
755
756 err = otx2_init_tc(vf);
757 if (err)
758 goto err_unreg_netdev;
759
760 err = otx2_register_dl(vf);
761 if (err)
762 goto err_shutdown_tc;
763
764 vf->af_xdp_zc_qidx = bitmap_zalloc(qcount, GFP_KERNEL);
765 if (!vf->af_xdp_zc_qidx) {
766 err = -ENOMEM;
767 goto err_unreg_devlink;
768 }
769
770 #ifdef CONFIG_DCB
771 /* Priority flow control is not supported for LBK and SDP vf(s) */
772 if (!(is_otx2_lbkvf(vf->pdev) || is_otx2_sdp_rep(vf->pdev))) {
773 err = otx2_dcbnl_set_ops(netdev);
774 if (err)
775 goto err_free_zc_bmap;
776 }
777 #endif
778 otx2_qos_init(vf, qos_txqs);
779
780 return 0;
781
782 #ifdef CONFIG_DCB
783 err_free_zc_bmap:
784 bitmap_free(vf->af_xdp_zc_qidx);
785 #endif
786 err_unreg_devlink:
787 otx2_unregister_dl(vf);
788 err_shutdown_tc:
789 otx2_shutdown_tc(vf);
790 err_unreg_netdev:
791 unregister_netdev(netdev);
792 err_wq_destroy:
793 cancel_work_sync(&vf->reset_task);
794 cancel_work_sync(&vf->rx_mode_work);
795 destroy_workqueue(vf->otx2_wq);
796 err_ipsec_clean:
797 cn10k_ipsec_clean(vf);
798 err_ptp_destroy:
799 otx2_ptp_destroy(vf);
800 err_detach_rsrc:
801 free_percpu(vf->hw.lmt_info);
802 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
803 qmem_free(vf->dev, vf->dync_lmt);
804 otx2_detach_resources(&vf->mbox);
805 err_disable_mbox_intr:
806 otx2vf_disable_mbox_intr(vf);
807 err_mbox_destroy:
808 otx2vf_vfaf_mbox_destroy(vf);
809 err_free_irq_vectors:
810 pci_free_irq_vectors(hw->pdev);
811 err_free_netdev:
812 pci_set_drvdata(pdev, NULL);
813 free_netdev(netdev);
814 return err;
815 }
816
otx2vf_remove(struct pci_dev * pdev)817 static void otx2vf_remove(struct pci_dev *pdev)
818 {
819 struct net_device *netdev = pci_get_drvdata(pdev);
820 struct otx2_nic *vf;
821
822 if (!netdev)
823 return;
824
825 vf = netdev_priv(netdev);
826
827 /* Disable 802.3x pause frames */
828 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
829 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
830 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
831 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
832 otx2_config_pause_frm(vf);
833 }
834
835 #ifdef CONFIG_DCB
836 /* Disable PFC config */
837 if (vf->pfc_en) {
838 vf->pfc_en = 0;
839 otx2_config_priority_flow_ctrl(vf);
840 }
841 #endif
842
843 otx2_unregister_dl(vf);
844 unregister_netdev(netdev);
845 if (vf->otx2_wq) {
846 cancel_work_sync(&vf->reset_task);
847 cancel_work_sync(&vf->rx_mode_work);
848 destroy_workqueue(vf->otx2_wq);
849 }
850 cn10k_ipsec_clean(vf);
851 otx2_ptp_destroy(vf);
852 otx2_mcam_flow_del(vf);
853 otx2_shutdown_tc(vf);
854 otx2_shutdown_qos(vf);
855 otx2_detach_resources(&vf->mbox);
856 otx2vf_disable_mbox_intr(vf);
857 free_percpu(vf->hw.lmt_info);
858 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
859 qmem_free(vf->dev, vf->dync_lmt);
860 otx2vf_vfaf_mbox_destroy(vf);
861 pci_free_irq_vectors(vf->pdev);
862 bitmap_free(vf->af_xdp_zc_qidx);
863 pci_set_drvdata(pdev, NULL);
864 free_netdev(netdev);
865 }
866
867 static struct pci_driver otx2vf_driver = {
868 .name = DRV_NAME,
869 .id_table = otx2_vf_id_table,
870 .probe = otx2vf_probe,
871 .remove = otx2vf_remove,
872 .shutdown = otx2vf_remove,
873 };
874
otx2vf_init_module(void)875 static int __init otx2vf_init_module(void)
876 {
877 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
878
879 return pci_register_driver(&otx2vf_driver);
880 }
881
otx2vf_cleanup_module(void)882 static void __exit otx2vf_cleanup_module(void)
883 {
884 pci_unregister_driver(&otx2vf_driver);
885 }
886
887 module_init(otx2vf_init_module);
888 module_exit(otx2vf_cleanup_module);
889