1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
4 * Author: Chen Huacai, chenhc@lemote.com
5 */
6
7 #include <irq.h>
8 #include <linux/init.h>
9 #include <linux/cpu.h>
10 #include <linux/sched.h>
11 #include <linux/sched/hotplug.h>
12 #include <linux/sched/task_stack.h>
13 #include <linux/smp.h>
14 #include <linux/cpufreq.h>
15 #include <linux/kexec.h>
16 #include <asm/processor.h>
17 #include <asm/smp.h>
18 #include <asm/time.h>
19 #include <asm/tlbflush.h>
20 #include <asm/cacheflush.h>
21 #include <loongson.h>
22 #include <loongson_regs.h>
23 #include <workarounds.h>
24
25 #include "smp.h"
26
27 DEFINE_PER_CPU(int, cpu_state);
28
29 #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
30
31 static void __iomem *ipi_set0_regs[16];
32 static void __iomem *ipi_clear0_regs[16];
33 static void __iomem *ipi_status0_regs[16];
34 static void __iomem *ipi_en0_regs[16];
35 static void __iomem *ipi_mailbox_buf[16];
36
37 static u32 (*ipi_read_clear)(int cpu);
38 static void (*ipi_write_action)(int cpu, u32 action);
39 static void (*ipi_write_enable)(int cpu);
40 static void (*ipi_clear_buf)(int cpu);
41 static void (*ipi_write_buf)(int cpu, struct task_struct *idle);
42
43 /* send mail via Mail_Send register for 3A4000+ CPU */
csr_mail_send(uint64_t data,int cpu,int mailbox)44 static void csr_mail_send(uint64_t data, int cpu, int mailbox)
45 {
46 uint64_t val;
47
48 /* send high 32 bits */
49 val = CSR_MAIL_SEND_BLOCK;
50 val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
51 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
52 val |= (data & CSR_MAIL_SEND_H32_MASK);
53 csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
54
55 /* send low 32 bits */
56 val = CSR_MAIL_SEND_BLOCK;
57 val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
58 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
59 val |= (data << CSR_MAIL_SEND_BUF_SHIFT);
60 csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
61 };
62
csr_ipi_read_clear(int cpu)63 static u32 csr_ipi_read_clear(int cpu)
64 {
65 u32 action;
66
67 /* Load the ipi register to figure out what we're supposed to do */
68 action = csr_readl(LOONGSON_CSR_IPI_STATUS);
69 /* Clear the ipi register to clear the interrupt */
70 csr_writel(action, LOONGSON_CSR_IPI_CLEAR);
71
72 return action;
73 }
74
csr_ipi_write_action(int cpu,u32 action)75 static void csr_ipi_write_action(int cpu, u32 action)
76 {
77 unsigned int irq = 0;
78
79 while ((irq = ffs(action))) {
80 uint32_t val = CSR_IPI_SEND_BLOCK;
81 val |= (irq - 1);
82 val |= (cpu << CSR_IPI_SEND_CPU_SHIFT);
83 csr_writel(val, LOONGSON_CSR_IPI_SEND);
84 action &= ~BIT(irq - 1);
85 }
86 }
87
csr_ipi_write_enable(int cpu)88 static void csr_ipi_write_enable(int cpu)
89 {
90 csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN);
91 }
92
csr_ipi_clear_buf(int cpu)93 static void csr_ipi_clear_buf(int cpu)
94 {
95 csr_writeq(0, LOONGSON_CSR_MAIL_BUF0);
96 }
97
csr_ipi_write_buf(int cpu,struct task_struct * idle)98 static void csr_ipi_write_buf(int cpu, struct task_struct *idle)
99 {
100 unsigned long startargs[4];
101
102 /* startargs[] are initial PC, SP and GP for secondary CPU */
103 startargs[0] = (unsigned long)&smp_bootstrap;
104 startargs[1] = (unsigned long)__KSTK_TOS(idle);
105 startargs[2] = (unsigned long)task_thread_info(idle);
106 startargs[3] = 0;
107
108 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
109 cpu, startargs[0], startargs[1], startargs[2]);
110
111 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3);
112 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2);
113 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1);
114 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0);
115 }
116
legacy_ipi_read_clear(int cpu)117 static u32 legacy_ipi_read_clear(int cpu)
118 {
119 u32 action;
120
121 /* Load the ipi register to figure out what we're supposed to do */
122 action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]);
123 /* Clear the ipi register to clear the interrupt */
124 writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]);
125 nudge_writes();
126
127 return action;
128 }
129
legacy_ipi_write_action(int cpu,u32 action)130 static void legacy_ipi_write_action(int cpu, u32 action)
131 {
132 writel_relaxed((u32)action, ipi_set0_regs[cpu]);
133 nudge_writes();
134 }
135
legacy_ipi_write_enable(int cpu)136 static void legacy_ipi_write_enable(int cpu)
137 {
138 writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
139 }
140
legacy_ipi_clear_buf(int cpu)141 static void legacy_ipi_clear_buf(int cpu)
142 {
143 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
144 }
145
legacy_ipi_write_buf(int cpu,struct task_struct * idle)146 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
147 {
148 unsigned long startargs[4];
149
150 /* startargs[] are initial PC, SP and GP for secondary CPU */
151 startargs[0] = (unsigned long)&smp_bootstrap;
152 startargs[1] = (unsigned long)__KSTK_TOS(idle);
153 startargs[2] = (unsigned long)task_thread_info(idle);
154 startargs[3] = 0;
155
156 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
157 cpu, startargs[0], startargs[1], startargs[2]);
158
159 writeq_relaxed(startargs[3],
160 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
161 writeq_relaxed(startargs[2],
162 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
163 writeq_relaxed(startargs[1],
164 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
165 writeq_relaxed(startargs[0],
166 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
167 nudge_writes();
168 }
169
csr_ipi_probe(void)170 static void csr_ipi_probe(void)
171 {
172 if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) {
173 ipi_read_clear = csr_ipi_read_clear;
174 ipi_write_action = csr_ipi_write_action;
175 ipi_write_enable = csr_ipi_write_enable;
176 ipi_clear_buf = csr_ipi_clear_buf;
177 ipi_write_buf = csr_ipi_write_buf;
178 } else {
179 ipi_read_clear = legacy_ipi_read_clear;
180 ipi_write_action = legacy_ipi_write_action;
181 ipi_write_enable = legacy_ipi_write_enable;
182 ipi_clear_buf = legacy_ipi_clear_buf;
183 ipi_write_buf = legacy_ipi_write_buf;
184 }
185 }
186
ipi_set0_regs_init(void)187 static void ipi_set0_regs_init(void)
188 {
189 ipi_set0_regs[0] = (void __iomem *)
190 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
191 ipi_set0_regs[1] = (void __iomem *)
192 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
193 ipi_set0_regs[2] = (void __iomem *)
194 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
195 ipi_set0_regs[3] = (void __iomem *)
196 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
197 ipi_set0_regs[4] = (void __iomem *)
198 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
199 ipi_set0_regs[5] = (void __iomem *)
200 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
201 ipi_set0_regs[6] = (void __iomem *)
202 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
203 ipi_set0_regs[7] = (void __iomem *)
204 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
205 ipi_set0_regs[8] = (void __iomem *)
206 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
207 ipi_set0_regs[9] = (void __iomem *)
208 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
209 ipi_set0_regs[10] = (void __iomem *)
210 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
211 ipi_set0_regs[11] = (void __iomem *)
212 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
213 ipi_set0_regs[12] = (void __iomem *)
214 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
215 ipi_set0_regs[13] = (void __iomem *)
216 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
217 ipi_set0_regs[14] = (void __iomem *)
218 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
219 ipi_set0_regs[15] = (void __iomem *)
220 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
221 }
222
ipi_clear0_regs_init(void)223 static void ipi_clear0_regs_init(void)
224 {
225 ipi_clear0_regs[0] = (void __iomem *)
226 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
227 ipi_clear0_regs[1] = (void __iomem *)
228 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
229 ipi_clear0_regs[2] = (void __iomem *)
230 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
231 ipi_clear0_regs[3] = (void __iomem *)
232 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
233 ipi_clear0_regs[4] = (void __iomem *)
234 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
235 ipi_clear0_regs[5] = (void __iomem *)
236 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
237 ipi_clear0_regs[6] = (void __iomem *)
238 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
239 ipi_clear0_regs[7] = (void __iomem *)
240 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
241 ipi_clear0_regs[8] = (void __iomem *)
242 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
243 ipi_clear0_regs[9] = (void __iomem *)
244 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
245 ipi_clear0_regs[10] = (void __iomem *)
246 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
247 ipi_clear0_regs[11] = (void __iomem *)
248 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
249 ipi_clear0_regs[12] = (void __iomem *)
250 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
251 ipi_clear0_regs[13] = (void __iomem *)
252 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
253 ipi_clear0_regs[14] = (void __iomem *)
254 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
255 ipi_clear0_regs[15] = (void __iomem *)
256 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
257 }
258
ipi_status0_regs_init(void)259 static void ipi_status0_regs_init(void)
260 {
261 ipi_status0_regs[0] = (void __iomem *)
262 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
263 ipi_status0_regs[1] = (void __iomem *)
264 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
265 ipi_status0_regs[2] = (void __iomem *)
266 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
267 ipi_status0_regs[3] = (void __iomem *)
268 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
269 ipi_status0_regs[4] = (void __iomem *)
270 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
271 ipi_status0_regs[5] = (void __iomem *)
272 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
273 ipi_status0_regs[6] = (void __iomem *)
274 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
275 ipi_status0_regs[7] = (void __iomem *)
276 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
277 ipi_status0_regs[8] = (void __iomem *)
278 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
279 ipi_status0_regs[9] = (void __iomem *)
280 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
281 ipi_status0_regs[10] = (void __iomem *)
282 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
283 ipi_status0_regs[11] = (void __iomem *)
284 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
285 ipi_status0_regs[12] = (void __iomem *)
286 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
287 ipi_status0_regs[13] = (void __iomem *)
288 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
289 ipi_status0_regs[14] = (void __iomem *)
290 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
291 ipi_status0_regs[15] = (void __iomem *)
292 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
293 }
294
ipi_en0_regs_init(void)295 static void ipi_en0_regs_init(void)
296 {
297 ipi_en0_regs[0] = (void __iomem *)
298 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
299 ipi_en0_regs[1] = (void __iomem *)
300 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
301 ipi_en0_regs[2] = (void __iomem *)
302 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
303 ipi_en0_regs[3] = (void __iomem *)
304 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
305 ipi_en0_regs[4] = (void __iomem *)
306 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
307 ipi_en0_regs[5] = (void __iomem *)
308 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
309 ipi_en0_regs[6] = (void __iomem *)
310 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
311 ipi_en0_regs[7] = (void __iomem *)
312 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
313 ipi_en0_regs[8] = (void __iomem *)
314 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
315 ipi_en0_regs[9] = (void __iomem *)
316 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
317 ipi_en0_regs[10] = (void __iomem *)
318 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
319 ipi_en0_regs[11] = (void __iomem *)
320 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
321 ipi_en0_regs[12] = (void __iomem *)
322 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
323 ipi_en0_regs[13] = (void __iomem *)
324 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
325 ipi_en0_regs[14] = (void __iomem *)
326 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
327 ipi_en0_regs[15] = (void __iomem *)
328 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
329 }
330
ipi_mailbox_buf_init(void)331 static void ipi_mailbox_buf_init(void)
332 {
333 ipi_mailbox_buf[0] = (void __iomem *)
334 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
335 ipi_mailbox_buf[1] = (void __iomem *)
336 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
337 ipi_mailbox_buf[2] = (void __iomem *)
338 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
339 ipi_mailbox_buf[3] = (void __iomem *)
340 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
341 ipi_mailbox_buf[4] = (void __iomem *)
342 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
343 ipi_mailbox_buf[5] = (void __iomem *)
344 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
345 ipi_mailbox_buf[6] = (void __iomem *)
346 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
347 ipi_mailbox_buf[7] = (void __iomem *)
348 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
349 ipi_mailbox_buf[8] = (void __iomem *)
350 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
351 ipi_mailbox_buf[9] = (void __iomem *)
352 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
353 ipi_mailbox_buf[10] = (void __iomem *)
354 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
355 ipi_mailbox_buf[11] = (void __iomem *)
356 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
357 ipi_mailbox_buf[12] = (void __iomem *)
358 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
359 ipi_mailbox_buf[13] = (void __iomem *)
360 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
361 ipi_mailbox_buf[14] = (void __iomem *)
362 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
363 ipi_mailbox_buf[15] = (void __iomem *)
364 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
365 }
366
367 /*
368 * Simple enough, just poke the appropriate ipi register
369 */
loongson3_send_ipi_single(int cpu,unsigned int action)370 static void loongson3_send_ipi_single(int cpu, unsigned int action)
371 {
372 ipi_write_action(cpu_logical_map(cpu), (u32)action);
373 }
374
375 static void
loongson3_send_ipi_mask(const struct cpumask * mask,unsigned int action)376 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
377 {
378 unsigned int i;
379
380 for_each_cpu(i, mask)
381 ipi_write_action(cpu_logical_map(i), (u32)action);
382 }
383
384 #ifdef CONFIG_IRQ_WORK
arch_irq_work_raise(void)385 void arch_irq_work_raise(void)
386 {
387 loongson3_send_ipi_single(smp_processor_id(), SMP_IRQ_WORK);
388 }
389 #endif
390
loongson3_ipi_interrupt(int irq,void * dev_id)391 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
392 {
393 int cpu = smp_processor_id();
394 unsigned int action;
395
396 action = ipi_read_clear(cpu);
397
398 if (action & SMP_RESCHEDULE_YOURSELF)
399 scheduler_ipi();
400
401 if (action & SMP_CALL_FUNCTION) {
402 irq_enter();
403 generic_smp_call_function_interrupt();
404 irq_exit();
405 }
406
407 if (action & SMP_IRQ_WORK)
408 irq_work_run();
409
410 return IRQ_HANDLED;
411 }
412
413 /*
414 * SMP init and finish on secondary CPUs
415 */
loongson3_init_secondary(void)416 static void loongson3_init_secondary(void)
417 {
418 unsigned int cpu = smp_processor_id();
419 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
420 STATUSF_IP3 | STATUSF_IP2;
421
422 /* Set interrupt mask, but don't enable */
423 change_c0_status(ST0_IM, imask);
424 ipi_write_enable(cpu);
425
426 per_cpu(cpu_state, cpu) = CPU_ONLINE;
427 cpu_set_core(&cpu_data[cpu],
428 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
429 cpu_data[cpu].package =
430 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
431 }
432
loongson3_smp_finish(void)433 static void loongson3_smp_finish(void)
434 {
435 int cpu = smp_processor_id();
436
437 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
438 local_irq_enable();
439 ipi_clear_buf(cpu);
440
441 pr_info("CPU#%d finished, CP0_ST=%x\n",
442 smp_processor_id(), read_c0_status());
443 }
444
loongson3_smp_setup(void)445 static void __init loongson3_smp_setup(void)
446 {
447 int i = 0, num = 0; /* i: physical id, num: logical id */
448 int max_cpus = 0;
449
450 init_cpu_possible(cpu_none_mask);
451
452 for (i = 0; i < ARRAY_SIZE(smp_group); i++) {
453 if (!smp_group[i])
454 break;
455 max_cpus += loongson_sysconf.cores_per_node;
456 }
457
458 if (max_cpus < loongson_sysconf.nr_cpus) {
459 pr_err("SMP Groups are less than the number of CPUs\n");
460 loongson_sysconf.nr_cpus = max_cpus ? max_cpus : 1;
461 }
462
463 /* For unified kernel, NR_CPUS is the maximum possible value,
464 * loongson_sysconf.nr_cpus is the really present value
465 */
466 i = 0;
467 while (i < loongson_sysconf.nr_cpus) {
468 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
469 /* Reserved physical CPU cores */
470 __cpu_number_map[i] = -1;
471 } else {
472 __cpu_number_map[i] = num;
473 __cpu_logical_map[num] = i;
474 set_cpu_possible(num, true);
475 /* Loongson processors are always grouped by 4 */
476 cpu_set_cluster(&cpu_data[num], i / 4);
477 num++;
478 }
479 i++;
480 }
481 pr_info("Detected %i available CPU(s)\n", num);
482
483 while (num < loongson_sysconf.nr_cpus) {
484 __cpu_logical_map[num] = -1;
485 num++;
486 }
487 csr_ipi_probe();
488 ipi_set0_regs_init();
489 ipi_clear0_regs_init();
490 ipi_status0_regs_init();
491 ipi_en0_regs_init();
492 ipi_mailbox_buf_init();
493 if (smp_group[0])
494 ipi_write_enable(0);
495
496 cpu_set_core(&cpu_data[0],
497 cpu_logical_map(0) % loongson_sysconf.cores_per_package);
498 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
499 }
500
loongson3_prepare_cpus(unsigned int max_cpus)501 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
502 {
503 if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
504 IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
505 pr_err("Failed to request IPI IRQ\n");
506 init_cpu_present(cpu_possible_mask);
507 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
508 }
509
510 /*
511 * Setup the PC, SP, and GP of a secondary processor and start it running!
512 */
loongson3_boot_secondary(int cpu,struct task_struct * idle)513 static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
514 {
515 pr_info("Booting CPU#%d...\n", cpu);
516
517 ipi_write_buf(cpu, idle);
518
519 return 0;
520 }
521
522 #ifdef CONFIG_HOTPLUG_CPU
523
loongson3_cpu_disable(void)524 static int loongson3_cpu_disable(void)
525 {
526 unsigned long flags;
527 unsigned int cpu = smp_processor_id();
528
529 set_cpu_online(cpu, false);
530 calculate_cpu_foreign_map();
531 local_irq_save(flags);
532 clear_c0_status(ST0_IM);
533 local_irq_restore(flags);
534 local_flush_tlb_all();
535
536 return 0;
537 }
538
539
loongson3_cpu_die(unsigned int cpu)540 static void loongson3_cpu_die(unsigned int cpu)
541 {
542 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
543 cpu_relax();
544
545 mb();
546 }
547
548 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
549 * flush all L1 entries at first. Then, another core (usually Core 0) can
550 * safely disable the clock of the target core. loongson3_play_dead() is
551 * called via CKSEG1 (uncached and unmmaped)
552 */
loongson3_type1_play_dead(int * state_addr)553 static void loongson3_type1_play_dead(int *state_addr)
554 {
555 register int val;
556 register long cpuid, core, node, count;
557 register void *addr, *base, *initfunc;
558
559 __asm__ __volatile__(
560 " .set push \n"
561 " .set noreorder \n"
562 " li %[addr], 0x80000000 \n" /* KSEG0 */
563 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
564 " cache 0, 1(%[addr]) \n"
565 " cache 0, 2(%[addr]) \n"
566 " cache 0, 3(%[addr]) \n"
567 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
568 " cache 1, 1(%[addr]) \n"
569 " cache 1, 2(%[addr]) \n"
570 " cache 1, 3(%[addr]) \n"
571 " addiu %[sets], %[sets], -1 \n"
572 " bnez %[sets], 1b \n"
573 " addiu %[addr], %[addr], 0x20 \n"
574 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
575 " sw %[val], (%[state_addr]) \n"
576 " sync \n"
577 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
578 " .set pop \n"
579 : [addr] "=&r" (addr), [val] "=&r" (val)
580 : [state_addr] "r" (state_addr),
581 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
582
583 __asm__ __volatile__(
584 " .set push \n"
585 " .set noreorder \n"
586 " .set mips64 \n"
587 " mfc0 %[cpuid], $15, 1 \n"
588 " andi %[cpuid], 0x3ff \n"
589 " dli %[base], 0x900000003ff01000 \n"
590 " andi %[core], %[cpuid], 0x3 \n"
591 " sll %[core], 8 \n" /* get core id */
592 " or %[base], %[base], %[core] \n"
593 " andi %[node], %[cpuid], 0xc \n"
594 " dsll %[node], 42 \n" /* get node id */
595 " or %[base], %[base], %[node] \n"
596 "1: li %[count], 0x100 \n" /* wait for init loop */
597 "2: bnez %[count], 2b \n" /* limit mailbox access */
598 " addiu %[count], -1 \n"
599 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
600 " beqz %[initfunc], 1b \n"
601 " nop \n"
602 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
603 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
604 " ld $a1, 0x38(%[base]) \n"
605 " jr %[initfunc] \n" /* jump to initial PC */
606 " nop \n"
607 " .set pop \n"
608 : [core] "=&r" (core), [node] "=&r" (node),
609 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
610 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
611 : /* No Input */
612 : "a1");
613 }
614
loongson3_type2_play_dead(int * state_addr)615 static void loongson3_type2_play_dead(int *state_addr)
616 {
617 register int val;
618 register long cpuid, core, node, count;
619 register void *addr, *base, *initfunc;
620
621 __asm__ __volatile__(
622 " .set push \n"
623 " .set noreorder \n"
624 " li %[addr], 0x80000000 \n" /* KSEG0 */
625 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
626 " cache 0, 1(%[addr]) \n"
627 " cache 0, 2(%[addr]) \n"
628 " cache 0, 3(%[addr]) \n"
629 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
630 " cache 1, 1(%[addr]) \n"
631 " cache 1, 2(%[addr]) \n"
632 " cache 1, 3(%[addr]) \n"
633 " addiu %[sets], %[sets], -1 \n"
634 " bnez %[sets], 1b \n"
635 " addiu %[addr], %[addr], 0x20 \n"
636 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
637 " sw %[val], (%[state_addr]) \n"
638 " sync \n"
639 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
640 " .set pop \n"
641 : [addr] "=&r" (addr), [val] "=&r" (val)
642 : [state_addr] "r" (state_addr),
643 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
644
645 __asm__ __volatile__(
646 " .set push \n"
647 " .set noreorder \n"
648 " .set mips64 \n"
649 " mfc0 %[cpuid], $15, 1 \n"
650 " andi %[cpuid], 0x3ff \n"
651 " dli %[base], 0x900000003ff01000 \n"
652 " andi %[core], %[cpuid], 0x3 \n"
653 " sll %[core], 8 \n" /* get core id */
654 " or %[base], %[base], %[core] \n"
655 " andi %[node], %[cpuid], 0xc \n"
656 " dsll %[node], 42 \n" /* get node id */
657 " or %[base], %[base], %[node] \n"
658 " dsrl %[node], 30 \n" /* 15:14 */
659 " or %[base], %[base], %[node] \n"
660 "1: li %[count], 0x100 \n" /* wait for init loop */
661 "2: bnez %[count], 2b \n" /* limit mailbox access */
662 " addiu %[count], -1 \n"
663 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
664 " beqz %[initfunc], 1b \n"
665 " nop \n"
666 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
667 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
668 " ld $a1, 0x38(%[base]) \n"
669 " jr %[initfunc] \n" /* jump to initial PC */
670 " nop \n"
671 " .set pop \n"
672 : [core] "=&r" (core), [node] "=&r" (node),
673 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
674 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
675 : /* No Input */
676 : "a1");
677 }
678
loongson3_type3_play_dead(int * state_addr)679 static void loongson3_type3_play_dead(int *state_addr)
680 {
681 register int val;
682 register long cpuid, core, node, count;
683 register void *addr, *base, *initfunc;
684
685 __asm__ __volatile__(
686 " .set push \n"
687 " .set noreorder \n"
688 " li %[addr], 0x80000000 \n" /* KSEG0 */
689 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
690 " cache 0, 1(%[addr]) \n"
691 " cache 0, 2(%[addr]) \n"
692 " cache 0, 3(%[addr]) \n"
693 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
694 " cache 1, 1(%[addr]) \n"
695 " cache 1, 2(%[addr]) \n"
696 " cache 1, 3(%[addr]) \n"
697 " addiu %[sets], %[sets], -1 \n"
698 " bnez %[sets], 1b \n"
699 " addiu %[addr], %[addr], 0x40 \n"
700 " li %[addr], 0x80000000 \n" /* KSEG0 */
701 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */
702 " cache 2, 1(%[addr]) \n"
703 " cache 2, 2(%[addr]) \n"
704 " cache 2, 3(%[addr]) \n"
705 " cache 2, 4(%[addr]) \n"
706 " cache 2, 5(%[addr]) \n"
707 " cache 2, 6(%[addr]) \n"
708 " cache 2, 7(%[addr]) \n"
709 " cache 2, 8(%[addr]) \n"
710 " cache 2, 9(%[addr]) \n"
711 " cache 2, 10(%[addr]) \n"
712 " cache 2, 11(%[addr]) \n"
713 " cache 2, 12(%[addr]) \n"
714 " cache 2, 13(%[addr]) \n"
715 " cache 2, 14(%[addr]) \n"
716 " cache 2, 15(%[addr]) \n"
717 " addiu %[vsets], %[vsets], -1 \n"
718 " bnez %[vsets], 2b \n"
719 " addiu %[addr], %[addr], 0x40 \n"
720 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
721 " sw %[val], (%[state_addr]) \n"
722 " sync \n"
723 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
724 " .set pop \n"
725 : [addr] "=&r" (addr), [val] "=&r" (val)
726 : [state_addr] "r" (state_addr),
727 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
728 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
729
730 __asm__ __volatile__(
731 " .set push \n"
732 " .set noreorder \n"
733 " .set mips64 \n"
734 " mfc0 %[cpuid], $15, 1 \n"
735 " andi %[cpuid], 0x3ff \n"
736 " dli %[base], 0x900000003ff01000 \n"
737 " andi %[core], %[cpuid], 0x3 \n"
738 " sll %[core], 8 \n" /* get core id */
739 " or %[base], %[base], %[core] \n"
740 " andi %[node], %[cpuid], 0xc \n"
741 " dsll %[node], 42 \n" /* get node id */
742 " or %[base], %[base], %[node] \n"
743 "1: li %[count], 0x100 \n" /* wait for init loop */
744 "2: bnez %[count], 2b \n" /* limit mailbox access */
745 " addiu %[count], -1 \n"
746 " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */
747 " beqz %[initfunc], 1b \n"
748 " nop \n"
749 " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */
750 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
751 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
752 " ld $a1, 0x38(%[base]) \n"
753 " jr %[initfunc] \n" /* jump to initial PC */
754 " nop \n"
755 " .set pop \n"
756 : [core] "=&r" (core), [node] "=&r" (node),
757 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
758 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
759 : /* No Input */
760 : "a1");
761 }
762
play_dead(void)763 void play_dead(void)
764 {
765 int prid_imp, prid_rev, *state_addr;
766 unsigned int cpu = smp_processor_id();
767 void (*play_dead_at_ckseg1)(int *);
768
769 idle_task_exit();
770 cpuhp_ap_report_dead();
771
772 prid_imp = read_c0_prid() & PRID_IMP_MASK;
773 prid_rev = read_c0_prid() & PRID_REV_MASK;
774
775 if (prid_imp == PRID_IMP_LOONGSON_64G) {
776 play_dead_at_ckseg1 =
777 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
778 goto out;
779 }
780
781 switch (prid_rev) {
782 case PRID_REV_LOONGSON3A_R1:
783 default:
784 play_dead_at_ckseg1 =
785 (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead);
786 break;
787 case PRID_REV_LOONGSON3B_R1:
788 case PRID_REV_LOONGSON3B_R2:
789 play_dead_at_ckseg1 =
790 (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead);
791 break;
792 case PRID_REV_LOONGSON3A_R2_0:
793 case PRID_REV_LOONGSON3A_R2_1:
794 case PRID_REV_LOONGSON3A_R3_0:
795 case PRID_REV_LOONGSON3A_R3_1:
796 play_dead_at_ckseg1 =
797 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
798 break;
799 }
800
801 out:
802 state_addr = &per_cpu(cpu_state, cpu);
803 mb();
804 play_dead_at_ckseg1(state_addr);
805 BUG();
806 }
807
loongson3_disable_clock(unsigned int cpu)808 static int loongson3_disable_clock(unsigned int cpu)
809 {
810 uint64_t core_id = cpu_core(&cpu_data[cpu]);
811 uint64_t package_id = cpu_data[cpu].package;
812
813 if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id])
814 return 0;
815
816 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
817 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
818 } else {
819 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
820 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
821 }
822 return 0;
823 }
824
loongson3_enable_clock(unsigned int cpu)825 static int loongson3_enable_clock(unsigned int cpu)
826 {
827 uint64_t core_id = cpu_core(&cpu_data[cpu]);
828 uint64_t package_id = cpu_data[cpu].package;
829
830 if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id])
831 return 0;
832
833 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
834 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
835 } else {
836 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
837 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
838 }
839 return 0;
840 }
841
register_loongson3_notifier(void)842 static int register_loongson3_notifier(void)
843 {
844 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
845 "mips/loongson:prepare",
846 loongson3_enable_clock,
847 loongson3_disable_clock);
848 }
849 early_initcall(register_loongson3_notifier);
850
851 #endif
852
853 const struct plat_smp_ops loongson3_smp_ops = {
854 .send_ipi_single = loongson3_send_ipi_single,
855 .send_ipi_mask = loongson3_send_ipi_mask,
856 .init_secondary = loongson3_init_secondary,
857 .smp_finish = loongson3_smp_finish,
858 .boot_secondary = loongson3_boot_secondary,
859 .smp_setup = loongson3_smp_setup,
860 .prepare_cpus = loongson3_prepare_cpus,
861 #ifdef CONFIG_HOTPLUG_CPU
862 .cpu_disable = loongson3_cpu_disable,
863 .cpu_die = loongson3_cpu_die,
864 #endif
865 #ifdef CONFIG_KEXEC_CORE
866 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
867 #endif
868 };
869